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IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
2.5V - 2.6V PHASE LOCKED LOOP DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
FEATURES: DESCRIPTION:
IDTCSPT857D
* 1 to 10 differential clock distribution * Optimized for clock distribution in DDR (Double Data Rate) SDRAM applications requiring improved output crosspoint voltage * Operating frequency: 60MHz to 220MHz * Very low skew: - <100ps for PC1600 - PC2700 - <75ps for PC3200 * Very low jitter: - <75ps for PC1600 - PC2700 - <50ps for PC3200 * 2.5V AVDD and 2.5V VDDQ for PC1600-PC2700 * 2.6V AVDD and 2.6V VDDQ for PC3200 * CMOS control signal input * Test mode enables buffers while disabling PLL * Low current power-down mode * Tolerant of Spread Spectrum input clock * Available in 48-pin TSSOP and TVSOP, 40-pin VFQFPN, and 56pin VFBGA packages
The CSPT857D is a PLL based clock driver that acts as a zero delay buffer to distribute one differential clock input pair(CLK, CLK ) to 10 differential output pairs (Y [0:9], Y [0:9]) and one differential pair of feedback clock output (FBOUT, FBOUT). External feedback pins (FBIN, FBIN) for synchronization of the outputs to the input reference is provided. A CMOS Enable/Disable pin is available for low power disable. When the input frequency falls below approximately 20MHz, the device will enter power down mode. In this mode, the receivers are disabled, the PLL is turned off, and the output clock drivers are tristated, resulting in a current consumption of less than 200A. The CSPT857D requires no external components and has been optimised for very low I/O phase error, skew, and jitter, while maintaining frequency and duty cycle over the operating voltage and temperature range. The CSPT857D, designed for use in both module assemblies and system motherboard based solutions, provides an optimum high-performance clock source. The CSPT857D is available in Commercial Temperature Range (0C to +70C) and Industrial Temperature Range (-40C to +85C). See Ordering Information for details.
APPLICATIONS:
* Meets or exceeds JEDEC standard JESD 82-1A for registered DDR clock driver * Meets proposed DDR1-400 specification * For all DDR1 speeds: PC1600 (DDR200), PC2100 (DDR266), PC2700 (DDR333), PC3200 (DDR400) * Along with SSTV16857, SSTVF16857, SSTV16859, SSTVM16859, SSTVF16859, SSTVN16859, DDR1 register, provides complete solution for DDR1 DIMMs
The IDT logo is a registered trademark of Integrated Device Technology, Inc.
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
1
c 2003 Integrated Device Technology, Inc.
OCTOBER 2003
DSC-6835/3
IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTIONAL BLOCK DIAGRAM
PWRDWN TEST MODE LOGIC Y0 Y0 Y1 Y1 Y2 Y2 Y3 Y3 Y4 Y4 CLK CLK FBIN FBIN PLL Y5 Y5 Y6 Y6 Y7 Y7 Y8 Y8 Y9 Y9 FBOUT FBOUT
AVDD
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IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
PWR DWN
6
Y5 Y5
Y6 Y6
GND GND NC NC GND GND
C
Y7 Y7 NC NC Y2 Y2
D
FBIN
VDDQ FBOUT
Y8 Y8
Y9 Y9
5
VDDQ FBIN FBOUT GND NC NC VDDQ VDDQ
E
4
GND VDDQ GND VDDQ Y0 Y0
A
NC NC
VDDQ GND VDDQ GND Y3 Y3
J
3
2
Y1 Y1
B
CLK CLK
F
AVDD GND VDDQ AGND
G H
Y4 Y4
K
1
VFBGA TOP VIEW
56 BALL VFBGA PACKAGE LAYOUT
0.65mm
6
5 4 3 2 1 A B C D E F G H J K
TOP VIEW
A 1 2 3 4 5 6
B
C
D
E
F
G
H
J
K
3
IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
PIN CONFIGURATIONS
VDDQ VDDQ
GND
Y6 Y6
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
GND Y5 Y5 VDDQ Y6 Y6 GND GND Y7 Y7 VDDQ PWRDWN FBIN FBIN VDDQ FBOUT FBOUT GND Y8 Y8 VDDQ Y9 Y9 GND
Y1
Y1
Y0
Y0
Y5
Y5
Y0 Y0
30 29 28 27 26 25 24 23 22 21 Y7 Y7 VDDQ PWRDWN FBIN FBIN VDDQ
40 GND Y2 Y2 VDDQ CLK CLK VDDQ AVDD AGND GND 1 2 3 4 5 6 7 8 9 10 11
39
38
37
36
35
34
33
32
31
VDDQ Y1 Y1 GND GND Y2 Y2
GND
VDDQ FBOUT FBOUT
VDDQ VDDQ CLK CLK VDDQ AVDD AGND
12
13
14
15
16
17
18
19
20
VDDQ
VDDQ
Y3
Y3
Y4
Y4
Y9
Y9
Y8
VFQFPN TOP VIEW
Y8
GND Y3 Y3
Unit V V V mA mA
ABSOLUTE MAXIMUM RATINGS(1)
Symbol VDDQ, AVDD VI(2) VO(2) IIK (VI <0) IOK (VO <0 or VO > VDDQ) IO Rating Supply Voltage Range Input Voltage Range Voltage range applied to any output in the high or low state Input Clamp Current Output Clamp Current Max -0.5 to +3.6 -0.5 to VDDQ + 0.5 -0.5 to VDDQ + 0.5 -50 50
VDDQ Y4 Y4 GND
TSSOP/ TVSOP TOP VIEW
Continuous Output Current
50 100 - 65 to +150
mA mA C
(VO =0 to VDDQ) VDDQ or GND Continuous Current TSTG Storage Temperature Range
CAPACITANCE(1)
Parameter CIN CI() CL Description Input Capacitance VI = VDDQ or GND Delta Input Capacitance VI = VDDQ or GND Load Capacitance -- 14 -- pF
NOTE: 1. Unused inputs must be held high or low to prevent them from floating.
Min. 2.5 -0.25
Typ. -- --
Max. 3.5 0.25
Unit pF pF
NOTES: 1. Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. The input and output negative-voltage ratings may be exceeded if the input and output clamp-current ratings are observed. 3. The maximum package power dissipation is calculated using a junction temperature of 150C and a board trace length of 750 mils.
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IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
RECOMMENDED OPERATING CONDITIONS
Symbol AVDD VDDQ TA Supply Voltage I/O Supply Voltage PC1600-PC2700 PC3200 Operating Free-Air Temperature Parameter Min. VDDQ - 0.12 2.3 2.5 -40 Typ. VDDQ 2.5 2.6 Max. 2.7 2.7 2.7 +85 Unit V V
C
PIN DESCRIPTION (TSSOP/TVSOP)
Pin Name AGND AVDD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND PWRDWN VDDQ Y[0:9] Y[0:9] Pin Number 17 16 13, 14 35, 36 32, 33 1, 7, 8, 18, 24, 25, 31, 41, 42, 48 37 4, 11, 12, 15, 21, 28, 34, 38, 45 3, 5, 10, 20, 22, 27, 29, 39, 44, 46 2, 6, 9, 19, 23, 26, 30, 40, 43, 47 Ground for analog supply Analog supply Differential clock input Feedback differential clock input Feedback differential clock output Ground Output enable for Y and Y I/O supply Buffered output of input clock, CLK Buffered output of input clock, CLK Description
PIN DESCRIPTION (VFBGA)
Pin Name AGND AVDD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND PWRDWN VDDQ Y[0:9] Y[0:9] Pin Number H1 G2 F1, F2 F5, F6 H6, G5 A3, A4, C1, C2, C5, C6, H2, H5, K3, K4 E6 B3, B4, E1, E2, E5, G1, G6, J3, J4 A1, A6, B2, B5, D1, D6, J2, J5, K1, K6 A2, A5, B1, B6, D2, D5, J1, J6, K2, K5 Ground for analog supply Analog supply Differential clock input Feedback differential clock input Feedback differential clock output Ground Output enable for Y and Y I/O supply Buffered output of input clock, CLK Buffered output of input clock, CLK Description
PIN DESCRIPTION (VFQFPN)
Pin Name AGND AVDD CLK, CLK FBIN, FBIN FBOUT, FBOUT GND PWRDWN VDDQ Y[0:9] Y[0:9] Pin Number 9 8 5, 6 25, 26 21, 22 1, 10 27 4, 7, 13, 18, 23, 24, 28, 33, 38 3, 12, 14, 17, 19, 29, 32, 34, 37, 39 2, 11, 15, 16, 20, 30, 31, 35, 36, 40 Ground for analog supply Analog supply Differential clock input Feedback differential clock input Feedback differential clock output Ground Output enable for Y and Y I/O supply Buffered output of input clock, CLK Buffered output of input clock, CLK Description
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IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
FUNCTION TABLE(1)
INPUTS AVDD GND GND X X Nominal(2) Nominal(2) Nominal(2,3) PWRDWN H H L L H H X CLK L H L H L H <20MHz CLK H L H L H L <20MHz Y L H Z Z L H Z Y H L Z Z H L Z OUTPUTS FBOUT L H Z Z L H Z FBOUT H L Z Z H L Z PLL Bypassed/OFF Bypassed/OFF OFF OFF ON ON OFF
NOTES: 1. H = HIGH Voltage Level L = LOW Voltage Level Z = High-Impedance OFF-State X = Don't Care 2. AVDD nominal is 2.5V for PC1600, PC2100, and PC2700. AVDD nominal is 2.6V for PC3200. 3. Additional feature that senses when the clock input is less than approximately 20MHz and places the part in sleep mode. Reciever inputs and PLL are turned off and outputs = tristate.
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC1600 PC2700
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C; Industrial: TA = -40C to +85C
Symbol VIK VIL (dc) VIH (dc) VIL (ac) VIH (ac) VOL VOH VIX VID(DC) (1) VID(AC) (1) IIN IDDPD IDDQ IADD Parameter Input Clamp Voltage (All Inputs) Static Input LOW Voltage Static Input HIGH Voltage Dynamic Input LOW Voltage Dynamic Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Input Differential Cross Voltage DC Input Differential Voltage AC Input Differential Voltage Input Current Power-Down Current on VDDQ and AVDD Dynamic Power Supply Current on VDDQ Dynamic Power Supply Current on AVDD VDDQ = 2.7V, VI = 0V to 2.7V AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L AVDD/VDDQ = Max., CLK = 200MHz, 120/14pF AVDD/VDDQ = Max., CLK = 170MHz, 120/14pF AVDD/VDDQ = Max., CLK = 170MHz
NOTE: 1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
Conditions VDDQ = 2.3V, II = -18mA PWRDWN PWRDWN CLK, CLK, FBIN, FBIN CLK, CLK, FBIN, FBIN AVDD/VDDQ = Min., IOL = 100A AVDD/VDDQ = Min., IOL = 12mA AVDD/VDDQ = Min., IOH = -100A AVDD/VDDQ = Min., IOH = -12mA
Min. - 0.3 1.7 1.7 VDDQ - 0.1 1.7 VDDQ/2 - 0.2 0.36 0.7
Typ.
Max. - 1.2 0.7 VDDQ + 0.3 0.7 VDDQ 0.1 0.6
Unit V V V V V
VDDQ/2 + 0.2 VDDQ + 0.6 VDDQ + 0.6 10 100 320 250 200 360 300 12
V V V A A mA mA
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IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
DC ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE FOR PC3200
Following Conditions Apply Unless Otherwise Specified: Commercial: TA = 0C to +70C; Industrial: TA = -40C to +85C
Symbol VIK VIL (dc) VIH (dc) VIL (ac) VIH (ac) VOL VOH VIX VID(DC) (1) VID(AC) (1) IIN IDDPD IDDQ IADD Parameter Input Clamp Voltage (All Inputs) Static Input LOW Voltage Static Input HIGH Voltage Dynamic Input LOW Voltage Dynamic Input HIGH Voltage Output LOW Voltage Output HIGH Voltage Input Differential Cross Voltage DC Input Differential Voltage AC Input Differential Voltage Input Current Power-Down Current on VDDQ and AVDD Dynamic Power Supply Current on VDDQ Dynamic Power Supply Current on AVDD VDDQ = 2.7V, VI = 0V to 2.7V AVDD/VDDQ = Max., CLK = 0MHz or PWRDWN = L AVDD/VDDQ = Max., CLK = 200MHz, 120/14pF AVDD/VDDQ = Max., CLK = 200MHz, 120/14pF AVDD/VDDQ = Max., CLK = 200MHz
NOTE: 1. VID is the magnitude of the difference between the input level on CLK and the input level on CLK.
Conditions VDDQ = 2.5V, II = -18mA PWRDWN PWRDWN CLK, CLK, FBIN, FBIN CLK, CLK, FBIN, FBIN AVDD/VDDQ = Min., IOL = 100A AVDD/VDDQ = Min., IOL = 12mA AVDD/VDDQ = Min., IOH = -100A AVDD/VDDQ = Min., IOH = -12mA
Min. - 0.3 1.7 1.7 VDDQ - 0.1 1.7 VDDQ/2 - 0.2 0.36 0.7
Typ.
Max. - 1.2 0.7 VDDQ + 0.3 0.7 VDDQ 0.1 0.6
Unit V V V V V
VDDQ/2 + 0.2 VDDQ + 0.6 VDDQ + 0.6 10 100 320 250 200 360 300 12
V V V A A mA mA
TIMING REQUIREMENTS FOR PC1600 - PC2700
Symbol fCLK tDC tL Parameter Operating Clock Frequency(1,2) Application Clock Frequency(1,3) Input Clock Duty Cycle Stabilization Time(4) Min. 60 60 40 Max. 200 200 60 100 Unit MHz MHz % s
NOTES: 1. The PLL will track a spread spectrum clock input. 2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. 3. Application clock frequency is the range over which timing specifications apply. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
TIMING REQUIREMENTS FOR PC3200
Symbol fCLK tDC tL Parameter Operating Clock Frequency(1,2) Application Clock Frequency(1,3) Input Clock Duty Cycle Stabilization Time(4) Min. 60 60 40 Max. 220 220 60 100 Unit MHz MHz % s
NOTES: 1. The PLL will track a spread spectrum clock input. 2. Operating clock frequency is the range over which the PLL will lock, but may not meet all timing specifications. 3. Application clock frequency is the range over which timing specifications apply. 4. Stabilization time is the time required for the integrated PLL circuit to obtain phase lock of its feedback signal to its reference signal after power up.
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IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS FOR PC1600 - PC2700
Symbol tPLH(1) tPHL(1) tJIT(PER) tJIT(CC) tJIT(HPER) tSLR(O) tSLR(I) t () tSK(O) tR, tF VOX(5) Description LOW to HIGH Level Propagation Delay Time HIGH to LOW Level Propagation Delay Time Jitter (period), see figure 6 Jitter (cycle-to-cycle), see figure 3 Half-Period Jitter, see figure 7 Output Clock Slew Rate (Single-Ended) Input Clock Slew Rate Static Phase Offset, see figure 4(2,3) Output Skew, see figure 5 Output Rise and Fall Times (20% to 80%) Output Differential Voltage Load: 120 / 14pF Differential outputs are terminated with 120 SSC SSC f3dB Modulation Frequency Clock Input Frequency Deviation PLL Loop Bandwidth 650 VDDQ/2 - 0.15 30 0 5 66/ 100/ 133/ 167/ 200 MHz Test Conditions Test mode, CLK to any output Test mode, CLK to any output 66MHz 100/ 133/ 167/ 200 MHz 66MHz 100/ 133/ 167/ 200 MHz 66MHz 100/ 133/ 167/ 200 MHz 100/ 133/ 167/ 200 MHz (20% to 80%) - 90 - 75 - 180 - 75 - 160 - 100 1 1 - 50 Min. Typ.(1) 4.5 4.5 90 75 180 75 160 100 2.5 4 50 75 900 VDDQ/2 + 0.15 50 -0.5 KHz % MHz V/ns V/ns ps ps ps V ps ps Max. Unit ns ns ps
The PLL on the CSPT857D will meet all the above test parameters while supporting SSC synthesizers(4) with the following parameters:
NOTES: 1. Refers to transition of non-inverting output. 2. Static phase offset does not include jitter. 3. t() is measured with input clock slew rate tSLR(I) = 2V/ns and an input differential voltage VID of 1.75V. 4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification. 5. VOX is specified at the SDRAM clock input or test load.
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IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
SWITCHING CHARACTERISTICS FOR PC3200
Symbol tPLH(1) tPHL(1) tJIT(PER) tJIT(CC) tJIT(HPER) tSLR(O) tSLR(I) t () tSK(O) tR, tF VOX(5) Description LOW to HIGH Level Propagation Delay Time HIGH to LOW Level Propagation Delay Time Jitter (period), see figure 6 Jitter (cycle-to-cycle), see figure 3 Half-Period Jitter, see figure 7 Output Clock Slew Rate (Single-Ended) Input Clock Slew Rate Static Phase Offset, see figure 4(2,3) Output Skew, see figure 5 Output Rise and Fall Times (20% to 80%) Output Differential Voltage Load: 120 / 14pF Differential outputs are terminated with 120 SSC SSC f3dB Modulation Frequency Clock Input Frequency Deviation PLL Loop Bandwidth 650 VDDQ/2 - 0.15 30 0 5 200 MHz Test Conditions Test mode, CLK to any output Test mode, CLK to any output 66MHz 200 MHz 66MHz 200 MHz 66MHz 200 MHz 200 MHz (20% to 80%) - 90 - 50 - 180 - 75 - 160 - 75 1 1 - 50 Min. Typ.(1) 4.5 4.5 90 50 180 75 160 75 2.5 4 50 75 900 VDDQ/2 + 0.15 50 -0.5 KHz % MHz V/ns V/ns ps ps ps V ps ps Max. Unit ns ns ps
The PLL on the CSPT857D will meet all the above test parameters while supporting SSC synthesizers(4) with the following parameters:
NOTES: 1. Refers to transition of non-inverting output. 2. Static phase offset does not include jitter. 3. t() is measured with input clock slew rate tSLR(I) = 2V/ns and an input differential voltage VID of 1.75V. 4. The SSC requirements meet the Intel PC100 SDRAM Registered DIMM specification. 5. VOX is specified at the SDRAM clock input or test load.
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IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
VDD
Z = 60 C = 14pF Z = 60 R = 120 VSS
C = 14pF VSS CSPT857D VSS
Figure 1. Output Load
VDDQ/2
Z = 60 C = 14pF VDDQ/2 Z = 60 C = 14pF VDDQ/2 CSPT857D VDDQ/2
R = 10
Z = 50 R = 50 0V
R = 10
Z = 50
R = 50 0V SCOPE
Figure 2. Output Load Test Circuit
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IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
Yx, FBOUT Yx, FBOUT
tcycle n tjit(cc) = tcycle n
tcycle n+1 tcycle n+1
Figure 3. Cycle-to-Cycle jitter
CLK CLK
FBIN FBIN
t(O)n
t(O)n + 1
t(O)
=
n=N 1 N
t(O)n
(N is a large number of samples)
Figure 4. Static Phase Offset
Yx Yx
Yx, FBOUT Yx, FBOUT
tsk(o)
Figure 5. Output Skew 11
IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
Yx, FBOUT Yx, FBOUT
tcycle n
Yx, FBOUT Yx, FBOUT 1 fo 1 fo
tjit(per)
=
tcycle n
Figure 6. Period jitter
Yx, FBOUT Yx, FBOUT
thalf period n
Yx, FBOUT Yx, FBOUT 1 fo
thalf period n+1
tjit(hper) = thalf period n
1 2*f o
Figure 7. Half-Period jitter
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IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
TEST CIRCUIT AND SWITCHING WAVEFORMS
80% Clock Inputs and Outputs 20%
80% VID, VOD 20%
tR
Figure 8. Input and Output Slew Rates
tF
APPLICATION INFORMATION
Clock Loading on the PLL outputs (pF) Clock Structure #1 #2 # of SDRAM Loads per Clock 2 4 Min. 4 8 Max. 7 14
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IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
APPLICATION INFORMATION
~2.5" ~0.6" (split to terminator)
SDRAM CSPT857D Z = 60 CLK C = 14pF CLK R = 120 R = 120 Z = 60
FBIN C = 14pF
(1)
8 more ~0.3"
SDRAM
R = 120 FBIN
Feedback path
Figure 9. Clock Structure 1
~2.5"
~0.6" (split to terminator)
SDRAM SDRAM CSPT857D Z = 60 CLK C = 14pF CLK SDRAM ~0.3" FBIN SDRAM R = 120
Stacked
R = 120 Z = 60
FBIN C = 14pF
(1)
8 more
Stacked
R = 120
Feedback path
Figure 10. Clock Structure 2
NOTE: 1. Memory module vendors may need to adjust the feedback capacitive load in order to meet DDR SDRAM registered DIMM timing requirements.
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IDTCSPT857D 2.5V - 2.6V PLL DIFFERENTIAL 1:10 SDRAM CLOCK DRIVER
COMMERCIAL AND INDUSTRIAL TEMPERATURE RANGES
ORDERING INFORMATION
IDTCSPT XXXXX Device Type X XX Package Process Blank I PA PAG PF BV NL 0C to +70C (Commercial) -40C to +85C (Industrial)
Thin Shrink Small Outline Package TSSOP - Green Thin Very Small Outline Package Very Fine Pitch Ball Grid Array Thermally-Enhanced Plastic Very Fine Pitch Flat No Lead Package VFQFPN MLF - Green
857D
2.5V - 2.6V PLL Differential 1:10 SDRAM Clock Driver
CORPORATE HEADQUARTERS 2975 Stender Way Santa Clara, CA 95054
for SALES: 800-345-7015 or 408-727-6116 fax: 408-492-8674 www.idt.com
for Tech Support: logichelp@idt.com (408) 654-6459
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