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PD - 95888
SMPS MOSFET
Applications * Zero Voltage Switching SMPS * Telecom and Server Power Supplies * Uninterruptible Power Supplies * Motor Control applications
IRFIB7N50L
HEXFET(R) Power MOSFET 320m 85ns 6.8A
VDSS RDS(on) typ. Trr typ. ID
500V
Features and Benefits * SuperFast body diode eliminates the need for external diodes in ZVS applications. * Lower Gate charge results in simpler drive requirements. * Enhanced dv/dt capabilities offer improved ruggedness. * Higher Gate voltage threshold offers improved noise immunity.
TO-220 Full-Pak
Absolute Maximum Ratings
ID @ TC = 25C IDM Parameter Continuous Drain Current, VGS @ 10V Max. 6.8 4.3 27 46 0.37 30 24 -55 to + 150 300 (1.6mm from case ) 10lbxin (1.1Nxm) W W/C V V/ns C Units A ID @ TC = 100C Continuous Drain Current, VGS @ 10V Pulsed Drain Current PD @TC = 25C Power Dissipation VGS dv/dt TJ TSTG
Linear Derating Factor Gate-to-Source Voltage Peak Diode Recovery dv/dt Operating Junction and
e
Storage Temperature Range Soldering Temperature, for 10 seconds Mounting torque, 6-32 or M3 screw
Diode Characteristics
Symbol
IS ISM VSD trr Qrr IRRM ton
Parameter
Continuous Source Current (Body Diode) Pulsed Source Current (Body Diode)A Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Forward Turn-On Time
Min. Typ. Max. Units
--- --- --- --- --- --- --- --- --- --- --- 85 130 280 570 5.9 6.8 A 27 1.5 130 200 420 860 8.9 V ns
Conditions
MOSFET symbol showing the integral reverse
G S D
p-n junction diode. TJ = 25C, IS = 6.8A, VGS = 0V TJ = 25C, IF = 6.8A TJ = 125C, di/dt = 100A/s
f f
f f
nC TJ = 25C, IS = 6.8A, VGS = 0V TJ = 125C, di/dt = 100A/s A TJ = 25C
Intrinsic turn-on time is negligible (turn-on is dominated by LS+LD)
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1
7/30/04
IRFIB7N50L
Static @ TJ = 25C (unless otherwise specified)
Symbol
V(BR)DSS V(BR)DSS/TJ RDS(on) VGS(th) IDSS IGSS RG
Parameter
Drain-to-Source Breakdown Voltage Breakdown Voltage Temp. Coefficient Static Drain-to-Source On-Resistance Gate Threshold Voltage Drain-to-Source Leakage Current Gate-to-Source Forward Leakage Gate-to-Source Reverse Leakage Internal Gate Resistance
Min. Typ. Max. Units
500 --- --- 3.0 --- --- --- --- --- --- 0.44 0.32 --- --- --- --- --- 0.88 --- --- 0.38 5.0 50 2.0 100 -100 ---
Conditions
V VGS = 0V, ID = 250A V/C Reference to 25C, ID = 1mA VGS = 10V, ID = 4.1A V VDS = VGS, ID = 250A A VDS = 500V, VGS = 0V mA VDS = 400V, VGS = 0V, TJ = 125C nA VGS = 30V VGS = -30V f = 1MHz, open drain
f
Dynamic @ TJ = 25C (unless otherwise specified)
Symbol
gfs Qg Qgs Qgd td(on) tr td(off) tf Ciss Coss Crss Coss Coss Coss eff. Coss eff. (ER)
Parameter
Forward Transconductance Total Gate Charge Gate-to-Source Charge Gate-to-Drain ("Miller") Charge Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Input Capacitance Output Capacitance Reverse Transfer Capacitance Output Capacitance Output Capacitance Effective Output Capacitance Effective Output Capacitance (Energy Related)
Min. Typ. Max. Units
4.7 --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- --- 23 36 47 19 2220 230 23 2780 63 140 100 --- 92 24 44 --- --- --- --- --- --- --- --- --- --- --- S nC
Conditions
VDS = 50V, ID = 4.1A ID = 6.8A VDS = 400V VGS = 10V, See Fig. 7 & 16 VDD = 250V ID = 6.8A RG = 9.0 VGS = 10V, See Fig. 11a & 11b VGS = 0V VDS = 25V = 1.0MHz, See Fig. 5 VGS = 0V, VDS = 1.0V, = 1.0MHz VGS = 0V, VDS = 400V, = 1.0MHz
f
ns
f
pF
VGS = 0V,VDS = 0V to 400V
g
Avalanche Characteristics
Symbol
EAS IAR EAR Parameter Single Pulse Avalanche Energyd Avalanche CurrentA Repetitive Avalanche Energy Typ. --- --- --- Max. 550 6.8 4.6 Units mJ A mJ
Thermal Resistance
Symbol
RJC RJA
Notes:
Parameter
Junction-to-Case Junction-to-Ambient
Typ.
--- ---
Max.
2.69 65
Units
C/W
Repetitive rating; pulse width limited by
max. junction temperature. (See Fig. 12). Starting TJ = 25C, L = 24mH, RG = 25, IAS = 6.8A, (See Figure 14). ISD 6.8, di/dt 650A/s, VDD V(BR)DSS, dv/dt = 24V/ns, TJ 150C.
Pulse width 300s; duty cycle 2%. Coss eff. is a fixed capacitance that gives the same charging time
as Coss while VDS is rising from 0 to 80% VDSS . Coss eff.(ER) is a fixed capacitance that stores the same energy as C oss while V DS is rising from 0 to 80% VDSS .
2
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IRFIB7N50L
100
TOP VGS 15V 10V 8.0V 7.0V 6.5V 6.0V 5.5V 5.0V
100
TOP VGS 15V 10V 8.0V 7.0V 6.5V 6.0V 5.5V 5.0V
ID, Drain-to-Source Current (A)
10
BOTTOM
ID, Drain-to-Source Current (A)
10
BOTTOM
1
5.0V 1
5.0V 0.1
60s PULSE WIDTH
0.01 0.1 1 Tj = 25C 0.1 100 0.1 1 10
60s PULSE WIDTH
Tj = 150C 10 100
V DS, Drain-to-Source Voltage (V)
V DS, Drain-to-Source Voltage (V)
Fig 1. Typical Output Characteristics
Fig 2. Typical Output Characteristics
100
3.0
RDS(on) , Drain-to-Source On Resistance (Normalized)
ID, Drain-to-Source Current ()
2.5
ID = 6.8A VGS = 10V
10
TJ = 175C
2.0
1.5
1
T J = 25C
1.0
VDS = 50V 60s PULSE WIDTH 0.1 3 4 5 6 7 8 9
0.5
0.0 -60 -40 -20 0 20 40 60 80 100 120 140 160
VGS, Gate-to-Source Voltage (V)
T J , Junction Temperature (C)
Fig 3. Typical Transfer Characteristics
Fig 4. Normalized On-Resistance vs. Temperature
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IRFIB7N50L
100000 VGS = 0V, f = 1 MHZ C iss = C gs + C gd, C ds SHORTED C rss = C gd C oss = C ds + C gd
12 10 8
10000
C, Capacitance(pF)
Ciss
1000
Energy (J)
6 4 2 0
Coss
100
Crss
10 1 10 100 1000
0
50 100 150 200 250 300 350 400 450 500 550 VDS, Drain-to-Source Voltage (V)
VDS, Drain-to-Source Voltage (V)
Fig 5. Typical Capacitance vs. Drain-to-Source Voltage
Fig 6. Typ. Output Capacitance Stored Energy vs. VDS
12.0 ID= 6.8A
VGS, Gate-to-Source Voltage (V)
100.00
VDS= 400V
ISD, Reverse Drain Current (A)
10.0 8.0 6.0 4.0 2.0 0.0 0 10 20
10.00
T J = 150C
1.00
0.10
T J = 25C
0.01
30 40 50 60 70
VGS = 0V 0.0 0.2 0.4 0.6 0.8 1.0 1.2
QG Total Gate Charge (nC)
VSD, Source-to-Drain Voltage (V)
Fig 7. Typical Gate Charge vs. Gate-to-Source Voltage
Fig 8. Typical Source-Drain Diode Forward Voltage
4
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IRFIB7N50L
100
OPERATION IN THIS AREA LIMITED BY R (on) DS
7 6
ID, Drain Current (A)
ID, Drain-to-Source Current (A)
10
100sec
5 4 3 2 1
1 DC 0.1 Tc = 25C Tj = 150C Single Pulse 1 10 100 1msec 10msec 1000 10000
0.01
0 25 50 75 100 125 150 T C , Case Temperature (C)
VDS, Drain-to-Source Voltage (V)
Fig 9. Maximum Safe Operating Area
Fig 10. Maximum Drain Current vs. Case Temperature
V DS VGS RG 10V
Pulse Width 1 s Duty Factor 0.1 %
RD
VDS 90%
D.U.T.
+
-VDD
10% VGS
td(on) tr t d(off) tf
Fig 11a. Switching Time Test Circuit
Fig 11b. Switching Time Waveforms
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IRFIB7N50L
10
Thermal Response ( Z thJC )
1
D = 0.50 0.20 0.10 0.05 0.02 0.01
J R1 R1 J 1 2 R2 R2 R3 R3 3 C 3
0.1
Ri (C/W) 0.2965 0.9847 1.4118
i (sec) 0.001144 0.151939 1.705500
0.01
1
2
0.001
SINGLE PULSE ( THERMAL RESPONSE )
Ci= i/Ri Ci i/Ri
Notes: 1. Duty Factor D = t1/t2 2. Peak Tj = P dm x Zthjc + Tc
0.01 0.1 1 10 100
0.0001 1E-006 1E-005 0.0001 0.001
t1 , Rectangular Pulse Duration (sec)
Fig 12. Maximum Effective Transient Thermal Impedance, Junction-to-Case
5.0
VGS(th) Gate threshold Voltage (V)
4.0
ID = 250A
3.0
2.0
1.0 -75 -50 -25 0 25 50 75 100 125 150
T J , Temperature ( C )
Fig 13. Threshold Voltage vs.Temperature
6
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IRFIB7N50L
2500
EAS , Single Pulse Avalanche Energy (mJ)
2000
ID TOP 1.4A 1.7A BOTTOM 6.8A
1500
1000
500
0 25 50 75 100 125 150
Starting T J , Junction Temperature (C)
Fig 14. Maximum Avalanche Energy vs. Drain Current
15V
V(BR)DSS
VDS L
DRIVER
tp
RG
20V
D.U.T
IAS tp
+ V - DD
A
0.01
I AS
Fig 15a. Unclamped Inductive Test Circuit
Current Regulator Same Type as D.U.T.
Fig 15b. Unclamped Inductive Waveforms
QG
50K 12V .2F .3F
10 V
D.U.T. + V - DS
QGS
QGD
VGS
3mA
VG
IG ID
Current Sampling Resistors
Charge
Fig 16a. Gate Charge Test Circuit
Fig 16b. Basic Gate Charge Waveform
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IRFIB7N50L
Peak Diode Recovery dv/dt Test Circuit
D.U.T
+
+
Circuit Layout Considerations * Low Stray Inductance * Ground Plane * Low Leakage Inductance Current Transformer
-
+
RG * * * * dv/dt controlled by RG Driver same type as D.U.T. ISD controlled by Duty Factor "D" D.U.T. - Device Under Test
+ VDD
Driver Gate Drive P.W. Period D=
P.W. Period VGS=10V
*
D.U.T. ISD Waveform Reverse Recovery Current Body Diode Forward Current di/dt D.U.T. VDS Waveform Diode Recovery dv/dt
VDD
Re-Applied Voltage Inductor Curent
Body Diode
Forward Drop
Ripple 5%
ISD
* VGS = 5V for Logic Level Devices Fig 17. For N-Channel HEXFET(R) Power MOSFETs
8
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IRFIB7N50L
TO-220 Full-Pak Package Outline
Dimensions are shown in millimeters (inches)
10.60 (.417) 10.40 (.409) o 3.40 (.133) 3.10 (.123) -A3.70 (.145) 3.20 (.126) 7.10 (.280) 6.70 (.263) 4.80 (.189) 4.60 (.181) 2.80 (.110) 2.60 (.102) LEAD ASSIGNMENTS 1 - GATE 2 - DRAIN 3 - SOURCE NOTES: 1 DIMENSIONING & TOLERANCING PER ANSI Y14.5M, 1982 2 CONTROLLING DIMENSION: INCH. 3.30 (.130) 3.10 (.122) -B13.70 (.540) 13.50 (.530) C A D B
16.00 (.630) 15.80 (.622)
1.15 (.045) MIN. 1 2 3
1.40 (.055) 3X 1.05 (.042) 2.54 (.100) 2X
3X
0.90 (.035) 0.70 (.028) 0.25 (.010) M AM B
3X
0.48 (.019) 0.44 (.017)
2.85 (.112) 2.65 (.104)
MINIMUM CREEPAGE DISTANCE BETWEEN A-B-C-D = 4.80 (.189)
TO-220 Full-Pak Part Marking Information
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Note: "P" in assembly line position indicates "Lead-Free"
DIU@SI6UDPI6G S@8UDAD@S GPBP 6TT@H7G GPUA8P9@
Q6SUAIVH7@S
DS A D' # B ( !# F A" # AAAAAAAAA" !
96U@A8P9@ @6SA(A2A ((( X @@FA!# GDI@AF
TO-220AB FullPak package is not recommended for Surface Mount Application. Data and specifications subject to change without notice. This product has been designed and qualified for the Industrial market. Qualification Standards can be found on IR's Web site.
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IR WORLD HEADQUARTERS: 233 Kansas St., El Segundo, California 90245, USA Tel: (310) 252-7105 TAC Fax: (310) 252-7903 Visit us at www.irf.com for sales contact information.07/04
9

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