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256MB, 512MB, 1GB Registered DIMM
SDRAM
SDRAM Registered Module
168pin Registered Module based on 256Mb E-die with 72-bit ECC
Revision 1.4 May 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
Revision History
Revision 0.0 (June, 2003) - First release Revision 1.0 (June, 2003) - Revision 1.0 release. Revision 1.1 (September, 2003) - Corrected typo. Revision 1.2 (February, 2004) - Corrected typo. Revision 1.3 (March. 2004) - Modified DC Characteristics Notes. Revision 1.4 (May, 2004) - Added Note 5. sentense of tRDL parameter
SDRAM
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
168Pin Registered DIMM based on 256Mb E-die (x4, x8)
Ordering Information
Part Number M390S3253ET1-C7A M390S3253ETU-C7A M390S6450ET1-C7A M390S6450ETU-C7A M390S6453ET1-C7A M390S2858ET1-C7A M390S2858ETU-C7A Density 256MB 256MB 512MB 512MB 512MB 1GB 1GB Organization 32Mx72 32Mx72 64Mx72 64Mx72 64Mx72 128Mx72 128Mx72 Component Composition 32Mx8(K4S560832E) * 9EA 32Mx8(K4S560832E) * 9EA 64Mx4(K4S560432E) * 18EA 64Mx4(K4S560432E) * 18EA 32Mx8(K4S560832E) * 18EA st.128Mx4(K4S510632E) * 18EA st.128Mx4(K4S510632E) * 18EA 54-TSOP(II) Component Package
SDRAM
Height 1,500mil 1,200mil 1,700mil 1,200mil 1,700mil 1,700mil 1,200mil
Operating Frequencies
7A @CL3 Maximum Clock Frequency CL-tRCD-tRP(clock) 133MHz(7.5ns) 3-3-3 @CL2 100MHz(10ns) 2-2-2
Feature
Burst mode operation Auto & self refresh capability (8192 Cycles/64ms) LVTTL compatible inputs and outputs Single 3.3V 0.3V power supply MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8 & Full page) Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * Serial presence detect with EEPROM * * * * *
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
PIN CONFIGURATIONS (Front side/back side)
Pin 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 DQ8 VSS DQ9 DQ10 DQ11 DQ12 DQ13 VDD DQ14 DQ15 CB0 CB1 VSS NC NC VDD WE DQM0 Pin 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Front DQM1 **CS0 DU VSS A0 A2 A4 A6 A8 A10/AP BA1 VDD VDD **CLK0 VSS DU **CS2 DQM2 DQM3 DU VDD NC NC CB2 CB3 VSS DQ16 DQ17 Pin 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 Front DQ18 DQ19 VDD DQ20 NC *VREF **CKE1 VSS DQ21 DQ22 DQ23 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS **CLK2 NC NC SDA SCL VDD Pin 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 101 102 103 104 105 106 107 108 109 110 111 112 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 DQ40 VSS DQ41 DQ42 DQ43 DQ44 DQ45 VDD DQ46 DQ47 CB4 CB5 VSS NC NC VDD CAS DQM4 Pin 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 Back DQM5 **CS1 RAS VSS A1 A3 A5 A7 A9 BA0 A11 VDD **CLK1 A12 VSS **CKE0 **CS3 DQM6 DQM7 *A13 VDD NC NC CB6 CB7 VSS DQ48 DQ49 Pin 141 142 143 144 145 146 147 148 149 150 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168
SDRAM
Back DQ50 DQ51 VDD DQ52 NC *VREF REGE VSS DQ53 DQ54 DQ55 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS **CLK3 NC SA0 SA1 SA2 VDD
Note : 1. * These pins are not used in this module.
2. Pins 82,83,165,166,167 should be NC in the system which does not support SPD. 3. ** About these pins, Refer to the Block Diagram of each.
Pin Description
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 CB0 ~ CB7 CLK0 ~ 3 CKE0, CKE1 CS0 ~ CS3 RAS CAS WE Select bank Data input/output Check bit (Data-in/data-out) Clock input Clock enable input Chip select input Row address strobe Colume address strobe Write enable Function Address input (Multiplexed) VDD VSS *VREF REGE SDA SCL SA0 ~ 2 DU NC Pin Name DQM0 ~ 7 DQM Power supply (3.3V) Ground Power supply for reference Register enable Serial data I/O Serial clock Address in EEPROM Dont use No connection Function
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs.
SDRAM
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tss prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12 Column address : (x4 : CA0 ~ CA9, CA11), (x8 : CA0 ~ CA9) Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) The device operates in the transparent mode when REGE is low. When REGE is high, the device operates in the registered mode. In registered mode, the Address and control inputs are latched if CLK is held at a high or low logic level. the inputs are stored in the latch/flip-flop on the rising edge of CLK. REGE is tied to VDD through 10K ohm Resistor on PCB. So if REGE of module is floating, this module will be operated as registered mode. Data inputs/outputs are multiplexed on the same pins. Check bits for ECC. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A12
Address
BA0 ~ BA1 RAS CAS WE DQM0 ~ 7
Bank select address Row address strobe Column address strobe Write enable Data input/output mask
REGE
Register enable
DQ0 ~ 63 CB0 ~ 7 VDD/VSS
Data input/output Check bit Power supply/ground
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
SDRAM
256MB, 32Mx72 ECC Module (M390S3253ET1) (Populated as 1 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM
PCLK0 BCS0 BCKE0 B0A0~B0A12,BBA0~1,BRAS,BCAS,BWE BDQM0 DQ0~7
10
* *
*
CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7
D0
* *
DQ8~15
10
*
D1
PCLK1
* * * * *
*
D2
BDQM1 CB0~7
10
BCS2 BDQM2 DQ16~23
10
*
CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7
D3
PCLK3
* *
*
D4
BDQM3 DQ24~31
10
*
DQ32~39 BDQM4
10
*
D5
D6
*
BDQM5 DQ40~47
10
* *
*
BDQM6 DQ48~55
10
CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7
D7
D8
BDQM7 DQ56~63
10
VSS VDD
A0~A9 RAS,CAS,WE DQM0,1,4,5 CS0 REGE PCLK2
10k
74ALVCF162835
B0A0~B0A9
CLK1,2,3
10 12pF 10 CLK0 12pF
2G AGND 1G AVCL
BRAS,BCAS,BWE BDQM0,1,4,5 BCS0 LE
OE
CDCF2509 CLK FIBIN
Cb*1
1Y0 1Y1 1Y2 1Y3 1Y4 2Y0 2Y1 2Y2 2Y3
PCLK0 PCLK1 PCLK2 PCLK3
FBOUT
VDD
A10,A11,A12,BA0~1 CS2 CKE0 DQM2,3,6,7
74ALVCF162835
Note 1. The actual values of Cb will depend upon the PLL chosen. B0A10,B0A11,B0A12,BBA0~1 BCS2 BCKE0 BDQM2,3,6,7
Serial PD SCL 47K
WP A0
A1
A2
SDA
LE
OE
SA0 SA1 SA2
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
SDRAM
256MB, 32Mx72 ECC Module (M390S3253ETU) (Populated as 1 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM
PCLK0 BCS0 BCKE0 B0A0~B0A12,BBA0~1,BRAS,BCAS,BWE BDQM0 DQ0~7
10
* *
*
CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7
D0
PCLK1
* *
*
D1
DQ8~15
10
PCLK2
*
BDQM1 CB0~7
10
*
D2
* * * *
PCLK3 BCS2 BDQM2 DQ16~23
10
CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7
D3
PCLK4
* *
*
D4
BDQM3 DQ24~31
10
*
DQ32~39 BDQM4
10
*
D5
D6
*
BDQM5 DQ40~47
10
*
BDQM6 DQ48~55
10
*
CLK CS CKE Add,CTL DQM DQ0~7 CLK CS CKE Add,CTL DQM DQ0~7
D7
D8
BDQM7 DQ56~63
10
VSS VDD
A0~A6,BA0~1 RAS,CAS,WE DQM0,1,4,5 CS0 REGE PCLK2
10k
74ALVCF162835
B0A0~B0A6
CLK1,2,3
10 12pF 10 CLK0 12pF
2G AGND 1G AVCL
BRAS,BCAS,BWE BDQM0,1,4,5 BCS0 LE
OE
CDCF2509 CLK FIBIN
Cb*1
1Y0 1Y1 1Y2 1Y3 1Y4 2Y0 2Y1 2Y2 2Y3
PCLK4 PCLK5 PCLK0 PCLK1 PCLK2 PCLK3
FBOUT
VDD
Note 1. The actual values of Cb will depend upon the PLL chosen. 74ALVCF162835 B0A7~B0A12,BBA0~BBA1 BCS2 BCKE0 BDQM2,3,6,7
A7~A12,BA0~1 CS2 CKE0 DQM2,3,6,7
Serial PD SCL
47K
WP A0
A1
A2
SDA
LE
OE
SA0 SA1 SA2
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
SDRAM
512MB 64Mx72 ECC Module (M390S6450ET1) (Populated as 1 bank of x4 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM
PCLK0 BCS0 B0CKE0 B0A0~B0A12,B0BA0,B0BA1,B0RAS,B0CAS,B0WE BDQM0 DQ0~3
10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D0
B1CKE0 BDQM4 DQ32~35
10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D9
D1
10
D10
DQ4~7
10
DQ36~39
PCLK1
D2
BDQM5 DQ40~43
10
D11
BDQM1 DQ8~11
10
PCLK2
D3
10
D12
DQ12~15
10
DQ44~47
D4
10
D13
CB0~3
10
CB4~7
PCLK3 BCS2
DQ16~19
10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D5
DQ48~51
10
D14
PCLK4
D6
BDQM6 DQ52~55
10
BDQM2 DQ20~23
10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D15
D7
DQ56~59
10
D16
DQ24~27
10
PCLK5
B1A0~B1A12,B1BA0,B1BA1,B1RAS,B1CAS,B1WE BDQM3 DQ28~31
10
CLK CS CKE Add,CTL DQM DQ0~3
D8
BDQM7 DQ60~63
10 VSS
CLK CS CKE Add,CTL DQM DQ0~3
D17
VDD
74ALVCF162835
VDD 10k
10 CLK1,2,3 12pF 10 CLK0
2G AGND 1G AVCL
A3~A10,BA0
B0A3~B0A10,B0BA0 B1A3~B1A10,B1BA0
CDCF2510 LE
OE
PCLK6 REGE A11,A12,BA1 CS2 CKE0 DQM2,3,6,7
74ALVCF162835
LE A0,A1,A2 RAS,CAS,WE CS0 DQM0,1,4,5 LE
OE
B0A11.B0A12.B0BA1 B1A11.B1A12.B1BA1 BCS2 B0CKE0 B1CKE0 BDQM2,3,6,7 B0A0,B0A1,B0A2 B1A0,B1A1,B1A2 B0RAS, B0CAS, B0WE B1RAS, B1CAS, B1WE BCS0 BDQM0,1,4,5
12pF
CLK FIBIN
Cb*1
IY0 IY1 IY2 IY3 IY4 2Y0 2Y1
PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6
FBOU
Note 1. The actual values of Cb will depend upon the PLL chosen.
74ALVCF162835
Serial PD SCL 47K
WP A0
A1
A2
SDA
OE
SA0 SA1 SA2
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
SDRAM
512MB 64Mx72 ECC Module (M390S6450ETU) (Populated as 1 bank of x4 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM
PCLK0 BCS0 B0CKE0 B0A0~B0A12,B0BA0~1, B0RAS, B0CAS, B0WE BDQM0 DQ0~3
10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D0
BDQM4
10
DQ32~35
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D9
PCLK1
D1
10
D10
DQ4~7
10
DQ36~39
PCLK2
D2
BDQM5 DQ40~43
10
D11
BDQM1 DQ8~11
10
PCLK3
D3
10
D12
DQ12~15
10
DQ44~47
PCLK4
D4
10
D13
CB0~3
10
CB4~7
PCLK5 BCS2 BDQM2 DQ16~19
10
D5
BDQM6 DQ48~51
10
D14
PCLK6
D6
D15
DQ20~23
10
DQ52~55
10
PCLK7
D7
BDQM7 DQ56~59
10
D16
BDQM3 DQ24~27
10
PCLK8 BCS2 B1CKE0 B1A0~B1A12,B1BA0~1, B1RAS, B1CAS, B1WE DQ28~31
10
D8
D17
DQ60~63
10 VSS
VDD 10k
10 12pF
PCLK9 REGE
LE
OE 10
74ALVCF162835
B1A0~B1A12,B1BA0~1, B1RAS, B1CAS CLK0
12pF
2G AGND 1G AVCL
A0~A12,BA0~1, RAS, CAS CKE0
74ALVCF162835
B0A0~B0A12,B0BA0~1, B0RAS, B0CAS B0CKE0 B1CKE0 CLK1,2,3
VDD
IY0 IY1 IY2 IY3 IY4 IY5 IY6 IY7 IY8 IY9 PCLK9 PCLK5 PCLK6 PCLK7 PCLK8 PCLK0 PCLK1 PCLK2 PCLK3 PCLK4
CDCF2510
CLK FIBIN Cb*1
FBOUT
LE
OE
Note 1. The actual values of Cb will depend upon the PLL chosen.
74ALVCF162835 WE DQM0~7,CS0,CS2 LE
OE
Serial PD
B0WE B1WE BDQM0~7, BCS0,BCS2
SCL
47K
WP A0
A1
A2
SDA
SA0 SA1 SA2
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
SDRAM
512MB, 64Mx72 ECC Module (M390S6453ET1) (Populated as 2 bank of x8 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM
PCLK0 BCS0 B0CKE0 B0A0~B0A12,B0BA0,B0BA1,B0RAS,B0CAS,B0WE BDQM0 DQ0~3
10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D0
B1CKE0 BDQM4 DQ32~35
10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D9
D1
10
D10
DQ4~7
10
DQ36~39
PCLK1
D2
BDQM5 DQ40~43
10
D11
BDQM1 DQ8~11
10
PCLK2
D3
10
D12
DQ12~15
10
DQ44~47
D4
10
D13
CB0~3
10
CB4~7
PCLK3 BCS2
DQ16~19
10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D5
DQ48~51
10
D14
PCLK4
D6
BDQM6 DQ52~55
10
BDQM2 DQ20~23
10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D15
D7
DQ56~59
10
D16
DQ24~27
10
PCLK5 B1A0~B1A12,B1BA0,B1BA1,B1RAS,B1CAS,B1WE BDQM3 DQ28~31
10
CLK CS CKE Add,CTL DQM DQ0~3
D8
BDQM7 DQ60~63
10 VSS
CLK CS CKE Add,CTL DQM DQ0~3
D17
VDD
74ALVCF162835
VDD 10k
10 CLK1,2,3 12pF 10 CLK0
2G AGND 1G AVCL
A3~A10,BA0
B0A3~B0A10,B0BA0 B1A3~B1A10,B1BA0
IY0 IY1 IY2 IY3 IY4
PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6
CDCF2510 LE
OE
PCLK6 REGE A11,A12,BA1 CS2 CKE0 DQM2,3,6,7
2Y0
74ALVCF162835
LE A0,A1,A2 RAS,CAS,WE CS0 DQM0,1,4,5 LE
OE
B0A11.B0A12.B0BA1 B1A11.B1A12.B1BA1 BCS2 B0CKE0 B1CKE0 BDQM2,3,6,7 B0A0,B0A1,B0A2 B1A0,B1A1,B1A2 B0RAS, B0CAS, B0WE B1RAS, B1CAS, B1WE BCS0 BDQM0,1,4,5
12pF
CLK FIBIN
Cb*1
FBOUT
2Y1
Note 1. The actual values of Cb will depend upon the PLL chosen.
74ALVCF162835
Serial PD SCL 47K
WP A0
A1
A2
SDA
OE
SA0 SA1 SA2
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
SDRAM
1GB, 128Mx72 ECC Module (M390S2858ET1) (Populated as 2 bank of x4 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM
BCS1,B2CKE0 BCS0,B0CKE0
PCLK0 B0RAS,B0CAS,B0WE,B0BA0,B0BA1
B0A0~B0A12
BDQM0
DQ0~3 10 PCLK1
CLK CS1,CKED0L CTL Add DQM DQ0~3 CLK CS1,CKED1L CTL Add DQM DQ0~3 CLK CS1,CKED2L CTL Add DQM DQ0~3 CLK CS1,CKED3L CTL Add DQM DQ0~3 CLK CS1,CKED4L CTL Add DQM DQ0~3
CLK CS0,CKED0U CTL Add DQM DQ0~3 CLK CS0,CKED1U CTL Add DQM DQ0~3 CLK CS0,CKED2U CTL Add DQM DQ0~3 CLK CS0,CKED3U CTL Add DQM DQ0~3 CLK CS0,CKED4U CTL Add DQM DQ0~3
BDQM4 DQ32~35 10
CLK CS0,CKE D9L CTL Add DQM DQ0~3 CLK CS0,CKE D10L CTL Add DQM DQ0~3 CLK CS0,CKED11L CTL Add DQM DQ0~3 CLK CS0,CKE D12L CTL Add DQM DQ0~3 CLK CS0,CKE D13L CTL Add DQM DQ0~3
CLK CS1,CKED9U CTL Add DQM DQ0~3 CLK D10U CS1,CKE CTL Add DQM DQ0~3 CLK D11U CS1,CKE CTL Add DQM DQ0~3 CLK D12U CS1,CKE CTL Add DQM DQ0~3 CLK CS1,CKED13U CTL Add DQM DQ0~3
DQ4~7 10 PCLK2
DQ36~39 10
BDQM1 DQ8~11 10 PCLK3
BDQM5 DQ40~43 10
DQ12~15 10 PCLK4
DQ44~47 10
CB0~3 10 BCS3,B3CKE0 BCS2,B1CKE0
CB4~7 10
PCLK5
BDQM2
DQ16~19 10 PCLK6
CLK CS1,CKED5L CTL Add DQM DQ0~3 CLK CS1 CTL Add DQM DQ0~3
CLK CS0,CKED5U CTL Add DQM DQ0~3 CLK CS0,CKED6U CTL Add DQM DQ0~3 CLK CS0,CKED7U CTL Add DQM DQ0~3 CLK CS0,CKED8U CTL Add DQM DQ0~3
BDQM6 DQ48~51 10
CLK CS0,CKE D14L CTL Add DQM DQ0~3 CLK CS0,CKE D15L CTL Add DQM DQ0~3 CLK D16L CS0,CKE CTL Add DQM DQ0~3 CLK CS0,CKE D17L CTL Add DQM DQ0~3
VSS
CLK D14U CS1,CKE CTL Add DQM DQ0~3 CLK CS1,CKED15U CTL Add DQM DQ0~3 CLK D16U CS1,CKE CTL Add DQM DQ0~3 CLK D17U CS1,CKE CTL Add DQM DQ0~3
D6L
DQ20~23 10 PCLK7
DQ52~55 10
BDQM3 DQ24~27 10 PCLK8
CLK CS1,CKED7L CTL Add DQM DQ0~3 CLK CS1,CKED8L CTL Add DQM DQ0~3
BDQM7 DQ56~59 10
B1RAS,B1CAS,B1WE,B1BA0,B1BA1
B1A0~B1A12 DQ28~31 10
DQ60~63 10
VDD
IY0 IY1 IY2 IY3 IY4 IY5 IY6 IY7 IY8 PCLK0 PCLK1 PCLK2 PCLK3 PCLK4 PCLK5 PCLK6 PCLK7 PCLK8 PCLK9
74ALVCF162835
VDD 10k
CLK1,2,3 12pF
PCLK9 REGE
A11,A12,BA1
LE
OE B0A11,B0A12.B0BA1 B1A11,B1A12.B1BA1
10 CLK0 12pF
CLK FBIN
Cb
*1
G AGND AVDD CDCF2510
A3~A10,BA0
B0A3~B0A10,B0BA0 B1A3~B1A10,B1BA0
10
FBOU
74ALVCF162835 CS2,CS3 CKE0 DQM2,3,6,7 LE A0,A1,A2 74ALVCF162835 RAS,CAS,WE CS0,CS1 DQM0,1,4,5 LE
OE OE
BCS2,BCS3 B0CKE0,B1CKE0 B2CKE0,B3CKE0 BDQM2,3,6,7 B0A0,B0A1,B0A2 B1A0,B1A1,B1A2 B0RAS, B0CAS, B0WE B1RAS, B1CAS, B1WE BCS0,BCS1 BDQM0,1,4,5
Note 1. The actual values of Cb will depend upon the PLL chosen.
Serial PD SCL 47K
WP A0
A1
A2
SDA
SA0 SA1 SA2
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
SDRAM
1GB, 128Mx72 ECC Module (M390S2858ETU) (Populated as 2 bank of x4 SDRAM Module) FUNCTIONAL BLOCK DIAGRAM
BCS1 PCLK0 BCS0 B0CKE0 B0A0~B0A12,B0BA0~1, B0RAS, B0CAS, B0WE BDQM0 DQ0~3
10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D0L
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D0U
BDQM4 DQ32~35
10
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D9L
CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3 CLK CS CKE Add,CTL DQM DQ0~3
D9
PCLK1
D1L
D1U
10
D10L
D10
DQ4~7
10
DQ36~39
PCLK2
D2L
D2U
BDQM5 DQ40~43
10
D11L
D11
BDQM1 DQ8~11
10
PCLK3
D3L
D3U
10
D12L
D12
DQ12~15
10
DQ44~47
PCLK4
D4L
D4U
10
D13L
D13
CB0~3
10
CB4~7
PCLK5 BCS2 BDQM2 DQ16~19
10
D5L
D5U
BDQM6 DQ48~51
10
D14L
D14
PCLK6
D6L
D6U
D15L
D15
DQ20~23
10
DQ52~55
10
PCLK7
D7L
D7U
BDQM7 DQ56~59
10
D16L
D16
BDQM3 DQ24~27
10
PCLK8 BCS2 B1CKE0 B1A0~B1A12,B1BA0~1, B1RAS, B1CAS, B1WE BDQM0 DQ28~31
BCS3
D8L
D8U
BDQM7 DQ60~63
10
D17L
D17
10
VSS
VDD 10k
10 12pF
PCLK9 REGE
LE
OE 10
74ALVCF162835
B1A0~B1A12,B1BA0~1, B1RAS, B1CAS CLK0
12pF
2G AGND 1G AVCL
A0~A12,BA0~1, RAS, CAS CKE0
74ALVCF162835
B0A0~B0A12,B0BA0~1, B0RAS, B0CAS B0CKE0 B1CKE0 CLK1,2,3
VDD
IY0 IY1 IY2 IY3 IY4 IY5 IY6 IY7 IY8 IY9 PCLK9 PCLK5 PCLK6 PCLK7 PCLK8 PCLK0 PCLK1 PCLK2 PCLK3 PCLK4
CDCF2510
CLK FIBIN Cb*1
FBOUT
LE
OE
Note 1. The actual values of Cb will depend upon the PLL chosen.
74ALVCF162835 WE DQM0~7,CS0~3 LE
OE
Serial PD
B0WE,B0CKE1 B1WE,B1CKE1 BDQM0~7, BCS0~3
SCL
47K
WP A0
A1
A2
SDA
SA0 SA1 SA2
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
STANDARD TIMING DIAGRAM WITH PLL & REGISTER (CL=2, BL=4)
SDRAM
*2 *1
Control Signal(RAS,CAS,WE) REG
*3 DOUT
8 9 10 11 12 13 14 15 16 17 18 19
*1. Register Input
0 CLK 1 2 3 4 5 6 7
RAS CAS WE
*2. Register Output
RAS
td tr td tr
CAS WE
*3. SDRAM
CAS latency(refer to *1) =2CLK+1CLK tSAC tRAC(refer to *1)
1CLK
DQ
tRAC(refer to *2)
Qa0
Qa1
Qa2
Qa3
Db0
Db1
Db2
Db3
CAS latency(refer to *2) =2CLK
tRDL
Row Active
Read Command
Precharge Command
Row Active
Write Command
Precharge Command
td, tr = Delay of register
Notes : 1. In case of module timing, command cycles delayed 1CLK with respect to external input timing at the address and input signal because of the buffering in register. Therefore, Input/Output signals of read/write function should be issued 1CLK earlier as compared to Unbuffered DIMMs. 2. DIN is to be issued 1clock after write command in external timing because DIN is issued directly to module.
: Dont care
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1.0 * # of component 50
SDRAM
Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Symbol VDD VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE(Max.)
Parameter Input capacitance (A0 ~ A11)
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200 mV) Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 CIN7 COUT1 COUT2 M390S3253ET1 M390S3253ETU 15 15 15 23 15 15 15 16 16 M390S6450ET1 M390S6450ETU 15 15 15 20 15 15 15 16 16 M390S6453ET1 19 19 33 12 12 12 12 19 19 M390S2858ET1 M390S2858ETU 15 15 15 20 15 15 15 22 22 Unit pF pF pF pF pF pF pF pF pF
Input capacitance (RAS, CAS, WE) Input capacitance (CKE0) Input capacitance (CLK0) Input capacitance (CS0, CS2) Input capacitance (DQM0 ~ DQM7) Input capacitance (BA0 ~ BA1) Data input/output capacitance(DQ0~DQ63) Data input/ouput capacitance (CB0~CB7)
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
DC CHARACTERISTICS M390S3253ETU(1) (32M x 72, 256MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Operating current (Burst mode) Refresh current Self refresh current Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V Version 7A 1,220 370 20 530 mA 95 405 60 575 230 mA mA mA
SDRAM
Unit mA mA
Note 1
ICC4 ICC5 ICC6
1,400 2,120 380
mA mA mA
1 2
M390S6450ETU(1) (64M x 72, 512MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Operating current (Burst mode) Refresh current Self refresh current Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V Version 7A 1,940 370 40 710 mA 185 460 110 800 455 mA mA mA Unit mA mA Note 1
ICC4 ICC5 ICC6
2,300 3,740 405
mA mA mA
1 2
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
DC CHARACTERISTICS M390S6453ET1 (64M x 72, 512MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Operating current (Burst mode) Refresh current Self refresh current Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V Version 7A 1,445 390 40 710
SDRAM
Unit mA mA
Note 1
mA 185 460 110 800 455 mA mA mA
ICC4 ICC5 ICC6
1,625 2,345 405
mA mA mA
1 2
M390S2858ETU(1) (128M x 72, 1GB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Parameter Operating current (One bank active) Precharge standby current in power-down mode Precharge standby current in non power-down mode Active standby current in power-down mode Active standby current in non power-down mode (One bank active) Operating current (Burst mode) Refresh current Self refresh current Symbol ICC1 ICC2P ICC2PS ICC2N ICC2NS ICC3P ICC3PS ICC3N ICC3NS Test Condition Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V Version 7A 2,390 425 75 1,070 mA 365 570 220 1,250 905 mA mA mA Unit mA mA Note 1
ICC4 ICC5 ICC6
2,750 4,190 460
mA mA mA
1 2
Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. 3. Unless otherwise noted, input swing level is CMOS(VIH/VIL=VDDQ/VSSQ)
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
SDRAM
Unit V V ns V
3.3V
Vtt = 1.4V
1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 Version 7A 15 20 20 45 100 65 2 2 CLK + tRP 1 1 1 2 1 ns ns ns ns us ns CLK CLK CLK CLK ea 1 2,5 5 2 2 3 4 1 1 1 1 Unit Note
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop. 5. In 100MHz and below 100MHz operating conditions, tRDL=1CLK and tDAL=1CLK + 20ns is also supported. SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + tRP.
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter CLK cycle time CLK to valid output delay Output data hold time CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 tCH tCL tSS tSH tSLZ tSHZ tOH 3 3 2.5 2.5 1.5 0.8 1 5.4 6 ns ns ns ns ns ns tSAC Symbol Min tCC 7.5 10 5.4 6 ns ns 7A Max 1000 ns Unit
SDRAM
Note
1
1,2
2 3 3 3 3 2
CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit L H H
CKEn-1 CKEn CS RAS CAS
SDRAM
(V=Valid, X=Dont care, H=Logic high, L=Logic low)
WE DQM BA0,1 A10/AP A0 ~ A9, A11, A12 Note
H H
X H L H X X
L L L H
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3
X X X V V
X Row address L H
Column address
3 3
Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection All banks Clock suspend or active power down Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
L L
4 4,5 4 4,5 6
H H H
X X X
L L L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
L H X
Column address
V X
L H
X
H L H
L H L
X X X X X X V X X 7
X H L
L H H
H
H L
X
H L
X H
X H
X H
X
Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
PACKAGE DIMENSIONS : 32Mx72 (M390S3253ET1)
SDRAM
Units : Inches (Millimeters)
5.250 (133.350) 0.118 (3.000) 5.014 (127.350)
0.054 (1.372) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100)
1.500 (38.1)
0.118 (3.000)
REG
PLL
REG
.118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890)
0.250 (6.350) .450 (11.430) 1.450 (36.830)
0.250 (6.350) 2.150 (54.61) 4.550 (115.57)
0.0984 0.008 (2.500 0.2)
A
B
C
0.700 (17.780)
0.150 Max (3.81 Max)
(3.99 Min)
0.157 Min
0.050 0.0039 (1.270 0.10) 0.0984 0.008 (2.500 0.2)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270)
Detail A
Detail B
Detail C
Tolerances : 0.005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E This module is based on JEDEC PC133 Specification
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
PACKAGE DIMENSIONS : 32Mx72 (M390S3253ETU)
SDRAM
Units : Inches (Millimeters)
5.250 (133.350) 0.118 (3.000) 5.014 (127.350)
PLL
0.054 (1.372)
R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 0.700 (17.780)
1.200 (38.1)
0.118 (3.000)
REG
REG
.118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890)
0.250 (6.350) .450 (11.430) 1.450 (36.830)
0.250 (6.350) 2.150 (54.61) 4.550 (115.57)
0.0984 0.008 (2.500 0.2 )
A
B
C
0.150 Max (3.81 Max)
(3.99 Min)
0.157 Min
0.050 0.0039 (1.270 0.10) 0.0984 0.008 (2.500 0.2)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270)
Detail A
Detail B
Detail C
Tolerances : 0.005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E This module is based on JEDEC PC133 Specification
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
PACKAGE DIMENSIONS : 64Mx72 (M390S6450ET1)
SDRAM
Units : Inches (Millimeters)
5.250 (133.350) 0.118 (3.000) 5.014 (127.350)
0.054 (1.372) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100)
1.700 (43.18)
0.118 (3.000)
REG
REG
PLL
.118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890)
0.250 (6.350) .450 (11.430) 1.450 (36.830)
0.250 (6.350) 2.150 (54.61) 4.550 (115.57)
0.0984 0.008 (2.500 0.2)
A
B
C
0.700 (17.780)
0.150 Max (3.81 Max)
REG
(4.19 Min)
0.165 Min
0.050 0.0039 (1.270 0.10) 0.0984 0.008 (2.500 0.2)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270)
Detail A
Detail B
Detail C
Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx4 SDRAM, TSOPII SDRAM Part No. : K4S560432E This module is based on JEDEC PC133 Specification
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
PACKAGE DIMENSIONS : 64Mx72 (M390S6450ETU)
SDRAM
Units : Inches (Millimeters)
5.250 (133.350) 0.118 (3.000) 5.014 (127.350)
PLL
0.054 (1.372)
R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 0.700 (17.780)
1.200 (30.48)
0.118 (3.000)
REG REG
.118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890)
0.250 (6.350) .450 (11.430) 1.450 (36.830)
0.250 (6.350) 2.150 (54.61) 4.550 (115.57)
0.0984 0.008 (2.500 0.2)
A
B
C
0.150 Max (3.81 Max) 0.157 Min (3.99 Min)
REG
0.050 0.0039 (1.270 0.10)
0.0984 0.008
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
(2.500 0.2)
0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270)
Detail A
Detail B
Detail C
Tolerances : 0.005(.13) unless otherwise specified The used device is 64Mx4 SDRAM, TSOPII SDRAM Part No. : K4S560432E This module is based on JEDEC PC133 Specification
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
PACKAGE DIMENSIONS : 64Mx72 (M390S6453ET1)
SDRAM
Units : Inches (Millimeters)
5.250 (133.350) 0.118 (3.000) 5.014 (127.350)
0.054 (1.372) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100)
1.700 (43.18)
0.118 (3.000)
REG
REG
PLL
.118DIA +0.004/-0.000 (3.000DIA +0.100/-0.000) 0.350 (8.890)
0.250 (6.350) .450 (11.430) 1.450 (36.830)
0.250 (6.350) 2.150 (54.61) 4.550 (115.57)
0.0984 0.008 (2.500 0.2)
A
B
C
0.700 (17.780)
0.150 Max (3.81 Max)
REG
(4.19 Min)
0.165 Min
0.050 0.0039 (1.270 0.10) 0.0984 0.008 (2.500 0.2)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270)
Detail A
Detail B
Detail C
Tolerances : 0.005(.13) unless otherwise specified The used device is 32Mx8 SDRAM, TSOPII SDRAM Part No. : K4S560832E This module is based on JEDEC PC133 Specification
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
PACKAGE DIMENSIONS : 128Mx72 (M390S2858ET1)
SDRAM
Units : Inches (Millimeters)
5.250 (133.350) 0.118 (3.000) 5.014 (127.350)
0.054 (1.372) R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100)
1.700 (43.18)
0.118 (3.000)
REG
REG
PLL
.118DIA 0.004 (3.000DIA 0.100) 0.350 (8.890)
A 0.250 (6.350) .450 (11.430) 1.450 (36.830)
B 0.250 (6.350)
C
2.150 (54.61) 4.550 (115.57)
0.100 Min (2.540 Min)
0.700 (17.780)
0.254 Max (6.452 Max)
REG
(3.99 Min)
0.157 Min
0.050 0.0039 (1.270 0.10)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
(2.540 Min)
0.100 Min
0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270)
Detail A Tolerances : 0.005(.13) unless otherwise specified
Detail B
Detail C
SDRAM Part No. : K4S510632E - The used device is stacked 128Mx4 SDRAM, TSOPII - Staktek's stacking technology is Samsung's stacking technology of choice This module is based on JEDEC PC133 Specification
Rev. 1.4 May 2004
256MB, 512MB, 1GB Registered DIMM
PACKAGE DIMENSIONS : 128Mx72 (M390S2858ETU)
SDRAM
Units : Inches (Millimeters)
5.250 (133.350) 0.118 (3.000) 5.014 (127.350)
PLL
0.054 (1.372)
R 0.079 (R 2.000) 0.157 0.004 (4.000 0.100) 0.700 (17.780)
1.200 (30.48)
0.118 (3.000)
REG REG
.118DIA 0.004 (3.000DIA 0.100) 0.350 (8.890)
A 0.250 (6.350) .450 (11.430) 1.450 (36.830)
B 0.250 (6.350)
C
2.150 (54.61) 4.550 (115.57)
0.100 Min (2.540 Min)
0.254 Max (6.452 Max)
REG
(3.99 Min)
0.157 Min
0.050 0.0039 (1.270 0.10)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
0.250 (6.350) 0.123 0.005 (3.125 0.125) 0.079 0.004 (2.000 0.100)
(2.540 Min)
0.100 Min
0.039 0.002 (1.000 0.050) 0.008 0.006 (0.200 0.150) 0.050 (1.270)
Detail A Tolerances : 0.005(.13) unless otherwise specified
Detail B
Detail C
SDRAM Part No. : K4S510632E - The used device is stacked 128Mx4 SDRAM, TSOPII - Staktek's stacking technology is Samsung's stacking technology of choice This module is based on JEDEC PC133 Specification
Rev. 1.4 May 2004

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