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256MB, 512MB Unbuffered SODIMM
SDRAM
SDRAM Unbuffered SODIMM
144pin Unbuffered SODIMM based on 512Mb B-die 64-bit Non ECC
Revision 1.2 March 2004
* Samsung Electronics reserves the right to change products or specification without notice.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
Revision History
Revision 1.0 (January, 2004) - First release Revision 1.1 (February, 2004) - Corrected typo. Revision 1.2 (March. 2004) - Corrected package dimension.
SDRAM
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
144Pin Unbuffered SODIMM based on 512Mb B-die(x8, x16)
Ordering Information
Part Number M464S3354BTS-C(L)7A M464S6554BTS-C(L)7A Density 256MB 512MB Organization 32M x 64 64M x 64 Component Composition 32Mx16(K4S511632B) * 4EA 32Mx16(K4S511632B) * 8EA Component Package 54-TSOP(II)
SDRAM
Height 1,000mil 1,250mil
Operating Frequencies
7A @CL3 Maximum Clock Frequency CL-tRCD-tRP(clock) 133MHz(7.5ns) 3-3-3 @CL2 100MHz(10ns) 2-2-2
Feature
* Burst mode operation * Auto & self refresh capability (8192 Cycles/64ms) * LVTTL compatible inputs and outputs * Single 3.3V 0.3V power supply * MRS cycle with address key programs Latency (Access from column address) Burst length (1, 2, 4, 8) Data scramble (Sequential & Interleave) * All inputs are sampled at the positive going edge of the system clock * Serial presence detect with EEPROM
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
PIN CONFIGURATIONS (Front side/back side)
Pin 1 3 5 7 9 11 13 15 17 19 21 23 25 27 29 31 33 35 37 39 41 43 45 47 49 Front VSS DQ0 DQ1 DQ2 DQ3 VDD DQ4 DQ5 DQ6 DQ7 VSS DQM0 DQM1 VDD A0 A1 A2 VSS DQ8 DQ9 DQ10 DQ11 VDD DQ12 DQ13 Pin 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 46 48 50 Back VSS DQ32 DQ33 DQ34 DQ35 VDD DQ36 DQ37 DQ38 DQ39 VSS DQM4 DQM5 VDD A3 A4 A5 VSS DQ40 DQ41 DQ42 DQ43 VDD DQ44 DQ45 Pin 51 53 55 57 59 Front DQ14 DQ15 VSS NC NC Pin 52 54 56 58 60 Back DQ46 DQ47 VSS NC NC Pin 95 97 99 101 103 105 107 109 111 113 115 117 119 121 123 125 127 129 131 133 135 137 139 141 143 Front DQ21 DQ22 DQ23 VDD A6 A8 VSS A9 A10/AP VDD DQM2 DQM3 VSS DQ24 DQ25 DQ26 DQ27 VDD DQ28 DQ29 DQ30 DQ31 VSS SDA VDD Pin 96 98 100 102 104 106 108 110 112 114 116 118 120 122 124 126 128 130 132 134 136 138 140 142 144
SDRAM
Back DQ53 DQ54 DQ55 VDD A7 BA0 VSS BA1 A11 VDD DQM6 DQM7 VSS DQ56 DQ57 DQ58 DQ59 VDD DQ60 DQ61 DQ62 DQ63 VSS SCL VDD
Voltage Key
61 63 65 67 69 71 73 75 77 79 81 83 85 87 89 91 93 **CLK0 VDD RAS WE **CS0 **CS1 DU VSS NC NC VDD DQ16 DQ17 DQ18 DQ19 VSS DQ20 62 64 66 68 70 72 74 76 78 80 82 84 86 88 90 92 94 **CKE0 VDD CAS **CKE1 A12 *A13 **CLK1 VSS NC NC VDD DQ48 DQ49 DQ50 DQ51 VSS DQ52
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
Pin Description
Pin Name A0 ~ A12 BA0 ~ BA1 DQ0 ~ DQ63 CLK0 ~ CLK1 CKE0 ~ CKE1 CS0 ~ CS1 RAS CAS Select bank Data input/output Clock input Clock enable input Chip select input Row address strobe Column address strobe Function Address input (Multiplexed) WE DQM0 ~ 7 VDD VSS SDA SCL DU NC Pin Name Write enable DQM Power supply (3.3V) Ground Serial data I/O Serial clock Dont use No connection Function
* SAMSUNG ELECTRONICS CO., Ltd. reserves the right to change products and specifications without notice.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
PIN CONFIGURATION DESCRIPTION
Pin CLK CS Name System clock Chip select Input Function Active on the positive going edge to sample all inputs.
SDRAM
Disables or enables device operation by masking or enabling all inputs except CLK, CKE and DQM Masks system clock to freeze operation from the next clock cycle. CKE should be enabled at least one cycle prior to new command. Disable input buffers for power down in standby. CKE should be enabled 1CLK+tSS prior to valid command. Row/column addresses are multiplexed on the same pins. Row address : RA0 ~ RA12 Column address : (x16 : CA0 ~ CA9) Selects bank to be activated during row address latch time. Selects bank for read/write during column address latch time. Latches row addresses on the positive going edge of the CLK with RAS low. Enables row access & precharge. Latches column addresses on the positive going edge of the CLK with CAS low. Enables column access. Enables write operation and row precharge. Latches data in starting from CAS, WE active. Makes data output Hi-Z, tSHZ after the clock and masks the output. Blocks data input when DQM active. (Byte masking) Data inputs/outputs are multiplexed on the same pins. Power and ground for the input buffers and the core logic.
CKE
Clock enable
A0 ~ A12
Address
BA0 ~ BA1 RAS CAS WE DQM0 ~ 7 DQ0 ~ 63 VDD/VSS
Bank select address Row address strobe Column address strobe Write enable Data input/output mask Data input/output Power supply/ground
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
256MB, 32Mx64 Module (M464S3354BTS) (Populated as 1 bank of x16 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
DQM0 CS0 LDQM CS DQ0 DQ1 DQ2 U0 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM5 DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47 DQM6 LDQM CS DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23 DQM3 DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
A0 ~ A12, BA0 & 1 RAS CAS WE CKE0 DQn VDD Vss 10
SDRAM
DQM4 DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39 LDQM CS DQ0 DQ1 DQ2 U2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 DQM1 DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15 DQM2
LDQM CS DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55 DQM7 DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
SCL 47K
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
U1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7 UDQM DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
Serial PD
WP SA0 SA1 SA2
U3
SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3 SDRAM U0 ~ U3 Every DQ pin of SDRAM CLK0
SDA
U0 U1 U2 U3 CLK1 10 10pF
Three 0.1uF X7R 0603Capacitors per each SDRAM
To all SDRAMs
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
512MB, 64Mx64 Module (M366S6554BTS) (Populated as 2 bank of x16 SDRAM Module)
FUNCTIONAL BLOCK DIAGRAM
CS1 CS0 DQM0 LDQM CS LDQM CS
SDRAM
DQM4 LDQM CS LDQM CS
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
DQM1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
UDQM
U0
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
UDQM
U4
DQ32 DQ33 DQ34 DQ35 DQ36 DQ37 DQ38 DQ39
DQM5
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
UDQM
U2
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
UDQM
U6
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQM2
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ40 DQ41 DQ42 DQ43 DQ44 DQ45 DQ46 DQ47
DQM6
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
LDQM
CS
LDQM
CS
LDQM
CS
LDQM
CS
DQ16 DQ17 DQ18 DQ19 DQ20 DQ21 DQ22 DQ23
DQM3
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
UDQM
U1
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
UDQM
U5
DQ48 DQ49 DQ50 DQ51 DQ52 DQ53 DQ54 DQ55
DQM7
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
UDQM
U3
DQ0 DQ1 DQ2 DQ3 DQ4 DQ5 DQ6 DQ7
UDQM
U7
DQ24 DQ25 DQ26 DQ27 DQ28 DQ29 DQ30 DQ31
A0 ~ A12, BA0 & 1 RAS CAS WE CKE0 CKE1 DQn VDD Vss
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U7 SDRAM U0 ~ U3 SDRAM U4 ~ U7
DQ56 DQ57 DQ58 DQ59 DQ60 DQ61 DQ62 DQ63
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
DQ8 DQ9 DQ10 DQ11 DQ12 DQ13 DQ14 DQ15
Serial PD SCL 47K
WP SA0 SA1 SA2
SDA
10
Every DQ pin of SDRAM CLK0/1
U0/U4 U1/U5 U2/U6 U3/U7
Three 0.1 uF X7R 0603 Capacitors per each SDRAM
To all SDRAMs
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
ABSOLUTE MAXIMUM RATINGS
Parameter Voltage on any pin relative to Vss Voltage on VDD supply relative to Vss Storage temperature Power dissipation Short circuit current Symbol VIN, VOUT VDD, VDDQ TSTG PD IOS Value -1.0 ~ 4.6 -1.0 ~ 4.6 -55 ~ +150 1.0 * # of component 50
SDRAM
Unit V V C W mA
Note : Permanent device damage may occur if "ABSOLUTE MAXIMUM RATINGS" are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability.
DC OPERATING CONDITIONS AND CHARACTERISTICS
Recommended operating conditions (Voltage referenced to VSS = 0V, TA = 0 to 70C) Parameter Supply voltage Input high voltage Input low voltage Output high voltage Output low voltage Input leakage current Symbol VDD VIH VIL VOH VOL ILI Min 3.0 2.0 -0.3 2.4 -10 Typ 3.3 3.0 0 Max 3.6 VDDQ+0.3 0.8 0.4 10 Unit V V V V V uA 1 2 IOH = -2mA IOL = 2mA 3 Note
Notes : 1. VIH (max) = 5.6V AC.The overshoot voltage duration is 3ns. 2. VIL (min) = -2.0V AC. The undershoot voltage duration is 3ns. 3. Any input 0V VIN VDDQ. Input leakage currents include Hi-Z output leakage for all bi-directional buffers with Tri-State outputs.
CAPACITANCE
(VDD = 3.3V, TA = 23C, f = 1MHz, VREF = 1.4V 200 mV) Parameter Symbol CIN1 CIN2 CIN3 CIN4 CIN5 CIN6 COUT M464S3354BTS Min 15 15 15 15 15 10 10 Max 25 25 25 21 25 12 12 M464S6454BTS Min 25 25 15 15 15 10 10 Max 45 45 25 21 25 12 12 pF pF pF pF pF pF pF Unit
Input capacitance (A0 ~ A12, BA0 ~ BA1) Input capacitance (RAS, CAS, WE) Input capacitance (CKE0 ~ CKE1) Input capacitance (CLK0 ~ CLK1) Input capacitance (CS0 ~ CS1) Input capacitance (DQM0 ~ DQM7) Data input/output capacitance (DQ0 ~ DQ63)
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
DC CHARACTERISTICS M464S3354BTS (32M x 64, 256MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Version Parameter Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. Test Condition 7A Operating current (One bank active) Precharge standby current in power-down mode ICC1 ICC2P ICC2PS ICC2N Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode ICC3P ICC3PS ICC3N ICC3NS 400 8
SDRAM
Unit
Note
mA
1
mA 8 80 mA 40 25 mA 25 120 100 mA mA
Active standby current in non power-down mode (One bank active)
Operating current (Burst mode) Refresh current Self refresh current
ICC4
520
mA
1
ICC5 ICC6
800 12 6
mA mA mA
2
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
DC CHARACTERISTICS M464S6554BTS (64M x 64, 512MB Module)
(Recommended operating condition unless otherwise noted, TA = 0 to 70C) Version Parameter Symbol Burst length = 1 tRC tRC(min) IO = 0 mA CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable CKE VIL(max), tCC = 10ns CKE & CLK VIL(max), tCC = CKE VIH(min), CS VIH(min), tCC = 10ns Input signals are changed one time during 20ns CKE VIH(min), CLK VIL(max), tCC = Input signals are stable IO = 0 mA Page burst 4Banks activated tCCD = 2CLKs tRC tRC(min) CKE 0.2V C L Notes : 1. Measured with outputs open. 2. Refresh period is 64ms. Test Condition 7A Operating current (One bank active) Precharge standby current in power-down mode ICC1 ICC2P ICC2PS ICC2N Precharge standby current in non power-down mode ICC2NS Active standby current in power-down mode ICC3P ICC3PS ICC3N ICC3NS 520 16
SDRAM
Unit
Note
mA
1
mA 16 160 mA 80 50 mA 50 240 200 mA mA
Active standby current in non power-down mode (One bank active)
Operating current (Burst mode) Refresh current Self refresh current
ICC4
640
mA
1
ICC5 ICC6
920 24 12
mA mA mA
2
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
AC OPERATING TEST CONDITIONS (VDD = 3.3V 0.3V, TA = 0 to 70C)
Parameter AC input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition Value 2.4/0.4 1.4 tr/tf = 1/1 1.4 See Fig. 2
SDRAM
Unit V V ns V
3.3V
Vtt = 1.4V
1200 Output 870 50pF VOH (DC) = 2.4V, IOH = -2mA VOL (DC) = 0.4V, IOL = 2mA Output Z0 = 50
50
50pF
(Fig. 1) DC output load circuit
(Fig. 2) AC output load circuit
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted) Parameter Row active to row active delay RAS to CAS delay Row precharge time Row active time Row cycle time Last data in to row precharge Last data in to Active delay Last data in to new col. address delay Last data in to burst stop Col. address to col. address delay Number of valid output data Symbol tRRD(min) tRCD(min) tRP(min) tRAS(min) tRAS(max) tRC(min) tRDL(min) tDAL(min) tCDL(min) tBDL(min) tCCD(min) CAS latency=3 CAS latency=2 Version 7A 15 20 20 45 100 65 2 2 CLK + tRP 1 1 1 2 1 Unit ns ns ns ns us ns CLK CLK CLK CLK ea 2 2 3 4 1 2 Note 1 1 1 1
Notes : 1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time and then rounding off to the next higher integer. 2. Minimum delay is required to complete write. 3. All parts allow every cycle column address change. 4. In case of row precharge interrupt, auto precharge and read burst stop.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
AC CHARACTERISTICS (AC operating conditions unless otherwise noted) REFER TO THE INDIVIDUAL COMPONENET, NOT THE WHOLE MODULE.
Parameter CLK cycle time CLK to valid output delay Output data hold time CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 CAS latency=3 CAS latency=2 Symbol 7A Min 7.5 10 Max 1000 5.4 6 3 3 2.5 2.5 1.5 0.8 1 5.4 6 Unit
SDRAM
Note
tCC
ns
1
tSAC
ns
1,2
tOH tCH tCL tSS tSH tSLZ tSHZ
ns ns ns ns ns ns ns
2 3 3 3 3 2
CLK high pulse width CLK low pulse width Input setup time Input hold time CLK to output in Low-Z CLK to output in Hi-Z CAS latency=3 CAS latency=2
Notes : 1. Parameters depend on programmed CAS latency. 2. If clock rising time is longer than 1ns, (tr/2-0.5)ns should be added to the parameter. 3. Assumed input rise and fall time (tr & tf) = 1ns. If tr & tf is longer than 1ns, transient time compensation should be considered, i.e., [(tr + tf)/2-1]ns should be added to the parameter.
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
SIMPLIFIED TRUTH TABLE
Command Register Mode register set Auto refresh Refresh Entry Self refresh Exit
CKEn-1 CKEn CS RAS CAS WE DQM BA0,1 A10/AP
SDRAM
(V=Valid, X=Dont care, H=Logic high, L=Logic low)
A0 ~ A9, A11, A12 Note
H H
X H L H X X
L L L H L L
L L H X L H
L L H X H L
L H H X H H
X X
OP code X
1,2 3 3 3 3
L H H
X X X V V
X Row address L H L H X V X L H X
Column address
Bank active & row addr. Read & column address Write & column address Burst stop Precharge Bank selection All banks Entry Exit Entry Precharge power down mode Exit DQM No operation command Auto precharge disable Auto precharge enable Auto precharge disable Auto precharge enable
4 4,5 4 4,5 6
H H H
X X X
L L L H L X H L H L
H H L X V X X H X V X
L H H X V X X H X V
L L L X V X X H X V
X X X
V
Column address
Clock suspend or active power down
H L H
L H L
X X X
X
X X V X X 7
L H H
H
X
H L
X H
X H
X H
X
Notes : 1. OP Code : Operand code A0 ~ A12 & BA0 ~ BA1 : Program keys. (@ MRS) 2. MRS can be issued only at all banks precharge state. A new command can be issued after 2 clock cycles of MRS. 3. Auto refresh functions are as same as CBR refresh of DRAM. The automatical precharge without row precharge command is meant by "Auto". Auto/self refresh can be issued only at all banks precharge state. 4. BA0 ~ BA1 : Bank select addresses. If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected. If BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank B is selected. If BA0 is "Low" and BA1 is "High" at read, write, row active and precharge, bank C is selected. If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected. If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected. 5. During burst read or write with auto precharge, new read/write command can not be issued. Another bank read/write command can be issued after the end of burst. New row active of the associated bank can be issued at tRP after the end of burst. 6. Burst stop command is valid at every burst length. 7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0), but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
PACKAGE DIMENSIONS : 32Mx64 (M464S3354BTS)
SDRAM
Units : Inches (Millimeters)
2.66 (67.56) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.24 (6.0) 0.79 (20.00) 2-R 0.078 Min (2.00 Min) 1.00 (25.40) 0.024 0.001 (0.600 0.050) 0.008 0.006 (0.200 0.150) 0.03 TYP (0.80 TYP)
1
59
61
143
0.13 (3.30)
0.91 (23.20)
0.10 (2.50)
0.18 (4.60) 0.083 (2.10)
1.29 (32.80)
2- 0.07 (1.80)
Z 0.15 (3.70)
2 60 62 144
Y
0.150 Max (3.80 Max) (3.20 Min) (4.00 Min) 0.125 Min 0.157 Min 0.16 0.0039 (4.00 0.10) 0.06 0.0039 (1.50 0.1)
0.04 0.0039 (1.00 0.10)
Detail Z
(2.540 Min)
0.100 Min
Detail Y
Tolerances : 0.006(.15) unless otherwise specified The used device is 32Mx16 SDRAM, TSOPII SDRAM Part No. : K4S511632B
Rev. 1.2 March 2004
256MB, 512MB Unbuffered SODIMM
PACKAGE DIMENSIONS : 64Mx64 (M464S6554BTS)
SDRAM
Units : Inches (Millimeters)
2.66 (67.56) 2.50 (63.60) 0.16 0.039 (4.00 0.10) 0.24 (6.0) 0.79 (20.00) 2-R 0.078 Min (2.00 Min) 1.25 (31.75) 0.024 0.001 (0.600 0.050) 0.008 0.006 (0.200 0.150) 0.03 TYP (0.80 TYP)
1
59
61
143
0.13 (3.30)
0.91 (23.20)
0.10 (2.50)
0.18 (4.60) 0.083 (2.10)
1.29 (32.80)
2- 0.07 (1.80)
Z 0.15 (3.70)
2 60 62 144
Y
0.150 Max (3.80 Max) (3.20 Min) (4.00 Min) 0.125 Min 0.157 Min 0.16 0.0039 (4.00 0.10) 0.06 0.0039 (1.50 0.1)
0.04 0.0039 (1.00 0.10)
Detail Z
(2.540 Min)
0.100 Min
Detail Y
Tolerances : .006(.15) unless otherwise specified The used device is 32Mx16 SDRAM, TSOPII SDRAM Part No. : K4S511632B
Rev. 1.2 March 2004

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