View M65677FP_1270428.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

MITSUBISHI ICs (TV)
M65677FP
DIGITAL NTSC/PAL ENCODER
DESCRIPTION
The M65677FP encodes CCIR601 or CCIR656 format Y/Cb/Cr data into analog NTSC and PAL video signals, including Digital Signal Processing functions such as Closed Caption encoding, Overlay OSD, Anti Video Copy Processing (Note1) e.t.c. It also includes peripheral processing function such as 10bit DAC e.t.c., so that low cost and compact system can be realized. Note (Note1): This device is protected by U.S. patent numbers 4631603, 4577216 and 4819098 and other intellectual property rights. The use of Macrovision Corporation's copy protection technology in the device must be authorized by Macrovision and is intended for home and other limited pay-par-view uses only, unless otherwise authorized in writing by Macrovision. Reverse engineering or disassembly is prohibited. (Note2): 6dB Amp max. output is 1.0VP-P. (Note3): Copy Generation Management System-A (IEC1880) (Note4): Wide Screen Signaling (ETS300 294)
FEATURES
* * * * * * * * * * * * * * * * *
Macrovision's video anti copy process Rev 7.01 supported (Note1) Overlay CGMS signal on line 20/283 for 525/60 (Note3) Generate CRCC for CGMS Signal Overlay WSS signal on line 23 for 625/50 (Note4) Color adjustment (TINT/color control) NTSC, B/G PAL or MPAL Video Outputs Component Y/C Video (S-Video) and CVBS or Y/U/V Outputs Supporting CCIR601 and CCIR656 format data Closed Caption Manager on line 21/284 for NTSC Generate ODD parity for Closed Caption Manager H/V Sync and Composite generating Overlay Digital OSD Supporting Y/Cb/Cr 4:4:4 Over sampling Filter 2ch 10bit DAC and 3ch 6dB Amp (Note2) 3.3V I/O interface I2C Bus Interface for Controls Power down mode
APPLICATION
DVB, DVD , Digital CATV, Video CD
PIN CONFIGURATION (TOP VIEW)
42 Ccomp
CVBS
DAC
DAY
Cref
Yref
C in
Y in
44 AVDD1
45 AVSS1
38 AVDD2
36 AVSS2
34 N.C.
40 N.C
41
39
46
43
37
35
Ycomp 49 N.C. 50 DVDD1 51 DVSS1 52 X out X in
53 54
48
47
33 32 N.C. 31 N.C. 30 DVDD1 29 28 27 26 25
C
Y
TEST SCL SDA ACK RESET Master/slave OSD2 OSD1 OSD0 OSDCK
DVSS2 55 PXD7 PXD6 PXD5 PXD4 PXD3 PXD2 PXD1 PXD0
56 57 58 59 60 61 62 63
M65677FP
24 23 22 21 20
19 DVSS1 18 DVDD1 17 DVDD2 10 11 12 13 14 15
DVDD2 64 DVSS2 16
5 8 3 4 6
DVSS2 1
2
DVASEL
VD9
VD8
7
VD7
VD6
9
VD5
VD4
VD3
VD2
VD1
PXCLK
Outline 64P6N-A
VD0
HD
VD
NC : NO CONNECTION
1
Y ref C ref
OSD Control I/F AVss1 LPF AVSS2 AVDD2
OSD2 OSD1 OSD0 DAC DAY Yin Cin Y Closed Caption Manager Y/U 6dB Y/Cb/Cr Y/U/V DAC Cb Cr V ENCODE Y/C MIX 6dB CVBS U CGMS/WSS Manager C/V 6dB C Y DAC Y AVdd1 BPF Clamp & bias
BLOCK DIAGRAM
OSDCK
Y
PXD [7:0]
Y
OSD Interface
Video output
Input Interface
Cb
CCIR601 or 656 Pixel Data from MPEG decoder Anti Copy Processing
VD [9:0]
Cr
TEST RESET
HD
VD
Sync Processing
DIGITAL NTSC/PAL ENCODER
From/To MPEG decoder
Master /Slave
DVdd2(X2) DVdd1(X2) DVss2(X2) DVss1(X2)
ACK
MITSUBISHI ICs (TV)
M65677FP
From micro controler
SDA
serial interface
SCL
2
MITSUBISHI ICs (TV)
M65677FP
DIGITAL NTSC/PAL ENCODER
ABSOLUTE MAXIMUM RATINGS
Symbol VDD VI VO Ta Tstg Parameter Supply voltage Digital input voltage Digital output voltage Operating temperature Storage temperature Min. -0.3 -0.3 -0.3 -20 -40 Limits Typ. Max. 4.5
VDD+0.3 VDD+0.3
Unit V V V C C
+25
+75 +125
RECOMMENDED OPERATING CONDITION (Ta=25C, DVDD=AVDD=3.3V, DVSS=AVSS=0V, unless otherwise noted)
Symbol Parameter Test conditions Min. 3.0 3.15 0 0 DVDD=3.0V DVDD=3.6V DVDD=3.0V, VI=0V or VI=3.6V f=1MHz, VDD=0V 0 2.5 7 Limits Typ. 3.3 3.3 Max. 3.6 3.45 45 55 0.8 3.6 15 15 0.05 3.25 7 4.0 15 10 2.0 1.0 1.5 7.5 5.50 5.10 0.8 1.6 -12 0.26 Ryicl= Iyich Iyids 20 0.45 0.40 0.30 0.95 0.90 1.00 10.0 6.00 6.00 11.5 6.50 6.85 15 Unit
Supply Digital supply voltage DVDDX AVDDX Analog supply voltage DIDD Digital current consumption AIDD Analog current consumption Digital input VIL Input voltage VIH IIL/IIL Input leakage current CI Input capacitance Digital output VOL Output voltage VOH CO Output capacitance I2C bus IO Output current IOZ Output leakage current (off) D/A converter Res Resolution INL Integral non-linearity error DNL Differential non-linearity error VfSMAX Maximum output amplitude 6-dB amplifier Rbias Bias resistor GV_YC Output gain (Y/C) GV_CV Output gain (CVBS) DRin Input dynamic range DRout Output dynamic range Iyich Yin clamp charge current Iyids Yin clamp discharge current Ryicl Vyicl Vyocl Vcvcl Vcin Vcob Iamp Yin clamp discharge current Yin input clamp voltage Y output clamp voltage CVBS output clamp voltage Cin input bias voltage C output bias voltage Output current
V V mA mA V V A pF V V pF mA A Bit LSB LSB VP-P k dB dB VP-P VP-P A A - V V V V V mA
DVDD=3.3V, | IO |<1A f=1MHz, VDD=0V DVDD=3.0V, VIL=0.4V DVDD=3.6V, VI=0V or VI=3.6V
-26 0.65 0.65 0.50 0.50 0.50 1.00 1.00
-50 1.80 70 0.55 0.60 0.70 1.05 1.10
3
MITSUBISHI ICs (TV)
M65677FP
DIGITAL NTSC/PAL ENCODER
DESCRIPTION OF PIN
Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Pin name DVSS2 PXCLK DVASEL HD VD VD9 VD8 VD7 VD6 VD5 VD4 VD3 VD2 VD1 VD0 DVSS2 DVDD2 DVDD1 DVSS1 OSDCK OSD0 OSD1 OSD2 Master/Slave RESET ACK SDA SCL TEST DVDD1 N.C. N.C. C N.C. CVBS AVSS2 Y AVDD2 Yin N.C. Cin I O I The color look-up table address input. MSB and LSB is OSD2 and OSD0, respectively. Synchronizing mode selection. "Low" is for the slave mode. "High" is for the master mode. Initializing reset. "LOW" is active. Acknowledge line (Open drain output). Serial data line/Acknowledge line (Open drain output). Serial clock line. Type Supply Digital ground for the I/O. O I I/O I/O Reference clock for input pixel data. The clock frequency is 27.0MHz. I2C slave address setting. "Low" is for the address of 40h, "High" is for the address of 42h. Horizontal sync signal input or output. It is an input and output in the slave and master mode, respectively. Vertical sync input or output. Or OddEven signal output. It is an input and output in the slave and master mode, respectively. Function
I/O
Video data outputs. In the Y/U/V output mode, the output is the 10-bit digital luma signal with a composite sync. VD9 is MSB and VD0 is LSB.
Supply Supply Supply Supply O
Digital ground for the I/O. Digital supply for the I/O. Digital supply for the internal logic. Digital ground for the internal logic. The reference clock for an external OSD microcontroller. The frequency is 13.5MHz or 6.25MHz, alternated by the I 2C bus control.
I I O I/O I I
For testing. It should be grounded during an actual use. Supply Digital supply for the internal logic. No connection. No connection. O The analog chroma output from a 6dB amplifier. The output amplitude is 1.0VP-P (typ.), while the input is 0.5VP-P. No connection.
The analog composite video signal from a 6dB amplifier. The output amplitude is 1.24VP-P (typ.). Supply Analog ground for 6dB amplifiers. The analog luma output from a 6dB amplifier. The output amplitude is 1.2VP-P (typ.), while input is 0.6VP-P. Supply Analog supply for 6dB amplifiers. O I The analog luma input from an external LPF. This input has bias circuit. The signal must input via a capacitor. No connection. The analog chroma input from an external LPF. This input has bias circuit. The signal must input via a capacitor.
4
MITSUBISHI ICs (TV)
M65677FP
DIGITAL NTSC/PAL ENCODER
DESCRIPTION OF PIN (cont.)
Pin No. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Pin name Ccomp DAC AVDD1 AVSS1 DAY Cref Yref Ycomp N.C. DVDD1 DVSS1 Xout Xin DVSS2 PXD7 PXD6 PXD5 PXD4 PXD3 PXD2 PXD1 PXD0 DVDD2 Type Function Phase compensation for chroma or V output DAC. I It should be connected to the analog ground via a capacitor. Chroma or V signal output. O The DAC output should be connected to the analog supply via a load resistor (R L). The output amplitude is set up by reference resistor (Rref) and RL. Supply Analog supply for DACs. Supply Analog ground for DACs. Luma or U signal output. O It should be connected to the analog supply via a load resistor (RL). The output amplitude is set up by reference resistor (Rref) and RL. I I I A reference current source for chroma or V signal output DAC. It should be connected to the analog supply via a reference resistor (Rref). A reference current source for Y or U DAC. It should be connected to the analog supply via a reference resistor (Rref).
Phase compensation for Y or U DAC. It should be connected to the analog ground via a capacitor. No connection. Supply Digital supply for the internal logic. Supply Digital ground for the internal logic. O I System clock output. It must be in no connection except for a connection to a X'tal oscillator.
System clock input. The clock frequency is only 27.0MHz. Supply Digital ground for the I/O.
I
Pixel data inputs. The acceptable video data are; * multiplexed video data (Y/Cb/Cr) including timing reference code of SAV and EAV, defined in CCIR Rec656 * multiplexed video data (Y/Cb/Cr) defined in CCIR Rec601 MSB and LSB is PXD7 and PXD0, respectively.
Supply Digital supply for the I/O.
5
MITSUBISHI ICs (TV)
M65677FP
DIGITAL NTSC/PAL ENCODER
APPLICATION EXAMPLE
(CCIR656 I/F, Y/C/CVBS Output Mode)
CVBS 0.1 75 220
75 10k 10k Filter Stage Filter Stage
DAC 200 C in 0.1 DAY
AVDD AVss Ccomp Ycomp Cref
Yref
Y in
2.2
47 0.01
0.1 0.1
200
Y C CVBS
2.2 0.1 2.2
220
75 Driver
75
C
Y
TEST Master/Slave DVASEL DVSS 47 0.01 DVDD X out X in VD(9:0)
Digital NTSC/PAL Encoder
M65677FP
PXD(7:0) PXCLK
RESET OSD(2:0) OSDCK ACK SDA SCL
R/G/B OSC1
OSD micro computer Lch VD HD RESET CS SCK SIN Rch Units Resistance : Capacitance : F
M35041
27MHz
HD VD
Audio DAC DIN LRCIN BCKIN XTI
47 0.01
8
VSS VDD
CLK in
SCL SDA/ACK RESET AO0 MPEG2 AO1 System/ AO2 Video/Audio AO3 Decoder M65773FP LRCLK BCLK BDEN BDREQ DOCLK DACCLK ACLKO ACLKI
16M SDRAM
27MHz XO
HSYNC VSYNC
PXCLK
PXD
BDER
BD
3.3k 8
RCLK BDEN BDREQ
Chanel Decoder
: 3.3V Power Supply (for Digital/Analog) : 5.0V Power Supply (for Analog)
RESET CS SCK SIN
BD
BDER
Host CPU
Audio out (R)
Audio out (L)
47 0.01 3.3k VDD VSS
3
6

▲Up To Search▲

Price & Availability of M65677FP

	To Download M65677FP Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .