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19-3643; Rev 0; 4/05
KIT ATION EVALU LE B AVAILA
Dual, 80Msps, 12-Bit, IF/Baseband ADC
General Description
The MAX12528 is a dual 80Msps, 12-bit analog-to-digital converter (ADC) featuring fully differential wideband track-and-hold (T/H) inputs, driving internal quantizers. The MAX12528 is optimized for low power, small size, and high dynamic performance in intermediate frequency (IF) and baseband sampling applications. This dual ADC operates from a single 3.3V supply, consuming only 726mW while delivering a typical 69.8dB signal-tonoise ratio (SNR) performance at a 175MHz input frequency. The T/H input stages accept single-ended or differential inputs up to 400MHz. In addition to low operating power, the MAX12528 features a 330W powerdown mode to conserve power during idle periods. A flexible reference structure allows the MAX12528 to use the internal 2.048V bandgap reference or accept an externally applied reference and allows the reference to be shared between the two ADCs. The reference structure allows the full-scale analog input range to be adjusted from 0.35V to 1.15V. The MAX12528 provides a common-mode reference to simplify design and reduce external component count in differential analog input circuits. The MAX12528 supports either a single-ended or differential input clock. User-selectable divide-by-two (DIV2) and divide-by-four (DIV4) modes allow for design flexibility and help eliminate the negative effects of clock jitter. Wide variations in the clock duty cycle are compensated with the ADC's internal duty-cycle equalizer (DCE). The MAX12528 features two parallel, 12-bit-wide, CMOS-compatible outputs. The digital output format is pin-selectable to be either two's complement or Gray code. A separate power-supply input for the digital outputs accepts a 1.7V to 3.6V voltage for flexible interfacing with various logic levels. The MAX12528 is available in a 10mm x 10mm x 0.8mm, 68-pin thin QFN package with exposed paddle (EP), and is specified for the extended (-40C to +85C) temperature range.
Features
Direct IF Sampling Up to 400MHz Excellent Dynamic Performance 70.7dB/69.8dB SNR at fIN = 70MHz/175MHz 78.2dBc/72.9dBc SFDR at fIN = 70MHz/175MHz 3.3V Low-Power Operation 760mW (Differential Clock Mode) 726mW (Single-Ended Clock Mode) Fully Differential or Single-Ended Analog Input Adjustable Differential Analog Input Voltage 750MHz Input Bandwidth Internal, External, or Shared Reference Differential or Single-Ended Clock Accepts 25% to 75% Clock Duty Cycle User-Selectable DIV2 and DIV4 Clock Modes Power-Down Mode CMOS Outputs in Two's Complement or Gray Code Out-of-Range and Data-Valid Indicators Compact, 68-Pin Thin QFN Package (10mm x 10mm x 0.8mm) Evaluation Kit Available (Order MAX12528EVKIT)
MAX12528
Ordering Information
PART TEMP RANGE PIN-PACKAGE PKG CODE T6800-2
MAX12528ETK -40C to +85C 68 Thin QFN-EP*
*EP = Exposed paddle.
Applications
IF and Baseband Communication Receivers Cellular, LMDS, Point-to-Point Microwave, MMDS, HFC, WLAN I/Q Receivers Medical Imaging Portable Instrumentation Digital Set-Top Boxes Low-Power Data Acquisition
PART MAX12528 MAX12557 MAX12527
Selector Guide
SAMPLING RATE (Msps) 80 65 65 RESOLUTION (Bits) 12 14 12
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products
1
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Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
ABSOLUTE MAXIMUM RATINGS
VDD to GND ................................................................-0.3V to +3.6V OVDD to GND............-0.3V to the lower of (VDD + 0.3V) and +3.6V INAP, INAN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V INBP, INBN to GND ...-0.3V to the lower of (VDD + 0.3V) and +3.6V CLKP, CLKN to GND ........................-0.3V to the lower of (VDD + 0.3V) and +3.6V REFIN, REFOUT to GND ..................-0.3V to the lower of (VDD + 0.3V) and +3.6V REFAP, REFAN, COMA to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6V REFBP, REFBN, COMB to GND ......-0.3V to the lower of (VDD + 0.3V) and +3.6V DIFFCLK/SECLK, G/T, PD, SHREF, DIV2, DIV4 to GND .........-0.3V to the lower of (VDD + 0.3V) and +3.6V D0A-D11A, D0B-D11B, DAV, DORA, DORB to GND..............................-0.3V to (OVDD + 0.3V) Continuous Power Dissipation (TA = +70C) 68-Pin Thin QFN 10mm x 10mm x 0.8mm (derate 70mW/C above +70C) ....................................4000mW Thermal Resistance jc........................................................0.4C/W Operating Temperature Range................................-40C to +85C Junction Temperature ...........................................................+150C Storage Temperature Range .................................-65C to +150C Lead Temperature (soldering, 10s)......................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, AIN = -0.5dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 80MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER DC ACCURACY Resolution Integral Nonlinearity Differential Nonlinearity Offset Error Gain Error ANALOG INPUT (INAP, INAN, INBP, INBN) Differential Input Voltage Range Common-Mode Input Voltage Analog Input Resistance RIN CPAR Analog Input Capacitance CSAMPLE CONVERSION RATE Maximum Clock Frequency Minimum Clock Frequency Data Latency DYNAMIC CHARACTERISTICS Small-Signal Noise Floor SSNF Input at -35dBFS fIN = 3MHz at -0.5dBFS Signal-to-Noise Ratio SNR fIN = 40MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS 67.1 71.0 69.3 72.1 71.2 70.7 70.7 69.8 dB dBFS Figure 5 8 fCLK 80 5 MHz MHz Clock Cycles Switched capacitance, each input (Figure 3) 4.5 Each input (Figure 3) Fixed capacitance to ground, each input (Figure 3) VDIFF Differential or single-ended inputs 1.024 VDD / 2 2 2 pF V V k INL DNL fIN = 3MHz fIN = 3MHz, no missing codes 12 0.6 0.3 0.1 0.5 1.6 0.85 0.7 4.3 Bits LSB LSB %FSR %FSR SYMBOL CONDITIONS MIN TYP MAX UNITS
2
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Dual, 80Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, AIN = -0.5dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 80MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS fIN = 3MHz at -0.5dBFS Signal-to-Noise Plus Distortion SINAD fIN = 40MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS Spurious-Free Dynamic Range SFDR fIN = 40MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS Total Harmonic Distortion THD fIN = 40MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS Second Harmonic HD2 fIN = 40MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS fIN = 3MHz at -0.5dBFS Third Harmonic HD3 fIN = 40MHz at -0.5dBFS fIN = 70MHz at -0.5dBFS fIN = 175MHz at -0.5dBFS Two-Tone Intermodulation Distortion (Note 2) fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS fIN1 = 68.5MHz at -7dBFS fIN2 = 71.5MHz at -7dBFS fIN1 = 172.5MHz at -7dBFS fIN2 = 177.5MHz at -7dBFS Input at -0.2dBFS, -3dB rolloff Figure 5 INAP = INAN = COMA INBP = INBN = COMB 67.2 64.6 74.7 MIN 68.9 TYP 70.8 70.2 69.6 67.7 85.6 81.8 78.2 72.9 -84.2 -79.3 -75.8 -71.9 -87.2 -85.2 -85 -81.5 -92.1 -85.5 -78.2 -72.9 -77.5 dBc -72.8 -78.6 dBc -74.3 78.6 dBc 74.3 750 1.2 <0.15 0.3 MHz ns psRMS LSBRMS dBc dBc -66.4 -73.3 dBc dBc dB MAX UNITS
MAX12528
TTIMD
3rd-Order Intermodulation Distortion
IM3
Two-Tone Spurious-Free Dynamic Range Full-Power Bandwidth Aperture Delay Aperture Jitter Output Noise
SFDRTT
FPBW tAD tAJ nOUT
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3
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, AIN = -0.5dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 80MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Overdrive Recovery Time INTERCHANNEL CHARACTERISTICS Crosstalk Rejection Gain Matching Offset Matching INTERNAL REFERENCE (REFOUT) REFOUT Output Voltage REFOUT Load Regulation REFOUT Temperature Coefficient REFOUT Short-Circuit Current TCREF Short to VDD--sinking Short to GND--sourcing VREFOUT -1mA < IREFOUT < +1mA 1.995 2.048 35 65 0.24 2.1 2.075 V mV/mA ppm/C mA fINA or fINB = 70MHz at -0.5dBFS fINA or fINB = 175MHz at -0.5dBFS 90 85 0.01 0.01 0.1 dB dB %FSR SYMBOL CONDITIONS 10% beyond full scale MIN TYP 1 MAX UNITS Clock cycle
BUFFERED REFERENCE MODE (REFIN is driven by REFOUT or an external 2.048V single-ended reference source; VREFAP/VREFAN/VCOMA and VREFBP/VREFBN/VCOMB are generated internally) REFIN Input Voltage REFIN Input Resistance COM_ Output Voltage REF_P Output Voltage REF_N Output Voltage Differential Reference Voltage Differential Reference Temperature Coefficient VREFIN RREFIN VCOMA VCOMB VREFAP VREFBP VREFAN VREFBN VREFA VREFB TCREF VDD / 2 VDD / 2 + (VREFIN x 3/8) VDD / 2 - (VREFIN x 3/8) VREFA = VREFAP - VREFAN VREFB = VREFBP - VREFBN 1.440 1.60 2.048 >50 1.65 2.418 0.882 1.536 30 1.590 1.70 V M V V V V ppm/C
UNBUFFERED EXTERNAL REFERENCE (REFIN = GND, VREFAP/VREFAN/VCOMA and VREFBP/VREFBN/VCOMB are applied externally, VCOMA = VCOMB = VDD / 2) REF_P Input Voltage REF_N Input Voltage COM_ Input Voltage Differential Reference Voltage VREFAP VREFBP VREFAN VREFBN VCOM VREFA VREFB VREF_P - VCOM VREF_N - VCOM VDD / 2 VREF_ = VREF_P - VREF_N = VREFIN x 3/4 +0.768 -0.768 1.65 1.536 V V V V
4
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Dual, 80Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, AIN = -0.5dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 80MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER REF_P Sink Current REF_N Source Current COM_ Sink Current REF_P, REF_N Capacitance COM_ Capacitance CLOCK INPUTS (CLKP, CLKN) Single-Ended Input High Threshold Single-Ended Input Low Threshold Minimum Differential Clock Input Voltage Swing Differential Input Common-Mode Voltage CLK_ Input Resistance CLK_ Input Capacitance RCLK CCLK VIH VIL DIFFCLK/SECLK = GND, CLKN = GND DIFFCLK/SECLK = GND, CLKN = GND DIFFCLK/SECLK = OVDD DIFFCLK/SECLK = OVDD Each input (Figure 4) Each input 0.8 x OVDD 0.2 x OVDD 5 5 5 D0A-D11A, D0B-D11B, DORA, DORB: ISINK = 200A DAV: ISINK = 600A D0A-D11A, D0B-D11B, DORA, DORB: ISOURCE = 200A DAV: ISOURCE = 600A Three-State Leakage Current (Note 3) ILEAK OVDD applied to input Input connected to ground OVDD 0.2 V OVDD 0.2 5 5 A 0.2 VDD / 2 5 2 0.8 x VDD 0.2 x VDD V V VP-P V k pF SYMBOL IREFAP IREFBP IREFAN IREFBN ICOMA ICOMB CREF_P, CREF_N CCOM_ CONDITIONS VREF_P = 2.418V VREF_N = 0.882V VCOM_ = 1.65V MIN TYP 1.2 0.85 0.85 13 6 MAX UNITS mA mA mA pF pF
MAX12528
DIGITAL INPUTS (DIFFCLK/SECLK, G/T, PD, DIV2, DIV4) Input High Threshold Input Low Threshold Input Leakage Current Digital Input Capacitance CDIN VIH VIL OVDD applied to input Input connected to ground V V A pF
DIGITAL OUTPUTS (D0A-D11A, D0B-D11B, DORA, DORB, DAV) Output-Voltage Low VOL 0.2 0.2 V
Output-Voltage High
VOH
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5
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, AIN = -0.5dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 80MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER D0A-D11A, DORA, D0B-D11B and DORB Three-State Output Capacitance DAV Three-State Output Capacitance POWER REQUIREMENTS Analog Supply Voltage Digital Output Supply Voltage VDD OVDD Normal operating mode fIN = 175MHz at -0.5dBFS, single-ended clock (DIFFCLK/SECLK = GND) Analog Supply Current IVDD Normal operating mode fIN = 175MHz at -0.5dBFS, differential clock (DIFFCLK/SECLK = OVDD) Power-down mode (PD = OVDD) clock idle Normal operating mode fIN = 175MHz at -0.5dBFS, single-ended clock (DIFFCLK/SECLK = GND) Analog Power Dissipation PVDD Normal operating mode fIN = 175MHz at -0.5dBFS, differential clock (DIFFCLK/SECLK = OVDD) Power-down mode (PD = OVDD) clock idle Normal operating mode fIN = 175MHz at -0.5dBFS Power-down mode (PD = OVDD) clock idle 3.15 1.70 3.30 2.0 3.60 VDD V V SYMBOL COUT (Note 3) CONDITIONS MIN TYP 3 MAX UNITS pF
CDAV
(Note 3)
6
pF
220
mA 230 250
0.1
726
mW 760 825
0.330 20.7 mA 0.004
Digital Output Supply Current
IOVDD
6
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Dual, 80Msps, 12-Bit, IF/Baseband ADC
ELECTRICAL CHARACTERISTICS (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference), CL 10pF at digital outputs, AIN = -0.5dBFS (differential), DIFFCLK/SECLK = OVDD, PD = GND, SHREF = GND, DIV2 = GND, DIV4 = GND, G/T = GND, fCLK = 80MHz, TA = -40C to +85C, unless otherwise noted. Typical values are at TA = +25C.) (Note 1)
PARAMETER Clock Pulse-Width High Clock Pulse-Width Low Data-Valid Delay Data Setup Time Before Rising Edge of DAV Data Hold Time After Rising Edge of DAV Wake-Up Time from Power-Down SYMBOL tCH tCL tDAV tSETUP tHOLD tWAKE (Note 4) (Note 4) VREFIN = 2.048V 5.0 5.5 10 CONDITIONS MIN TYP 6.2 6.2 5.3 MAX UNITS ns ns ns ns ns ms
MAX12528
TIMING CHARACTERISTICS (Figure 5)
Note 1: Specifications +25C guaranteed by production test, <+25C guaranteed by design and characterization. Note 2: Two-tone intermodulation distortion measured with respect to a single-carrier amplitude, and not the peak-to-average input power of both input tones. Note 3: During power-down, D0A-D11A, D0B-D11B, DORA, DORB, and DAV are high impedance. Note 4: Guaranteed by design and characterization.
Typical Operating Characteristics
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, AIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
FFT PLOT (16,384-POINT DATA RECORD)
MAX12528 toc01
FFT PLOT (32,768-POINT DATA RECORD)
MAX12528 toc02
FFT PLOT (32,768-POINT DATA RECORD)
-10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 fCLK = 80MHz fIN = 69.8999023MHz AIN = -0.437dBFS fIN SNR = 71dB SINAD = 69.2dB THD = -73.9dBc SFDR = 74.6dBc HD2 = -94.6dBc HD3 = -74.6dBc HD3 HD2
MAX12528 toc03
0 -10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 5 10 15 20 fIN
AMPLITUDE (dBFS)
HD2 HD3
fCLK = 80MHz fIN = 2.99926758MHz AIN = -0.46dBFS SNR = 70.9dB SINAD = 70.7dB THD = -84dBc SFDR = 85.5dBc HD2 = -86dBc HD3 = -101dBc
0 -10 -20 -30 -40 -50 -60 -70 -80 -90 -100 -110 -120
fCLK = 80MHz fIN = 39.5092773MHz AIN = -0.482dBFS SNR = 71.1dB SINAD = 70.5dB THD = -79.1dBc SFDR = 82.7dBc HD2 = -87.6dBc HD3 = -82.7dBc HD2
0
fIN
HD3
25
30
35
40
0
5
10
15
20
25
30
35
40
0
5
10
15
20
25
30
35
40
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
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7
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, AIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
TWO-TONE IMD PLOT (16,384-POINT DATA RECORD)
MAX12528 toc05
FFT PLOT (32,768-POINT DATA RECORD)
MAX12528 toc04
TWO-TONE IMD PLOT (16,384-POINT DATA RECORD)
fCLK = 65.00352MHz fIN1 = 172.50293MHz AIN1 = -6.99dBFS fIN2 = 177.40198MHz AIN2 = -7.01dBFS IM3 = -88.9dBc IMD = -82.2dBc fIN2 - fIN1 -80 -100 -120 fIN2
MAX12528 toc06
0 -10 -20 -30 AMPLITUDE (dBFS) -40 -50 -60 -70 -80 -90 -100 -110 -120 0 5
0 -20 AMPLITUDE (dBFS) -40 -60 fIN1 fIN2
fIN
AMPLITUDE (dBFS)
fCLK = 80MHz fIN = 174.9780273MHz AIN = -0.468dBFS SNR = 69.5dB SINAD = 67.9dB THD = -73.1dBc SFDR = 75dBc HD2 = -79.3dBc HD3 HD3 = -75dBc HD2
fCLK = 65.00352MHz fIN1 = 68.49889MHz fIN2 = 71.49832MHz AIN1 = -6.96dBFS AIN2 = -7.02dBFS IM3 = -92.3dBc IMD = -89.1dBc 2fIN2 + fIN1
0 -20 -40 -60
fIN1
fIN1 + fIN2
-80 -100 -120
10
15
20
25
30
35
40
0
5
10
15
20
25
30
0
5
10
15
20
25
30
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
ANALOG INPUT FREQUENCY (MHz)
INTEGRAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX12528 toc07
DIFFERENTIAL NONLINEARITY vs. DIGITAL OUTPUT CODE
MAX12528 toc08
SNR, SINAD vs. ANALOG INPUT FREQUENCY (fCLK = 80MHz, AIN = -0.5dBFS)
70 68 66 SNR, SINAD (dB) 64 62 60 58 56 54 52 50 SINAD SNR
MAX12528 toc09
1.0 0.8 0.6 0.4
fCLK = 80MHz fIN = 2.1655273MHz
1.0 0.8 0.6 0.4 DNL (LSB) 0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0
fCLK = 80MHz fIN = 2.1655273MHz
72
INL (LSB)
0.2 0 -0.2 -0.4 -0.6 -0.8 -1.0 0 512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
0
512 1024 1536 2048 2560 3072 3584 4096 DIGITAL OUTPUT CODE
0
50
100 150 200 250 300 350 400 fIN (MHz)
-THD, SFDR vs. ANALOG INPUT FREQUENCY (fCLK = 80MHz, AIN = -0.5dBFS)
MAX12528 toc10
SNR, SINAD vs. ANALOG INPUT AMPLITUDE (fCLK = 80MHz, fIN = 70MHz)
MAX12528 toc11
-THD, SFDR vs. ANALOG INPUT AMPLITUDE (fCLK = 80MHz, fIN = 70MHz)
80 70 60 50 -THD 40 30 20 SFDR
MAX12528 toc12
90 85 80 -THD, SFDR (dBc) 75 70 65 60 55 50 0 50 -THD SFDR
75 SNR 65 55 45 35 25 15 SINAD
90
100 150 200 250 300 350 400 fIN (MHz)
SNR, SINAD (dB)
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 AIN (dBFS)
0
-THD, SFDR (dB)
-55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 AIN (dBFS)
0
8
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Dual, 80Msps, 12-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, AIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
SNR, SINAD vs. ANALOG INPUT AMPLITUDE (fCLK = 80MHz, fIN = 175MHz)
MAX12528 toc13
MAX12528
-THD, SFDR vs. ANALOG INPUT AMPLITUDE (fCLK = 80MHz, fIN = 175MHz)
MAX12528 toc14
SNR, SINAD vs. CLOCK SPEED (fIN = 70MHz, AIN = -0.5dBFS)
SNR
MAX12528 toc15
75 65 SNR, SINAD (dB) 55 45 35 25 15 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 AIN (dBFS) 0
90 80 70 -THD, SFDR (dBc) 60 -THD 50 40 SFDR
75
SNR
70 SNR, SINAD (dB) SINAD
65
SINAD
60
55 30 20 -55 -50 -45 -40 -35 -30 -25 -20 -15 -10 -5 AIN (dBFS) 0 50 10 20 30 40 50 60 70 80 fCLK (MHz)
-THD, SFDR vs. CLOCK SPEED (fIN = 70MHz, AIN = -0.5dBFS)
MAX12528 toc16
SNR, SINAD vs. CLOCK SPEED (fIN = 175MHz, AIN = -0.5dBFS)
MAX12528 toc17
-THD, SFDR vs. CLOCK SPEED (fIN = 175MHz, AIN = -0.5dBFS)
85 80 -THD, SFDR (dBc) SFDR
MAX12528 toc18
90 SFDR 85 80 -THD, SFDR (dBc) 75 70 65 60
75 SNR 70 SNR, SINAD (dB)
90
-THD
65
SINAD
75 70 65 60 -THD
60
55 55 50 10 20 30 40 50 60 70 80 fCLK (MHz) 50 10 20 30 40 50 60 70 80 fCLK (MHz) 55 50 10 20 30 40 50 60 70 80 fCLK (MHz)
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE (fIN = 70MHz)
MAX12528 toc19
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE (fIN = 70MHz)
MAX12528 toc20
SNR, SINAD vs. ANALOG SUPPLY VOLTAGE (fIN = 175MHz)
SNR 70 SNR, SINAD (dB)
MAX12528 toc21
75
SNR
90 85 SFDR 80 -THD, SFDR (dBc)
75
70 SNR, SINAD (dB) SINAD
65
75 70 -THD 65 60 55
65 SINAD 60
60
55
55
50 3.0 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6
50 3.0 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6
50 3.0 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6
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9
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, AIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
-THD, SFDR vs. ANALOG SUPPLY VOLTAGE (fIN = 175MHz)
MAX12528 toc22
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE (fIN = 70MHz)
MAX12528 toc23
-THD, SFDR vs. DIGITAL SUPPLY VOLTAGE (fIN = 70MHz)
85 80 -THD, SFDR (dBc)
MAX12528 toc24
90 85 80 -THD, SFDR (dBc) SFDR 75 70 65 60 55 50 3.0 3.1 3.2 3.3 VDD (V) 3.4 3.5 -THD
75
SNR
90
70 SNR, SINAD (dB) SINAD
65
75 70 65 60 55
SFDR
60
-THD
55
50 3.6 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 OVDD (V)
50 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 OVDD (V)
SNR, SINAD vs. DIGITAL SUPPLY VOLTAGE (fIN = 175MHz)
MAX12528 toc25
-THD, SFDR vs. DIGITAL POWER SUPPLY (fIN = 175MHz)
MAX12528 toc26
PDISS, IVDD (ANALOG) vs. ANALOG SUPPLY VOLTAGE (fIN = 175MHz)
900 800 PDISS, IVDD (mW, mA) 700 600 500 400 300 200 IVDD PDISS (ANALOG)
MAX12528 toc27
75 SNR 70 SNR, SINAD (dB)
80
1000
76 -THD, SFDR (dBc) SFDR 72
65 SINAD 60
68 -THD 64
55
50 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 OVDD (V)
60 1.5 1.8 2.1 2.4 2.7 3.0 3.3 3.6 OVDD (V)
100 3.0 3.1 3.2 3.3 VDD (V) 3.4 3.5 3.6
PDISS, IOVDD (DIGITAL) vs. DIGITAL SUPPLY VOLTAGE (fIN = 175MHz)
MAX12528 toc28
SNR, SINAD vs. CLOCK DUTY CYCLE (fIN = 70MHz, AIN = -0.5dBFS)
MAX12528 toc29
-THD, SFDR vs. CLOCK DUTY CYCLE (fIN = 70MHz, AIN = -0.5dBFS)
MAX12528 toc30
100 90 80 PDISS, IOVDD (mW, mA) 70 60 50 40 30 20 10 0 1.5 1.8 2.1 2.4 2.7 3.0 3.3 IOVDD PDISS (DIGITAL)
75 SNR 70 SNR, SINAD (dB)
90 85 -THD, SFDR (dBc) 80 75 70 65 SFDR
65
SINAD
60
-THD
55 SINGLE-ENDED CLOCK DRIVE 25 35 45 55 65 75
50 3.6 OVDD (V)
60
SINGLE-ENDED CLOCK DRIVE 25 35 45 55 65 75
CLOCK DUTY CYCLE (%)
CLOCK DUTY CYCLE (%)
10
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Dual, 80Msps, 12-Bit, IF/Baseband ADC
Typical Operating Characteristics (continued)
(VDD = 3.3V, OVDD = 2.0V, GND = 0, REFIN = REFOUT (internal reference mode), CL 5pF at digital outputs, AIN = -0.5dBFS, DIFFCLK/SECLK = OVDD, PD = GND, G/T = GND, fCLK = 80MHz (50% duty cycle), TA = +25C, unless otherwise noted.)
SNR, SINAD vs. TEMPERATURE (fIN = 175MHz, AIN = -0.5dBFS)
MAX12528 toc31
MAX12528
-THD, SFDR vs. TEMPERATURE (fIN = 175MHz, AIN = -0.5dBFS)
MAX12528 toc32
72 SNR 70 SNR, SINAD (dB) 68 66 SINAD 64 62 60 -40 -15 10 35 60
90 85 -THD, SFDR (dBc) 80 SFDR 75 70 -THD 65 60
85
-40
-15
10
35
60
85
TEMPERATURE (C)
TEMPERATURE (C)
GAIN ERROR vs. TEMPERATURE (VREFIN = 2.048V)
MAX12528 toc33
OFFSET ERROR vs. TEMPERATURE
0.15 OFFSET ERROR (%FSR) 0.10 0.05 0 -0.05 -0.10 -0.15
MAX12528 toc34
2.0 1.5 1.0 GAIN ERROR (%FSR) 0.5 0 -0.5 -1.0 -1.5 -2.0 -40 -15 10 35 TEMPERATURE (C) 60
0.20
85
-0.20 -40 -15 10 35 TEMPERATURE (C) 60 85
______________________________________________________________________________________
11
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
Pin Description
PIN 1, 4, 5, 9, 13, 14, 17 2 3 6 NAME GND INAP INAN COMA FUNCTION Converter Ground. Connect all ground pins and the exposed paddle (EP) together. Channel A Positive Analog Input Channel A Negative Analog Input Channel A Common-Mode Voltage I/O. Bypass COMA to GND with a 0.1F capacitor. Channel A Positive Reference I/O. Channel A conversion range is 2/3 x (VREFAP - VREFAN). Bypass REFAP with a 0.1F capacitor to GND. Connect a 10F and a 1F bypass capacitor between REFAP and REFAN. Place the 1F REFAP-to-REFAN capacitor as close to the device as possible on the same side of the PC board. Channel A Negative Reference I/O. Channel A conversion range is 2/3 x (VREFAP - VREFAN). Bypass REFAN with a 0.1F capacitor to GND. Connect a 10F and a 1F bypass capacitor between REFAP and REFAN. Place the 1F REFAP-to-REFAN capacitor as close to the device as possible on the same side of the PC board. Channel B Negative Reference I/O. Channel B conversion range is 2/3 x (VREFBP - VREFBN). Bypass REFBN with a 0.1F capacitor to GND. Connect a 10F and a 1F bypass capacitor between REFBP and REFBN. Place the 1F REFBP-to-REFBN capacitor as close to the device as possible on the same side of the PC board. Channel B Positive Reference I/O. Channel B conversion range is 2/3 x (VREFBP - VREFBN). Bypass REFBP with a 0.1F capacitor to GND. Connect a 10F and a 1F bypass capacitor between REFBP and REFBN. Place the 1F REFBP-to-REFBN capacitor as close to the device as possible on the same side of the PC board. Channel A Common-Mode Voltage I/O. Bypass COMB to GND with a 0.1F capacitor. Channel B Negative Analog Input Channel B Positive Analog Input Differential/Single-Ended Input Clock Drive. This input selects between single-ended or differential clock input drives. DIFFCLK/SECLK = GND: Selects single-ended clock input drive. DIFFCLK/SECLK = OVDD: Selects differential clock input drive. Negative Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differential clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply the clock signal to CLKP and connect CLKN to GND. Positive Clock Input. In differential clock input mode (DIFFCLK/SECLK = OVDD), connect a differential clock signal between CLKP and CLKN. In single-ended clock mode (DIFFCLK/SECLK = GND), apply the single-ended clock signal to CLKP and connect CLKN to GND. Divide-by-Two Clock-Divider Digital Control Input. See Table 2 for details. Divide-by-Four Clock-Divider Digital Control Input. See Table 2 for details. Analog Power Input. Connect VDD to a 3.15V to 3.60V power supply. Bypass VDD to GND with a parallel capacitor combination of 10F and 0.1F. Connect all VDD pins to the same potential. Output-Driver Power Input. Connect OVDD to a 1.7V to VDD power supply. Bypass OVDD to GND with a parallel capacitor combination of 10F and 0.1F. No Connection
7
REFAP
8
REFAN
10
REFBN
11
REFBP
12 15 16
COMB INBN INBP DIFFCLK/ SECLK
18
19
CLKN
20 21 22 23-26, 61, 62, 63 27, 43, 60 28, 29, 45, 46
CLKP DIV2 DIV4 VDD OVDD N.C.
12
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Dual, 80Msps, 12-Bit, IF/Baseband ADC
Pin Description (continued)
PIN 30 31 32 33 34 35 36 37 38 39 40 41 NAME D0B D1B D2B D3B D4B D5B D6B D7B D8B D9B D10B D11B Channel B CMOS Digital Output, Bit 0 (LSB) Channel B CMOS Digital Output, Bit 1 Channel B CMOS Digital Output, Bit 2 Channel B CMOS Digital Output, Bit 3 Channel B CMOS Digital Output, Bit 4 Channel B CMOS Digital Output, Bit 5 Channel B CMOS Digital Output, Bit 6 Channel B CMOS Digital Output, Bit 7 Channel B CMOS Digital Output, Bit 8 Channel B CMOS Digital Output, Bit 9 Channel B CMOS Digital Output, Bit 10 Channel B CMOS Digital Output, Bit 11 (MSB) Channel B Data Out-of-Range Indicator. The DORB digital output indicates when the channel B analog input voltage is out of range. DORB = 1: Digital outputs exceed full-scale range. DORB = 0: Digital outputs are within full-scale range. Data-Valid Digital Output. The rising edge of DAV indicates that data is present on the digital outputs. The MAX12528 evaluation kit (MAX12528 EV kit) utilizes DAV to latch data into any external back-end digital logic. Channel A CMOS Digital Output, Bit 0 (LSB) Channel A CMOS Digital Output, Bit 1 Channel A CMOS Digital Output, Bit 2 Channel A CMOS Digital Output, Bit 3 Channel A CMOS Digital Output, Bit 4 Channel A CMOS Digital Output, Bit 5 Channel A CMOS Digital Output, Bit 6 Channel A CMOS Digital Output, Bit 7 Channel A CMOS Digital Output, Bit 8 Channel A CMOS Digital Output, Bit 9 Channel A CMOS Digital Output, Bit 10 Channel A CMOS Digital Output, Bit 11 (MSB) Channel A Data Out-of-Range Indicator. The DORA digital output indicates when the channel A analog input voltage is out of range. DORA = 1: Digital outputs exceed full-scale range. DORA = 0: Digital outputs are within full-scale range. Output Format Select Digital Input. G/T = GND: Two's-complement output format selected. G/T = OVDD: Gray-code output format selected. Power-Down Digital Input. PD = GND: ADCs are fully operational. PD = OVDD: ADCs are powered down. FUNCTION
MAX12528
42
DORB
44 47 48 49 50 51 52 53 54 55 56 57 58 59
DAV D0A D1A D2A D3A D4A D5A D6A D7A D8A D9A D10A D11A DORA
64
G/T
65
PD
______________________________________________________________________________________
13
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
Pin Description (continued)
PIN NAME FUNCTION Shared Reference Digital Input. SHREF = VDD: Shared reference enabled. SHREF = GND: Shared reference disabled. When sharing the reference, externally connect REFAP and REFBP together to ensure that VREFAP equals VREFBP. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure that VREFAN = VREFBN. Internal Reference Voltage Output. The REFOUT output voltage is 2.048V and REFOUT can deliver 1mA. For internal reference operation, connect REFOUT directly to REFIN or use a resistive divider from REFOUT to set the voltage at REFIN. Bypass REFOUT to GND with a 0.1F capacitor. For external reference operation, REFOUT is not required and must be bypassed to GND with a 0.1F capacitor. Single-Ended Reference Analog Input. For internal reference and buffered external reference operation, apply a 0.7V to 2.3V DC reference voltage to REFIN. Bypass REFIN to GND with a 4.7F capacitor. Within its specified operating voltage, REFIN has a >50M input impedance, and the differential reference voltage (VREF_P - VREF_N) is generated from REFIN. For unbuffered external reference operation, connect REFIN to GND. In this mode REF_P, REF_N, and COM_ are high-impedance inputs that accept the external reference voltages. Exposed Paddle. EP is internally connected to GND. Externally connect EP to GND to achieve specified dynamic performance.
66
SHREF
67
REFOUT
68
REFIN
--
EP
+ MAX12528
FLASH ADC DAC
-
x2
IN_P STAGE 1 IN_N DIGITAL ERROR CORRECTION STAGE 2 STAGE 9
STAGE 10 END OF PIPELINE
D0_ THROUGH D11_
Figure 1. Pipeline Architecture--Stage Blocks
Detailed Description
The MAX12528 uses a 10-stage, fully differential, pipelined architecture (Figure 1) that allows for highspeed conversion while minimizing power consumption. Samples taken at the inputs move progressively through the pipeline stages every half clock cycle. From input to output the total latency is 8 clock cycles.
14
Each pipeline converter stage converts its input voltage to a digital output code. At every stage, except the last, the error between the input voltage and the digital output code is multiplied and passed along to the next pipeline stage. Digital error correction compensates for ADC comparator offsets in each pipeline stage and ensures no missing codes. Figure 2 shows the MAX12528 functional diagram.
______________________________________________________________________________________
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
CLOCK
INAP INAN
12-BIT PIPELINE ADC
DIGITAL ERROR CORRECTION
DATA FORMAT
OUTPUT DRIVERS
D0A TO D11A DORA
REFAP COMA REFAN
CHANNEL A REFERENCE SYSTEM
MAX12528
G/T
REFIN REFOUT SHREF REFBP COMB REFBN CHANNEL B REFERENCE SYSTEM
INTERNAL REFERENCE GENERATOR
DAV
OVDD
INBP INBN
12-BIT PIPELINE ADC
DIGITAL ERROR CORRECTION CLOCK
DATA FORMAT
OUTPUT DRIVERS
D0B TO D11B DORB
DIFFCLK/SECLK CLOCK CLKP CLKN CLOCK DIVIDER DUTY-CYCLE EQUALIZER POWER CONTROL AND BIAS CIRCUITS
VDD
PD
DIV2 DIV4
GND
Figure 2. Functional Diagram
______________________________________________________________________________________
15
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
Table 1. Reference Modes
BOND WIRE INDUCTANCE 1.5nH IN_P CPAR 2pF VDD *CSAMPLE 4.5pF VDD
MAX12528
VREFIN
REFERENCE MODE
BOND WIRE INDUCTANCE 1.5nH IN_N
Internal Reference Mode. REFIN is driven by REFOUT either through a 35% VREFOUT direct short or a resistive divider. to 100% VCOM_ = VDD / 2 VREFOUT VREF_P = VDD / 2 + 3/8 x VREFIN VREF_N = VDD / 2 - 3/8 x VREFIN Buffered External Reference Mode. An external 0.7V to 2.3V reference voltage is applied to REFIN. VCOM_ = VDD / 2 VREF_P = VDD / 2 + 3/8 x VREFIN VREF_N = VDD / 2 - 3/8 x VREFIN Unbuffered External Reference Mode. REF_P, REF_N, and COM_ are driven by external reference sources. The full-scale analog input range is (VREF_P - VREF_N) x 2/3.
CPAR 2pF
*CSAMPLE 4.5pF
0.7V to 2.3V
SAMPLING CLOCK *THE EFFECTIVE RESISTANCE OF THE SWITCHED SAMPLING CAPACITORS IS: RIN =
1 fCLK x CSAMPLE
<0.5V
Figure 3. Internal T/H Circuit
Analog Inputs and Input Track-and-Hold (T/H) Amplifier
Figure 3 displays a simplified functional diagram of the input T/H circuit. This input T/H circuit allows for high analog input frequencies of 175MHz and beyond and supports a VDD / 2 common-mode input voltage. The MAX12528 sampling clock controls the switchedcapacitor input T/H architecture (Figure 3) allowing the analog input signals to be stored as charge on the sampling capacitors. These switches are closed (track mode) when the sampling clock is high and open (hold mode) when the sampling clock is low (Figure 4). The analog input signal source must be able to provide the dynamic currents necessary to charge and discharge the sampling capacitors. To avoid signal degradation, these capacitors must be charged to one-half LSB accuracy within one-half of a clock cycle. The analog input of the MAX12528 supports differential or singleended input drive. For optimum performance with differential inputs, balance the input impedance of IN_P and IN_N and set the common-mode voltage to midsupply (VDD / 2). The MAX12528 provides the optimum common-mode voltage of VDD / 2 through the COM output when operating in internal reference mode and buffered external reference mode. This COM output voltage can be used to bias the input network as shown in Figures 9, 10, and 11.
MAX12528. The power-down logic input (PD) enables and disables the reference circuit. REFOUT has approximately 17k to GND when the MAX12528 is powered down. The reference circuit requires 10ms to power up and settle to its final value when power is applied to the MAX12528 or when PD transitions from high to low. The internal bandgap reference produces a buffered reference voltage of 2.048V 1% at the REFOUT pin with a 50ppm/C temperature coefficient. Connect an external 0.1F bypass capacitor from REFOUT to GND for stability. REFOUT sources up to 1mA and sinks up to 0.1mA for external circuits with a 35mV/mA load regulation. Short-circuit protection limits IREFOUT to a 2.1mA source current when shorted to GND and a 0.24mA sink current when shorted to VDD. Similar to REFOUT, REFIN should be bypassed with a 4.7F capacitor to GND.
Reference Configurations
The MAX12528 full-scale analog input range is 2/3 x VREF with a VDD / 2 0.5V common-mode input range. VREF is the voltage difference between REFAP (REFBP) and REFAN (REFBN). The MAX12528 provides three modes of reference operation. The voltage at REFIN (VREFIN) selects the reference operation mode (Table 1). Connect REFOUT to REFIN either with a direct short or through a resistive divider to enter internal reference mode. COM_, REF_P, and REF_N are low-impedance outputs with VCOM_ = VDD / 2, VREFP = VDD / 2 + 3/8 x VREFIN, and VREF_N = VDD / 2 - 3/8 x VREFIN. Bypass REF_P, REF_N, and COM_ each with a 0.1F capacitor to GND. Bypass REF_P to REF_N with a 10F capacitor.
Reference Output
An internal bandgap reference is the basis for all the internal voltages and bias currents used in the
16
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Dual, 80Msps, 12-Bit, IF/Baseband ADC
Bypass REFIN and REFOUT to GND with a 0.1F capacitor. The REFIN input impedance is very large (>50M). When driving REFIN through a resistive divider, use resistances 10k to avoid loading REFOUT. Buffered external reference mode is virtually identical to the internal reference mode except that the reference source is derived from an external reference and not the MAX12528's internal bandgap reference. In buffered external reference mode, apply a stable reference voltage source between 0.7V to 2.3V at REFIN. Pins COM_, REF_P, and REF_N are low-impedance outputs with VCOM_ = VDD / 2, VREF_P = VDD / 2 + 3/8 x VREFIN, and VREF_N = VDD / 2 - 3/8 x VREFIN. Bypass REF_P, REF_N, and COM_ each with a 0.1F capacitor to GND. Bypass REF_P to REF_N with a 10F capacitor. Connect REFIN to GND to enter unbuffered external reference mode. Connecting REFIN to GND deactivates the on-chip reference buffers for COM_, REF_P, and REF_N. With their buffers deactivated, COM_, REF_P, and REF_N become high-impedance inputs and must be driven with separate, external reference sources. Drive VCOM_ to VDD / 2 5%, and drive REF_P and REF_N so VCOM_ = (VREF_P_ + VREF_N_) / 2. The analog input range is (V REF_P_ - V REF_N ) x 2/3. Bypass REF_P, REF_N, and COM_ each with a 0.1F capacitor to GND. Bypass REF_P to REF_N with a 10F capacitor. For all reference modes, bypass REFOUT with a 0.1F and REFIN with a 4.7F capacitor to GND. The MAX12528 also features a shared reference mode, in which the user can achieve better channel-to-channel matching. When sharing the reference (SHREF = VDD), externally connect REFAP and REFBP together to ensure that VREFAP = VREFBP. Similarly, when sharing the reference, externally connect REFAN to REFBN together to ensure that VREFAN = VREFBN. Connect SHREF to GND to disable the shared reference mode of the MAX12528. In this independent reference mode, a better channel-to-channel isolation is achieved. For detailed circuit suggestions and how to drive the ADC in buffered/unbuffered external reference mode, see the Applications Information section. duty-cycle independent. Due to this DLL, the MAX12528 requires approximately 100 clock cycles to acquire and lock to new clock frequencies.
MAX12528
Clock Input and Clock Control Lines
The MAX12528 accepts both differential and singleended clock inputs with a wide 25% to 75% input clock duty cycle. For single-ended clock input operation, connect DIFFCLK/SECLK and CLKN to GND. Apply an external single-ended clock signal to CLKP. To reduce clock jitter, the external single-ended clock must have sharp falling edges. For differential clock input operation, connect DIFFCLK/SECLK to OV DD . Apply an external differential clock signal to CLKP and CLKN. Consider the clock input as an analog input and route it away from any other analog inputs and digital signal lines. CLKP and CLKN enter high impedance when the MAX12528 is powered down (Figure 4). Low clock jitter is required for the specified SNR performance of the MAX12528. The analog inputs are sampled on the falling (rising) edge of CLKP (CLKN), requiring this edge to have the lowest possible jitter. Jitter limits the maximum SNR performance of any ADC according to the following relationship: 1 SNR = 20 x log 2 x x fIN x t J where fIN represents the analog input frequency and tJ is the total system clock jitter. Clock jitter is especially critical for undersampling applications. For instance, assuming that clock jitter is the only noise source, to obtain the specified 69.8dB of SNR with an input frequency of 175MHz the system must have less than 0.29ps of clock jitter. However, in reality there are other noise sources such as thermal noise and quantization noise that contribute to the system noise requiring the clock jitter to be less than 0.14ps to obtain the specified 69.8dB of SNR at 175MHz. Clock-Divider Control Inputs (DIV2, DIV4) The MAX12528 features three different modes of sampling/clock operation (see Table 2). Pulling both control lines low, the clock-divider function is disabled and the converters sample at full clock speed. Pulling DIV4 low and DIV2 high enables the divide-by-two feature, which sets the sampling speed to one-half the selected clock frequency. In divide-by-four mode, the converter sampling speed is set to one-fourth the clock speed of the MAX12528. Divide-by-four mode is achieved by applying a high level to DIV4 and a low level to DIV2. The option to select either one-half or one-fourth of the clock speed for
Clock Duty-Cycle Equalizer
The MAX12528 has an internal clock duty-cycle equalizer, which makes the converter insensitive to the duty cycle of the signal applied to CLKP and CLKN. The converters allow clock duty-cycle variations from 25% to 75% without negatively impacting the dynamic performance. The clock duty-cycle equalizer uses a delay-locked loop (DLL) to create internal timing signals that are
______________________________________________________________________________________
17
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
Table 2. Clock-Divider Control Inputs
VDD S1H
DIV4
MAX12528
10k
DIV2 0 1 0 1
FUNCTION Clock Divider Disabled fSAMPLE = fCLK Divide-by-Two Clock Divider fSAMPLE = fCLK / 2 Divide-by-Four Clock Divider fSAMPLE = fCLK / 4 Not Allowed
0 0 1
CLKP 10k
S2H
DUTY-CYCLE EQUALIZER 10k
1
S1L CLKN
cuitry can be latched with the rising edge of the conversion clock (CLKP - CLKN). Data-Valid Output DAV is a single-ended version of the input clock that is compensated to correct for any input clock duty-cycle variations. The MAX12528 output data changes on the falling edge of DAV, and DAV rises once the output data is valid. The falling edge of DAV is synchronized to have a 5.4ns delay from the falling edge of the input clock. Output data at D0A/B-D11A/B and DORA/B are valid from 7ns before the rising edge of DAV to 7ns after the rising edge of DAV. DAV enters high impedance when the MAX12528 is powered down (PD = OV DD ). DAV enters its highimpedance state 10ns after the rising edge of PD and becomes active again 10ns after PD transitions low. DAV is capable of sinking and sourcing 600A and has three times the driving capabilities of D0A/B-D11A/B and DORA/B. DAV is typically used to latch the MAX12528 output data into an external digital back-end circuit. Keep the capacitive load on DAV as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX12528, thereby degrading its dynamic performance. Buffering DAV
10k SWITCHES S1_ AND S2_ ARE OPEN DURING POWER-DOWN MAKING CLKP AND CLKN HIGH IMPEDANCE. SWITCHES S2_ ARE OPEN IN SINGLE-ENDED CLOCK MODE.
S2L GND
Figure 4. Simplified Clock Input Circuit
sampling provides design flexibility, relaxes clock requirements, and can minimize clock jitter.
System Timing Requirements
Figure 5 shows the timing relationship between the clock, analog inputs, DAV indicator, DOR_ indicators, and the resulting output data. The analog input is sampled on the falling (rising) edge of CLKP (CLKN) and the resulting data appears at the digital outputs 8 clock cycles later. The DAV indicator is synchronized with the digital output and optimized for use in latching data into digital back-end circuitry. Alternatively, digital back-end cirDIFFERENTIAL ANALOG INPUT (IN_P-IN_N) (VREF_P - VREF_N) x 2/3 N+3 N-3 N-2 N-1 N N+1 N +2 N+4 N+5 N+6
N+7 N+8
N+9
(VREF_N - VREF_P) x 2/3 tAD CLKN CLKP tDAV DAV tSETUP D0_-D11_ tHOLD N-3 8.0 CLOCK-CYCLE DATA LATENCY DOR N-2 tCL tCH
N-1
N
N+1
N+2
N+3
N+4
N+5 tSETUP
N+6
N+7
N+8
N+9 tHOLD
Figure 5. System Timing Diagram 18 ______________________________________________________________________________________
Dual, 80Msps, 12-Bit, IF/Baseband ADC
externally isolates it from heavy capacitive loads. Refer to the MAX12557 EV kit schematic for recommendations of how to drive the DAV signal through an external buffer. Data Out-of-Range Indicator The DORA and DORB digital outputs indicate when the analog input voltage is out of range. When DOR_ is high, the analog input is out of range. When DOR_ is low, the analog input is within range. The valid differential input range is from (V REF_P - V REF_N ) x 2/3 to (V REF_N VREF_P) x 2/3. Signals outside of this valid differential range cause DOR_ to assert high as shown in Table 1. DOR is synchronized with DAV and transitions along with the output data D11-D0. There is an 8 clock-cycle latency in the DOR function as is with the output data (Figure 5). DOR_ is high impedance when the MAX12528 is in power-down (PD = high). DOR_ enters a high-impedance state within 10ns after the rising edge of PD and becomes active 10ns after PD's falling edge. Digital Output Data and Output Format Selection The MAX12528 provides two 12-bit, parallel, tri-state output buses. D0A/B-D11A/B and DORA/B update on the falling edge of DAV and are valid on the rising edge of DAV. The MAX12528 output data format is either Gray code or two's complement depending on the logic input G/T. With G/T high, the output data format is Gray code. With G/T low, the output data format is set to two's complement. See Figure 8 for a binary-to-Gray and Gray-tobinary code conversion example. The following equations, Table 3, Figure 6, and Figure 7 define the relationship between the digital output and the analog input. Gray Code (G/T = 1): VIN_P - VIN_N = 2/3 x (VREF_P - VREF_N) x 2 x (CODE10 - 2048) / 4096 Two's Complement (G/T = 0): VIN_P - VIN_N = 2/3 x (VREF_P - VREF_N) x 2 x CODE10 / 4096 where CODE10 is the decimal equivalent of the digital output code as shown in Table 3.
MAX12528
Table 3. Output Codes vs. Input Voltage
GRAY-CODE OUTPUT CODE (G/T = 1) DECIMAL HEXADECIMAL EQUIVALENT EQUIVALENT OF DOR OF D11A-D0A D11A-D0A D11B-D0B D11B-D0B (CODE10) 1 0 0 0 0 0 0 0 0 0 1 0x800 0x800 0x801 0xC03 0xC01 0xC00 0x400 0x401 0x001 0x000 0x000 +4095 +4095 +4094 +2050 +2049 +2048 +2047 +2046 +1 0 0 TWO'S COMPLEMENT OUTPUT CODE (G/T = 0) DECIMAL VIN_P - VIN_N HEXADECIMAL EQUIVALENT VREF_P = 2.418V EQUIVALENT OF VREF_N = 0.882V DOR OF D11A-D0A D11A-D0A D11B-D0B D11B-D0B (CODE10) 1 0 0 0 0 0 0 0 0 0 1 0x7FF 0x7FF 0x7FE 0x002 0x001 0x000 0xFFF 0xFFE 0x801 0x800 0x800 +2047 +2047 +2046 +2 +1 0 -1 -2 -2047 -2048 -2048 >+1.0235V (DATA OUT OF RANGE) +1.0235V +1.0230V +0.0010V +0.0005V +0.0000V -0.0005V -0.0010V -1.0235V -1.0240V <-1.0240V (DATA OUT OF RANGE)
BINARY D11A-D0A D11B-D0B
BINARY D11A-D0A D11B-D0B
1000 0000 0000 1000 0000 0000 1000 0000 0001 1100 0000 0011 1100 0000 0001 1100 0000 0000 0100 0000 0000 0100 0000 0001 0000 0000 0001 0000 0000 0000 0000 0000 0000
0111 1111 1111 0111 1111 1111 0111 1111 1110 0000 0000 0010 0000 0000 0001 0000 0000 0000 1111 1111 1111 1111 1111 1110 1000 0000 0001 1000 0000 0000 1000 0000 0000
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19
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
1 LSB = 4/3 x (VREFP - VREFN) / 4096 2/3 x (VREFP - VREFN) 0x7FF 0x7FE 0x7FD GRAY OUTPUT CODE (LSB) 2/3 x (VREFP - VREFN) 0x800 0x801 0x803 1 LSB = 4/3 x (VREFP - VREFN) / 4096 2/3 x (VREFP - VREFN) 2/3 x (VREFP - VREFN)
TWO'S-COMPLEMENT OUTPUT CODE (LSB)
0x001 0x000 0xFFF
0xC01 0xC00 0xC00
0x803 0x802 0x801 0x800 -2047 -2045 -1 0 +1 +2045 +2047
0x002 0x003 0x001 0x000 -2047 -2045 -1 0 +1 +2045 +2047
DIFFERENTIAL INPUT VOLTAGE (LSB)
DIFFERENTIAL INPUT VOLTAGE (LSB)
Figure 6. Two's-Complement Transfer Function (G/T = 0)
Figure 7. Gray-Code Transfer Function (G/T = 1)
The digital outputs D0A/B-D11A/B are high impedance when the MAX12528 is in power-down (PD = 1) mode. D0A/B-D11A/B enter this state 10ns after the rising edge of PD and become active again 10ns after PD transitions low. Keep the capacitive load on the MAX12528 digital outputs D0A/B-D11A/B as low as possible (<15pF) to avoid large digital currents feeding back into the analog portion of the MAX12528 and degrading its dynamic performance. Adding external digital buffers on the digital outputs helps isolate the MAX12528 from heavy capacitive loads. To improve the dynamic performance of the MAX12528, add 220 resistors in series with the digital outputs close to the MAX12528. Refer to the MAX12557 EV kit schematic for guidelines of how to drive the digital outputs through 220 series resistors and external digital output buffers.
In power-down mode all internal circuits are off, the analog supply current reduces to less than 100A, and the digital supply current reduces to less than 1A. The following list shows the state of the analog inputs and digital outputs in power-down mode: 1) INAP/B and INAN/B analog inputs are disconnected from the internal input amplifier (Figure 3). 2) REFOUT has approximately 17k to GND. 3) REFAP/B, COMA/B, and REFAN/B enter a highimpedance state with respect to VDD and GND, but there is an internal 4k resistor between REFAP/B and COMA/B, as well as an internal 4k resistor between REFAN/B and COMA/B. 4) D0A-D11A, D0B-D11B, DORA, and DORB enter a high-impedance state. 5) DAV enters a high-impedance state. 6) CLKP and CLKN clock inputs enter a high-impedance state (Figure 4). The wake-up time from power-down mode is dominated by the time required to charge the capacitors at REF_P, REF_N, and COM. In internal reference mode and buffered external reference mode the wake-up time is typically 10ms. When operating in the unbuffered external reference mode the wake-up time is dependent on the external reference drivers.
Power-Down Input
The MAX12528 has two power modes that are controlled with a power-down digital input (PD). With PD low, the MAX12528 is in its normal operating mode. With PD high, the MAX12528 is in power-down mode. The power-down mode allows the MAX12528 to efficiently use power by transitioning to a low-power state when conversions are not required. Additionally, the MAX12528 parallel output bus goes high-impedance in power-down mode, allowing other devices on the bus to be accessed.
20
______________________________________________________________________________________
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
BINARY-TO-GRAY CODE CONVERSION 1) THE MOST SIGNIFICANT GRAY-CODE BIT IS THE SAME AS THE MOST SIGNIFICANT BINARY BIT. D11 0 0 1 1 1 D7 0 1 0 0 D3 1 1 0 D0 0 BIT POSITION BINARY GRAY CODE GRAY-TO-BINARY CODE CONVERSION 1) THE MOST SIGNIFICANT BINARY BIT IS THE SAME AS THE MOST SIGNIFICANT GRAY-CODE BIT. D11 0 0 1 0 0 D7 1 1 1 0 D3 1 0 1 D0 0 BIT POSITION GRAY CODE BINARY
2) SUBSEQUENT GRAY-CODE BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: GRAYX = BINARYX + BINARYX + 1 WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION: GRAY10 = BINARY10 + BINARY11 GRAY10 = 1 + 0 GRAY10 = 1
2) SUBSEQUENT BINARY BITS ARE FOUND ACCORDING TO THE FOLLOWING EQUATION: BINARYX = BINARYX+1 + GRAYX WHERE + IS THE EXCLUSIVE OR FUNCTION (SEE TRUTH TABLE BELOW) AND X IS THE BIT POSITION: BINARY10 = BINARY11 + GRAY10 BINARY10 = 0 + 1 BINARY10 = 1
D11 0 0 + 1 1 1 1
D7 0 1 0 0
D3 1 1 0
D0 0
BIT POSITION BINARY GRAY CODE 0
D11 1 + 0 1 0 0
D7 1 1 1 0
D3 1 0 1
D0 0
BIT POSITION GRAY CODE BINARY
3) REPEAT STEP 2 UNTIL COMPLETE: GRAY9 = BINARY9 + BINARY10 GRAY9 = 1 + 1 GRAY9 = 0
3) REPEAT STEP 2 UNTIL COMPLETE: BINARY9 = BINARY10 + GRAY9 BINARY9 = 1 + 0 BINARY9 = 1
D11 0 0 1 1 + 1 0 1
D7 0 1 0 0
D3 1 1 0
D0 0
BIT POSITION BINARY GRAY CODE 0 0
D11 1 + 1 1 0 0
D7 1 1 1 0
D3 1 0 1
D0 0
BIT POSITION GRAY CODE BINARY
4) THE FINAL GRAY-CODE CONVERSION IS: D11 0 0 1 1 1 0 1 0 D7 0 1 1 1 0 1 0 0 D3 1 1 1 0 0 1 D0 0 0 BIT POSITION BINARY GRAY CODE
4) THE FINAL BINARY CONVERSION IS: D11 0 0 1 1 0 1 0 1 D7 1 0 1 1 1 0 0 0 D3 1 1 0 1 1 0 D0 0 0 BIT POSITION GRAY CODE BINARY
EXCLUSIVE OR TRUTH TABLE FIGURE 8 SHOWS THE GRAY-TO-BINARY AND BINARY-TO-GRAY CODE CONVERSION IN OFFSET BINARY FORMAT. THE OUTPUT FORMAT OF THE MAX12528 IS TWO'S-COMPLEMENT BINARY, HENCE EACH MSB OF THE TWO'S-COMPLEMENT OUTPUT CODE MUST BE INSERTED TO REFLECT TRUE OFFSET BINARY FORMAT. A 0 0 1 1 B 0 1 0 1 Y = A + 0 1 1 0 B
Figure 8. Binary-to-Gray and Gray-to-Binary Code Conversion ______________________________________________________________________________________ 21
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
Applications Information
Using Transformer Coupling
In general, the MAX12528 provides better SFDR and THD with fully differential input signals than singleended input drive, especially for input frequencies above 125MHz. In differential input mode, even-order harmonics are lower as both inputs are balanced, and each of the ADC inputs only requires half the signal swing compared to single-ended input mode. An RF transformer (Figure 9) provides an excellent solution to convert a single-ended input source signal to a fully differential signal, required by the MAX12528 for optimum performance. Connecting the center tap of the transformer to COM provides a VDD / 2 DC level shift to the input. Although a 1:1 transformer is shown, a step-up transformer can be selected to reduce the drive requirements. A reduced signal swing from the input driver, such as an op amp, can also improve the overall distortion. The configuration of Figure 9 is good for frequencies up to Nyquist (fCLK / 2). The circuit of Figure 10 converts a single-ended input signal to fully differential just as Figure 9. However, Figure 10 utilizes an additional transformer to improve the common-mode rejection allowing high-frequency signals beyond the Nyquist frequency. A set of 75 and 113 termination resistors provide an equivalent 50 termination to the signal source. The second set of termination resistors connects to COM_ providing the correct input common-mode voltage. Two 0 resistors in series with the analog inputs allow high IF input frequencies. These 0 resistors can be replaced with lowvalue resistors to limit the input bandwidth.
Single-Ended AC-Coupled Input Signal
Figure 11 shows an AC-coupled, single-ended input application. The MAX4108 provides high speed, high bandwidth, low noise, and low distortion to maintain the input signal integrity.
24.9 IN_P 5.6pF 0.1F VIN N.C.
VIN 0.1F
MAX4108
1 T1 5 3
6 2 0.1F 4
MAX12528
COM_
100
0 IN_P 5.6pF 24.9
MAX12528
COM_ 0.1F
MINICIRCUITS TT1-6 OR T1-1T
100
24.9 IN_N 5.6pF
24.9 IN_N 5.6pF
Figure 9. Transformer-Coupled Input Drive for Input Frequencies Up to Nyquist
Figure 11. Single-Ended, AC-Coupled Input Drive
0* 0.1F VIN N.C. 1 5 T1 6 2 75 1% N.C. 75 1% N.C. 1 5 T2 6 2 113 0.5% N.C. 0.1F 3 4 MINICIRCUITS ADT1-1WT 3 4 MINICIRCUITS ADT1-1WT 113 0.5% 0* IN_N 5.6pF *0 RESISTORS CAN BE REPLACED WITH LOW-VALUE RESISTORS TO LIMIT THE INPUT BANDWIDTH. COM_ IN_P 5.6pF
MAX12528
Figure 10. Transformer-Coupled Input Drive for Input Frequencies beyond Nyquist
22
______________________________________________________________________________________
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
3.3V
0.1F
2.2F
VDD REFIN 0.1F 1 5 16.2k 1F 3 5 1
MAX4230
REF_P 0.1F
0.1F
2.048V
MAX12528
47 300F 6V REF_N
10F
0.1F
MAX6029 (EUK21)
2
4
2 REFOUT 0.1F GND COM_
0.1F
1.47k
0.1F
NOTE: ONE FRONT-END REFERENCE CIRCUIT IS CAPABLE OF SOURCING UP TO 15mA AND SINKING UP TO 30mA OF OUTPUT CURRENT.
3.3V
0.1F
2.2F
VDD REFIN REF_P 0.1F
MAX12528
REF_N
10F
0.1F
0.1F
REFOUT 0.1F GND
COM_ 0.1F
Figure 12. External Buffered (MAX4230) Reference Drive Using a MAX6029 Bandgap Reference
Buffered External Reference Drives Multiple ADCs
The buffered external reference mode allows for more control over the MAX12528 reference voltage and allows multiple converters to use a common reference. The REFIN input impedance is >50M. Figure 12 shows the MAX6029 precision 2.048V bandgap reference used as a common reference for multiple converters. The 2.048V output of the MAX6029 passes through a single-pole 10Hz LP filter to the MAX4230.
The MAX4250 buffers the 2.048V reference and provides additional 10Hz LP filtering before its output is applied to the REFIN input of the MAX12528.
Unbuffered External Reference Drives Multiple ADCs
The unbuffered external reference mode allows for precise control over the MAX12528 reference and allows multiple converters to use a common reference. Connecting REFIN to GND disables the internal reference,
23
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Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
3.3V 3V 0.1F 1 5 20k 1% 0.1F 20k 1% 1 4
MAX4230
0.1F
2.2F
MAX6029 (EUK30)
2
REF_P
VDD REFOUT
10F 2.413V 47 0.1F 330F 6V 1.47k
0.1F
0.1F
MAX12528
REF_N
0.47F 52.3k 1%
3
10F 6V
COM_ 0.1F 1 4
MAX4230
GND
REFIN
1.647V 47 3.3V 10F 6V 1.47k 0.1F 2.2F 330F 6V
3 52.3k 1%
1 4 20k 1%
MAX4230
0.880V 47 0.1F 10F 6V 1.47k 0.1F 330F 6V 10F 0.1F REF_P VDD REFOUT 0.1F
3
20k 1%
MAX12528
REF_N
20k 1% COM_ 0.1F REFIN
GND
Figure 13. External Unbuffered Reference Driving Multiple ADCs
allowing REF_P, REF_N, and COM_ to be driven directly by a set of external reference sources. Figure 13 uses a MAX6029 precision 3.000V bandgap reference as a common reference for multiple converters. A seven-component resistive divider chain follows the MAX6029 voltage reference. The 0.47F capacitor along this chain creates a 10Hz LP filter. Three MAX4230 amplifiers buffer taps along this resistor chain providing 2.413V, 1.647V, and 0.880V to the MAX12528 REF_P, REF_N, and COM_ reference inputs. The feedback around the MAX4230 op amps provides additional 10Hz LP filtering. Reference voltages 2.413V and 0.880V set the full-scale analog input
24
range for the converter to 1.022V ([VREF_P - VREF_N] x 2/3). Note that one single power supply for all active circuit components removes any concern regarding powersupply sequencing when powering up or down.
Grounding, Bypassing, and Board Layout
The MAX12528 requires high-speed board layout design techniques. Refer to the MAX12528 EV kit data sheet for a board layout reference. Locate all bypass capacitors as close to the device as possible, preferably on the same side as the ADC, using surface-
______________________________________________________________________________________
Dual, 80Msps, 12-Bit, IF/Baseband ADC
mount devices for minimum inductance. Bypass VDD to GND with a 220F ceramic capacitor in parallel with at least one 10F, one 4.7F, and one 0.1F ceramic capacitor. Bypass OVDD to GND with a 220F ceramic capacitor in parallel with at least one 10F, one 4.7F, and one 0.1F ceramic capacitor. High-frequency bypassing/decoupling capacitors should be located as close as possible to the converter supply pins. Multilayer boards with ample ground and power planes produce the highest level of signal integrity. All grounds and the exposed backside paddle of the MAX12528 package (package code: T6800-2) must be connected to the same ground plane. The MAX12528 relies on the exposed backside paddle connection for a low-inductance ground connection. Isolate the ground plane from any noisy digital system ground planes such as a DSP or output buffer ground. Route high-speed digital signal traces away from the sensitive analog traces. Keep all signal lines short and free of 90 turns. Ensure that the differential, analog input network layout is symmetric and that all parasitic components are balanced equally. Refer to the MAX12528 EV kit data sheet for an example of symmetric input layout.
Gain Error
Gain error is a figure of merit that indicates how well the slope of the actual transfer function matches the slope of the ideal transfer function. The slope of the actual transfer function is measured between two data points: positive full scale and negative full scale. Ideally, the positive full-scale MAX12528 transition occurs at 1.5 LSBs below positive full scale, and the negative full-scale transition occurs at 0.5 LSB above negative full scale. The gain error is the difference of the measured transition points minus the difference of the ideal transition points.
MAX12528
Small-Signal Noise Floor (SSNF)
SSNF is the integrated noise and distortion power in the Nyquist band for small-signal inputs. The DC offset is excluded from this noise calculation. For this converter, a small signal is defined as a single tone with an amplitude of -35dBFS. This parameter captures the thermal and quantization noise characteristics of the data converter and can be used to help calculate the overall noise figure of a digital receiver signal path.
Signal-to-Noise Ratio (SNR)
For a waveform perfectly reconstructed from digital samples, the theoretical maximum SNR is the ratio of the full-scale analog input (RMS value) to the RMS quantization error (residual error). The ideal, theoretical minimum analog-to-digital noise is caused by quantization error only and results directly from the ADC's resolution (N bits): SNR[max] = 6.02 x N + 1.76 In reality, there are other noise sources besides quantization noise: thermal noise, reference noise, clock jitter, etc. SNR is computed by taking the ratio of the RMS signal to the RMS noise. RMS noise includes all spectral components to the Nyquist frequency excluding the fundamental, the first six harmonics (HD2 through HD7), and the DC offset. SNR = 20 x log (SIGNALRMS / NOISERMS)
Parameter Definitions
Integral Nonlinearity (INL)
INL is the deviation of the values on an actual transfer function from a straight line. For the MAX12528, this straight line is between the endpoints of the transfer function, once offset and gain errors have been nullified. INL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.
Differential Nonlinearity (DNL)
DNL is the difference between an actual step width and the ideal value of 1 LSB. A DNL error specification of less than 1 LSB guarantees no missing codes and a monotonic transfer function. For the MAX12528, DNL deviations are measured at every step of the transfer function and the worst-case deviation is reported in the Electrical Characteristics table.
Signal-to-Noise Plus Distortion (SINAD)
SINAD is computed by taking the ratio of the RMS signal to the RMS noise plus distortion. RMS noise plus distortion includes all spectral components to the Nyquist frequency excluding the fundamental and the DC offset.
Offset Error
Offset error is a figure of merit that indicates how well the actual transfer function matches the ideal transfer function at a single point. Ideally, the midscale MAX12528 transition occurs at 0.5 LSB above midscale. The offset error is the amount of deviation between the measured midscale transition point and the ideal midscale transition point.
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25
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
Total Harmonic Distortion (THD)
THD is the ratio of the RMS sum of the first six harmonics of the input signal to the fundamental itself. This is expressed as:
V22 + V32 + V4 2 + V52 + V62 + V72 THD = 20 x log V1
CLKN CLKP tAD ANALOG INPUT tAJ SAMPLED DATA
where V1 is the fundamental amplitude, and V2 through V7 are the amplitudes of the 2nd- through 7th-order harmonics (HD2 through HD7).
Spurious-Free Dynamic Range (SFDR)
SFDR is the ratio expressed in decibels of the RMS amplitude of the fundamental (maximum signal component) to the RMS value of the next largest spurious component, excluding DC offset.
T/H
HOLD
TRACK
HOLD
Figure 14. T/H Aperture Timing
Aperture Delay
Aperture delay (tAD) is the time defined between the rising edge of the sampling clock and the instant when an actual sample is taken (Figure 14).
Intermodulation Distortion (IMD)
IMD is the total power of the IM2 to IM5 intermodulation products to the Nyquist frequency relative to the total input power of the two input tones fIN1 and fIN2. The individual input tone levels are at -7dBFS. The intermodulation products are as follows: 2nd-Order Intermodulation products (IM2): fIN1 = fIN2, fIN2 - fIN1 3rd-Order Intermodulation products (IM3): 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1 4th-Order Intermodulation products (IM4): 3 x fIN1 - fIN2, 3 x fIN2 - fIN1, 3 x fIN1 + fIN2, 3 x fIN2 + fIN1, 2 x fIN1 - 2 x fIN2, 2 x fIN1 + 2 x fIN2, 2 x fIN2 - 2 x fIN1 5th-Order Intermodulation products (IM5): 3 x fIN1 - 2 x fIN2, 3 x fIN2 - 2 x fIN1, 3 x fIN1 + 2 x fIN2, 3 x fIN2 + 2 x fIN1, 4 x fIN1 - fIN2, 4 x fIN2 - fIN1, 4 x fIN1 + fIN2, 4 x fIN2 + fIN1 Note that the two-tone intermodulation distortion is measured with respect to a single-carrier amplitude and not the peak-to-average input power of both input tones.
Full-Power Bandwidth
A large -0.2dBFS analog input signal is applied to an ADC and the input frequency is swept up to the point where the amplitude of the digitized conversion result has decreased by -3dB. This point is defined as fullpower input bandwidth frequency.
Output Noise (nOUT)
The output noise (nOUT) parameter is similar to thermal plus quantization noise and is an indication of the converter's overall noise performance. No fundamental input tone is used to test for nOUT. IN_P, IN_N, and COM_ are connected together and 1024k data points are collected. nOUT is computed by taking the RMS value of the collected data points after the mean is removed.
Overdrive Recovery Time
Overdrive recovery time is the time required for the ADC to recover from an input transient that exceeds the full-scale limits. The MAX12528 specifies overdrive recovery time using an input transient that exceeds the full-scale limits by 10%. The MAX12528 requires one clock cycle to recover from an overdrive condition.
3rd-Order Intermodulation (IM3)
IM3 is the total power of the 3rd-order intermodulation product to the Nyquist frequency relative to the total input power of the two input tones fIN1 and fIN2. The individual input tone levels are at -7dBFS. The 3rdorder intermodulation products are 2 x fIN1 - fIN2, 2 x fIN2 - fIN1, 2 x fIN1 + fIN2, 2 x fIN2 + fIN1.
Crosstalk
Coupling onto one channel being driven by a (-0.5dBFS) signal when the adjacent interfering channel is driven by a full-scale signal. Measurement includes all spurs resulting from both direct coupling and mixing components.
Aperture Jitter
Figure 14 shows the aperture jitter (tAJ), which is the sample-to-sample variation in the aperture delay.
26
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Dual, 80Msps, 12-Bit, IF/Baseband ADC
Gain Matching
Gain matching is a figure of merit that indicates how well the gains between the two channels are matched to each other. The same input signal is applied to both channels and the maximum deviation in gain is reported (typically in dB) as gain matching.
TOP VIEW
OVDD N.C. DAV N.C. D4A D3A D2A D1A D0A
Pin Configuration
DORB D11B D10B D9B D8B D7B D6B D5B
MAX12528
51
50 49 48 47
46 45 44 43 42 41
40 39 38 37 36 35 34 D4B 33 D3B 32 D2B 31 D1B 30 D0B 29 N.C. 28 N.C. 27 OVDD
D5A 52 D6A 53 D7A 54 D8A 55 D9A 56 D10A 57 D11A 58 DORA 59 OVDD 60 VDD 61 VDD 62 VDD 63 G/T 64 PD 65 SHREF 66 REFOUT 67 REFIN 68
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17
Offset Matching
Like gain matching, offset matching is a figure of merit that indicates how well the offsets between the two channels are matched to each other. The same input signal is applied to both channels and the maximum deviation in offset is reported (typically in %FSR) as offset matching.
MAX12528
26 VDD 25 VDD 24 VDD 23 VDD 22 DIV4 21 DIV2
EXPOSED PADDLE (GND)
20 CLKP 19 CLKN 18 DIFFCLK/SECLK
INAN
INAP
GND
GND
COMA
GND
COMB
GND
GND
REFAN
REFBN
REFAP
REFBP
INBN
GND
THIN QFN
______________________________________________________________________________________
INBP
GND
27
Dual, 80Msps, 12-Bit, IF/Baseband ADC MAX12528
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
68L QFN THIN.EPS
PACKAGE OUTLINE 68L THIN QFN, 10x10x0.8mm
21-0142
C
1
2
PACKAGE OUTLINE 68L THIN QFN, 10x10x0.8mm
21-0142
C
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
28 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2005 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products, Inc.

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