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19-3279; Rev 0; 5/04
KIT ATION EVALU ABLE AVAIL
Low-Voltage DDR Linear Regulator
General Description Features
o Internal Power MOSFETs with Current Limit (3A typ) o Fast Load-Transient Response o External Reference Input with Reference Output Buffer o 1.1V to 3.6V Power Input o 15mV (max) Load-Regulation Error o Thermal Fault Protection o Shutdown Input o Power-Good Window Comparator with 2ms (typ) Delay o Small, Low-Profile 10-Pin 3mm x 3mm TDFN Package o Ceramic or Polymer Output Capacitors
MAX1510
The MAX1510 DDR linear regulator sources and sinks up to 3A peak (typ) using internal n-channel MOSFETs. This linear regulator delivers an accurate 0.5V to 1.5V output from a low-voltage power input (VIN = 1.1V to 3.6V). The MAX1510 uses a separate 3.3V bias supply to power the control circuitry and drive the internal n-channel MOSFETs. The MAX1510 provides current and thermal limits to prevent damage to the linear regulator. Additionally, the MAX1510 generates a power-good (PGOOD) signal to indicate that the output is in regulation. During startup, PGOOD remains low until the output is in regulation for 2ms (typ). The internal soft-start limits the input surge current. The MAX1510 powers the active-DDR termination bus that requires a tracking input reference. The MAX1510 can also be used in low-power chipsets and graphics processor cores that require dynamically adjustable output voltages. The MAX1510 is available in a 10-pin 3mm x 3mm thin DFN package.
Applications
Notebook/Desktop Computers DDR Memory Termination Active Termination Buses Graphics Processor Core Supplies Chipset/RAM Supplies as Low as 0.5V
MAX1510ETB PART
Ordering Information
TEMP RANGE -40C to +85C PINPACKAGE 10 TDFN (3mm x 3mm) TOP MARK ABD
Pin Configuration
TOP VIEW
Typical Operating Circuit
VIN (1.1V TO 3.6V) IN OUT OUTS VOUT = VTT
REFOUT 1 VCC 2 AGND 3 REFIN 4
10 IN 9 OUT
VBIAS (2.7V TO 3.6V) VCC SHDN PGOOD VDDQ (2.5V OR 1.8V) REFIN REFOUT VREFOUT = VTTR
MAX1510
PGND AGND
MAX1510
8 PGND 7 SHDN 6 OUTS
PGOOD 5
TDFN 3mm x 3mm
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim/Dallas Direct! at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Low-Voltage DDR Linear Regulator MAX1510
ABSOLUTE MAXIMUM RATINGS
IN to PGND...............................................................-0.3V to +4V OUT to PGND ..............................................-0.3V to (VIN + 0.3V) OUTS to AGND ............................................-0.3V to (VIN + 0.3V) VCC to AGND............................................................-0.3V to +4V REFIN, REFOUT, SHDN, PGOOD to AGND ..-0.3V to (VCC + 0.3V) PGND to AGND .....................................................-0.3V to +0.3V REFOUT Short Circuit to AGND .................................Continuous OUT Continuous RMS Current: 100s ..................................1.6A 1s......................................2.5A Continuous Power Dissipation (TA = +70C) 10-Pin 3mm x 3mm Thin DFN (derated 24.4mW/C above +70C)...........................1951mW Operating Temperature Range MAX1510ETB...................................................-40C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TA = -40C to +85C, unless otherwise noted. Typical values are at TA= +25C.) (Note 1)
PARAMETER Input Voltage Range Quiescent Supply Current (VCC) Shutdown Supply Current (VCC) Quiescent Supply Current (VIN) Shutdown Supply Current (VIN) Feedback-Voltage Error Load-Regulation Error Line-Regulation Error OUTS Input Bias Current OUTPUT Output Adjust Range OUT On-Resistance Output Current Slew Rate OUT Power-Supply Rejection Ratio OUT to OUTS Resistance Discharge MOSFET OnResistance PSRR ROUTS RDISCHARGE SHDN = GND High-side MOSFET (source) (IOUT = 0.1A) Low-side MOSFET (sink) (IOUT = -0.1A) COUT = 100F, IOUT = 0.1A to 2A 10Hz < f < 10kHz, IOUT = 200mA, COUT = 100F 0.5 0.10 0.10 3 80 12 8 1.5 0.25 0.25 V A/s dB k IOUTS SYMBOL VIN VCC ICC ICC(SHDN) IIN IIN(SHDN) VOUTS Power input Bias supply Load = 0, VREFIN > 0.45V SHDN = GND, VREFIN > 0.45V SHDN = GND, REFIN = GND Load = 0 SHDN = GND REFIN to OUTS IOUT = 200mA -1A IOUT +1A 1.4V VIN 3.3V, IOUT = 100mA -1 TA = 25C TA = -40C to +85C -4 -6 -15 1 +1 CONDITIONS MIN 1.1 2.7 0.7 350 50 0.4 0.1 0 TYP MAX 3.6 3.6 1.3 600 100 10 10 +4 +6 +15 UNITS V mA A A mA A mV mV mV A
2
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Low-Voltage DDR Linear Regulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN = 1.8V, VCC = 3.3V, VREFIN = VOUTS = 1.25V, SHDN = VCC, circuit of Figure 1, TA = -40C to +85C, unless otherwise noted. Typical values are at TA= +25C.) (Note 1)
PARAMETER REFERENCE REFIN Voltage Range REFIN Input Bias Current REFIN Undervoltage-Lockout Voltage REFOUT Voltage REFOUT Load Regulation FAULT DETECTION Thermal-Shutdown Threshold VCC Undervoltage-Lockout Threshold IN Undervoltage-Lockout Threshold Current-Limit Threshold Soft-Start Current-Limit Time INPUTS AND OUTPUTS PGOOD Lower Trip Threshold PGOOD Upper Trip Threshold PGOOD Propagation Delay PGOOD Startup Delay PGOOD Output Low Voltage PGOOD Leakage Current SHDN Logic Input Threshold SHDN Logic Input Current IPGOOD tPGOOD With respect to feedback threshold, hysteresis = 12mV With respect to feedback threshold, hysteresis = 12mV OUTS forced 25mV beyond PGOOD trip threshold Startup rising edge, OUTS within 100mV of the feedback threshold ISINK = 4mA OUTS = REFIN (PGOOD high impedance), PGOOD = VCC + 0.3V Logic high Logic low SHDN = VCC or GND 0.8 -1 +1 -200 100 5 1 -150 150 10 2 -100 200 35 3.5 0.3 1 2.0 mV mV s ms V A V V A ILIMIT tSS TSHDN VUVLO Rising edge, hysteresis = 15C Rising edge, hysteresis = 100mV Rising edge, hysteresis = 55mV 1.8 2.45 +165 2.55 0.9 3 200 2.65 1.1 4.2 C V V A s VREFOUT VREFOUT VREFIN IREFIN Rising edge, hysteresis = 75mV VCC = 3.3V, IREFOUT = 0 IREFOUT = 5mA VREFIN -0.01 -20 0.5 -1 0.35 VREFIN 1.5 +1 0.45 VREFIN +0.01 +20 V A V V mV SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX1510
Note 1: Limits are 100% production tested at TA = +25C. Limits over the operating temperature range are guaranteed through correlation using statistical-quality-control (SQC) methods.
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3
Low-Voltage DDR Linear Regulator MAX1510
Typical Operating Characteristics
(Circuit of Figure 1. TA = +25C, unless otherwise noted)
MAXIMUM OUTPUT CURRENT vs. INPUT VOLTAGE
MAX1510 toc02
OUTPUT LOAD REGULATION
VREFIN = 0.9V
MAX1510 toc01
OUTPUT LOAD REGULATION
1.300 3.0 VREFIN = 1.25V
VOUT = 0.9V MAXIMUM OUTPUT CURRENT (A) 2.5 2.0 1.5 1.0 0.5 0
0.94 0.92 VOUT (V) 0.90 0.88 0.86 0.84 -3 -2 -1 0 IOUT (A) 1 2 3 VIN = 1.2V
VOUT = 1.25V
1.275 VIN = 1.5V VIN = 1.8V 1.250
VOUT (V)
THERMALLY LIMITED DROPOUT VOLTAGE LIMITED
1.225
VIN = 1.5V
1.200 -3 -2 -1 0 IOUT (A) 1 2 3
1.0
1.5
2.0
2.5
3.0
INPUT VOLTAGE (V)
INPUT CURRENT (IIN) vs. INPUT VOLTAGE (VIN)
MAX1510 toc04
BIAS CURRENT (ICC) vs. INPUT VOLTAGE (VIN)
MAX1510 toc05
BIAS CURRENT (ICC) vs. LOAD CURRENT (IOUT)
VIN = 1.5V 1.2 1.0 ICC (mA) 0.8 VOUT = 0.90V 0.6 0.4 0.2 ENTERING DROPOUT VOUT = 1.25V
MAX1510 toc06
250 VOUT = 1.25V VOUT = 0.90V
1.0 0.9 0.8 0.7
IIN (mA)
1.4
200
VOUT = 1.25V
IIN (A)
150
0.6 0.5 0.4 0.3 DROPOUT
100
50
0.2 0.1
0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 VIN (V)
0.0 0.0 0.5
INPUT UVLO 1.0 1.5 2.0 2.5 3.0 3.5
0.0 -2 -1 0 IOUT (A) 1 2
VIN (V)
POWER GROUND CURRENT (IPGND) vs. SOURCE LOAD CURRENT (IOUT)
MAX1510 toc07
INPUT CURRENT (IIN) vs. SINK LOAD CURRENT (IOUT)
VIN = 1.5V 6 5
MAX1510 toc08
DROPOUT VOLTAGE vs. OUTPUT CURRENT
MAX1510 toc09
0.25 VIN = 1.5V 0.20
7
0.6 0.5 DROPOUT VOLTAGE (V) 0.4 0.3 0.2 0.1 0 VOUT = 0.9V VOUT = 1.25V
IPGND (mA)
ICC (mA)
0.15 VOUT = 1.25V ENTERING DROPOUT
4 3
VOUT = 0.90V VOUT = 1.25V
0.10
2 0.05 VOUT = 0.90V 1 0 0.0 0.5 1.0 IOUT (A) 1.5 2.0 -2.0 -1.5 -1.0 IOUT (A) -0.5 0.0
0.00
0
0.5
1.0
1.5
2.0
2.5
3.0
OUTPUT CURRENT (A)
4
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MAX1510 toc03
0.96
Low-Voltage DDR Linear Regulator
Typical Operating Characteristics (continued)
(Circuit of Figure 1. TA = +25C, unless otherwise noted)
REFOUT VOLTAGE ERROR vs. REFOUT LOAD CURRENT
15 REFOUT VOLTAGE ERROR (mV) 10 5 0 -5 -10 -15 -20 -10 -5 0 5 10 500s/div REFOUT LOAD CURRENT (mA) 1.25V VOUT 0V 4V PGOOD 0V
MAX1510 toc10
MAX1510
STARTUP WAVEFORM
MAX1510 toc11
20
5V SHDN 0V
SHUTDOWN WAVEFORM
MAX1510 toc12
SOURCE LOAD TRANSIENT
5V SHDN 0V 2V 1V VOUT 0V 4V PGOOD 0V 1A IOUT 0A VOUT AC-COUPLED 1mV/div
MAX1510 toc13
RLOAD = 100
100s/div
20.0s/div
SOURCE/SINK LOAD TRANSIENT
MAX1510 toc14
LINE TRANSIENT
MAX1510 toc15
3.3V VOUT AC-COUPLED 5mV/div VIN (1V/div) 1.5V
+1.5A IOUT -1.5A IOUT = 100mA 4.00s/div 40s/div
VOUT (10mV/div) AC-COUPLED 0.9V
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5
Low-Voltage DDR Linear Regulator MAX1510
Typical Operating Characteristics (continued)
(Circuit of Figure 1. TA = +25C, unless otherwise noted)
DYNAMIC OUTPUT-VOLTAGE TRANSIENT
MAX1510 toc16
DYNAMIC OUTPUT-VOLTAGE TRANSIENT
MAX1510 toc17
VIN = 1.5V
2.5V VOUTADJ 1.8V
VIN = 1.8V
2.5V VOUTADJ 1.8V
1.2V VREFOUT 0.9V 1.2V VOUT 0.9V 20.0s/div 20.0s/div
1.2V VREFOUT 0.9V 1.2V VOUT 0.9V
SINK CURRENT-LIMIT DISTRIBUTION
MAX1510 toc18
SOURCE CURRENT-LIMIT DISTRIBUTION
SAMPLE SIZE = 200 SAMPLE PERCENTAGE (%) 40 +25C +85C
MAX1510 toc19
50 SAMPLE SIZE = 200 SAMPLE PERCENTAGE (%) 40 +25C +85C
50
30
30
20
20
10
10
0 -4.0 -3.5 -3.0 -2.5 -2.0 SINK CURRENT LIMIT (A)
0 2.0 2.5 3.0 3.5 4.0 SOURCE CURRENT LIMIT (A)
6
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Low-Voltage DDR Linear Regulator
Pin Description
PIN 1 2 3 4 5 NAME REFOUT VCC AGND REFIN PGOOD FUNCTION Buffered Reference Output. The output of the unity-gain reference input buffer sources and sinks over 5mA. Bypass REFOUT to AGND with a 0.33F or greater ceramic capacitor. Analog Supply Input. Connect to the system supply voltage (+3.3V). Bypass VCC to AGND with a 1F or greater ceramic capacitor. Analog Ground. Connect the backside pad to AGND. External Reference Input. REFIN sets the output regulation voltage (VOUTS = VREFIN). Open-Drain Power-Good Output. PGOOD is low when the output voltage is more than 150mV (typ) above or below the regulation point, during soft-start, and when shut down. 2ms after the output reaches the regulation voltage during startup, PGOOD becomes high impedance. Output Sense Input. The OUTS regulation level is set by the voltage at REFIN. Connect OUTS to the remote DDR termination bypass capacitors. OUTS is internally connected to OUT through a 12k resistor. Shutdown Control Input. Connect to VCC for normal operation. Connect to analog ground to shut down the linear regulator. The reference buffer remains active in shutdown. Power Ground. Internally connected to the output sink MOSFET. Output of the Linear Regulator Power Input. Internally connected to the output source MOSFET.
MAX1510
6
OUTS
7 8 9 10
SHDN PGND OUT IN
Detailed Description
The MAX1510 is a low-voltage, low-dropout DDR termination linear regulator with an external bias supply input and a buffered reference output (see Figures 1 and 2). VCC is powered by a 2.7V to 3.6V supply that is commonly available in laptop and desktop computers. The 3.3V bias supply drives the gate of the internal pass transistor, while a lower voltage input at the drain of the transistor (IN) is regulated to provide VOUT. By using separate bias and power inputs, the MAX1510 can drive an n-channel high-side MOSFET and use a lower input voltage to provide better efficiency. The MAX1510 regulates its output voltage to the voltage at REFIN. When used in DDR applications as a termination supply, the MAX1510 delivers 1.25V or 0.9V at 3A peak (typ) from an input voltage of 1.1V to 3.6V. The MAX1510 sinks up to 3A peak (typ) as required in a termination supply. The MAX1510 provides shoot-through protection, ensuring that the source and sink MOSFETs do not conduct at the same time, yet produces a fast source-to-sink load transient.
VIN = 1.1V TO 3.6V CIN2 10F VOUT = VTT = VDDQ / 2 IN OUT COUT1 100F
MAX1510
3.3V BIAS SUPPLY R3 100k POWER-GOOD PGOOD ON OFF R1 10k VDDQ R2 10k CREFIN 1000pF REFIN REFOUT SHDN OUTS C1 1.0F VCC PGND AGND
VREFOUT = VTTR CREFOUT 0.33F
Figure 1. Standard Application Circuit
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7
Low-Voltage DDR Linear Regulator MAX1510
3.3V BIAS SUPPLY
VCC UVLO EN SOFTSTART
IN
INPUT 1.1V TO 3.6V
OFF
ON
SHDN THERMAL SHDN
VDDQ
REFIN OUT VTT
Gm
PGND
VTTR
REFOUT
12k OUTS
AGND REFIN +150mV EN 8
REFIN -150mV
POWERGOOD
PGOOD DELAY LOGIC
MAX1510
Figure 2. Functional Diagram
8
_______________________________________________________________________________________
Low-Voltage DDR Linear Regulator
The MAX1510 features an open-drain PGOOD output that transitions high 2ms after the output initially reaches regulation. PGOOD goes low within 10s of when the output goes out of regulation by 150mV. The MAX1510 features current- and thermal-limiting circuitry to prevent damage during fault conditions. connected to ceramic bypass capacitors (0.33F to 1.0F). REFOUT is active when VREFIN > 0.45V and V CC is above V UVLO . REFOUT is independent of SHDN.
MAX1510
Shutdown
Drive SHDN low to disable the error amplifier, gatedrive circuitry, and pass transistor (Figure 2). In shutdown, OUT is terminated to GND with an 8 MOSFET. REFOUT is independent of SHDN. Connect SHDN to VCC for normal operation.
3.3V Bias Supply (VCC)
The VCC input powers the control circuitry and provides the gate drive to the pass transistor. This improves efficiency by allowing VIN to be powered from a lower supply voltage. Power V CC from a well-regulated 3.3V supply. Current drawn from the VCC supply remains relatively constant with variations in VIN and load current. Bypass VCC with a 1F or greater ceramic capacitor as close to the device as possible.
Current Limit
The MAX1510 features source and sink current limits to protect the internal N-channel MOSFETs. The source and sink MOSFETs have a typical 3A current limit (1.8A min). This current limit prevents damage to the internal power transistors, but the device can enter thermal shutdown if the power dissipation increases the die temperature above +165C (see the Thermal-Overload Protection section).
VCC Undervoltage Lockout (UVLO) The VCC input undervoltage-lockout (UVLO) circuitry ensures that the regulator starts up with adequate voltage for the gate-drive circuitry to bias the internal pass transistor. The UVLO threshold is 2.55V (typ). VCC must remain above this level for proper operation. Power Supply Input (IN)
IN provides the source current for the linear regulator's output, OUT. IN connects to the drain of the internal nchannel power MOSFET. IN can be as low as 1.1V, minimizing power dissipation. The input UVLO prohibits operation below 0.8V (typ). Bypass IN with a 10F or greater capacitor as close to the device as possible.
Soft-Start Current Limit
Soft-start gradually increases the internal source current limit to reduce input surge currents at startup. Fullsource current limit is available after the 200s soft-start timer has expired. The soft-start current limit is given by: I xt ILIMIT(SS) = LIMIT t SS where I LIMIT and t SS are from the Electrical Characteristics.
Reference Input (REFIN)
The MAX1510 regulates OUTS to the voltage set at REFIN, making the MAX1510 ideal for memory applications where the termination supply must track the supply voltage. Typically, REFIN is set by an external resistive voltage-divider connected to the memory supply (VDDQ) as shown in Figure 1. The maximum output voltage of 1.5V is limited by the gate-drive voltage of the internal n-channel power transistor.
Thermal-Overload Protection
Thermal-overload protection prevents the linear regulator from overheating. When the junction temperature exceeds +165C, the linear regulator and reference buffer are disabled, allowing the device to cool. Normal operation resumes once the junction temperature cools by 15C. Continuous short-circuit conditions result in a pulsed output until the overload is removed. A continuous thermal-overload condition results in a pulsed output. For continuous operation, do not exceed the absolute maximum junction-temperature rating of +150C.
Buffered Reference Output (REFOUT)
REFOUT is a unity-gain transconductance amplifier that generates the DDR reference supply. It sources and sinks greater than 5mA. The reference buffer is typically
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9
Low-Voltage DDR Linear Regulator MAX1510
SHDN 200s
CURRENT LIMIT
OUTPUT OVERLOAD CONDITION
POWER-GOOD WINDOW
OUT 2ms STARTUP DELAY PGOOD 10s PROPAGATION DELAY 10s PROPAGATION DELAY
Figure 3. MAX1510 PGOOD and Soft-Start Waveforms
Power-Good (PGOOD)
The MAX1510 provides an open-drain PGOOD output that goes high 2ms (typ) after the output initially reaches regulation during startup. PGOOD transitions low 10s after the output goes out of regulation by 150mV, or when the device enters shutdown. Connect a pullup resistor from PGOOD to VCC for a logic-level output. Use a 100k resistor to minimize current consumption.
REFERENCE VOLTAGE (VREF)
R1 CREFIN REFIN R2
MAX1510
Applications Information
Dynamic Output-Voltage Transitions
By changing the voltage at REFIN, the MAX1510 can be used in applications that require dynamic outputvoltage changes between two set points (graphics processors). Figure 4 shows a dynamically adjustable resistive voltage-divider network at REFIN. Using an external signal MOSFET, a resistor can be switched in and out of the REFIN resistor-divider, changing the voltage at REFIN. The two output voltages are determined by the following equations: R2 VOUT(LOW) = VREF R1 + R2 (R2 + R3) VOUT(HIGH) = VREF R1 + (R2 + R3)
10
VOUT(LOW) VOUT(HIGH) R3
VOUT(LOW) = VREF
()
R2 R1 + R2 (R2 + R3) R1 + (R2 + R3)
VOUT(HIGH) = VREF
Figure 4. Dynamic Output-Voltage Change
______________________________________________________________________________________
Low-Voltage DDR Linear Regulator
For a step voltage change at REFIN, the rate of change of the output voltage is limited by the total output capacitance, the current limit, and the load during the transition. Adding a capacitor across REFIN and AGND filters noise and controls the rate of change of the REFIN voltage during dynamic transitions. With the additional capacitance, the REFIN voltage slews between the two set points with a time constant given by REQ x CREFIN, where REQ is the equivalent parallel resistance seen by the slew capacitor.
MAX1510
SAFE OPERATING REGION
3.5 MAXIMUM OUTPUT CURRENT (A) 3.0 2.5 2.0 1.5 VIN(MAX) - VOUT(MIN) 1.0 0.5 0 0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 INPUT-OUTPUT DIFFERENTIAL VOLTAGE (V) TA = +100C TA = 0C TO +70C 100s RMS LIMIT DROPOUT VOLTAGE LIMITED MAXIMUM CURRENT LIMIT 1s RMS LIMIT
Operating Region and Power Dissipation
The maximum power dissipation of the MAX1510 depends on the thermal resistance of the 10-pin TDFN package and the circuit board, the temperature difference between the die and ambient air, and the rate of airflow. The power dissipated in the device is: PSRC = ISRC x (VIN - VOUT) PSINK = ISINK x VOUT The resulting maximum power dissipation is: PDIS(MAX) = TJ(MAX) - TA JC + CA
Figure 5. Power Operating Region--Maximum Output Current vs. Input-Output Differential Voltage
VDROPOUT = RDS(ON) x IOUT For low output-voltage applications the sink current is limited by the output voltage and the RDS(ON) of the MOSFET.
where TJ(MAX) is the maximum junction temperature (+150C), TA is the ambient temperature, JC is the thermal resistance from the die junction to the package case, and CA is the thermal resistance from the case through the PC board, copper traces, and other materials to the surrounding air. For optimum power dissipation, use a large ground plane with good thermal contact to the backside pad, and use wide input and output traces. When 1 square inch of copper is connected to the device, the maximum allowable power dissipation of a 10-pin DFN package is 1951mW. The maximum power dissipation is derated by 24.4mW/C above TA = +70C. Extra copper on the PC board increases thermal mass and reduces thermal resistance of the board. Refer to the MAX1510 evaluation kit for a layout example. The MAX1510 delivers up to 3A and operates with input voltages up to 3.6V, but not simultaneously. High output currents can only be achieved when the input-output differential voltages are low (Figure 5).
Input Capacitor Selection
Bypass IN to PGND with a 10F or greater ceramic capacitor. Bypass VCC to AGND with a 1F ceramic capacitor for normal operation in most applications. Typically, the LDO is powered from the output of a step-down controller (memory supply) that has additional bulk capacitance (polymer or tantalum) and distributed ceramic capacitors.
Output Capacitor Selection
The MAX1510 output stability is independent of the output capacitance for C OUT from 10F to 220F. Capacitor ESR between 2m and 50m is needed to maintain stability. Within the recommended capacitance and ESR limits, the output capacitor should be chosen to provide good transient response. IOUT(P-P) x ESR = VOUT(P-P) where IOUT(P-P) is the maximum peak-to-peak loadcurrent step (typically equal to the maximum source load plus the maximum sink load), and VOUT(P-P) is the allowable peak-to-peak voltage tolerance. Using larger output capacitance can improve efficiency in applications where the source and sink currents change rapidly. The capacitor acts as a reservoir for the rapid source and sink currents, so no extra current is supplied by the MAX1510 or discharged to ground, improving efficiency.
11
Dropout Operation
A regulator's minimum input-to-output voltage differential (dropout voltage) determines the lowest usable supply voltage. Because the MAX1510 uses an n-channel pass transistor, the dropout voltage is a function of the drain-to-source on-resistance (RDS(ON) = 0.25 max) multiplied by the load current (see the Typical Operating Characteristics):
______________________________________________________________________________________
Low-Voltage DDR Linear Regulator MAX1510
Noise, PSRR, and Transient Response
The MAX1510 operates with low-dropout voltage and low quiescent current in notebook computers while maintaining good noise, transient response, and AC rejection specifications. Improved supply-noise rejection and transient response can be achieved by increasing the values of the input and output capacitors. Use passive filtering techniques when operating from noisy sources. The MAX1510 load-transient response graphs (see the Typical Operating Characteristics) show two components of the output response: a DC shift from the output impedance due to the load-current change and the transient response. A typical transient response for a step change in the load current from -1.5A to +1.5A is 10mV. Increasing the output capacitor's value and decreasing the ESR attenuate the overshoot.
PC Board Layout Guidelines
The MAX1510 requires proper layout to achieve the intended output power level and low noise. Proper layout involves the use of a ground plane, appropriate component placement, and correct routing of traces using appropriate trace widths. Refer to the MAX1510 evaluation kit for a layout example. 1) Minimize high-current ground loops. Connect the ground of the device, the input capacitor, and the output capacitor together at one point. 2) To optimize performance, a ground plane is essential. Use all available copper layers in applications where the device is located on a multilayer board. 3) Connect the input filter capacitor less than 10mm from IN. The connecting copper trace carries large currents and must be at least 2mm wide, preferably 5mm wide. 4) Connect the backside pad to a large ground plane. Use as much copper as necessary to decrease the thermal resistance of the device. In general, more copper provides better heatsinking capabilities.
Chip Information
TRANSISTOR COUNT: 3496 PROCESS: BiCMOS
12
______________________________________________________________________________________
Low-Voltage DDR Linear Regulator
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
6, 8, &10L, DFN THIN.EPS
MAX1510
D
N
PIN 1 INDEX AREA
E
DETAIL A
E2
C L
C L
L A e e
L
PACKAGE OUTLINE, 6, 8, 10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm
NUMBER OF LEADS SHOWN ARE FOR REFERENCE ONLY
21-0137
E
1
2
COMMON DIMENSIONS SYMBOL A D E A1 L k A2 MIN. 0.70 2.90 2.90 0.00 MAX. 0.80 3.10 3.10 0.05
0.40 0.20 0.25 MIN. 0.20 REF.
PACKAGE VARIATIONS PKG. CODE T633-1 T833-1 T1033-1 T1433-1 N 6 8 10 14 D2 1.500.10 1.500.10 1.500.10 1.700.10 E2 2.300.10 2.300.10 2.300.10 2.300.10 e 0.95 BSC 0.65 BSC 0.50 BSC 0.40 BSC JEDEC SPEC MO229 / WEEA MO229 / WEEC MO229 / WEED-3 ---b 0.400.05 0.300.05 0.250.05 0.200.03 [(N/2)-1] x e 1.90 REF 1.95 REF 2.00 REF 2.40 REF
PACKAGE OUTLINE, 6, 8, 10 & 14L, TDFN, EXPOSED PAD, 3x3x0.80 mm
21-0137
E
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 ____________________ 13 (c) 2004 Maxim Integrated Products Printed USA is a registered trademark of Maxim Integrated Products.

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