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19-0603; Rev 1; 6/07
KIT ATION EVALU ABLE AVAIL
40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode
General Description Features
High-Efficiency Switcher Mode (Buck Mode) or Low-Quiescent-Current Linear Regulator (LDO Mode) Operation Wide Operating Input Voltage Range +5V to +40V Buck Mode +4V to +40V LDO Mode Fixed 3.3V or 5V and Adjustable (1.24V to 11V) Output Voltage Versions 6A (typ) Shutdown Current Fixed 135kHz or 330kHz Switching Frequency External Frequency Synchronization Programmable Soft-Start Integrated Microprocessor Reset (RESET) Circuit with Programmable Timeout Period Thermal and Short-Circuit Protection -40C to +125C Automotive Temperature Range Thermally-Enhanced Package Dissipates 2.6W at TA = +70C (16-Pin TQFN) 1.7W at TA = +70C (20-Pin TSSOP)
MAX5096/MAX5097
The MAX5096/MAX5097 easy-to-use, Dual ModeTM, DC-DC converters operate as LDO (low dropout) or switch-mode buck converters. At a high output load, the converters operate as high-efficiency pulse-widthmodulated (PWM) switch-mode converters and reduce the power dissipation. The devices switch to a low-quiescent-current (IQ) LDO mode of operation at light load. During the key-off condition, the system's microcontroller drives the LDO/BUCK input on the fly and forces the MAX5096/MAX5097 into LDO Mode, thereby reducing the quiescent current significantly. In Buck Mode, the MAX5096/MAX5097 operate from a 5V to 40V input voltage range and deliver up to 600mA of load current with excellent load and line regulation. The fixed-switching frequency versions of 135kHz and 330kHz are available. The MAX5096/MAX5097 DC-DC internal oscillator can be synchronized to an external clock. External compensation and a current-mode control scheme make it easy to design with. In LDO Mode, the MAX5096/MAX5097 operate from a 4V to 40V input voltage. The LDO Mode operation is intended for a lower output load current of up to 100mA. The quiescent current at 100A load in LDO Mode is only 41A (typ). The MAX5096/MAX5097 feature an enable input that shuts down the device, reducing the current consumption to 6A (typ). Additional features include a power-on reset output with a capacitor-adjustable timeout period, programmable soft-start, output tracking, output overload, short-circuit and thermal shutdown protections. The MAX5096/MAX5097 operate over the -40C to +125C automotive temperature range and are available in thermally enhanced 20-pin TSSOP or 16-pin TQFN packages.
Ordering Information
PART TEMP RANGE PIN-PACKAGE PKG CODE T1655-2 T1655-2 U20E-4 U20E-4 T1655-2 T1655-2 U20E-4 U20E-4
MAX5096AATE+* -40C to +125C 16 TQFN-EP** MAX5096BATE+ -40C to +125C 16 TQFN-EP** MAX5096AAUP+* -40C to +125C 20 TSSOP-EP** MAX5096BAUP+* -40C to +125C 20 TSSOP-EP** MAX5097AATE+ -40C to +125C 16 TQFN-EP** MAX5097BATE+* -40C to +125C 16 TQFN-EP** MAX5097AAUP+* -40C to +125C 20 TSSOP-EP** MAX5097BAUP+* -40C to +125C 20 TSSOP-EP**
*Future product--contact factory for availability. +Denotes lead-free package. **EP = Exposed pad.
Applications
LX IN IN
Pin Configurations
LX
TOP VIEW TOP VIEW
Automotive Industrial
+
PGND SGND RESET BP 1 2 3 4
16
15
14
13
+
IN 1 12 EN 11 OUT IN 2 IN 3 PGND 4 SGND 5 RESET 6 9 LDO/BUCK BP 7 N.C. 8 SYNC 9 SS 10 20 LX 19 LX 18 N.C.
MAX5096 MAX5097
MAX5096 MAX5097
17 EN 16 OUT 15 ADJ 14 N.C. 13 LDO/BUCK 12 COMP 11 CT
10 ADJ
5 SYNC
6 SS
7 CT
8 COMP
Dual Mode is a trademark of Maxim Integrated Products, Inc.
TQFN
TSSOP
________________________________________________________________ Maxim Integrated Products
1
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40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode MAX5096/MAX5097
ABSOLUTE MAXIMUM RATINGS
(All voltages referenced to PGND, unless otherwise noted.) IN (transient, 1ms) ..................................................-0.3V to +45V SGND ....................................................................-0.3V to +0.3V LX....................................................................-1V to (VIN + 0.3V) LX Current ................................................................................2A EN ................................................................-0.3V to (VIN + 0.3V) BP, SYNC, LDO/BUCK, RESET to SGND...............-0.3V to +12V BP, RESET Output Current..................................................25mA CT, SS, ADJ, COMP to SGND ....................-0.3V to (VBP + 0.3V) OUT ........................................................................-0.3V to +11V OUT Short-Circuit Duration ........................................Continuous Continuous Power Dissipation (TA = +70C)* 16-Pin TQFN (derate 33.3mW/C above +70C) ........2666mW 20-Pin TSSOP (derate 21.7mW/C above +70C) ......1739mW *As per JEDEC 51 Standard--Multilayer Board.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Thermal Resistance: (JA, 16-Pin TQFN)* ...................................................30.0C/W (JC, 16-Pin TQFN).......................................................1.7C/W (JA, 20-Pin TSSOP)* .................................................46.0C/W (JC, 20-Pin TSSOP)........................................................2C/W Operating Temperature Range .........................-40C to +125C Junction Temperature ......................................................+150C Storage Temperature Range .............................-60C to +150C Lead Temperature (soldering, 10s) .................................+300C
ELECTRICAL CHARACTERISTICS
(VIN = +14V, IOUT = 1mA, CIN = 100F, COUT = 22F, L = 22H, CBP = 1F, VEN = +2.4V (Figure 2), SGND = PGND = 0V, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER SYSTEM INPUT Input Voltage Range (LDO Mode) Input Voltage Range (Buck Mode) Internal Input Undervoltage Lockout Internal Input Undervoltage Lockout Hysteresis BP (Internal Regulator) Output Voltage VIN_LDO VIN_BUCK VUVLO LDO/BUCK = high LDO/BUCK = low VBP rising 4 5 3.5 3.65 0.2 3.75 4 4.20 40 40 3.9 V V V V V SYMBOL CONDITIONS MIN TYP MAX UNITS
VUVLO_HYS VBP falling VBP VIN = +4.5V, IBP = 100A LDO/BUCK = high, measured at input supply TA = -40C to +125C return, VOUT = 5V, IOUT = 100A LDO/BUCK = high, measured at input supply TA = -40C to return, VOUT = 5V, +125C IOUT = 100mA VIN = 14V, VOUT = 5V, IOUT = 0 TA = -40C to +125C TA = -40C to +85C
IQ Quiescent Supply Current (LDO Mode) IQ
38
70 A
44
100
Buck Converter No-Load Supply Current
IQ_BUCK
680 6 6 19
A
Shutdown Supply Current
ISHDN
VEN = 0V, measured from VIN
A 12
2
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40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +14V, IOUT = 1mA, CIN = 100F, COUT = 22F, L = 22H, CBP = 1F, VEN = +2.4V (Figure 2), SGND = PGND = 0V, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER BUCK MODE Supply Current (Buck Converter On) IS LDO/BUCK = low, VADJ = 1.4V, MAX5096, no switching LDO/BUCK = low, VADJ = 1.4V, MAX5097, no switching 135kHz version 693 980 A SYMBOL CONDITIONS MIN TYP MAX UNITS
MAX5096/MAX5097
Supply Current (Buck Converter On) Fixed Output Voltage ADJ Set Point ADJ Input Bias Current Dual Mode ADJ Threshold Maximum Duty Cycle Error Amplifier Transconductance Adjustable Output Voltage Range Minimum Output Current Switch Current Limit Internal Switch On-Resistance Switch Leakage Current Efficiency Switching Frequency Synchronization SYNC Input SYNC Input High Threshold SYNC Input Low Threshold SYNC Input Minimum High Pulse Width SYNC Input Leakage LDO MODE Guaranteed Output Current
IS
330kHz Version 4.85 3.196 1.21
720 5 3.3 1.235 5 125 62 100 55 1.235 136 600 1.15 1.5 0.9 0.05 85 81 120 300 120 300 2.0 135 330
1000 5.12 3.391 1.27 100
A
VOUT VFB IFB VADJTH_R VADJTH_F DMAX GmEA VADJ IOUT ISW_LIM RDS(ON) ISW_L fSW fSYNC VSYNCH VSYNCL
5V version, 5.5V VIN 40V, no load 3.3V version, 5.5V VIN 40V, no load 50% duty cycle, no load VADJ = 1.5V ADJ rising ADJ falling VADJ = 0.5V VCOMP = VADJ, ICOMP = 10A VIN = 6.5V to 40V VIN = 6V to 40V VIN = 14V, IDRAIN = 100mA VEN = 0V VIN = 14V, VOUT = 5V, IOUT = 400mA VIN = 14V, VOUT = 3.3V, IOUT = 400mA MAX5096 MAX5097 MAX5096 MAX5097 VBP = 4V VBP = 4V
V V nA mV %
210 11.000 1.90 2.1 3
S V mA A A %
148 350 500 500 0.8
kHz kHz kHz kHz V V ns
250 VSYNC =11V IOUT (Note 2) 100 1
A mA
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40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode MAX5096/MAX5097
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +14V, IOUT = 1mA, CIN = 100F, COUT = 22F, L = 22H, CBP = 1F, VEN = +2.4V (Figure 2), SGND = PGND = 0V, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER SYMBOL CONDITIONS 5V version, MAX5096B/MAX5097B, 5.5V VIN 40V, IOUT = 10mA 3.3V version, MAX5096A/MAX5097A, 4V VIN 40V, IOUT = 10mA IOUT = 10mA VADJ = 4V IOUT = 10mA IOUT = 100mA, VOUT = 0.98 x VOUT(NOMINAL) (5V version only), MAX5096B/MAX5097B Rising edge of EN to VOUT = 10% VOUT(NOMINAL), RL = 500, VADJ = SGND, LDO/BUCK = 4V, CSS = 2nF VOUT / VIN 5V version, +5.5V VIN +40V, IOUT = 100mA 3.3V version, +4V VIN +40V, IOUT = 100mA 5V version, IOUT = 100A to 100mA, VIN = +14V 3.3V version, IOUT = 100A to 100mA, VIN = +14V TJ = +25C TJ = -40C to +125C TJ = +25C TJ = -40C to +125C 1.237 MIN 4.89 89 1.21 TYP 5 3.3 1.2375 0.5 MAX 5.09 3.378 1.26 100 11.000 0.37 UNITS V V V nA V V
Output Voltage
VOUT
ADJ Set Point ADJ Input Bias Current Adjustable Output Voltage Range Dropout Voltage
VADJ IFB VADJ VDO
Startup Response Time
300
s
0.125 mV/V 0.093 0.242 0.242 0.164 0.164 60 150 2.0 0.8 330 500 0.374 1 mV/mA 0.237 1 dB mA V V A Clock Periods s 1 32 100
Line Regulation
Load Regulation
VOUT / IOUT
Power-Supply Rejection Ratio Short-Circuit Current LDO/BUCK High Threshold LDO/BUCK Low Threshold LDO/BUCK Input Leakage Transition Timing from LDO Mode to Buck Mode Transition Timing from Buck Mode to LDO Mode
PSRR ISC
IOUT = 10mA, f = 100Hz, 500mVP-P, VOUT = +5V, VIN = +14V VIN = 6V
BUCK MODE (LDO MODE TRANSITION)
LDO/BUCK = 11V Falling edge of LDO/BUCK to buck converter on Rising edge of LDO/BUCK to LDO operation ISS VSS-REF VENH VSS = 0.1V VOUT = VOUT(NOMINAL) - 20% EN = high, regulator on 3 0.9 1.4
SOFT-START, ENABLE (EN) AND RESET Soft-Start Charge Current Soft-Start Reference Voltage EN High-Voltage Threshold 5 0.99 7 1.1 A V V
4
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40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode
ELECTRICAL CHARACTERISTICS (continued)
(VIN = +14V, IOUT = 1mA, CIN = 100F, COUT = 22F, L = 22H, CBP = 1F, VEN = +2.4V (Figure 2), SGND = PGND = 0V, TA = TJ = -40C to +125C, unless otherwise noted. Typical values are at TA = TJ = +25C.) (Note 1)
PARAMETER EN Low-Voltage Threshold EN Input Pulldown RESET Voltage Threshold High RESET Voltage Threshold Low RESET Output-Low Voltage RESET Output-High Leakage Current RESET Output Minimum Timeout Period VOUT to RESET Delay Delay Comparator Threshold Delay Comparator Threshold Hysteresis CT Charge Current CT Discharge Current THERMAL SHUTDOWN Thermal Shutdown Temperature Thermal Shutdown Hysteresis TJ(SHDN) TJ(SHDN) Temperature rising +165 20 C C ICH IDISCH VCT = 1V 0.74 VCT_TH VRESET_H VRESET_L VRL IRH SYMBOL VENL Regulator off VEN = 2V, LDO/BUCK = 4V VOUT rising VOUT falling ISINK = 1mA VRESET = 5V, VADJ = 1.5V CCT = 0 VOUT falling 10mV/s, CCT = 0 VCT rising 1.18 25 6 1.2374 100 1 13.8 1.20 1.29 89 87 0.5 92 90 94 92 0.2 1 CONDITIONS MIN TYP MAX 0.4 UNITS V A % VOUT % VOUT V A s s V mV A mA
MAX5096/MAX5097
Note 1: Limits to -40C are guaranteed by design. Note 2: The continuous maximum output current from LDO is limited by package power dissipation.
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40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode MAX5096/MAX5097
Typical Operating Characteristics
(VIN = +14V, VEN = +2.4V, MAX5097AATE+, Figures 2 and 4, TA = +25C, unless otherwise specified.)
OUTPUT VOLTAGE vs. INPUT VOLTAGE (LDO MODE)
MAX5096 toc01
OUTPUT VOLTAGE vs. INPUT VOLTAGE (BUCK MODE)
MAX5096 toc02
QUIESCENT SUPPLY CURRENT vs. TEMPERATURE (LDO MODE)
70 60 50 40 30 20 10 IOUT = 0 IOUT = 100A VIN = 14V VOUT = 3.3V IOUT = 100mA
MAX5096 toc03
4.0 3.5 OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 IOUT = 50mA 0 1 10 INPUT VOLTAGE (V)
4.0 3.5 OUTPUT VOLTAGE (V) 3.0 2.5 2.0 1.5 1.0 0.5 IOUT = 600mA 0
80 QUIESCENT SUPPLY CURRENT (A)
0 1 10 INPUT VOLTAGE (V) 100 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
100
NO-LOAD SUPPLY CURRENT vs. TEMPERATURE (BUCK MODE)
MAX5096 toc04
SHUTDOWN CURRENT vs. TEMPERATURE
VEN = 0V VIN = 14V
MAX5096 toc05
OUTPUT VOLTAGE vs. TEMPERATURE (LDO MODE)
VOUT = 3.3V 3.4 OUTPUT VOLTAGE (V) IOUT = 10mA 3.3 IOUT = 10mA IOUT = 100A
MAX5096 toc06
710 NO-LOAD SUPPLY CURRENT (A) 700 690 680 670 660 650 640 VIN = 14V VOUT = 3.3V
14 12 SHUTDOWN CURRENT (A) 10 8 6 4 2 0
3.5
3.2
3.1
3.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C) -40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
OUTPUT VOLTAGE vs. TEMPERATURE (BUCK MODE)
MAX5096 toc07
DROPOUT VOLTAGE vs. OUTPUT CURRENT (LDO MODE)
MAX5096 toc08
EFFICIENCY vs. LOAD CURRENT (VOUT = 3.3V)
90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 VIN = 5V VIN = 14V VIN = 24V VIN = 40V fSW = 330kHz
MAX5096 toc09
3.38 VOUT = 3.3V 3.36 OUTPUT VOLTAGE (V) 3.34 3.32 3.30 IOUT = 100mA 3.28 3.26 3.24 IOUT = 100A
0.18 0.16 DROPOUT VOLTAGE (V) 0.14 0.12 0.10 0.08 0.06 0.04 0.02 0 VOUT = 5V
100
IOUT = 600mA
-40 -25 -10 5 20 35 50 65 80 95 110 125 TEMPERATURE (C)
0
20
40
60
80
100
0.01
0.1 LOAD CURRENT (A)
1
OUTPUT CURRENT (mA)
6
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40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode MAX5096/MAX5097
Typical Operating Characteristics (continued)
(VIN = +14V, VEN = +2.4V, MAX5097AATE+, Figures 2 and 4, TA = +25C, unless otherwise specified.)
EFFICIENCY vs. LOAD CURRENT (VOUT = 5V)
MAX5096 toc10
LOAD-TRANSIENT RESPONSE (LDO MODE)
MAX5096 toc11
LOAD-TRANSIENT RESPONSE (BUCK MODE)
MAX5096 toc12
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 0.01 0.1 LOAD CURRENT (A) 1 VIN = 5.5V VIN = 14V
VIN = 14V IOUT = 100A to 50mA IOUT 50mA/div IOUT 200mA/div
VIN = 24V VIN = 40V VOUT 50mV/div VOUT AC-COUPLED 100mV/div VIN = 14V ISTEP = 300mA to 600mA 2ms/div 1ms/div
VIN STARTUP RESPONSE (LDO MODE)
MAX5096 toc13
ENABLE STARTUP RESPONSE (LDO MODE)
MAX5096 toc14
VIN STARTUP RESPONSE (BUCK MODE)
MAX5096 toc15
VIN = 14V IOUT = 0A CCT = 0.047F
VIN 10V/div VEN 10V/div VOUT 2V/div RESET 5V/div
VIN VIN = 14V IOUT = 100mA 10V/div CCT = 0.047F VEN 5V/div VOUT 2V/div RESET 5V/div
VIN = 14V IOUT = 0A CCT = 0.047F
VIN 10V/div
VEN 5V/div VOUT 2V/div RESET 5V/div
10ms/div
10ms/div
10ms/div
ENABLE STARTUP RESPONSE (BUCK MODE)
MAX5096 toc16
SHUTDOWN RESPONSE THROUGH VIN (LDO MODE)
VIN 10V/div
MAX5096 toc17
SHUTDOWN RESPONSE THROUGH VIN (BUCK MODE)
VIN 10V/div
MAX5096 toc18
IOUT = 50mA
IOUT = 50mA
VIN = 14V IOUT = 600mA CCT = 0.047F
VIN 10V/div
VEN 5V/div VOUT 2V/div RESET 5V/div
VEN 10V/div VOUT 2V/div RESET 5V/div
VEN 10V/div VOUT 2V/div RESET 5V/div
10ms/div
100ms/div
100ms/div
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7
40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode MAX5096/MAX5097
Typical Operating Characteristics (continued)
(VIN = +14V, VEN = +2.4V, MAX5097AATE+, Figures 2 and 4, TA = +25C, unless otherwise specified.)
LX VOLTAGE AND INDUCTOR CURRENT
MAX5096 toc19
LX VOLTAGE AND INDUCTOR CURRENT
MAX5096 toc20
LX VOLTAGE, SYNC INPUT, AND INDUCTOR CURRENT
MAX5096 toc21
IOUT = 0A
IOUT = 600mA VLX 10V/div VLX 5V/div INDUCTOR CURRENT 500mA/div
VLX 10V/div
SYNC INPUT 5V/div INDUCTOR CURRENT 500mA/div
INDUCTOR CURRENT 200mA/div
2s/div
1s/div
1s/div
TRANSITION FROM BUCK MODE TO LDO MODE
MAX5096 toc22
TRANSITION FROM LDO MODE TO BUCK MODE
MAX5096 toc23
LDO/BUCK 5V/div LDO/BUCK 3V/div VOUT AC-COUPLED 200mV/div IOUT 100mA/div VIN = 14V IOUT = 100mA 400s/div 100s/div VIN = 14V IOUT = 100mA VOUT AC-COUPLED 200mV/div IOUT 100mA/div
8
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40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode
Pin Description
PIN TQFN 1 2 TSSOP 4 5 NAME FUNCTION Power Ground. Return path for p-channel power MOSFET driver. Connect the input capacitor return, freewheeling diode anode, and output capacitor return terminals to PGND. Signal Ground. Connect SGND to PGND near the input bypass capacitor return terminal. Open-Drain, Active-Low Reset Output. RESET asserts low when OUT drops below the reset threshold. When output rises above 92% of the programmed level, RESET becomes high impedance after the reset timeout period. Connect a pullup resistor from RESET to the converter output to create a logic output. 4V Internal Regulator Output. Bypass BP to SGND with a 1F or greater ceramic capacitor. Synchronization Input. Connect SYNC to an external clock for synchronization. Connect SYNC to SGND when not used. Soft-Start Timer Input. Connect an external capacitor from SS to SGND to adjust the softstart timeout period (see the Soft-Start (SS) section). Reset Timeout Period. Connect a capacitor from CT to SGND to set the reset timeout period (see the Power-On Reset Output RESET section). Buck Converter (Buck Mode) Control Loop Compensation. See the Compensation Network section for compensation network design. LDO mode does not need external compensation. LDO Mode/Buck Mode Select. Drive LDO/BUCK low to select the Buck Mode. The Buck Mode activates after 32 internal/external clock cycles. Force the LDO/BUCK high (> 2V), to select LDO Mode. The Buck Mode stops and LDO Mode is activated with a 100s delay. Regulator Output Feedback Point. Connect ADJ to SGND for a fixed 3.3V (MAX5096A/MAX5097A) or 5V (MAX5096B/MAX5097B). For adjustable output voltage, use an external resistive divider to set VOUT. VADJ regulating set point is 1.237V. Converter Output. OUT must always be connected to the regulator output. Connect at least a 22F low-ESR (equivalent series resistance) capacitor from OUT to PGND for stable operation. Enable Input. EN is internally pulled to ground. Drive EN high to turn on the regulator. Force EN low or leave unconnected to place the device in shutdown mode. Drain Connection of Internal p-Channel High-Side Switch Regulator Input. Bypass IN to PGND with a parallel combination of low-ESR ceramic and aluminum capacitor to handle the input ripple current. No Connection. Not internally connected. Exposed Pad. Connect externally to a large ground plane (SGND) for improved heat dissipation. Do not use EP as an electrical ground connection.
MAX5096/MAX5097
PGND SGND
3
6
RESET
4 5 6 7
7 9 10 11
BP SYNC SS CT
8
12
COMP
9
13
LDO/BUCK
10
15
ADJ
11
16
OUT
12 13, 14 15, 16 -- EP
17 19, 20 1, 2, 3 8, 14, 18 EP
EN LX IN N. C. EP
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9
40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode MAX5096/MAX5097
IN
CIN VOUT CURRENT SENSE
INTERNAL 4V LDO
BP
CBP -+ DC
OSCILLATOR AND RAMP GENERATOR CURRENT LIMITER
VIN
DC-DC ENABLE PWM PWM COMPARATOR + gm COMP GATE DRIVER MUX FB SS VREF COUT R1 0.9 LX L + VOUT
BUCK MODE GM AMPLIFIER + FB SS VREF + FEEDBACK SELECTOR 0.12V
ADJ OUT R2
RC
SYNC
SYNCRO
CP
CC LDO/BUCK MODE SELECTOR LDO/ BUCK SELECTOR
LDO MODE AMPLIFIER
RPU
EN BIAS SOFTSTART INTERNAL BANDGAP UVLO THERMAL PROTECTION RESET
RESET
SS CSS
MAX5096 MAX5097
CT CCT SGND PGND
Figure 1. Simplified Diagram
10
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40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode
Detailed Description
The MAX5096/MAX5097 are easy-to-use, high-efficiency, PWM current-mode, step-down switching converters in normal operation. The MAX5096/MAX5097 have an internal high-side p-channel 0.9 switch and use a low forward-drop freewheeling diode for rectification. In Buck Mode, the p-channel switches at the 135kHz or 330kHz frequency. Buck Mode uses a current-mode control architecture that offers excellent line-transient response, easier frequency compensation, and cycleby-cycle current limiting. The buck converter is compensated externally for a selected value/type of output inductor and capacitor. The internal p-channel switch acts as a pass element when operating in the low-quiescent-current LDO Mode. The LDO Mode can be selected on the fly through the LDO/BUCK input. During the key-off condition, the system's microcontroller drives the LDO/BUCK input high and forces the MAX5096/MAX5097 into LDO Mode, reducing the quiescent current to 1A (typ). When in LDO Mode, the device is capable of delivering up to 100mA, which may be limited by the device power dissipation. The LDO and switcher share the same pass element and the reference; however, the error amplifiers are different with their own compensation schemes. The MAX5096/MAX5097 include an integrated microprocessor reset circuit with an adjustable reset timeout period. The internal reset circuit monitors the regulator output voltage and asserts RESET low when the regulator output falls below the reset threshold voltage. Other features include an enable input, externally programmable soft-start, optimized current-limit protection in both LDO and Buck Modes, and thermal shutdown. turned on and off while in both Buck and LDO Modes. Each time the EN is toggled, the output rises with a programmed soft-start period.
MAX5096/MAX5097
Internal Regulator (BP)/ Undervoltage Lockout
The MAX5096/MAX5097 include an internal 4V auxiliary regulator to power internal circuitry. Bypass the auxiliary regulator output (BP) to SGND with a 1F ceramic capacitor physically located close to the device. The regulator is not intended to supply the external circuit other than pulling up the LDO/BUCK input or RESET. Do not load BP externally by more than 2mA. The regulator output is regulated to 4V with 7% accuracy during steady state. During turn-on, the BP voltage stabilizes after 250s with a 1F capacitor at BP. Drive EN high to turn on the internal regulator. The internal UVLO with hysteresis ensures stable operation, resulting in the monotonic rise of the output voltage. The UVLO circuit monitors the output of the regulator. The rising UVLO threshold is internally set to 3.65V (BP rising) with a 185mV hysteresis (BP falling). The 3.65V UVLO at the no-load BP output guarantees operation at VIN lower than 4V.
Soft-Start (SS)
Soft-start provides for the monotonic, glitch-free turn-on of the converter. Soft-start limits the input inrush current which may cause a glitch, especially if the source impedance is high. The soft-start period required also depends on the output capacitance and the closedloop bandwidth of converter. The soft-start period for the MAX5096/MAX5097 is externally programmable using a single capacitor (C SS ). The soft-start is achieved by the controlled ramping up of the error amplifier reference input. At startup, after VIN is applied and the UVLO threshold is reached, the device enters soft-start. During soft-start, 5A is sourced into the capacitor (CSS) connected from SS to SGND (Figure 2) causing the reference voltage to ramp up slowly. When VSS reaches 1.237V, the output becomes fully active. Set the soft-start time (tSS) using following equation: V t SS = SS x CSS ISS where VSS is 1.237V, ISS is 5A, tSS is in seconds, and CSS is in Farads. Pulling EN low quickly discharges the CSS capacitor, making it ready for the next soft-start period.
Enable Input (EN)
EN is a logic-level enable input that turns the device on or off. The logic-high and logic-low voltages for the EN input are 1.4V and 0.4V, respectively. Drive EN high to turn on the device, and drive it low to place the device in shutdown. Leaving EN unconnected disables the device since the EN is internally pulled low with a 0.5A current, however, a forced pulldown of EN improves the noise immunity. The MAX5096/MAX5097 draw 6A (typ) of supply current when in shutdown. EN withstands up to +40V, allowing EN to be connected directly to IN for always-on operation. The converter may be
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11
40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode MAX5096/MAX5097
VIN VIN CIN 100F EN 22H LDO/BUCK SYNC COMP RC 100k CP 22pF CC 1.2nF LX D1* B260/ MURS105 COUT 22F (CER.) VOUT + BP 1.0F
MAX5096 MAX5097
ADJ
OUT 100k SS RESET GND PGND *USE MURS105 IN APPLICATIONS WHERE LDO MODE QUIESCENT CURRENT IS CRITICAL. RESET
CSS 0.047F
CT CCT 0.01F
Figure 2. Fixed Output Voltage Configuration
Output Voltage Tracking/Sequencing
The output voltages of multiple MAX5096/MAX5097 converters can be made to track by using the SS pin during turn-on and turn-off (see Figure 3). SS is pulled up using a 5A current source and connecting SS of multiple MAX5096/MAX5097s, raising the references with the same slope. Tracking the converters reduces the differential voltages between the core and I/O voltages during turn-on, turn-off, and brownout. If any one converter output drops due to shutdown or an overload fault situation, the SS drops, pulling down all the converters simultaneously. The rate of fall of output voltages, however, depends on the output capacitance and load of the individual converter. Multiple voltage sequencing can be done by daisychaining several MAX5096/MAX5097s. The RESET of the first converter can be connected to EN of the second converter. This allows the first converter to come up first every time the system is powered up.
a high-impedance state after the active timeout period (tRP). The active timeout period is externally programmable using a single capacitor from CT to ground. Use the following equation to calculate the required timeout period for the power-on reset: V tRP = CT -TH x CCT ICH where VCT-TH is 1.237V, ICH is 1A, tRP is in seconds, and CCT is in Farads. To obtain a logic-voltage output, connect a pullup resistor from RESET to a logic-supply voltage. The internal open-drain MOSFET can sink 1mA while providing a TTL logic-low signal. If unused, ground RESET or leave it unconnected. The power-on reset behavior is the same in both the LDO and Buck Modes of operation.
Power-On Reset Output (RESET)
A supervisor circuit is integrated in the MAX5096/ MAX5097. RESET is an open-drain output. RESET pulls low as soon as VOUT drops below 90% of its nominal regulation voltage. Once the output voltage rises above 92% of the set output voltage, the RESET output enters
12
Oscillator/Synchronization Input (SYNC)
The MAX5096/MAX5097 internal oscillator generates a factory-preset frequency of either 135kHz (MAX5096) or 330kHz (MAX5097). The 135kHz version keeps the maximum fundamental frequency below 150kHz, which keeps the third harmonic below 450kHz and under the
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40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode
VOUT3 VOUT2 VOUT1
Applications Information
Output Voltage Selection
The MAX5096/MAX5097 can be configured as either a preset fixed output voltage or an adjustable output voltage device. Connect ADJ to ground to select the factory-preset output voltage option (Figure 2). The MAX5096A/MAX5097A and MAX5096B/MAX5097B provide a fixed output voltage equal to 3.3V and 5V, respectively (see the Selector Guide). The MAX5096/ MAX5097 become an adjustable version as soon as the devices detect about 125mV at the ADJ pin. The resistor-divider at ADJ increases the ADJ voltage above 125mV and also adjusts the output voltage depending upon the resistor values. In adjustable mode, select an output between +1.273V and +11V using two external resistors connected as a voltage-divider to ADJ (Figure 4). Set the output voltage using the following equation: R1 VOUT = VADJ x 1 + R2 where VADJ = 1.273V and R2 is chosen to be approximately 100k. Connect ADJ to GND if adjustable mode is not used.
MAX5096/MAX5097
SOFT-START RATIOMETRIC TRACKING OUTPUTS VOUT1 VOUT2 VOUT3
STOP
STOP SOFT-START SEQUENCED OUTPUTS
Figure 3. Output Voltage Tracking/Sequencing
lower end of the AM band. The MAX5096 is suitable for noise-sensitive applications like AM radio power supply. For an application where size is more important, use the MAX5097, which runs at 330kHz frequency. The high-frequency operation reduces the size and cost of the external inductor and capacitor. The MAX5096/MAX5097 can be synchronized using an external signal. The MAX5096 can be synchronized from 120kHz to 500kHz, while the MAX5097 is capable of synchronizing from 300kHz to 500kHz. The external synchronization feature makes frequency hopping possible depending on the selected AM channel. Connect SYNC to ground, if not used.
Inductor Selection
Three key inductor parameters must be specified for proper operation with the MAX5096/MAX5097: inductance value (L), peak inductor current (I PEAK), and inductor saturation current (I SAT ). The minimum required inductance is a function of operating frequency, input-to-output voltage differential, and the peak-topeak inductor current (IP-P). Higher IP-P allows for a lower inductor value, while a lower IP-P requires a higher inductor value. A lower inductor value minimizes size and cost and improves large-signal and transient response, but reduces efficiency due to higher peak currents and higher peak-to-peak output voltage ripple for the same output capacitor. On the other hand, higher inductance increases efficiency by reducing the ripple current. Resistive losses due to extra wire turns can exceed the benefit gained from lower ripple current levels, especially when the inductance is increased while keeping the dimension of the inductor constant. A good compromise is to choose IP-P equal to 40% of the full load current. Calculate the inductor value using the following equation: (V - V ) V L = OUT IN OUT VIN x fSW x IP-P
Thermal Protection
When the junction temperature exceeds TJ = +165C, an internal thermal sensor signals the shutdown logic, which turns off the regulator (both in Buck Mode and LDO Mode), and discharges the soft-start capacitor allowing the IC to cool. The thermal sensor turns the regulator on again after the IC's junction temperature cools by 20C, resulting in a cycled output during continuous thermal-overload conditions. The thermal hysteresis and a soft-start period limit the average power dissipation into the device during continuous fault condition. During operation, do not exceed the absolute maximum junction temperature rating of TJ = +150C.
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13
40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode MAX5096/MAX5097
5V TO 40V VIN VIN CIN 100F EN 22H LDO/BUCK SYNC COMP RC LX VOUT D1* COUT B260/ MURS105 22F + BP 1.0F
MAX5096 MAX5097
ADJ
R1
CP
CC
R2 OUT RPU SS CT RESET GND CCT PGND RESET *USE MURS105 IN APPLICATIONS WHERE LDO MODE QUIESCENT CURRENT IS CRITICAL.
CSS
Figure 4. Adjustable Output Voltage Configuration
use typical values of VIN and fSW so that efficiency is optimum for typical conditions. The switching frequency (fSW) is fixed at 135kHz (MAX5096) and 330kHz (MAX5097). f SW can also be varied from 120kHz to 500kHz (MAX5096) and from 300kHz to 500kHz (MAX5097) when synchronized to an external clock (see the Oscillator/ Synchronization Input (SYNC) section). The peak-to-peak inductor current, which reflects the peak-to-peak output ripple, is worst at the maximum input voltage. See the Output Capacitor Selection section to verify that the worst-case output ripple is acceptable. The inductor saturating current (ISAT) is also important to avoid runaway current during continuous output short circuit. Select an inductor with an ISAT specification higher than the maximum peak current limit of 1.9A. The Buck Mode operation determines the inductor and output capacitor values. However, the values of the inductor, its DCR, and the output capacitance/ESR affect the closed-loop transfer function both in Buck and LDO Modes. The internal compensation of the MAX5096/MAX5097 in LDO Mode limits the values of these external components. Make sure that the combination of output inductor, capacitor, and ESR falls within the range specified in following Table 1.
Table 1. Inductor/Output Capacitor Selection
INDUCTOR OUTPUT CAPACITOR (COUT) 22F, ESR = 5m to 20m (ceramic) 22H 47F, ESR = 40m to 150m 100F, ESR = 30m to 100m 470F / ESR = 60 to 400m 22F, ESR = 5m to 20m (ceramic) 47H 47F / ESR = 40m to 150m 100F / ESR = 30m to 100m 470F / ESR = 60m to 400m 22F, ESR = 5m to 20m (ceramic) 100H 47F / ESR = 40m to 150m 100F / ESR = 30m to 100m 470F / ESR = 60m to 400m
Output Capacitor Selection
The allowable output voltage ripple and the maximum deviation of the output voltage during load steps determine the output capacitance and its ESR. The output
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40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode
ripple is mainly composed of V Q (caused by the capacitor discharge) and VESR (caused by the voltage drop across the ESR of the output capacitor). Normally, a good approximation of the output voltage ripple is VRIPPLE VESR + VQ. If using ceramic capacitors, assume the contribution to the output voltage ripple from the ESR and the capacitor discharge to be equal to 20% and 80%, respectively. If using aluminum electrolyte capacitors, assume the contribution to the output voltage ripple from the ESR and the capacitor discharge to be equal to 90% and 10%, respectively. Use the following equations for calculating the output capacitance and its ESR for required peak-to-peak output voltage ripple. COUT = IP-P 16 x VQ x fSW VESR IP-P where ISTEP is the load step, tSTEP is the rise time of the load step, and tRESPONSE is the response time of the controller. The response time of the converter is approximately one third of the inverse of its closed-loop bandwidth and also depends on the phase margin.
MAX5096/MAX5097
Rectifier Selection
The MAX5096/MAX5097 require an external Schottky/ fast-recovery diode rectifier as a freewheeling diode. Connect this rectifier close to the device using short leads and short PC board traces. Choose a rectifier with a continuous current rating greater than the highest output current-limit threshold (1.9A) and with a voltage rating greater than the maximum expected input voltage, VIN. Use a low forward-voltage-drop Schottky rectifier to limit the negative voltage at LX. Avoid higher than necessary reverse-voltage Schottky rectifiers that have higher forward-voltage drops. Use a 60V (max) Schottky rectifier with a 2A current rating. The Schottky rectifier leakage current at high temperature significantly increases the quiescent current in LDO Mode. In applications where LDO Mode quiescent current is important, use an ultra-fast switching diode to limit the leakage current. In this type of application, use MURS105, MURS120 for their fast-switching and lowleakage features.
ESR =
IP-P is the peak-to-peak inductor current and fSW is the converter's switching frequency. The allowable deviation of the output voltage during fast load transients also determines the output capacitance, its ESR, and its equivalent series inductance (ESL). The output capacitor supplies the load current during a load step until the controller responds with a greater duty cycle. The response time (tRESPONSE ) depends on the closed-loop bandwidth of the converter (see the Compensation Network section). The resistive drop across the output capacitor's ESR, the drop across the capacitor's ESL, and the capacitor discharge, causes a voltage drop during the load step. Use a combination of low-ESR tantalum/aluminum electrolytic and ceramic capacitors for better transient load and voltage ripple performance. Non-leaded capacitors and/or multiple parallel capacitors help reduce the ESL. Keep the maximum output voltage deviation below the tolerable limits of the electronics being powered. Use the following equations to calculate the required ESR, ESL, and capacitance value during a load step: ESR = VESR ISTEP xt I COUT = STEP RESPONSE VQ VESL x t STEP ISTEP
Input Capacitor Selection
The discontinuous input current of the buck converter causes large input ripple currents and therefore, the input capacitor must be carefully chosen to keep the input voltage ripple within design requirements. The input voltage ripple is comprised of VQ (caused by the capacitor discharge) and VESR (caused by the ESR of the input capacitor). The total voltage ripple is the sum of VQ and VESR. Calculate the input capacitance and ESR required for a specified ripple using the following equations (continuous mode): ESR = VESR IP-P IOUT _ MAX + 2 IOUT _ MAX x D(1- D) VQ x fSW (VIN - VOUT ) x VOUT and VIN x fSW x L
CIN = where
IP-P =
ESL =
V D = OUT VIN IOUT_MAX is the maximum output current and D is the duty cycle.
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40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode MAX5096/MAX5097
Compensation Network
The MAX5096/MAX5097 in LDO Mode are compensated internally with a compensation network around the LDO error amplifier. When in Buck Mode, the DC-DC gM amplifier must be externally compensated using a network connected from COMP to ground. The currentmode control architecture reduces the compensation network to a single pole-zero. The RC and C network, connected from the internal transconductance amplifier output to SGND, can provide a single pole-zero pair. Choose all the power components like the inductor, output capacitor, and ESR first and design the compensation network around them. Choose the closedloop bandwidth (fC) to be approximately 1/10 of the switching frequency. See the following equations to calculate the compensation values for the low-ESR output capacitor with ESR zero frequency, approximately a decade higher than fC. Calculate the dominant pole due to the output capacitor (COUT) and the load (ROUT): 1 fPO = 2 x x COUT x ROUT where ROUT = VOUT / ILOAD. Calculate the RC using following equation: RC = VO x fC gMC x ROUT x gm x VADJ x fPO
Switching Between LDO Mode and Buck Mode
The MAX5096/MAX5097 switch between the Buck Mode and LDO Mode on the fly. However, care must be taken to reduce output glitch or overshoot during the switching. Buck Mode to LDO Mode The LDO Mode is intended for the low 100mA output current while the buck converter delivers up to 600mA output current. It is important to first reduce the output load below 100mA before switching to the LDO Mode. If the output load is higher than 100mA, the MAX5096/MAX5097 may go into the current limit and the output will drop significantly. Whenever the mode is changed, output is expected to glitch because the loop dynamics change due to different error amplifiers when operating in the LDO and Buck Modes. The output voltage undershoot can be minimized by reducing the output load during switching and using larger output capacitance. LDO Mode to Buck Mode When switching from the LDO Mode to Buck Mode, a fixed amount of delay (32 cycles) is applied so that the buck converter control loop and oscillator reach their steady-state conditions. The 32-cycle delay translates to approximately 250s and 100s for 150kHz and 330kHz switching frequency versions, respectively. It is recommended that the output load of 600mA must be delayed by at least this much time to allow the MAX5096/MAX5097 to switch to high-current Buck Mode. This ensures that the output does not drop due to the LDO current-limit protection mechanism.
where g MC is the control to output gain of the MAX5096/MAX5097 buck converter and is equal to 1.06. VADJ is the feedback set point equal to 1.237V and gm (transconductance amplifier gain) is equal to 136S. See Figure 2. Place a zero (f Z) at 0.9 x f PO: CC = 1 2 x x RCFPO x fPO
PC Board Layout Guidelines
1) Proper PC board layout is essential. Minimize ground noise by connecting the anode of the freewheeling rectifier, the input bypass capacitor ground lead, and the output filter capacitor ground lead to a large PGND plane. 2) Minimize lead lengths to reduce stray capacitance, trace resistance, and radiated noise. In particular, place the Schottky/fast recovery rectifier diode right next to the device.
Finally, place a high-frequency pole at the frequency equal to half of the converter switching frequency (fSW). CP = 1 x RC x fSW
Place the compensation network physically close to the MAX5096/MAX5097.
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40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode
3) Connect the exposed pad of the IC to the SGND plane. Do not make a direct connection between the exposed pad plane and SGND (pin 2) under the IC. Connect the exposed pad and pin 2 to the SGND plane separately. Connect the ground connection of the feedback resistive divider, the soft-start capacitor, the adjustable reset timeout capacitor, and the compensation network to the SGND plane. Connect the SGND plane and PGND plane at one point near the input bypass capacitor at VIN. 4) Use the large SGND plane as a heatsink for the MAX5096/MAX5097. Use large PGND and LX planes as heatsinks for the rectifier diode and the inductor.
MAX5096/MAX5097
Chip Information
PROCESS: BiCMOS
Selector Guide
PART MAX5096A_ _ _ MAX5096B_ _ _ MAX5097A_ _ _ MAX5097B_ _ _ OUTPUT VOLTAGE (V) +3.3/Adjustable +5.0/Adjustable +3.3/Adjustable +5.0/Adjustable SWITCHING FREQUENCY (kHz) 135 135 330 330
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17
40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode MAX5096/MAX5097
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
21-0140
K
1
2
18
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QFN THIN.EPS
40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
MAX5096/MAX5097
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
21-0140
K
2
2
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19
40V, 600mA Buck Converters with LowQuiescent-Current Linear Regulator Mode MAX5096/MAX5097
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information, go to www.maxim-ic.com/packages.)
TSSOP 4.4mm BODY.EPS
PACKAGE OUTLINE, TSSOP, 4.40 MM BODY, EXPOSED PAD
XX XX
21-0108
E
1 1
Revision History
Pages changed at Rev 1: 1, 2, 3, 5, 20
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
20 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.
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