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19-0725; Rev 0; 8/07
KIT ATION EVALU BLE AVAILA
Dual, 3A, 2MHz Step-Down Regulator
General Description Features
o 35m On-Resistance Internal MOSFETs o Dual, 3A, PWM Step-Down Regulators o Fully Protected Against Overcurrent, Short Circuit, and Overtemperature o 1% Output Accuracy over Load, Line, and Temperature o Operates from 2.35V to 3.6V Supply o REFIN on One Channel for Tracking or External Reference o Integrated Boost Diodes o Adjustable Output from 0.6V to 0.9 x VIN o Soft-Start Reduces Inrush Supply Current o 0.5MHz to 2MHz Adjustable Switching, or FSYNC Input o All-Ceramic-Capacitor Design o 180 Out-of-Phase Operation Reduces Input Ripple Current o Individual Enable Inputs and PWRGD Outputs o Available in 5mm x 5mm Thin QFN Package
MAX8833
The MAX8833 high-efficiency, dual step-down regulator is capable of delivering up to 3A at each output. The device operates from a 2.35V to 3.6V supply, and provides output voltages from 0.6V to 0.9 x VIN, making it ideal for on-board point-of-load applications. Total output error is less than 1% over load, line, and temperature. The MAX8833 operates in PWM mode with a switching frequency ranging from 0.5MHz to 2MHz, set by an external resistor. It can also be synchronized to an external clock in the same frequency range. Two internal switching regulators operate 180 out-of-phase to reduce the input ripple current, and consequently reduce the required input capacitance. The high operating frequency minimizes the size of external components. High efficiency, internal dual-nMOS design keeps the board cool under heavy loads. The voltage-mode control architecture and the high-bandwidth (> 15MHz typ) voltage-error amplifier allow a type III compensation scheme to be utilized to achieve fast response under both line and load transients, and also allow for ceramic output capacitors. Programmable soft-start reduces input inrush current. Two enable inputs allow the turning on/off of each output individually, resulting in great flexibility for systemlevel designs. A reference input is provided to facilitate output-voltage tracking applications. The MAX8833 is available in a 32-pin thin QFN (5mm x 5mm) package with 0.8mm max height.
Ordering Information
PART MAX8833ETJ+ PIN-PACKAGE 32 Thin QFN (5mm x 5mm) PKG CODE T3255-4
Applications
ASIC/CPU/DSP Power Supplies DDR Power Supplies Set-Top Box Power Supplies Printer Power Supplies Network Power Supplies
Note: The device is specified over the -40C to +85C extended temperature range.
+Denotes a lead-free package.
Typical Operating Circuit
INPUT1 2.35V TO 3.6V IN1 IN2 BST1 BST2 LX1 LX2 INPUT2 2.35V TO 3.6V
OUTPUT1 1.2V / 3A
OUTPUT2 1.5V / 3A
PGND1
PGND2
MAX8833
FB1 FB2
COMP1 TYPE III COMPENSATION
COMP2 TYPE III COMPENSATION
PWRGD1 PWRGD2 ON OFF EN1 GND EN2 OFF ON
Pin Configuration appears at end of data sheet.
________________________________________________________________ Maxim Integrated Products 1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Dual, 3A, 2MHz Step-Down Regulator MAX8833
ABSOLUTE MAXIMUM RATINGS
IN_, LX_, VDD, VDL, PWRGD_ to GND..................-0.3V to +4.5V VDD, VDL to IN_.....................................................-0.3V to +4.5V EN_, SS_, COMP_, FB_, REFIN, FSYNC to GND ......-0.3V to the lower of (VVDD + 0.3V) and (VVDL + 0.3V) Continuous LX_ Current (Note 1) ...................................5.5ARMS BST_ to LX_ ...........................................................-0.3V to +4.5V PGND_ to GND......................................................-0.3V to +0.3V Continuous Power Dissipation (TA = +70C) 32-Pin Thin QFN (5mm x 5mm) (derate 34.5mW/C above +70C) ..........................2758.6mW Operating Ambient Temperature Range .............-40C to +85C Operating Junction Temperature Range ...........-40C to +125C Storage Temperature Range .............................-65C to +150C Lead Temperature (soldering, 10s) .................................+300C JC ...................................................................................1.7C/W
Note 1: LX_ have internal clamp diodes to PGND_ and IN_. Applications that forward bias these diodes should take care not to exceed the IC's package power-dissipation limits.
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
ELECTRICAL CHARACTERISTICS
(VIN = VVDD = VVDL = 3.3V, VFB = 0.5V, VSS_ = VREFIN = 600mV, PGND_ = GND, RFSYNC = 10k, L = 0.47H, CBST_ = 0.1F, CSS = 0.022F, PWRGD not connected; TA = -40C to +85C, typical values are at TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER IN1, IN2, VDL, VDD IN_, VDL, and VDD Voltage Range IN_ Supply Current VDD + VDL Supply Current Shutdown Supply Current (IIN1 + IIN2 + IVDD + IVDL) IN_, VDD Undervoltage Lockout Threshold UVLO Monitors VDD, IN1, and IN2 IN_, VDD Undervoltage Lockout Deglitch BST1, BST2 Shutdown BST_ Current COMP1, COMP2 COMP Clamp Voltage, High COMP Slew Rate COMP Shutdown Resistance ERROR AMPLIFIER FB_ Regulation Voltage FB_ Regulation Voltage with External Reference Error Amplifier Common-Mode-Input Range Error Amplifier Maximum Output Current FB_ Input Bias Current VFB_ = 0.605V TA = +25C TA = +85C VCOMP_ = 1V to 2V VVDD = VIN = 2.5V to 3.3V VCOMP_ = 1V to 2V VVDD = VIN = 2.5V to 3.3V 0.594 0.594 0 1 40 37 300 0.600 0.600 0.606 0.606 VVDD 1.6 V V V mA nA From COMP_ to GND, VEN_ = 0V VVDD = VIN_= 2.3V to 3.6V, VFB_ = 0.7V 1.80 2.00 1.40 7 25 2.25 V V/s VIN_ = VVDD = VVDL = VBST_ = 3.6V, VEN_ = 0V, VLX_ = 0 or 3.6V TA = +25C TA = +85C 0.02 2 A (Note 3) 1MHz switching, no load 1MHz switching, VDD = VDL VIN_ = VVDD = VVDL = VBST_ - VLX_ = 3.6V, VEN_ = 0V Rising Falling 1.8 VIN = 2.5V VIN = 3.3V VVDD = 2.5V VVDD = 3.3V TA = +25C TA = +85C 0.3 2.0 1.9 2 2.2 2.35 1.9 2.8 7.2 10 15 11 3.60 3.5 5 V mA mA A V s CONDITIONS MIN TYP MAX UNITS
2
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Dual, 3A, 2MHz Step-Down Regulator
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VVDD = VVDL = 3.3V, VFB = 0.5V, VSS_ = VREFIN = 600mV, PGND_ = GND, RFSYNC = 10k, L = 0.47H, CBST_ = 0.1F, CSS = 0.022F, PWRGD not connected; TA = -40C to +85C, typical values are at TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER REFIN, SS2 REFIN Input Bias Current VFB_ = 0.610V VVDD = 2.35V to 2.6V REFIN Common-Mode Range VVDD = 2.6V to 3.6V LX1, LX2 (All Pins Combined) LX_ On-Resistance, High LX_ On-Resistance, Low LX_ Current-Limit Threshold ILX_ = -2A ILX_ = -2A VIN = VBST - VLX_ = 3.3V VIN = VBST - VLX_ = 2.5V VIN = 3.3V VIN = 2.5V 4.6 TA = +25C TA = +85C TA = +25C TA = +85C 0.9 1.80 -10 -0.1 1.0 2.0 50 95 RFSYNC = 10k 90 3 0.7 1.7 VEN_ = 0 or 3.6V, VVDD = 3.6V VSS_ = 300mV In shutdown or a fault condition TA = +25C TA = +85C 5 -1 0.01 8 335 11 +1 95 1.1 2.2 MHz ns ns % ARMS V V A -0.1 40 42 35 37 5.5 6.4 10 A 54 55 m m A 0 VVDD 1.70 TA = +25C TA = +85C 0 90 65 VVDD 1.65 V 500 nA CONDITIONS MIN TYP MAX UNITS
MAX8833
High-side sourcing and freewheeling VIN = 3.6V, VEN = 0V VLX_ = 3.6V VLX_ = 0V
LX_ Leakage Current
LX_ Switching Frequency LX_ Minimum Off-Time LX_ Minimum On-Time LX_ Maximum Duty Cycle Maximum LX_ Output Current EN1, EN2 EN_ Logic-Low EN_ Logic-High EN_ Input Current SS1, SS2 SS_ Charging Current REFIN, SS2 Discharge Resistance THERMAL SHUTDOWN Thermal-Shutdown Threshold (Independent Channels) Thermal-Shutdown Hysteresis
RFSYNC = 10k RFSYNC = 4.75k
A
+165 20
C C
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3
Dual, 3A, 2MHz Step-Down Regulator MAX8833
ELECTRICAL CHARACTERISTICS (continued)
(VIN = VVDD = VVDL = 3.3V, VFB = 0.5V, VSS_ = VREFIN = 600mV, PGND_ = GND, RFSYNC = 10k, L = 0.47H, CBST_ = 0.1F, CSS = 0.022F, PWRGD not connected; TA = -40C to +85C, typical values are at TA = +25C, unless otherwise noted.) (Note 2)
PARAMETER FSYNC FSYNC Capture Range FSYNC Input Threshold FSYNC Output Voltage Phase Shift from LX1 to LX2 PWRGD1, PWRGD2 PWRGD1 Threshold Voltage PWRGD2 Threshold Voltage PWRGD_ Hysteresis PWRGD_ Falling Edge Deglitch PWRGD_ Output-Low Voltage PWRGD_ Leakage Current IPWRGD_ = 4mA VPWRGD = 3.6V, VFB_ = 0.9V TA = +25C TA = +85C 0.01 35 VFB1 rising with respect to VREFIN, and VREFIN > 540mV typ VFB2 rising with respect to VSS2, and VSS2 > 540mV typ 88 88 90 90 2.6 45 0.03 55 0.15 1 92 92 % % % s V A 250 1.3 0.975 1.5 1.0 180 2500 1.7 1.025 kHz V V Degrees CONDITIONS MIN TYP MAX UNITS
Note 2: All devices 100% production tested at +25C. Limits over temperature are guaranteed by design. Note 3: VVDD must equal VVDL and be equal to or greater than VIN_.
Typical Operating Characteristics
(VIN1 = VIN2 = 3.3V. MAX8833, circuit of Figure 6, TA = +25C, unless otherwise noted.)
EFFICIENCY vs. LOAD CURRENT WITH 3.3V INPUT
MAX8833 toc01
EFFICIENCY vs. LOAD CURRENT WITH 2.5V INPUT
MAX8833 toc02
SWITCHING FREQUENCY vs. RFSYNC
2200 SWITCHING FREQUENCY (kHz) 2000 1800 1600 1400 1200 1000 800 600 400
MAX8833 toc03
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 100 1000 LOAD CURRENT (mA) VOUT = 2.5V VOUT = 1.2V VOUT = 1.8V
100 90 80 EFFICIENCY (%) 70 60 50 40 30 20 10 0 VOUT = 1.8V VOUT = 1.2V
2400
10,000
100
1000 LOAD CURRENT (mA)
10,000
3
6
9
12 RFSYNC (k)
15
18
21
4
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Dual, 3A, 2MHz Step-Down Regulator
Typical Operating Characteristics (continued)
(VIN1 = VIN2 = 3.3V. MAX8833, circuit of Figure 6, TA = +25C, unless otherwise noted.)
SWITCHING FREQUENCY vs. TEMPERATURE
MAX8833 toc04
MAX8833
FEEDBACK VOLTAGE vs. TEMPERATURE
608 FEEDBACK VOLTAGE (mV) 606 604 602 600 598 596 594 592 590
MAX8833 toc05
1100 1080 SWITCHING FREQUENCY (kHz) 1060 1040 1020 1000 980 960 940 920 900 -40 -15 10 35 60
610
85
-40
-15
10
35
60
85
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
SHUTDOWN SUPPLY CURRENT vs. SUPPLY VOLTAGE
9 8 SUPPLY CURRENT (nA) 7 6 5 4 3 2 1 0 2.35 2.60 2.85 3.10 3.35 3.60 IOUT 1.5A IIN1 + IIN2 + IVDL + IVDD
MAX8833 toc06
LOAD TRANSIENT
MAX8833 toc07
10
1.8V OUTPUT VOUT 100mV/div
3.0A 1.5A 1A/div
20s/div
SUPPLY VOLTAGE (V)
SWITCHING WAVEFORMS
MAX8833 toc08
SOFT-START AND SHUTDOWN
MAX8833 toc09
VLX1
2V/div
VEN2
5V/div
IL1
2A/div
VOUT2
1V/div
VLX2
VPWRGD 2V/div IIN
2V/div
IL2 400ns/div
2A/div 400s/div 3A LOAD
1A/div
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5
Dual, 3A, 2MHz Step-Down Regulator MAX8833
Typical Operating Characteristics (continued)
(VIN1 = VIN2 = 3.3V. MAX8833, circuit of Figure 6, TA = +25C, unless otherwise noted.)
OUTPUT PEAK CURRENT LIMIT vs. OUTPUT VOLTAGE
MAX8833 toc10
SHORT CIRCUIT AND RECOVERY
MAX8833 toc11
OUTPUT SEQUENCING (EN2 = PWRGD1)
MAX8833 toc12
8 OUTPUT PEAK CURRENT LIMIT (A) 7 6
VOUT1
500mV/div V OUT1
1V/div 1V/div
5 VOUT2 4 3 2 1 0 0.8 1.1 1.4 1.7 2.0 2.3 2.6 1ms/div OUTPUT VOLTAGE (V) IL1 0A 1ms/div 2A/div VPWRGD1 VPWRGD2 2V/div 2V/div
OUTPUT TRACKING (EN1 = EN2)
MAX8833 toc13
EXTERNAL SYNCHRONIZATION
MAX8833 toc14
VOUT1
1V/div 1V/div
PULSE GENERATOR SIGNAL. A 10k RESISTOR IS CONNECTED BETWEEN THE PULSE GENERATOR AND FSYNC
2V/div
VOUT2 2V/div VPWRGD1 VPWRGD2 2V/div VLX2 VLX1
2V/div
2V/div
1ms/div DDR TRACKING 1.8V, 0.9V
400ns/div
6
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Dual, 3A, 2MHz Step-Down Regulator
Pin Description
PIN 1 NAME FUNCTION Power-Good Open-Drain Output for Regulator 1. PWRGD1 is high impedance when VREFIN 0.54V and PWRGD1 VFB1 0.9 x VREFIN. PWRGD1 is low when VREFIN < 0.54V, EN1 is low, VDD or IN1 is below UVLO, the thermal shutdown is activated, or when VFB1 < 0.9 x VREFIN. REFIN VDD GND N.C. VDL External Reference Input for Regulator 1. Connect an external reference to REFIN, or connect REFIN to SS1 to use the internal reference. REFIN is discharged to GND through 335 when EN1 is low or regulator 1 is shut down due to a fault condition. Supply Voltage. Connect a 10 resistor from VDD to VDL and connect a 0.1F capacitor from VDD to GND. Analog Ground. Connect GND to the analog ground plane. Connect the analog and power ground planes together at a single point near the IC. No Connection Supply Voltage Input for Low-Side Gate Drive. Connect VDL to IN_ or the highest available supply voltage less than 3.6V. Connect a 1F capacitor from VDL to the power ground plane. Frequency Set and Synchronization. Connect a 4.75k to 20.5k resistor from FSYNC to GND to set switching frequency or drive with a 250kHz to 2.5MHz clock signal to synchronize switching. RFSYNC = (T - 0.05s) x (10k / 0.95s), where T is the oscillator period.
MAX8833
2 3 4 5 6
7
FSYNC
8
Power-Good Open-Drain Output for Regulator 2. PWRGD2 is high impedance when VSS2 0.54V and VFB2 PWRGD2 0.9 x VSS2. PWRGD2 is low when VSS2 < 0.54V, EN2 is low, VDD or IN2 is below UVLO, the thermal shutdown is activated, or when VFB2 < 0.9 x VSS2. SS2 FB2 Soft-Start for Regulator 2. Connect a capacitor from SS2 to GND to set the soft-start time. See the Setting the SoftStart Time section. SS2 is internally pulled low with 335 when EN2 is low or regulator 2 is in a fault condition. Feedback Input for Regulator 2. Connect FB2 to the center of an external resistor-divider from the output to GND to set the output voltage from 0.6V to 90% of VIN1. FB2 is high impedance when the IC is shut down. Compensation for Regulator 2. COMP2 is the output of the internal voltage-error amplifier. Connect external compensation network from COMP2 to FB2. See the Compensation Design section. COMP2 is internally pulled to GND when the output is shut down. Enable Input for Regulator 2. Drive EN2 high to enable regulator 2, or drive low for shutdown. For always-on operation, connect EN2 to VDD. Power-Supply Input for Regulator 2. The voltage range is 2.35V to 3.6V. Connect two 10F and one 0.1F ceramic capacitors from IN2 to PGND2. Power Ground for Regulator 2. Connect all PGND_ pins to the power ground plane. Connect the power ground and analog ground planes together at a single point near the IC. Inductor Connection for Regulator 2. Connect an inductor between LX2 and the regulator output. LX2 is high impedance when the IC is shut down. Bootstrap Connection for Regulator 2. Connect a 0.1F capacitor from BST2 to LX2. BST2 is the supply for the high-side gate drive. BST2 is charged from VDL with an internal pMOS switch. In shutdown, there is an internal diode junction from LX2 to BST and from VDL to BST2. Bootstrap Connection for Regulator 1. Connect a 0.1F capacitor from BST1 to LX1. BST1 is the supply for the high-side gate drive. BST1 is charged from VDL with an internal pMOS switch. In shutdown, there is an internal diode junction from LX1 to BST and from VDL to BST1. Inductor Connection for Regulator 1. Connect an inductor between LX1 and the regulator output. LX1 is high impedance when the IC is shut down. Power Ground for Regulator 1. Connect all PGND_ pins to the power ground plane. Connect the power ground and analog ground planes together at a single point near the IC.
9 10
11
COMP2
12 13, 14 15, 16, 17 18, 19
EN2 IN2 PGND2 LX2
20
BST2
21
BST1
22, 23 24, 25, 26
LX1 PGND1
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7
Dual, 3A, 2MHz Step-Down Regulator MAX8833
Pin Description (continued)
PIN 27, 28 29 NAME IN1 EN1 FUNCTION Power-Supply Input for Regulator 1. The voltage range is 2.35V to 3.6V. Connect two 10F and one 0.1F ceramic capacitors from IN1 to PGND1. Enable Input for Regulator 1. Drive EN1 high to enable regulator 1, or low for shutdown. For always-on operation, connect EN1 to VDD. Compensation for Regulator 1. COMP1 is the output of the internal voltage-error amplifier. Connect external compensation network from COMP1 to FB1. See the Compensation Design section. COMP1 is internally pulled to GND when the output is shut down. Feedback Input for Regulator 1. Connect FB1 to the center of an external resistor-divider from the output to GND to set the output voltage from 0.6V to 90% of VIN1. FB1 is high impedance when the IC is shut down. Soft-Start for Regulator 1. Connect a capacitor from SS1 to GND to set the startup time. See the Setting the Soft-Start Time section. SS1 is internally pulled low with 335 in shutdown or in a fault condition. Exposed Pad. Connect the exposed pad to the power ground plane.
30
COMP1
31 32 --
FB1 SS1 EP
Detailed Description
PWM Controller
The controller logic block is the central processor that determines the duty cycle of the high-side MOSFET under different line, load, and temperature conditions. Under normal operation, where the current-limit and temperature protection are not triggered, the control logic block takes the output from the PWM comparator and generates the driver signals for both high-side and low-side MOSFETs. It also contains the break-beforemake logic and the timing for charging the bootstrap capacitors. The error signal from the voltage-error amplifier is compared with the ramp signal generated by the oscillator at the PWM comparator and, thus, the required PWM signal is produced. The high-side switch is turned on at the beginning of the oscillator cycle and turns off when the ramp voltage exceeds the VCOMP signal or the current-limit threshold is exceeded. The low-side switch is then turned on for the remainder of the oscillator cycle. The two switching regulators operate at the same switching frequency with 180 phase shift to reduce the input-capacitor ripple current requirement. Figure 1 shows the MAX8833 functional diagram.
cycle is skipped to continue ramping down the inductor current. When the inductor current stays above the valley current limit for 12s and the FB_ is below 0.7 x VREFIN, the regulator enters hiccup mode. During hiccup mode, the SS_ capacitor is discharged to zero and the soft-start sequence begins after a predetermined time period.
Undervoltage Lockout (UVLO)
When the VDD supply voltage drops below the falling undervoltage threshold (typically 1.9V), the MAX8833 enters its undervoltage lockout mode (UVLO). UVLO forces the device to a dormant state until the input voltage is high enough to allow the device to function reliably. In UVLO, LX_ nodes of both regulators are in the high-impedance state. PWRGD1 and PWRGD2 are forced low in UVLO. When VVDD rises above the rising undervoltage threshold (typically 2V), the IC powers up normally as described in the Startup and Sequencing section. The UVLO circuitry also monitors the IN1 and IN2 supplies. When the IN_ voltage drops below the falling undervoltage threshold (typically 1.9V), the corresponding regulator shuts down, and corresponding PWRGD_ goes low. The regulator powers up when VIN_ rises above the rising undervoltage threshold (typically 2V).
Current Limit
The MAX8833 provides both peak and valley current limits to achieve robust short-circuit protection. During the high-side MOSFET's on-time, if the drain-source current reaches the peak current-limit threshold (specified in the Electrical Characteristics table), the high-side MOSFET turns off and the low-side MOSFET turns on, allowing the current to ramp down. At the next clock, the high-side MOSFET is turned on only if the inductor current is below the valley current limit. Otherwise, the PWM
8
Power-Good Output (PWRGD_)
PWRGD1 and PWRGD2 are open-drain outputs that indicate when the corresponding output is in regulation. PWRGD1 is high impedance when VREFIN 0.54V and VFB1 0.9 x VREFIN. PWRGD1 is low when VREFIN < 0.54V, EN1 is low, VVDD or VIN1 is below VUVLO, the thermal-overload protection is activated, or when VFB1 < 0.9 x VREFIN.
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Dual, 3A, 2MHz Step-Down Regulator MAX8833
VDL
VDD SHUTDOWN CONTROL UVLO CIRCUITRY
CURRENT-LIMIT COMPARATOR DC + -
BST CAP CHARGING SWITCH IN1
BST1 + LX1 IN1 ILIM THRESHOLD
EN1 EN2
BIAS GENERATOR
IN2
VDD
IN1
VOLTAGE REFERENCE REF EN1 CLOCK
CONTROL LOGIC
LX1
SS1
SOFT-START 1
PGND1 BST CAP CHARGING SWITCH VDL
THERMAL SHUTDOWN1 SS2 SOFT-START 2 PWM COMPARATOR + + CURRENT-LIMIT COMPARATOR IN2 DC
REFIN FB1
+ ERROR AMPLIFIER
BST2 + LX2 IN2 ILIM THRESHOLD
COMP1 COMP LOW DETECTOR FROM SS2 (0.6V) + FB2 ERROR AMPLIFIER COMP2 COMP LOW DETECTOR CLOCK CLOCK
PWM COMPARATOR + EN2
CONTROL LOGIC
LX2
THERMAL SHUTDOWN2
PGND2
OSCILLATOR + FB1 + + FB2 + SHDN
FSYNC
REFIN 540mV THERMAL SHUTDOWN1 THERMAL SHUTDOWN2 540mV
SHDN
PWRGD1
REF
THERMAL SHUTDOWN
0.9 x VREFIN SS2
PWRGD2
MAX8833
0.9 x VSS2
GND
Figure 1. Functional Diagram
_______________________________________________________________________________________ 9
Dual, 3A, 2MHz Step-Down Regulator MAX8833
The power-good, open-drain output for regulator 2 (PWRGD2) is high impedance when VSS2 0.54V and VFB2 0.9 x VSS2. PWRGD2 is low when VSS2 < 0.54V, EN2 is low, VVDD or VIN2 is below VUVLO, the thermal-overload protection is activated, or when VFB2 < 0.9 x VSS2.
IN1 RRUVB UVLO UVLO
THERM SHDN TLIM REG1 ON
External Reference Input (REFIN)
The MAX8833 has an external reference input. Connect an external reference between 0 and VVDD - 1.6V to REFIN to set the FB1 regulation voltage. To use the internal 0.6V reference, connect REFIN to SS1. When the IC is shut down, REFIN is pulled to GND through 335.
BIAS GEN
VDD
Startup and Sequencing
The MAX8833 features separate enable inputs (EN1 and EN2) for the two regulators. Driving EN_ high enables the corresponding regulator; driving EN_ low turns the regulator off. Driving both EN1 and EN2 low puts the IC in low-power shutdown mode, reducing the supply current typically to 30nA. The MAX8833 regulators power up when the following conditions are met (see Figure 2): * * * * * EN_ is logic-high. VVDD is above the UVLO threshold. VIN_ is above the UVLO threshold. The internal reference is powered. The IC is not in thermal overload (TJ < +165C).
EN1 REF EN2 REF RDY RRUVB UVLO
UVLO RRUVB
UVLO
REG2 ON TLIM
IN2
THERM SHDN
Figure 2. Startup Control Diagram
Once these conditions are met, the MAX8833 begins soft-start. FB2 regulates to the voltage at SS2. During soft-start, the SS2 capacitor is charged with a constant 8A current source so that its voltage ramps up for the
soft-start time. See the Setting the Soft-Start Time section to select the SS2 capacitor for the desired soft-start time. FB1 regulates to the voltage at REFIN. Connect REFIN to SS1 to use the internal reference with softstart time set independently by the SS1 capacitor (see Figure 3a).
EN1 OUT1 PWRGD1 10k 10k
PWRGD1
EN1 EN1
VDD
EN2 EN2 SS2
EN2 OUT2 PWRGD2
PWRGD2
SS1
REFIN
Figure 3a. Startup and Sequencing Options--Two Independent Output Startup and Shutdown Waveforms
10
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Dual, 3A, 2MHz Step-Down Regulator MAX8833
For ratiometric tracking applications, connect REFIN to the center of a voltage-divider from the output of regulator 2 to GND (see Figure 3b). In this application, the EN_ inputs are connected to each other and driven as a single enable input. Regulator 2 starts up with a normal softstart (C SS2 sets the time), and regulator 1 output ratiometrically tracks the regulator 2 output voltage. The voltage-divider resistors set the VOUT1/VOUT2 ratio (see the Setting the Output Voltage section). In Figure 3b, VOUT1 regulates to half of VOUT2. Note that a capacitance of 1000pF should be connected to SS1 for stability. Figure 3c shows the output sequencing application using an external reference. Sequencing is achieved by connecting EN2 to PWRGD1. In this mode, regulator 2 starts once regulator 1 reaches regulation.
EN 10k OUT2
PWRGD1
EN1 EN
VDD OUT1 10k PWRGD2
EN2
PWRGD2
SS2
PWRGD1
SS1
REFIN
OUT2 10k 10k
Figure 3b. Startup and Sequencing Options--Ratiometric Tracking Startup and Shutdown Waveforms VOUT1 Track VOUT2
EN1 PWRGD1 10k VDD PWRGD1 10k SS2 PWRGD2 OUT2 SS1 PWRGD2 REFIN REFIN EN1 EN1
OUT1
EN2
Figure 3c. Startup and Sequencing Options--Sequencing Startup and Shutdown Waveforms with External Reference
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11
Dual, 3A, 2MHz Step-Down Regulator MAX8833
EN 10k
PWRGD1
EN1 EN
OUT1 OUT2
VDD 10k
EN2
PWRGD1 PWRGD2
SS2
PWRGD2
SS1
REFIN
Figure 3d. Startup and Sequencing Options--Matching Startup Slopes of Output Voltages with Internal Reference
In Figure 3d, EN1 and EN2 are connected together and driven as a single input. Although both outputs begin ramping up at the same time, slope matching is achieved by selecting the SS_ capacitors. See the Setting the Soft-Start Time section for information on selecting the SS_ capacitors. In Figure 3d, the slope of the output voltages during soft-start is equal. This is achieved by setting the ratio of the soft-start capacitors equal to the ratio of the output voltages: CSS1 VOUT1 = CSS2 VOUT2
Design Procedure
Setting the Output Voltage
The output voltages for regulator 1 (with REFIN connected to SS1) and regulator 2 are set with a resistor voltage-divider connected from the output to FB_ to GND as shown in Figure 4. Select a value for the resistor connected from output to FB_ (R4 in Figure 4) between 2k and 10k. Use the following equations to find the value for the resistor connected from FB_ to GND (R6 in Figure 4): R6 = 0.6 x R4 (VOUT - 0.6)
Synchronization (FSYNC)
The MAX8833 operates from 500kHz to 2MHz using either its internal oscillator, or an externally supplied clock. See the Setting the Switching Frequency section.
LX_
L
CO
OUTPUT
Thermal-Overload Protection
Thermal-overload protection limits the total power dissipation of the MAX8833. Internal thermal sensors monitor the junction temperature at each of the regulators. When the junction temperature exceeds +165C, the corresponding regulator is shut down, allowing the IC to cool. The thermal sensor turns the regulator on after the junction temperature cools by +20C. In a continuous thermal-overload condition, this results in a pulsed output.
MAX8833
FB_ R7 COMP_
R8 R4 C11 C9 R6 C10
Figure 4. Type III Compensation Network
12
______________________________________________________________________________________
Dual, 3A, 2MHz Step-Down Regulator
In DDR tracking applications such as Figure 7, the FB1 regulation voltage tracks the voltage at REFIN. In Figure 7, the output of regulator 1 tracks VOUT2, and the ratio of the output voltages is set as follows: VOUT1 R19 = VOUT2 R1 + R19 tant, an LIR of around 40% to 50% is recommended. Once all the parameters are chosen, the inductor value is determined as follows: L= VOUT x (VIN - VOUT )
MAX8833
fS x VIN x LIR x IOUT(MAX)
Setting the Switching Frequency
The MAX8833 has an adjustable internal oscillator that can be set to any frequency from 500kHz to 2MHz. To set the switching frequency, connect a resistor from FSYNC to GND. Calculate the resistor value from the following equation: 1 10k RFSYNC = - 50ns fS 950ns The MAX8833 can also be synchronized to an external clock from 500kHz to 2MHz by connecting the clock signal to FSYNC through a 10k isolation resistor. The external sync frequency must be higher than the frequency that would be produced by RFSYNC. The two regulators switch at the same frequency as the FSYNC clock, and are 180 out-of-phase with each other. The external clock duty cycle may range between 10% and 90% to ensure 180 out-of-phase operation.
where fS is the switching frequency. Choose a standard value close to the calculated value. The exact inductor value is not critical and can be adjusted to make tradeoffs among size, cost, and efficiency. Find a low-loss inductor with the lowest possible DC resistance that fits the allotted dimensions. The peak inductor current is determined as: LIR IPEAK = 1 + x IOUT(MAX) 2 IPEAK must not exceed the chosen inductor's saturation current rating or the minimum current-limit specification for the MAX8833.
Input-Capacitor Selection
The input capacitor for each regulator serves to reduce the current peaks drawn from the input power supply and reduces switching noise in the IC. The total input capacitance for each rail must be equal to or greater than the value given by the following equation to keep the input-voltage ripple within specifications and minimize the high-frequency ripple current being fed back to the input source: CIN _ MIN _ = D _ x IOUT _ fSW x VIN _ RIPPLE _
Setting the Soft-Start Time
The two step-down regulators have independent adjustable soft-start. Capacitors from SS_ to GND are charged from a constant 8A (typ) current source to the feedback-regulation voltage. The value of the softstart capacitors is calculated from the desired soft-start time as follows: 8A CSS _ = t SS x 0.6V
Inductor Selection
There are several parameters that must be examined when determining which inductor to use: maximum input voltage, output voltage, load current, switching frequency, and LIR. LIR is the ratio of inductor current ripple to DC load current. A higher LIR value allows for a smaller inductor, but results in higher losses and higher output ripple. On the other hand, higher inductor values increase efficiency, but eventually resistive losses due to extra turns of wire exceed the benefit gained from lower AC current levels. A good compromise between size and efficiency is a 30% LIR. For applications in which size and transient response are impor-
where D is the quiescent duty cycle (VOUT / VIN); fSW is the switching frequency; and VIN_RIPPLE is the peak-topeak input-voltage ripple, which should be less than 2% of the minimum DC input voltage. The impedance of the input capacitor at the switching frequency should be less than that of the input source so high-frequency switching currents do not pass through the input source but are instead shunted through the input capacitor. High source impedance requires high-input capacitance. The input capacitor must meet the ripple current requirement imposed by the switching currents. The RMS input ripple current, IRIPPLE_, is given by: IRIPPLE _ = IOUT _ x D x (1 - D)
______________________________________________________________________________________
13
Dual, 3A, 2MHz Step-Down Regulator MAX8833
Output-Capacitor Selection
The key selection parameters for the output capacitor are capacitance, ESR, ESL, and voltage-rating requirements. These affect the overall stability, output ripple voltage, and transient response of the DC-DC converter. The output ripple occurs due to variations in the charge stored in the output capacitor, the voltage drop due to the capacitor's ESR, and the voltage drop due to the capacitor's ESL. Calculate the output-voltage ripple due to the output capacitance, ESR, and ESL as: VRIPPLE = VRIPPLE(C) + VRIPPLE(ESR) + VRIPPLE(ESL) where the output ripple due to output capacitance, ESR, and ESL is: VRIPPLE(C) = IP-P 8 x COUT x fS time, the controller responds by regulating the output voltage back to its predetermined value. The controller response time depends on the closed-loop bandwidth. A higher bandwidth yields a faster response time, preventing the output from deviating further from its regulating value. See the Compensation Design section for more details.
Compensation Design
The power-stage transfer function consists of one double pole and one zero. The double pole is introduced by the output filtering inductor, L, and the output filtering capacitor, C O . The ESR of the output filtering capacitor determines the zero. The double pole and zero frequencies are given as follows: fP1_ LC = fP2 _ LC = 1 R + ESR 2 x L x C O x O RO + RL 1 2 x ESR x CO
VRIPPLE(ESR) = IP-P x ESR I VRIPPLE(ESL) = P-P x ESL t ON or: I VRIPPLE(ESL) = P-P x ESL t OFF whichever is greater. It should be noted that the above ripple voltage components add vectrorially rather than algebraically, thus making VRIPPLE a conservative estimate. The peak inductor current (IP-P) is: V -V V IP-P = IN OUT x OUT fS x L VIN Use these equations for initial capacitor selection. Determine final values by testing a prototype or an evaluation circuit. A smaller ripple current results in less output-voltage ripple. Since the inductor ripple current is a function of the inductor value, the output-voltage ripple decreases with larger inductance. Use ceramic capacitors for low ESR and low ESL at the switching frequency of the converter. The low ESL of ceramic capacitors makes ripple voltages due to ESL negligible. Load-transient response depends on the selected output capacitance. During a load transient, the output instantly changes by ESR x ILOAD. Before the controller can respond, the output deviates further, depending on the inductor and output capacitor values. After a short
14
fZ _ ESR =
where RL is equal to the sum of the output inductor's DC resistance and the internal switch resistance, RDS(ON). A typical value for RDS(ON) is 35m. RO is the output load resistance, which is equal to the rated output voltage divided by the rated output current. ESR is the total ESR of the output-filtering capacitor. If there is more than one output capacitor of the same type in parallel, the value of the ESR in the above equation is equal to that of the ESR of a single-output capacitor divided by the total number of output capacitors. The high-switching-frequency range of the MAX8833 allows the use of ceramic output capacitors. Since the ESR of ceramic capacitors is typically very low, the frequency of the associated transfer-function zero is higher than the unity-gain crossover frequency, fC, and the zero cannot be used to compensate for the double pole created by the output filtering inductor and capacitor. The double pole produces a gain drop of 40dB and a phase shift of 180 per decade. The error amplifier must compensate for this gain drop and phase shift to achieve a stable high-bandwidth closed-loop system. Therefore, use type III compensation as shown in Figure 4. Type III compensation possesses three poles and two zeros with the first pole, fP1_EA, located at 0Hz (DC). Locations of other poles and zeros of type III compensation are given by: fZ1_ EA = 1 2 x R7 x C9
______________________________________________________________________________________
Dual, 3A, 2MHz Step-Down Regulator MAX8833
fZ2 _ EA = 1 2 x R4 x C11 1 2 x R7 x C10 1 2 x R8 x C11 C9 = 2.5 x VIN R 2 x fC x R4 x 1 + L RO
fP2 _ EA =
fP3 _ EA =
These equations are based on the assumptions that C9 >> C10, and R4 >> R8, which are true in most applications. Placement of these poles and zeros is determined by the frequencies of the double pole and ESR zero of the power stage transfer function. It is also a function of the desired closed-loop bandwidth. Figure 5 shows the pole zero cancellations in the type III compensation design. The following section outlines the step-by-step design procedure to calculate the required compensation components. Begin by setting the desired output voltage as described in the Setting the Output Voltage section. The crossover frequency fC (or closed-loop, unity-gain bandwidth of the regulator) should be between 10% and 20% of the switching frequency, f S . A higher crossover frequency results in a faster transient response. Too high of a crossover frequency can result in instability. Once f C is chosen, calculate C9 (in farads) from the following equation:
where V IN is the input voltage in volts, f C is the crossover frequency in Hertz, R4 is the upper feedback resistor (in ohms), RL is the sum of the inductor resistance and the internal switch on-resistance, and RO is the output load resistance (VOUT/IOUT). Due to the underdamped nature of the output LC double pole, set the two zero frequencies of the type III compensation less than the LC double-pole frequency to provide adequate phase boost. Set the two zero frequencies to 80% of the LC double-pole frequency. Hence: R7 = L x CO x (RO + ESR) 1 x RL + RO 0.8 x C9 L x CO x (RO + ESR) 1 x RL + RO 0.8 x R4
C11 =
Set the third compensation pole, f P3_EA, at f Z_ESR, which yields: R8 = CO x ESR C11
OPEN-LOOP GAIN COMPENSATION TRANSFER FUNCTION THIRD POLE DOUBLE POLES
GAIN
SECOND POLE POWER-STAGE TRANSFER FUNCTION
FIRST AND SECOND ZEROS
FREQUENCY
Figure 5. Pole Zero Cancellations in Compensation Design
______________________________________________________________________________________ 15
Dual, 3A, 2MHz Step-Down Regulator MAX8833
Set the second compensation pole at 1/2 the switching frequency. Calculate C10 as follows: C10 = 1 x R7 x fS * * Connect input, output, and VDL capacitors to the power ground plane (PGND_). Keep the path of switching currents short and minimize the loop area formed by LX_, the output capacitor(s), and the input capacitor(s). Place the IC decoupling capacitors as close as possible to the IC pins, connecting all other groundterminated capacitors, resistors, and passive components to the reference or analog ground plane (AGND). Separate the power and analog ground planes, using a single-point common connection point (typically, at the CIN cathode. Connect the exposed pad to the analog ground plane, allowing sufficient copper area to help cool the device. If the exposed pad is used as a common PGND_-to-AGND connection point, avoid running high current through the exposed pad by using separate vias to connect the PGND_ pins to the power ground plane rather than connecting them to the exposed pad on the top layer. Use caution when routing feedback and compensation node traces; avoid routing near high dV/dt nodes (LX_) and high-current paths. Place the feedback and compensation components as close as possible to the IC pins. Reference the MAX8833 Evaluation Kit for an example layout.
The recommended range for R4 is 2k to 10k. Note that the loop compensation remains unchanged if only R6's resistance is altered to set different outputs.
*
Applications Information
PCB Layout Guidelines
Careful PCB layout is critical to achieve low switching losses and clean, stable operation. The switching power stage requires particular attention. It is highly recommended to duplicate the MAX8833 layout for optimum performance. If deviation is necessary, follow these guidelines for a good PCB layout: * A multilayer PCB is recommended. Use inner-layer ground (and power) planes to minimize noise coupling. * Place the input ceramic decoupling capacitor directly across and as close as possible to IN_ and PGND_. This is to help contain the high switching currents within a small loop. Connect IN_ and PGND_ separately to large copper areas to help cool the IC and further improve efficiency and long-term reliability. *
*
*
*
*
16
______________________________________________________________________________________
Dual, 3A, 2MHz Step-Down Regulator MAX8833
INPUT 2.35V TO 3.6V C16 0.1F VDD R11 10 C8 0.22F
IN1 C1 10F C4 OUT1 0.1F 1.2V/3A C18 47F C3 0.1F PGND1 L1 0.56H BST1 C6 0.1F LX1 R8 200 C11 1000pF R7 10k C9 330pF COMP1
VDD
VDL
IN2 C2 0.1F PGND2 BST2 C17 0.1F LX2 GND R9 1k C15 220pF COMP2 R10 27k C13 150pF L2 0.56H C19 22F C20 0.1F OUT2 1.8V/3A C23 10F
R4 10k
R13 40.2k
MAX8833
R6 10k
C10 OPEN
FB1
FB2
C14 OPEN C12 0.022F VDD R10 20k
R12 29k
VDD R15 20k PWRGD1 EN1 ON OFF C5 0.022F
REFIN SS1 PWRGD1 EN1 EXPOSED PAD
SS2 FSYNC PWRGD2 EN2 R5 10k
PWRGD2 EN2 ON OFF
Figure 6. 1MHz Typical Application Circuit
______________________________________________________________________________________
17
Dual, 3A, 2MHz Step-Down Regulator MAX8833
INPUT 2.5V TO 3.6V C16 0.1F VDD R11 10 C8 0.22F
IN1 C1 10F C4 OUT1 0.1F 0.9V/3A C18 47F C3 0.1F PGND1 L1 1H BST1 C6 0.1F LX1 R8 200 C11 1000pF OUT2 R7 10k C9 330pF COMP1
VDD
VDL
IN2 C2 0.1F PGND2 BST2 C17 0.1F LX2 GND R9 1k C15 220pF COMP2 PGND2 R10 27k C13 150pF L2 1H C19 22F C20 0.1F OUT2 1.8V/3A C23 10F
R4 10k
R13 40.2k
MAX8833
R1 1k VDD R19 1k PWRGD1 EN1 ON OFF R15 20k
C10 OPEN
FB1 REFIN C7 1000pF SS1 PWRGD1 EN1 EXPOSED PAD
FB2
C14 OPEN C12 0.022F VDD R10 20k
R12 20k
SS2 FSYNC PWRGD2 EN2 R5 5k
PWRGD2 EN2 ON OFF
Figure 7. Tracking DDR Application Circuit
18
______________________________________________________________________________________
Dual, 3A, 2MHz Step-Down Regulator
Pin Configuration
PROCESS: BiCMOS
PGND1 BST1 BST2 LX1 LX2 LX1 LX2
Chip Information
MAX8833
TOP VIEW
24 PGND1 25 PGND1 26 IN1 27 IN1 28 EN1 29 COMP1 30 FB1 31 SS1 32 1 PWRGD1
23
22
21
20
19
18
17 16 15 14 13 PGND2 PGND2 IN2 IN2 EN2 COMP2 FB2 SS2
MAX8833
PGND2 12 11 10 9 8 PWRGD2
+
2 REFIN 3 VDD 4 GND 5 N.C. 6 VDL 7 FSYNC
THIN QFN (5mm x 5mm)
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19
Dual, 3A, 2MHz Step-Down Regulator MAX8833
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
21-0140
K
1
2
20
______________________________________________________________________________________
QFN THIN.EPS
Dual, 3A, 2MHz Step-Down Regulator
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
MAX8833
PACKAGE OUTLINE, 16, 20, 28, 32, 40L THIN QFN, 5x5x0.8mm
21-0140
K
2
2
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
21 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products. Inc.

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