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FUJITSU SEMICONDUCTOR DATA SHEET
DS04-28216-2E
ASSP For Video Applications
CMOS
8-bit 100 MSPS A/D Converter
MB40C328
s DESCRIPTION
MB40C328 is a high-speed A/D converter using a fast CMOS technology.
s FEATURES
* * * * * * * * * Resolution : Linearity error : Maximum conversion rate : Power supply voltage : Digital input/output voltage range : Analog input voltage range : Analog input capacitance : Power dissipation : Additional features : 8 bit 0.40% (standard) 100 MSPS (minimum) 3.3 V single (standard) CMOS level compatible 0 to 3.0 V (2 Vp-p) 22 pF (standard) 210 mW (standard) Reference voltage generator circuit: VREFT = 3.0 V, VREFB = 1.0 V High impedance output, power down function 1:2 demultiplex output enable (RESET action enable) 1/2 deviding clock output Cross sampling at 50 MHz (two-phase CLK) enable (CLKA, CLKB) : LQFP48 (7 mm x 7 mm, lead pitch 0.5 mm)
* Package
s PACKAGE
48-pin plastic LQFP
(FPT-48P-M05)
MB40C328
s PIN ASSIGNMENT
DA0 (LSB)
CLKOA
VREFT
DVDD
AVDD
DVSS
AVSS
VRT
DA1
DA2 38
48
47
46
45
44
43
42
41
40
39
VR2 VR1 AVDD AVSS VREFB VRB AVSS VINA AVDD CKSEL CE AVSS
1 2 3 4 5 6 7 (TOP VIEW) 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
37 36 35 34 33 32 31 30 29 28 27 26 25
DA3
VR3
DA4 DA5 DA6 DA7 (MSB) DVSS CLKA CLKB CLK RESET DVDD DB0 (LSB) DB1
AVDD
DVDD
DVSS
(MSB) DB7
OE
DSEL
CLKOB
DB6
DB5
DB4
DB3
2
DB2
MB40C328
s PIN DESCRIPTION
Pin No. 3, 9, 13, 45 16, 27, 43 4, 7, 12, 44 18, 32, 41 33 to 40 19 to 26 11 14 10 15 28 29 31 30 42 17 8 2 1 48 46 47 6 5 Symbol AVDD DVDD AVSS DVSS DA7 to DA0 DB7 to DB0 CE OE CKSEL DSEL RESET CLK CLKA CLKB CLKOA CLKOB VINA VR1 VR2 VR3 VRT VREFT VRB VREFB Analog power supply (+3.3 V) Digital power supply (+3.3 V) Analog power supply ground pin (0 V) Digital power supply ground pin (0 V) Digital output pin (Port A) DA7: MSB, DA0: LSB Digital output pin (Port B) DB7: MSB, DB0: LSB Power down at CE input "H" (internal pull-up resistor) Digital output (Both Port A, B) and clock output (CLKOA, CLKOB) are high impedance at OE input "H". Mode of operation setting input pin (Refer to s MODE SETTING) Dividing circuit reset input pin (See s TIMING CHART 2, 3) Clock input pin (max 100 MHz) A ch clock input pin (max 50 MHz) B ch clock input pin (max 50 MHz) Clock output pin (See s TIMING CHART 1 to 4) Clock output pin (See s TIMING CHART 1 to 4) Analog input pin Input range is VRT to VRB (0 V to 3.0 V: 2 Vp-p) Reference 1/4 voltage output pin (Add 0.1 F for AVSS) Reference 1/2 voltage output pin (Add 0.1 F for AVSS) Reference 3/4 voltage output pin (Add 0.1 F for AVSS) Reference voltage input pin on top side Reference voltage output pin = By connecting to VRT, 0.9 x AVDD (. . 3 V) is generated. Reference voltage input pin on bottom side Reference voltage output pin By connecting to VRB, 0.3 x AVDD (. . 1 V) is generated. = Description
The values in parentheses are standard.
s PRECAUTIONS ON USE
* Be sure to ground the pins of AVDD, DVDD, VRT, VRB, VR1, VR2, and VR3 via high-frequency capacitor. Place the high-frequency capacitor as close as possible to the pin. * To avoid generation of undesired current owing to indetermination of internal logic, set CE to "H" at powering on and input more than five clock pulses just after operation (CE: "H" "L").
3
MB40C328
s BLOCK DIAGRAM
CKSEL DSEL
VINA
CLKOA
AVDD
DVDD
VREFT
Mode setting Timing circuit
AVDD VRT
CLKA A ch FF A output buffer DA0 to DA7
CLK
CLK select
VR3 VR2 VR1
Output selector
CLKB
B ch
FF
B output buffer
DB0 to DB7
Timing circuit VRB AVDD AVSS
RESET
CE
CLKOB
AVSS
DVSS
OE
VREFB
4
MB40C328
s ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Symbol AVDD, DVDD VINA, VRT, VRB, VREFT, VREFB, VR1, VR2, VR3, CE, CKSEL Input/output voltage DA0 to DA7, DB0 to DB7, CLKOA, CLKOB, CLKA, CLKB, CLK, DSEL, OE, RESET TSTG Rating Min. -0.3 -0.3 Max. +4.0 AVDD+0.3* Unit V V
-0.3
DVDD+0.3*
V
Storage temperature * : Do not exceed +4.0 V.
-55
+125
C
WARNING: Semiconductor devices can be permanently damaged by application of stress (voltage, current, temperature, etc.) in excess of absolute maximum ratings. Do not exceed these ratings.
5
MB40C328
s RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Analog input voltage Analog reference voltage: T Analog reference voltage: B Analog reference voltage range Digital "H" level input voltage Digital "L" level input voltage Digital input current Single-phase clock frequency Two-phase clock frequency Minimum clock pulse width (single-phase) Minimum clock pulse width (two-phase) Clock pulse rising/falling time RESET signal setup time RESET signal hold time Operating temperature range OE, DSEL, RESET, CLK, CLKA, CLKB CKSEL, CE OE, DSEL, RESET, CLK, CLKA, CLKB CKSEL, CE IID fCLK fCLKA, fCLKB tWS+, tWS- tWD+, tWD- tr, tf ts th Ta VILD Symbol AVDD, DVDD VINA VRT VRB VRT - VRB VIHD Value Min. 3.00 VRB -- 0.00 1.90 DVDD - 0.5 AVDD - 0.5 -- -- -20 0.1 0.1 4.0 8.0 -- 3.0 3.0 -20 Typ. 3.30 -- -- -- 2.00 -- -- -- -- -- -- -- 5.0 10.0 2.0 -- -- -- Max. 3.60 VRT 3.00 -- 2.10 -- -- 0.5 0.5 5 100 50 -- -- -- -- -- 70 Unit V V V V V V V V V A MHz MHz ns ns ns ns ns C
WARNING: The recommended operating conditions are required in order to ensure the normal operation of the semiconductor device. All of the device's electrical characteristics are warranted when the device is operated within these ranges. Always use semiconductor devices within their recommended operating condition ranges. Operation outside these ranges may adversely affect reliability and could result in device failure. No warranty is made with respect to uses, operating conditions, or combinations not represented on the data sheet. Users considering application outside the listed conditions are advised to contact their FUJITSU representatives beforehand.
6
MB40C328
s ELECTRICAL CHARACTERISTICS
* DC Characteristics in Analog Section
(AVDD = DVDD = 3.00 V to 3.60 V, Ta = -20C to +70C) Parameter Resolution Linearity error Differential linearity error Analog input capacity Reference voltage: T Reference voltage: B Reference current Analog supply current Digital supply current Standby current Symbol -- LE DLE CINA VREFT VREFB IRB AIDD DIDD ISB Value Min. -- -- -- -- 0.88 x AVDD 0.27 x AVDD -15 -- -- -- Typ. 8 0.40 0.20 22 0.91 x AVDD 0.3 x AVDD -10 42.0 20.0 100 Max. -- 0.6 0.36 -- 0.94 x AVDD 0.33 x AVDD -- 85.0 40.0 -- Unit bit % % pF V V mA mA mA mA
* DC Characteristics in Digital Section
(AVDD = DVDD = 3.00 V to 3.60 V, Ta = -20C to +70C) Parameter Digital "H" level output voltage Digital "L" level output voltage Digital "H" level output current Digital "L" level output current Symbol VOHD VOLD IOHD IOLD Value Min. DVDD - 0.4 -- -400 -- Typ. -- -- -- -- Max. DVDD 0.4 -- 1.6 Unit V V A mA
7
MB40C328
* Switching Characteristics
(AVDD = DVDD = 3.00 V to 3.60 V, Ta = -20C to +70C) Parameter Maximum conversion rate Aperture time Timing chart 1 Timing chart 2 Digital output delay time Timing chart 3 Timing chart 4 Symbol fS tAD tpdS tpdSO tpdM1 tpdM1O tpdM2 tpdM2O tpdD tpdDO Value Min. 100 -- 2.5 tWS+ + 2.5 2.5 T + 2.5 2.5 T + 2.5 2.5 tWD + 2.5
+
Typ. -- 1.7 6.0 tWS+ + 6.0 5.5 T + 5.5 5.5 T + 5.5 6.5 tWD + 6.5
+
Max. -- -- 9.0 tWS+ + 10 10 T + 10 10 T + 10 11 tWD + 11
+
Unit MSPS ns ns ns ns ns ns ns ns ns
s DIGITAL OUTPUT BUFFER LOAD CIRCUIT
To the measurement point CL = 18 pF
Measurement point
DVSS
Note: CL includes a stray capacitance of a probe and a fixture.
s MODE SETTING
CKCEL H H L L DCEL H L H L Mode CLK input-straight output mode CLK input-demultiplex output (in-phase) mode CLK input-demultiplex output (two-phase) mode Two-phase CLK input mode (CLKA, CLKB) Timing Chart Timing chart 1 Timing chart 2 Timing chart 3 Timing chart 4
8
MB40C328
s TIMING CHART 1
CLK input-straight output mode * * * * * * * CLK = 100 MHz (max) CLKA = CLKB = "L" (DVSS) CKSEL = "H" (AVDD) DSEL = "H" (DVDD) RESET = "H" (DVDD) CE = "L" (AVSS) OE = "L" (DVSS)
tr
tf DVDDI - 0.5 V 0.5 V
tWS+
tWS- 1.5 V
VIHD CLK input VIHD
N-1 N tAD
N+1
N+2
N+3
N+4
N+5 tpdS (max) tpdS (typ) tpdS (min)
N+6
N+7
VINA input
VOHD DA0 to DA7 VOLD VOHD DB0 to DB7 VOLD VOHD CLKOA VOLD VOHD CLKOB VOLD
N DVDD - 0.4 V N+1 0.4 V
N-7
N-6
N-5
N-4
N-3
N-2
N-1
ALL "L" fix
tpdSO(max) tpdSO(typ) tpdSO(min) DVDD - 0.4 V 0.4 V
ALL "L" fix
* VINA input -- Sampling at CLK rising * DA0 to DA7 -- Output (after 5 CLK + tpdS from Sampling) at CLK rising
9
MB40C328
s TIMING CHART 2
CLK input-demultiplex output (in-phase) mode * * * * * * CLK = 100 MHz (max) CLKA = CLKB = "L" (DVSS) CKSEL = "H" (AVDD) DSEL = "L" (DVSS) CE = "L" (AVSS) OE = "L" (DVSS)
tr
tf DVDD - 0.5 V 0.5 V
T
tWS+ tWS- 1.5 V
VIHD CLK input VILD
N-1 N-2
N-1
N tAD
N+1
N+2
N+3
N+4
N+5
N+6
N+7
N+8
N+9
N + 10
VINA input VOHD or N - 10 or N - 8 DA0 to DA7 VOLD
N - 10 N-9 N-9
N-7 or N - 8 N-8
N-5 or N - 6
N-3 or N - 4
VOHD or N - 11 or N - 9 or N - 9 or N - 7 DB0 to DB7 VOLD VOHD CLKOA VOLD VOHD CLKOB VOLD
th tS th tS 1.5 V
N - 10 N - 8
N-6 or N - 7
N-4 or N - 5
tpdM1(max) tpdM1(typ) tpdM1(min) N+1 DVDD - 0.4 V N-1 N+3 or N - 2 0.4V tpdM1(max) tpdM1(typ) tpdM1(min) N N-2 DVDD - 0.4 V N+2 or N - 3 0.4V tpdM1O(max) tpdM1O(typ) tpdM1O(min) DVDD - 0.4 V 0.4 V
ALL "L" fix
VIHD RESET input VILD
* VINA input -- Sampling at CLK rising * DA0 to DA7 -- Output (after 5 CLK + tpdM1 from Sampling) at CLK rising * DB0 to DB7 -- Output (after 6 CLK + tpdM1 from Sampling) at CLK rising
10
MB40C328
s TIMING CHART 3
CLK input-demultiplex output (two-phase) mode * * * * * * CLK = 100 MHz (max) CLKA = CLKB = "L" (DVSS) CKSEL = "L" (AVSS) DSEL = "H" (DVDD) CE = "L" (AVSS) OE = "L" (DVSS)
tWS+ tWS-
tr
VIHD CLK input VILD
N-3 N-2
tf DVDD - 0.5 V 0.5 V N-1 N tAD N+1 N+2
T
1.5 V N+3 N+4 N+5 N+6 N+7 N+8 N+9 N + 10
VINA input
N-9 N-9
VOHD or N - 10 or N - 8 DA0 to DA7 VOLD
N - 10 N-8
tpdM2(max) tpdM2(typ) tpdM2(min) N-5 or N - 6 N-3 or N - 4 N-1 or N - 2 tpdM2(max) tpdM2(typ) tpdM2(min) N-2 or N - 3
N-7 or N - 8 N-8
N+1 DVDD - 0.4 V 0.4 V
N+3
VOHD or N - 9 or N - 9 or N - 7 DB0 to DB7 VOLD VOHD CLKOA VOLD
N N+2
N-6 or N - 7
N-4 or N - 5
DVDD-0.4 V 0.4 V tpdM2O(max) tpdM2O(typ) tpdM2O(min)
VOHD CLKOB VOLD
th tS th tS 1.5 V
DVDD - 0.4 V 0.4 V tpdM2O(max) tpdM2O(typ) tpdM2O(min) DVDD - 0.4 V 0.4 V
VIHD RESET input VILD
* VINA input -- Sampling at CLK rising * DA0 to DA7 -- Output (after 5 CLK + tpdM2 from Sampling) at CLK rising * DB0 to DB7 -- Output (after 5 CLK + tpdM2 from Sampling) at CLK rising
11
MB40C328
s TIMING CHART 4
Two-phase CLK input mode (CLKA, CLKB) * * * * * * * CLK = "L" (DVSS) or "H" (DVDD) CLKA = CLKB = 50 MHz (max) CKSEL = "L" (AVSS) DSEL = "L" (DVSS) RESET = "H" (DVDD) or "L" (DVSS) CE = "L" (AVSS) OE = "L" (DVSS)
tWD-
tWD+
tr
tf DVDD - 0.5 V 0.5 V 1.5 V
VIHD CLKA input VILD
tWD+ tWD- tr
tf DVDD - 0.5 V 0.5 V 1.5 V
VIHD CLKB input VILD DA0 to DA7 VINA input
N(Ach) tAD
N + 1(Bch) N + 2(Ach) N + 3(Bch) N + 4(Ach) N + 5(Bch) N + 6(Ach) N + 7(Bch) tAD
tpdD(max) tpdD(typ) tpdD(min) N-4 N-2
VOHD DA0 to DA7 VOLD VOHD DB0 to DB7 VOLD
N-6
N DVDD-0.4 V 0.4 V tpdD(max) tpdD(typ) tpdD(min)
N-5
N-3
N-1 tpdDO(max) tpdDO(typ) tpdDO(min)
N+1 DVDD - 0.4 V 0.4 V
VOHD CLKOA VOLD VOHD CLKOB VOLD
DVDD - 0.4 V 0.4 V tpdDO(max.) tpdDO(typ) tpdDO(min.) DVDD - 0.4 V 0.4 V
* VINA input -- Sampling (A ch) at CLKA falling Sampling (B ch) at CLKB falling * DA0 to DA7 -- Output (after 2.5 CLK + tpdD from Sampling) at CLKA rising * DB0 to DB7 -- Output (after 2.5 CLK + tpdD from Sampling) at CLKB rising
12
MB40C328
s TYPICAL CONNECTION EXAMPLE
DA0(LSB)
CLKOA
DA1
DA2
VRT
+
+3.3 V
DA3
+3.3 V
VR3 48
VREFT 47
VRT 46
AVDD 45
AVSS 44
DVDD 43
CLKOA 42
DVSS 41
(LSB)DA0 40
DA1 39
DA2 38
1 VR2 2 VR1 3 AVDD 4 AVSS
+
DA3 37 DA4 36 DA5 35 DA6 34
VRB
DA4 DA5 DA6 DA7(MSB)
(MSB)DA7 33 DVSS 32 (TOP VIEW) CLKA 31 CLKB 30 CLK 29 RESET 28 DVDD 27 (LSB)DB0 26 19 DB7(MSB) 17 CLKOB 15 DSEL 16 DVDD DB1 25 20 DB6 21 DB5 22 DB4 23 DB3 24 DB2 13 AVDD 18 DVSS
5 VREFB 6 VRB 7 AVSS
CLKA CLKB CLK RESET
VINA
8 VINA 9 AVDD
CKSEL CE
10 CKSEL 11 CE 12 AVSS 14 OE
DB0(LSB) DB1
DSEL
CLKOB
OE
(MSB)DB7
DB6
DB5
DB4
DB3
0.1 F
+ To avoid voltage fluctuation at operation of reference voltage generator circuit (VREFT, VREFB)
VREFT: 150 F, VREFB: 330 F
DB2
13
MB40C328
s ORDERING INFORMATION
Part number MB40C328PFV Package 48-pin Plastic LQFP (FPT-48P-M05) Remark
14
MB40C328
s PACKAGE DIMENSION
48-pin Plastic LQFP (FPT-48P-M05)
Note ) Pins width and pins thickness include plating thickness.
9.000.20(.354.008)SQ 7.000.10(.276.004)SQ
36 25
37
24
0.08(.003)
INDEX
Details of "A" part 1.50 -0.10
+0.20 +.008
48
13
(Mounting height)
.059 -.004 "A"
LEAD No.
1
12
0.500.08 (.020.003)
0.18 -0.03 .007
+0.08 +.003 -.001
0.08(.003)
M
0.1450.055 (.006.002)
0~8
0.500.20 (.020.008) 0.45/0.75 (.018/.030)
0.100.10 (.004.004) (Stand off) 0.25(.010)
C
1998 FUJITSU LIMITED F48013S-3C-6
Dimensions in mm (inches).
15
MB40C328
FUJITSU LIMITED
For further information please contact:
Japan FUJITSU LIMITED Corporate Global Business Support Division Electronic Devices KAWASAKI PLANT, 4-1-1, Kamikodanaka, Nakahara-ku, Kawasaki-shi, Kanagawa 211-8588, Japan Tel: +81-44-754-3763 Fax: +81-44-754-3329
All Rights Reserved. The contents of this document are subject to change without notice. Customers are advised to consult with FUJITSU sales representatives before ordering. The information and circuit diagrams in this document are presented as examples of semiconductor device applications, and are not intended to be incorporated in devices for actual use. Also, FUJITSU is unable to assume responsibility for infringement of any patent rights or other rights of third parties arising from the use of this information or circuit diagrams. The contents of this document may not be reproduced or copied without the permission of FUJITSU LIMITED. FUJITSU semiconductor devices are intended for use in standard applications (computers, office automation and other office equipments, industrial, communications, and measurement equipments, personal or household devices, etc.). CAUTION: Customers considering the use of our products in special applications where failure or abnormal operation may directly affect human lives or cause physical injury or property damage, or where extremely high levels of reliability are demanded (such as aerospace systems, atomic energy controls, sea floor repeaters, vehicle operating controls, medical devices for life support, etc.) are requested to consult with FUJITSU sales representatives before such use. The company will not be responsible for damages arising from such use without prior approval. Any semiconductor devices have inherently a certain rate of failure. You must protect against injury, damage or loss from such failures by incorporating safety design measures into your facility and equipment such as redundancy, fire protection, and prevention of over-current levels and other abnormal operating conditions. If any products described in this document represent goods or technologies subject to certain restrictions on export under the Foreign Exchange and Foreign Trade Control Law of Japan, the prior authorization by Japanese government should be required for export of those products from Japan.
http://www.fujitsu.co.jp/
North and South America FUJITSU MICROELECTRONICS, INC. 3545 North First Street, San Jose, CA 95134-1804, USA Tel: +1-408-922-9000 Fax: +1-408-922-9179 Customer Response Center Mon. - Fri.: 7 am - 5 pm (PST) Tel: +1-800-866-8608 Fax: +1-408-922-9179
http://www.fujitsumicro.com/
Europe FUJITSU MICROELECTRONICS EUROPE GmbH Am Siebenstein 6-10, D-63303 Dreieich-Buchschlag, Germany Tel: +49-6103-690-0 Fax: +49-6103-690-122
http://www.fujitsu-fme.com/
Asia Pacific FUJITSU MICROELECTRONICS ASIA PTE LTD #05-08, 151 Lorong Chuan, New Tech Park, Singapore 556741 Tel: +65-281-0770 Fax: +65-281-0220
http://www.fmap.com.sg/
F0001 (c) FUJITSU LIMITED Printed in Japan

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