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OKI Semiconductor ML9227
GENERAL DESCRIPTION
FEDL9227-01
Issue Date:Dec., 18, 2002
27-Bit Duplex/Triplex VFD Controller/Driver with Digital Dimming, ADC and Key scan
The ML9227 is a full CMOS controller/driver for Duplex or Triplex vacuum fluorescent display tube. It conststs of 27-segment driver outputs and 3-grid pre-driver outputs, so that it can drive directly up to 81-segment VFD. ML9227 features a digital dimming function, a 6-ch ADC, a 5 x 5 key scan circuit and an encoder type switch interface. ML9227 provides an interface with a microcontroller only by three signal lines: DATA I/O, CLOCK, CS.
FEATURES
* Supply voltage (VDISP) * Duplex/Triplex selectable * Applicable VFD tube : 8 to 18.5 V (Built-in 5 V regulator for logic)
: 2 Grids x 27 Anodes VFD tube : 3 Grids x 27 Anodes VFD tube * 27-segment driver outputs : IOH = -5 mA at VOH = VDISP-0.8 V (SEG1 to 19) IOH = -10 mA at VOH = VDISP-0.8 V (SEG20 to 27) IOL = 500 uA at VOL = 2.0 V (SEG1 to 27) * 3-grid pre-driver outputs : IOH = -5 mA at VOH = VDISP-0.8 V IOL = 10 mA at VOL = 2.0 V * Built-in digital dimming circuit (10-bit resolution) * Built-in 6-ch A/D converter * Built-in 5 x 5 keyscan circuit * Interface circuit for an encoder type rotary switch * Built-in oscillation circuit (external R and C) * Built-in Power-On-Reset circuit * Package: 64-pin plastic QFP (QFP64-P-1420-1.00-BK) Product name: ML9227GA
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ML9227
BLOCK DIAGRAM
SEG1 SEG27 GRID1 GRID2 GRID3
D-GND VDISP VCC (5 V) VREG (5 V) L-GND 5V Regulator & Power On Reset
0H 7H
27 Segment Driver
3 Grid pre Driver
POR in1-27 Out1-27 81 to 27 Segment Control in1-27 in1-27
1H Mode Select POR 0H POR
Out1-27
Segment Latch
2H 0H POR
Out1-27
Segment Latch
3H 0H POR
Out1-27
Segment Latch
in1-3
1 in1-27
2 in1-27
3 in1-27
CS CLOCK DATA I/O
POR POR
Out1-3
Out1-27
27 bit Shift Register
4H POR
Control
3 bit Shift Register
in1-10 Dimming Latch Out1-10
OSC0
OSC
POR
10 bit Digital Dimming
DIM OUT SYNC OUT1 DUP/TRI
Timing Generator
SYNC OUT2
6ch, 8 bit A/D Converter
7H 5H 6H
5 x 5 Key Scan and Encoder Switch Interface
INT
CH1
CH6
COL1
COL5
ROW1
ROW5
A1
B1
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ML9227
PIN CONFIGURATION (TOP VIEW)
SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 54 SEG13 53 SEG12 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 24 25 26 27 28 29 30 31 20 21 22 23 32
64
63
62
61
60
59
58
57
56
VDISP SEG25 SEG26 SEG27 GRID1 GRID2 GRID3 D-GND ROW1 ROW2 ROW3 ROW4 ROW5 COL1 COL2 COL3 COL4 COL5 NC
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19
55
VDISP SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 CH6 CH5 CH4 CH3 CH2 CH1 VREG
A1
B1
SYNC OUT2
SYNC OUT1
L-GND DATA I/O
VCC OSC0
DUP/TRI
CLOCK
CS
NC: No connection (OPEN) 64-pin Plastic QFP
DIM OUT
INT
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PIN DESCRIPTIONS
Pin 1, 51 8 26 24 33 40 to 50, 52 to 59 Symbol VDISP D-GND L-GND VCC VREG Type -- -- -- O O Description Power supply pins Pin1 and pin51 should be connected externally. D-GND is ground pin for the VFD driver circuit. L-GND is ground pin for the logic circuit. Pins 8 and 26 should be connected externally. 5 V output pin for internal logic portion and external logic circuit Reference voltage (5 V) output pin for A/D converter Segment (anode) signal output pins for a VFD tube These pins can be directly connected to the VFD tube. External circuit is not required. lOH -5 mA Segment (anode) signal output pins for a VFD tube These pins can be directly connected to the VFD tube. External circuit is not required. lOH -10 mA Inverted Grid signal output pins 5, 6, 7 GRID1 to 3 O For pre-driver, the external circuit is required. lOL 10 mA Chip Select input pin Data input/output operation is valid when this pin is set at a High level. Serial clock input pin Data is input and/or output through the DATA l/O pin at the rising edge of the serial clock. Serial data input/output pin Data is input to/comes out from the shift register at the rising edge of the serial clock. Interrupt signal output to micro controller. When any key of key matrix is pressed or released, key scanning is started. After the completion of the one cycle, this pin goes to high level and keeps the high level until key scan stop mode is selected. Duplex/Triplex operation select input pin Duplex (1/2 duty) operation is selected when this pin is set at a VCC level. Triplex (1/3 duty) operation is selected when this pin is set at a GND level. Analog voltage input pin for the 8-bit A/D converter Input pin for the encoder type rotary switch. The phase of an An/Bn input is detected. Return inputs from the key matrix These pins are active low. When key matrix are in the inactive sate, these pins are at high level through the internal pull-up resistors. All the inputs do not have the chattering absorption function for the key scans. Key switch scanning outputs Normally low level is output through these pin. When any switch of key matrix is depressed or released, key scanning is started and is continued until key scan stop mode is selected. When key scan stop mode is selected, all outputs of ROW1 to 5 go back to low level.
SEG1 to 19
O
60 to 64, 2 to 4
SEG20 to 27
O
29
CS
l
28
CLOCK
l
27
DATA l/O
l/O
22
INT
O
23
DUP/TRl
l
34 to 39 20, 21
CH1 to 6 A1, B1
l O
14 to 18
COL1 to 5
l
9 to 13
ROW1 to 5
O
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ML9227
Pin 32 30, 31
Symbol DIM OUT SYNC OUT 1, 2
Type O O Dimming pulse output
Description Connect this pin to the slave side DIM IN pin. Synchronous signal input Connect these pins to the SYNC IN1 and SYNC IN2 pins of a slave side. RC oscillator connecting pins. Oscillation frequency depends on display tubes to be used. For details refer to ELECTRICAL CHARACTERISTICS. VCC OSC0 R
25
OSC0
l/O
Co
19
NC
-
OPEN pins.
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Power Dissipation Storage Temperature Symbol VDISP VIN PD TSTG lO1 Output Current lO2 lO3 lO4 Ta = 85 C Condition -- -- QFP64-P-1420-1.00-BK -- SEG1 to 19 SEG20 to 27 GRID1 to 3 DIM OUT, SYNC OUT1, SYNC OUT2 Rating -0.3 to +20 -0.3 to +6.0 250 -55 to +150 -10.0 to +2.0 -20.0 to +2.0 -10.0 to +20.0 -2.0 to +2.0 Unit V V mW C mA mA mA mA
RECOMMENDED OPERATING CONDITIONS
Parameter Driver Supply Voltage High Level Input Voltage Low Level Input Voltage Clock Frequency Oscillation Frequency Frame Frequency Operating Temperature Symbol VDISP VIH VIL fC fOSC fFR TOP Condition -- All inputs except OSC0 All inputs except OSC0 -- R = 10 k 5%, Co= 27 pF 5% R = 10 k 5% Co = 27 pF 5% -- 1/3 Duty 1/2 Duty Min. 8.0 3.8 -- -- 2.2 179 268 -40 Typ. 13.0 -- -- -- 3.3 269 403 -- Max. 18.5 -- 0.8 2.0 4.4 358 538 +85 Unit V V V MHz MHz Hz Hz C
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ELECTRICAL CHARACTERISTICS DC Characteristics
(Ta = -40 to +85C, VDISP = 8.0 to 18.5 V) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol VIH VIL lIH1 lIH2 lIL1 lIL2 VOH1 High Level Output Voltage VOH2 VOH3 VOH4 VOL1 Low Level Output Voltage VOL2 VOL3 VOL4 Supply Current Supply Voltage for Logic IDISP VL Applied pin *1) *1) *2) *3) *2) *3) SEG1 to 19 SEG20 to 27 GRID1 to 3 *4) SEG1 to 19 SEG20 to 27 GRID1 to 3 *5) VDISP VCC VDISP = 9.5V VDISP = 9.5V Condition -- -- VIH = 3.8 V VIH = 3.8 V VIL = 0.0 V VIL = 0.0 V lOH1 = -5 mA lOH2 = - 10 mA lOH3 = -5 mA lOH4 = -200 A Output Open lOL1 = 500 A lOL2 = 500 A lOL3 = 10 mA lOL4 = 300 A R = 10 k 5%, Co= 27 pF 5% no load C = 0.01 F 10%, lo = 0 to -10 mA Min. 3.8 -- -5.0 -70 -5.0 -160 VDISP-0.8 VDISP-0.8 VDISP-0.8 4.0 4.5 -- -- -- -- -- 4.5 Max. -- 0.8 +5.0 -5.0 +5.0 -10 -- -- -- -- -- 2.0 2.0 2.0 0.4 10 5.5 Unit V V A A A A V V V V V V V V V mA V
*1) *2) *3) *4) *5)
CS, CLOCK, DATA I/O, DUP/TRI, A1, B1, COL1 to 5 CS, CLOCK, DATA I/O, DUP/TRI, A1, B1 COL1 to 5 DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2 DATA I/O, INT, DIM OUT, SYNC OUT1, SYNC OUT2, ROW1 to 5
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AC Characteristics
(Ta = -40 to +85C, VDISP = 8.0 to 18.5 V) Parameter Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time CS Off Time CS Setup Time (CS-Clock) CS Hold Time (Clock-CS) DATA Output Delay Time (Clock-DATA l/O) Output Slew Rate Time VDD Rise Time VDD Off Time CS Wait Time Symbol fC tCW tDS tDH tCSL tCSS tCSH tPD tR tF tPRZ tPOF tRSOFF CL=100 pF Condition -- -- -- -- R = 10 k 5%, Co = 27 pF 5% -- -- -- tR = 20 to 80% tF = 80 to 20% Min. -- 200 200 200 20 200 200 -- -- -- -- 5.0 400 Max. 2.0 -- -- -- -- -- -- 1.0 2.0 2.0 100 -- -- Unit MHz ns ns ns s ns ns s s s s ms s
Mounted in a unit Mounted in a unit, VDISP = 0.0 V --
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TIMING DIAGRAMS Data Input Timing
CS
tCSS 1/fC tCW tCW tCSH
tCSL
-3.8 V -0.8 V -3.8 V -0.8 V
CLOCK tDS DATA I/O (INPUT) VALID VALID tDH
-3.8 V VALID VALID -0.8 V
Data Output Timing
CS
tCSS tCSH
-3.8 V -0.8 V -3.8 V
CLOCK tPD DATA I/O (OUTPUT)
-0.8 V -3.8 V -0.8 V
Reset Timing
VDISP tPRZ tRSOFF -3.8 V CS -0.0 V tPOF -0.8 VDISP -0.0 V
Driver Output Timing
SEG1-27, GRID1-3 tR tF -0.8 VDISP -0.2 VDISP
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ML9227
A/D Converter Characteristics
(Ta = -40 to +85C, VDISP = 8.0 to 18.5 V) Parameter Reference Voltage (VREG) Output Current Input Voltage Range Conversion Time/Channel Resolution Linearity error Differentiation linearity error Zero scale error Full-scale error Condition -- -- -- R = 10 k 5%, C2 = 27 pF 5% Min. 4.5 -- GND 256 -- -- -- -- -- Typ. 5.0 -- -- 310 -- -- -- -- -- Max. 5.5 -10 VREG 394 8 2.0 2.0 +2.0 -2.0 Unit V mA V s bit LSB LSB LSB LSB
Terminological definition
The minimum input analog value which can be recognized. It can decompose into 28= 256,(VRH-VRL)/256,in 8 bits. The deviation between the ideal conversion characteristic as a 8-bit A/D converter and the actual conversion characteristic is said. (Therefore, a quantization error is not included.) The ideal conversion characteristic means the step which divided the voltage between VRH to VRL into 256 division into equal parts. The smoothness of the conversion characteristic is shown, and ideally, the width of the analog input voltage corresponding to change for 1 bit of digital outputs is 1LSB= (VRH-VRL)/256, and says the deviation of this ideal bit size and the bit size in the arbitrary points of the conversion range. Digital output "000H" to "001H" changes, and the deviation of the ideal conversion characteristic of a point and the actual conversion characteristic is said. Digital output "0FEH" to "0FFH" changes, and the deviation of the ideal conversion characteristic of a point and the actual conversion characteristic is said.
Resolution Linearity error
Differentiation linearity error
Zero scale error
Full scale error
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Key scan Characteristics
(Ta = -40 to +85C, VDISP = 8.0 to 18.5 V) Parameter Key scan Cycle Time Key scan Pulse Width Condition R = 10 k 5%, Co = 27 pF 5% R = 10 k 5%, Co = 27 pF 5% Min. 160 32 Typ. 194 39 Max. 246 49 Unit s s
Rotary switch characteristic
(Ta = -40 to +85C, VDISP = 8.0 to 18.5 V)
Parameter Phase input time Phase input fixed time
Sign
tABW tABH
Condition R = 10 k 5%, Co = 27 pF 5%
Min. 950
Typ. --
Max. --
Unit s
Rotary switch input timing
A
B
tABW tABH tABW tABH tABW tABW
Key scan Timing
Key scan Cycle Time ROW1 Key scan Pulse Width ROW2
ROW3
ROW4
ROW5
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Output Timming(Duplex Operation) *1 bit time = 4/fOSC
Solid line : The dimming data is 1016/1024 Dotted line : The dimming data is 64/1024 2048 bit times(1 display cycle) GRID1 1016 bit times 8 bit times GRID2 1016 bit times 1016 bit times 8 bit times 8 bit times VDISP D-GND VDISP D-GND VDISP 64 bit times SEG1-27 64 bit times 64 bit times D-GND VDISP D-GND 5V DIM OUT L-GND 5V SYNC OUT1 L-GND 5V SYNC OUT2 L-GND
GRID3
Output Timming(Triplex Operation) *1 bit time = 4/fOSC
Solid line : The dimming data is 1016/1024 Dotted line : The dimming data is 64/1024 3072 bit times(1 display cycle) GRID1 1016 bit times 8 bit times GRID2 1016 bit times 8 bit times 8 bit times VDISP D-GND VDISP D-GND 1016 bit times 64 bit times SEG1-27 64 bit times 64 bit times VDISP D-GND VDISP D-GND 5V DIM OUT L-GND 5V SYNC OUT1 L-GND 5V SYNC OUT2 L-GND
GRID3
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ML9227
FUNCTIONAL DESCRIPTION
Power-on Reset When power is turned on, ML9227 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: * The contents of the shift registers and latches are set to "0". * The digital dimming duty cycle is set to "0". * All segment outputs are set to Low level. * GRID1 outputs are set to Low level. * GRID2 to 3 outputs are set to High level. * All the ROW outputs are set to Low level. * INT output is set to Low level.
Mode Data ML9227 has the seven function modes. The function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data (M0 to M2) is as follows:
FUNCTION MODE 0 1 2 3 4 5 6 7 OPERATING MODE Segment Data for GRID1-3 Input Segment Data for GRID1 Input Segment Data for GRID2 Input Segment Data for GRID3 Input Digital Dimming Data Input Key scan Stop Switch Data Output A/D Data Output FUNCTION DATA M0 0 1 0 1 0 1 0 1 M1 0 0 1 1 0 0 1 1 M2 0 0 0 0 1 1 1 1
Data Input and Output Data input and output through the DATA-I/O pin is valid only when the CS pin is set at a High level. The input data to DATA I/O pin is shifted into the shift register at the rising edge of the serial clock. The data is automatically loaded to the latches when the CS pin is set at a Low level. 10-bit dimming data (D1 to D10) and 27-bit segment data (S1 to S27) are used for inputting of dimming data and display data. To transfer these two data, the mode data (M0 to M2) must be sent after each of these data succeddingly. The output data from the DATA I/O pin is output from the shift register at the rising edge of the serial clock. ML9227 outputs 48-bit (6ch x 8bits) A/D data (A11 to A68) and 29-bit key data (S11 to S55, R1 and Q1 to Q3). To receive these data, the mode data (M0 to M2) must be sent first and then CS must be set once to Low level and set again to High level. Then inputting serial clocks, these data are output from the DATA I/O pin. When the CS pin is set at a Low level, the DATA I/O pin returns to an input pin. To stop the keyscan, the only mode data (M0 to M2) must be sent. After the mode data transfer, the key scanning is stopped immediately.
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Segment Data Input [Function Mode: 0 to 3] * ML9227 receives the segment data when function mode 0 to 3 are selected. * The same segment data is transferred to the 3 segment data latch correspond to GRID1 to 3 at the same time when the function mode 0 is selected. * The segment data is transferred to only one segment data latch that is selected by mode data, when the function mode is 1, 2 or 3 is selected. * Segment output (SEG1 to 27) becomes High level when the segment data (S1 to 27) is High level. [Data Format] Input Data Segment Data Mode Data
Bit Input Data 1 S1 LSB 2 S2
: : :
30 bits 27 bits 3 bits
3 S3 4 S4 --------------------24 25 S24 S25 26 S26 27 S27 MSB 28 29 30 M0 M1 M2 Mode Data (3 bits)
Segment Data (27 bits)
[Bit correspondence between segment output and segment data]
SEG n Segment data SEG n Segment data 1
S1
2
S2
3
S3
4
S4
5
S5
6
S6
7
S7
8
S8
9
S9
10
S10
11
S11
12
S12
13
S13
14
S14
15
S15
16
S16
17
S17
18
S18
19
S19
20
S20
21
S21
22
S22
23
S23
24
S24
25
S25
26
S26
27
S27
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Digital Dimming Data Input [Function Mode: 4] * ML9227 receives the digital dimming data when function mode 4 is selected. * The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. * The 10-bit digital dimming data is input from LSB. [Data Format] Input Data Digital Dimming Data Mode Data
Bit Input Data 1 D1 LSB 2 D2
: : :
13 bits 10 bits 3 bits
3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 D9 10 D10 MSB 11 12 13 M0 M1 M2 Mode Data (3 bits)
Digital Dimming Data (10 bits)
(LSB) D1 D2 0 0 1 0
D3 0 0
D4 0 0
Dimming Data D5 D6 D7 0 0 0 0 0 0
D8 0 0
D9 0 0
(MSB) D10 0 0
Duty Cycle 0/1024 1/1024
1 0 1
1 0 0
1 0 0
0 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1015/1024 1016/1024 1016/1024
1
1
1
1
1
1
1
1
1
1
1016/1024
Key scan Stop [Function Mode: 5] * ML9227 stops a key scanning when function mode 5 are selected. * To select this mode, the only mode data (M0 to M2) is needed. * The actual time lag range between receipt of the keyscan stop command and the ceasing of scanning is 2.4 s to 3.6 s [Input Data Format] Input Data Mode Data
Bit Input Data 28 M0
: :
29
3 bits 3 bits
30 M2
M1
Mode Data (3 bits)
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Switch Data Output [Function Mode: 6] * ML9227 output the switch data when function mode 6 is selected. * To select this mode, the only mode data (M0 to M2) is needed. * When ML9227 recieves this mode, the DATA I/O pin is changed to an output pin. * 29-bit switch data come out from the DATA I/O pin synchronizing with the rise edge of the clock. * When the CS pin is set at the low level, the DATA I/O pin returns to an input pin. * R1 = 0, implies Right rotation of the knob (Clockwise) * R1 = 1, implies Left rotation of the knob (Counter Clockwise) * Contact Count bits are Q1 (LSB) to Q3 (MSB) [Input Data Format] Input Data Mode Data
Bit Input Data 28 M0
: :
29
3 bits 3 bits
30 M2
M1
Mode Data (3 bits)
[Output Data Format] Output Data 5 x 5 push switch Data Encoder switch Data
Bit Output Data Bit Output Data 1
S11
: : :
2
S12
29 bits 25 bits 4 bits
3 4
S14
5
S15
6
S21
7
S22
8
S23
9
S24
10
S25
11
S31
12
S32
13
S33
14
S34
15
S35
S13
16
S41
17
S42
18
S43
19
S44
20
S45
21
S51
22
S52
23
S53
24
S54
25
S55
26
R1
27
Q1
28
Q2
29
Q3
Sij: i = ROW1 to 5, j = COL1 to 5 Sij = 1: Switch ON Sij = 0: Switch OFF
[5x5 Push switch]
ROW1 COL1
S11 S21 S31 S41 S51
ROW2
ROW3
ROW4
ROW5
COL2
S12 S22 S32 S42 S52
COL3
S13 S23 S33 S43 S53
COL4
S14 S24 S34 S44 S54
COL5
S15 S25 S35 S45 S55
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Key scan Keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. Then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. The INT pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the INT pin can be used as an interrupt signal. [Key scan Timing]
ROW 0
ROW 1 ROW 2
ROW 3
ROW 4 1 Cycle INT
Depress/Release
Key scan stop mode is selected.
Note:
Key scanning cannot be stopped by selecting the key scan stop mode only once if: - key scanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the key scan stop mode is selected. To stop key scanning, it is required to select the key scan stop mode once again.
Depress Depress Release
INT
Key scan
Key scan
CS
MODE5 MODE5 : Key scan stop
MODE5
MODE5
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A/D Data Output [Function Mode: 7] * ML9227 output the A/D data when function mode 7 is selected. * To select this mode, the only mode data (M0 to M2) is needed. * When ML9227 recieves this mode, the DATA I/O pin is changed to an output pin. * 48-bit A/D data come out from the DATA I/O pin synchronizeing with the rise edge of the clock. * When the CS pin is set at the low level, the DATA I/O pin returns to an input pin. [Input Data Format] Input Data Mode Data
Bit Input Data 28 M0
: :
29
3 bits 3 bits
30 M2
M1
Mode Data (3 bits)
[Output Data Format] Output Data A/D Data
Bit Output Data A/D Bit Output Data A/D Bit Output Data A/D 1
A11 (LSB)
: :
2
A12
48 bits 48 bits
4
A14
3
A13
5
A15
6
A16
7
A17
8
9
10
A22
11
A23
12
A24
13
A25
14
A26
15
A27
16
A28 (MSB)
A18 A21 (MSB) (LSB)
17
A31 (LSB)
18
A32
19
A33
CH1 20 21
A34 A35
22
A36
23
A37
24
25
26
A42
27
A43
CH2 28 29
A44 A45
30
A46
31
A47
32
A48 (MSB)
A38 A41 (MSB) (LSB)
33
A51 (LSB)
34
A52
35
A53
CH3 36 37
A54 A55
38
A56
39
A57
40
41
42
A62
43
A63
CH4 44 45
A64 A65
46
A66
47
A67
48
A68 (MSB)
A58 A61 (MSB) (LSB)
CH5
CH6
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ML9227
The rotary encoder switch function As Figure 1 shows, the rotary encoder switch circuit is consisted of Phase detection, Interrupt generation, Up/down counter, Direction latch and Parallel-in serial-out shift register.
A B
Phase Detection
UP DOWN
Interrupt Generation
for INT
UP/DOWN Counter
Q3 Q2 Q1
Direction Latch
R1
P-in/S-out Shift Register
Output data
Figure 1 The Rotary Encoder Switch Circuit
1) Phase detection 1-1) Clockwise When signal A and B input as Figure 2, the phase detection circuit outputs UP signal after the chattering absorption period. At this time, the output INT also goes to high level, so this signal can be used as an interrupt. The INT stays High level until the keyscan stop mode is selected.
A
B chattering absorption time UP (internal)
INT
Figure 2 The Input and Output Timing in Case of Clockwise
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1-2) Counter clockwise When signal A and B input as Figure 3, the phase detection circuit outputs Down signal after the chattering absorption period. At this time, the output INT also goes to High level. The INT stays High level until the keyscan stop mode is selected.
A chattering absorption time B
DOWN (internal)
INT
Figure 3 The Input and Output Timing in Case of Counter Clockwise
2) UP/DOWN COUNTER When the UP/DOWN COUNTER is input UP, it counts up and when it is input DOWN, it counts down. But if overcounte of "111" occurs the UP/DOWN COUNTER stays "111".
A
B Q1, Q2, Q3 100 010 110 001 101 011 111 111
Figure 4
3) Direction latch When the Direction latch is input DOWN the output R goes "1". But if the UP pulse is input and the counts value change to plus value, the output R goes to "0".
A
B
R1 Q1, Q2, Q3 100 010 100 000 100 010
Figure 5
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FEDL9227-01
OKI Semiconductor
ML9227
4) P-in/S-out shift resistor When the keyscan stop mode is selected and CS goes L, INT signal goes "L".
CS C1 C2 C3 C4 C5 C1 C2 C3 C4 C5 Data I/O ROW1 ROW2 C1 C2 C3 C4 C5 R1 Q1 Q2 Q3 ROW5 Rotary
CLOCK
INT
INT signal goes "L".
Figure 6
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Application Circuits OKI Semiconductor
VCC VDISP SEG1 SEG56 GRID1 GRID2 GRID3 S1 S2 S3 G1 G2 S57 S58 S59 SEG1 SEG27 GRID1 DUP/TRI M/S GND GRID2 GRID3 ML9213 (SLAVE)
VDISP VDD
ML9227 (MASTER)
VDISP
DUP/TRI
VREG
CH1 to 6
GND
Duplex VFD Tube
5x5 SYNC OUT 2 SYNC OUT 1 DIM OUT SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 SYNC OUT 2 SYNC OUT 1 DIM OUT OSC 0 L-GND GND
ROW1 to 5 Ef
Key matrix
COL1 to 5
1. Circuit for the duplex VFD tube with 118 segments (2 Grid x 59 Anode)
Micro controller
CS DATA I/O CLOCK VCC
OSC0
L-GND
FEDL9227-01
ML9227
GND
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OKI Semiconductor
VCC VDISP SEG1 ML9213 (SLAVE) SEG56 GRID1 GRID2 GRID3 S1 S2 S3 G1 G2 G3 Ef SYNC OUT 2 SYNC OUT 1 DIM OUT SYNC OUT 2 SYNC OUT 1 DIM OUT SYNC IN 2 SYNC IN 1 DIM IN CS DATA IN CLOCK OSC 1 OSC 0 L-GND GND S57 S58 S59 DUP/TRI M/S GND SEG1 SEG27 GRID1 GRID2 GRID3
VDD
VDISP
ML9227 (MASTER)
VDISP
VREG
CH1 to 6
GND
5x5 Key matrix
ROW1 to 5
Triplex VFD Tube
COL1 to 5
DUP/TRI
GND
CS DATA I/O CLOCK
2. Circuit for the triplex VFD tube with 177 segments (3 Grid x 59 Anode)
Micro controller
VCC
OSC0
L-GND
FEDL9227-01
GND
ML9227
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FEDL9227-01
OKI Semiconductor
ML9227
PACKAGE DIMENSIONS
(Unit: mm)
QFP64-P-1420-1.00-BK
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 1.25 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL9227-01
OKI Semiconductor
ML9227
REVISION HISTORY
Document No.
FEDL9227-01
Date
Dec., 18, 2002
Page Previous Current Edition Edition
- - Final edition 1
Description
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FEDL9227-01
OKI Semiconductor
ML9227
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not, unless specifically authorized by Oki, authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2002 Oki Electric Industry Co., Ltd.
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