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OKI Semiconductor ML9228
82-Bit Duplex/Triplex VFD Controller/Driver with Digital Dimming, Keyscan
FEDL9228-01 Issue Date: Oct. 20, 2004
GENERAL DESCRIPTION
The ML9228 is a full CMOS controller/driver for Duplex or Triplex vacuum fluorescent display tube. It conststs of 82-segment driver outputs and 3-grid pre-driver outputs, so that it can drive directly up to 246-segment VFD. ML9228 features a digital dimming function, a 5 x 6 keyscan circuit.
FEATURES
* Driver Supply voltage (VDISP) * Logic Supply voltage (VDD) * Duplex/Triplex selectable * Applicable VFD tube : 8.0V to 18.5V : 3.3V10%, 5.0V10%
: 2 Grids x 82 Anodes VFD tube : 3 Grids x 82 Anodes VFD tube * 82-segment driver outputs : IOH = -6 mA at VOH = VDISP-0.8 V (SEG1 to 82) * 3-grid pre-driver outputs : IOL = 10 mA at VOL = 2 V * Built-in digital dimming circuit (10-bit resolution) * Built-in 5 x 6 keyscan circuit * Built-in oscillation circuit (external R and C) * Built-in Power-On-Reset circuit * Package: 128-pin plastic QFP (QFP128-P-1420-0.50-K) (ML9228 GA)
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BLOCK DIAGRAM
SEG1 SEG82 GRID1 GRID2 GRID3
D-GND VDISP VDD Power On Reset L-GND BLANK
0H 7H
82 Segment Driver
3 Grid pre Driver
POR Out1-82 246 to 82 Segment Control in1-82
in1-82
in1-82
1H Mode Select POR 0H POR
Out1-82
Segment Latch
2H 0H POR
Out1-82
Segment Latch
3H 0H POR
Out1-82
Segment Latch
in1-3
1 in1-82
2 in1-82
3 in1-82
RESET CS CLOCK DATA I/O
Control
Out1-3
3 bit Shift Register
Out1-82
82 bit Shift Register
4H POR
in1-10 Dimming Latch Out1-10
POR
POR
OSCO
OSC
POR
10 bit Digital Dimming
7H
DUP/TRI
Timing Generator
5H 6H
5 x 6 Key Scan Interface
INT
COL1
COL6
ROW1
ROW5
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PIN CONFIGURATION (TOP VIEW)
126 SEG73 125 SEG72
124 SEG71 123 SEG70
122 SEG69 121 SEG68
120 SEG67 119 SEG66
118 SEG65 117 SEG64
116 SEG63 115 SEG62
114 SEG61 113 SEG60 112 SEG59
109 SEG56 108 SEG55
111 SEG58 110 SEG57
107 SEG54 106 SEG53
128 NC 127 NC
105 SEG52 104 NC
103 NC 102 NC 101 NC 100 SEG51 99 SEG50 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 75 74 73 72 71 70 SEG49 SEG48 SEG47 SEG46 SEG45 SEG44 SEG43 SEG42 SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 NC NC 69 68 67 66 65 64
NC NC SEG74 SEG75 SEG76 SEG77 SEG78 SEG79 SEG80 SEG81 SEG82 VDISP D-GND VDD INT ROW2 ROW3 ROW4
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 17 18 19
ROW1 16
ROW5 20 COL2 COL3 COL4 COL5 COL6 DUP/TRI COL1 21 22 23 24 25 26
27 BLANK 28 RESET 29 CS 30
CLOCK 31 DATA I/O 32 OSC0 33 L-GND 34 NC 35 NC 36 NC 37 NC 38 39 40 41 43 45 42 44
NC: No connection 64-pin Plastic QFP
59 60 47 48 54 55 56 58 61 62 46 49 50 51 52 53 57 63
NC NC
SEG8 SEG9
SEG13 SEG14
GRID1
D-GND
SEG11 SEG12
SEG10
NC : No Connection
SEG15
SEG16 SEG17
GRID2 GRID3 SEG1 SEG2
SEG3
SEG4
SEG5
SEG6
SEG7
VDISP
NC NC
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PIN DESCRIPTIONS
Pin 12,42 14 13,41 37 3 to 11, 46 to 62, 67 to 100, 105 to 126 43,44,45 GRID1 to 3 O Symbol VDISP VDD D-GND L-GND Type -- -- -- -- Description High Level Power supply pins Pin12 and pin42 should be connected externally. Low Level Power supply pin D-GND is ground pins for the VFD driver circuit. L-GND is ground pin for the logic circuit. Pin13,Pin37 and Pin41 should be connected externally. Segment (anode) signal output pins for a VFD tube These pins can be directly connected to the VFD tube. External circuit is not required. lOH -6 mA, lOL 500 Inverted Grid signal output pins For pre-driver, the external circuit is required. lOH -6 mA, lOL 10 mA Chip Select input pin Data input/output operation is valid when this pin is set at a High level. Serial clock input pin Data is input and/or output through the DATA l/O pin at the rising edge of the serial clock. Serial data input/output pin Data is input to/comes out from the shift register at the rising edge of the serial clock. Interrupt signal output to microcontroller. When any key of key matrix is pressed or released, key scanning is started. After the completion of the one cycle, this pin goes to high level and keeps the high level until keyscan stop mode is selected. Duplex/Triplex operation select input pin. DUP/TRl = L(L-GND) : Triplex DUP/TRl = H(VDD) COL1 to 6 : Duplex Return inputs from the key matrix These pins are active low. When key matrix are in the inactive sate, these pins are at high level through the internal pull-up resistors. All the inputs do not have the chattering absorption function for the keyscans. Key switch scanning outputs Normally low level is output through these pin. When any switch of key matrix is depressed or released, key scanning is started and is continued until keyscan stop mode is selected. When keyscan stop mode is selected, all outputs of ROW1 to 5 go back to low level. Display off control input. 28 BLANK I BLANK = L(L-GND) : Display off(SEG1-82 = L) BLANK = H(VDD) : Display on
SEG1 to 82
O
30
CS
l
31
CLOCK
l
32
DATA l/O
l/O
15
INT
O
27
DUP/TRl
l
21 to 26
l
16 to 20
ROW1 to 5
O
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Pin
Symbol
Type
Description The contents of the shift registers and latches are set to "0". The digital dimming duty cycle is set to "0". All segment outputs are set to Low level. Grid1 output is set to Low level. Grid2,3 outputs are set to High level. All the ROW outputs are set to Low level. INT output is set to Low level. RC oscillator connecting pins VDD OSC0 Oscillation frequency changes with display pipes to be used. Please refer to the right figure. R2 C2
29
RESET
I
33
OSC0
l/O
1,2,35,36, 37,38, 40,63,64, 66,65, 101,102, 127,128 NC -- Open pin
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ABSOLUTE MAXIMUM RATINGS
Parameter Supply Voltage Input Voltage Power Dissipation Storage Temperature Output Current Symbol VDISP VDD VIN PD TSTG lO1 lO3 lO4 Condition -- -- -- Ta = 85 C -- SEG1 to 82 GRID1 to 3 ROW1 to 5, DATA I/O Rating -0.3 to +20 -0.3 to +6.5 -0.3 to +6.0 590 -55 to +150 -10.0 to +2.0 -7.0 to +20.0 -2.0 to +2.0 mA mW C V Unit
RECOMMENDED OPERATING CONDITIONS
Parameter Driver Supply Voltage Logic Supply Voltage Symbol VDISP VDD Condition -- Unit Supply Voltage 5.0 V (Typ) Unit Supply Voltage 3.3 V (Typ) VDD = 5.0 V (Typ) Oscillation Frequency fOSC R2 = 10 k 5%, C2 = 27 pF 5% VDD = 3.3 V (Typ) R2 = 8.2 k 5%, C2 = 27 pF 5% VDD=5.0 V (Typ) R2 = 10 k 5% C2 = 27 pF 5% Frame Frequency fFR VDD=3.3 V (Typ) R2 = 8.2 k 5% C2 = 27 pF 5% Operating Temperature TOP -- 1/3 Duty 1/2 Duty 211 317 -40 269 403 -- 325 Hz 488 +85 C 1/3 Duty 1/2 Duty Min. 8.0 4.5 3.0 2.6 2.6 211 317 Typ. 13.0 5.0 3.3 3.3 3.3 269 403 Max. 18.5 5.5 3.6 4.0 4.0 325 Hz 488 MHz MHz V Unit
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ELECTRICAL CHARACTERISTICS DC Characteristics
(Ta = -40 to +85C, VDD = 5.0 V10%, VDISP = 8.0 to 18.5 V) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol VIH VIL lIH1 lIH2 lIL1 lIL2 VOH1 High Level Output Voltage VOH2 VOH3 VOL1 Low Level Output Voltage VOL2 VOL3 IDISP Supply Current Applied pin *1) *1) *2) *3) *2) *3) SEG1 to 82 GRID1 to 3 *4) SEG1 to 82 GRID1 to 3 *5) VDISP VDISP = 9.5V Condition -- -- VIH = VDD VIH = VDD VIL = 0.0 V VIL = 0.0 V lOH1 = -6 mA lOH3 = -6 mA lOH4 = -120 A Output Open VDISP = 9.5V lOL1 = 500 A lOL3 = 10 mA lOL4 = 120 A Min. 0.7 VDD -- -5.0 -50 -5.0 -120 VDISP-0.8 VDISP-0.8 VDD-0.8 VDD-0.2 -- -- -- -- Max. -- 0.3 VDD +5.0 -5.0 +5.0 -10 -- -- -- -- 2.0 2.0 0.8 500 A V V Unit V V A A
R2 = 10 k 5%, C2 = 27 pF 5%, no load IDD ISLP1 ISLP2 VDD VDISP VDD R2 = 10 k 5%, C2 = 27 pF 5% Sleep Mode Sleep Mode -- -- -- 5.0 5.0 5.0 mA A A
*1) *2) *3) *4) *5)
CS, CLOCK, DATA I/O, DUP/TRI, BLANK, RESET, COL1 to 6 CS, CLOCK, DATA I/O, DUP/TRI, BLANK, RESET COL1 to 6 DATA I/O, INT DATA I/O, INT, ROW1 to 5
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DC Characteristics
(Ta = -40 to +85C, VDD = 3.3 V10%, VDISP = 8.0 to 18.5 V) Parameter High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Symbol VIH VIL lIH1 lIH2 lIL1 lIL2 VOH1 High Level Output Voltage VOH3 VOH3 VOL1 Low Level Output Voltage VOL2 VOL3 IDISP Supply Current Applied pin *1) *1) *2) *3) *2) *3) SEG1 to 82 GRID1 to 3 *4) SEG1 to 82 GRID1 to 3 *5) VDISP VDISP = 9.5V Condition -- -- VIH = VDD VIH = VDD VIL = 0.0 V VIL = 0.0 V lOH1 = -6 mA lOH3 = -6 mA lOH4 = -100 A Output Open VDISP = 9.5V lOL1 = 500 A lOL3 = 10 mA lOL4 = 100 A Min. 0.8 VDD -- -5.0 -40 -5.0 -100 VDISP-0.8 VDISP-0.8 VDD -0.4 VDD -0.2 -- -- -- -- Max. -- 0.2 VDD +5.0 -5.0 +5.0 -5.0 -- -- -- -- 2.0 2.0 0.4 500 A V V Unit V V A A
R2 = 8.2 k 5%, C2 = 27 pF 5%, no load IDD ISLP1 ISLP2 VDD VDISP VDD R2 = 8.2 k 5%, C2 = 27 pF 5% Sleep Mode Sleep Mode -- -- -- 4.0 5.0 5.0 mA A A
*1) *2) *3) *4) *5)
CS, CLOCK, DATA I/O, DUP/TRI, BLANK, RESET, COL1 to 6 CS, CLOCK, DATA I/O, DUP/TRI, BLANK, RESET COL1 to 6 DATA I/O, INT DATA I/O, INT, ROW1 to 5
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AC Characteristics
(Ta = -40 to +85C, VDD = 5.0 V10%, VDISP = 8.0 to 18.5 V) Parameter Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time CS Off Time CS Setup Time (CS-Clock) CS Hold Time (Clock-CS) DATA Output Delay Time (Clock-DATA l/O) Output Slew Rate Time VDD Rise Time VDD Off Time CS Wait Time Symbol fC tCW tDS tDH tCSL tCSS tCSH tPD tR tF tPRZ tPOF tRSOFF CL=100 pF Condition -- -- -- -- R2 = 10 k 5%, C2 = 27 pF 5% -- -- -- tR = 20 to 80% tF = 80 to 20% Min. -- 200 200 200 20 200 200 -- -- -- -- 5.0 400 Max. 2.0 -- -- -- -- -- -- 1.0 2.0 2.0 100 -- -- Unit MHz ns ns ns s ns ns s s s s ms s
Mounted in a unit Mounted in a unit, VDD = 0.0 V --
(Ta = -40 to +85C, VDD = 3.3 V10%, VDISP = 8.0 to 18.5 V) Parameter Clock Frequency Clock Pulse Width Data Setup Time Data Hold Time CS Off Time CS Setup Time (CS-Clock) CS Hold Time (Clock-CS) DATA Output Delay Time (Clock-DATA l/O) Output Slew Rate Time VDD Rise Time VDD Off Time CS Wait Time Symbol fC tCW tDS tDH tCSL tCSS tCSH tPD tR tF tPRZ tPOF tRSOFF CL=100 pF Condition -- -- -- -- R2 = 8.2 k 5%, C2 = 27 pF 5% -- -- -- tR = 20 to 80% tF = 80 to 20% Min. -- 400 400 400 20 400 400 -- -- -- -- 5.0 400 Max. 1.0 -- -- -- -- -- -- 1.0 2.0 2.0 100 -- -- Unit MHz ns ns ns s ns ns s s s s ms s
Mounted in a unit Mounted in a unit, VDD = 0.0 V --
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TIMING DIAGRAMS
VDD = 3.3 V10% 0.8 VDD 0.2 VDD VDD = 5.0 V10% 0.7 VDD 0.3 VDD
VIH VIL
Data Input Timing
CS tCSS 1/fC tCW CLOCK tDS DATA I/O (INPUT) VALID VALID tDH - VIH VALID VALID - VIL tCW tCSH tCSL - VIH - VIL - VIH - VIL
Data Output Timing
tCSS CS tCSH CLOCK tPD DATA I/O (OUTPUT) - VIH - VIL - VIH - VIL - VIH - VIL
Power-On Reset Timing
VDD
tPRZ tRSOFF
tPOF
-0.8 VDD -0.0 V - VIH
CS - VIL
Driver Output Timing
BLANK tR tF -VIH -VIL -0.8 VDISP -0.2 VDISP tR tF -0.8 VDISP -0.2 VDISP
SEG1-82
GRID1-3
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Keyscan Characteristics
(Ta = -40 to +85C, VDD = 5.0 V10%, VDISP = 8.0 to 18.5 V) Parameter Keyscan Cycle Time Keyscan Pulse Width Condition R2 = 10 k 5%, C2 = 27 pF 5% R2 = 10 k 5%, C2 = 27 pF 5% Min. 160 32 Typ. 194 39 Max. 246 49 Unit s s
(Ta = -40 to +85C, VDD = 3.3 V10%, VDISP = 8.0 to 18.5 V) Parameter Keyscan Cycle Time Keyscan Pulse Width Condition R2 = 8.2 k 5%, C2 = 27 pF 5% R2 = 8.2 k 5%, C2 = 27 pF 5% Min. 160 32 Typ. 194 39 Max. 246 49 Unit s s
Keyscan Timing
Keyscan Cycle Time ROW1
Keyscan Pulse Width
ROW2
ROW3
ROW4
ROW5
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Output Timing (Duplex Operation) *1 bit time = 4/fOSC Solid line: When dimming data is made into 1016/1024 Dotted line: When dimming data is made into 64/1024
2048 bit times1 (display cycle) GRID1 1016 bit times 8 bit times GRID2 1016 bit times 1016 bit times 8 bit times 8 bit times VDISP D-GND VDISP D-GND VDISP 64 bit times SEG1-82 64 bit times 64 bit times D-GND VDISP D-GND
GRID3
Output Timing (Triplex Operation) *1 bit time = 4/fOSC Solid line: When dimming data is made into 1016/1024 Dotted line: When dimming data is made into 64/1024
3072 bit times (1 display cycle) GRID1 1016 bit times 8 bit times GRID2 1016 bit times 8 bit times 8 bit times VDISP D-GND VDISP D-GND 1016 bit times 64 bit times SEG1-82 64 bit times 64 bit times VDISP D-GND VDISP D-GND
GRID3
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FUNCTIONAL DESCRIPTION Power-on Reset When power is turned on, ML9228 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: * The contents of the shift registers and latches are set to "0". * The digital dimming duty cycle is set to "0". * All segment outputs are set to Low level. * Grid1 output is set to Low level. Grid2,3 outputs are set to High level. * All the ROW outputs are set to Low level. * INT output is set to Low level. Reset When power is turned on, ML9228 is initialized by the internal power-on reset circuit. The status of the internal circuit after initialization is as follows: * The contents of the shift registers and latches are set to "0". * The digital dimming duty cycle is set to "0". * All segment outputs are set to Low level. * Grid1 output is set to Low level. Grid2,3 outputs are set to High level. * All the ROW outputs are set to Low level. * INT output is set to Low level. * A command is received by the signal of Low(L-GND) level. Blank All segment outputs are set as a Low level. * A command is received by the signal of Low(L-GND) level. Data Input and Output Data input and output through the DATA-I/O pin is valid only when the CS pin is set at a High level. The input data to DATA I/O pin is shifted into the shift register at the rising edge of the serial clock. The data is automatically loaded to the latches when the CS pin is set at a Low level. 10-bit dimming data (D1 to D10) and 82-bit segment data (S1 to S82) are used for inputting of dimming data and display data. To transfer these two data, the mode data (M0 to M2) must be sent after each of these data succeddingly. The output data from the DATA I/O pin is output from the shift register at the rising edge of the serial clock. ML9228 outputs 30-bit key data (S11 to S56). To receive these data, the mode data (M0 to M2) must be sent first and then CS must be set once to Low level and set again to High level. Then inputting serial clocks, these data are output from the DATA I/O pin. When the CS pin is set at a Low level, the DATA I/O pin returns to an input pin. To stop the keyscan, the only mode data (M0 to M2) must be sent. After the mode data transfer, the key scanning is stopped immediately.
CS
CLOCK
DATA I/O
M0 M1 M2
M0 M1 M2
S11 S12 S13 S14 S15 S21 S22
S44 S45 S51 S52 S53 S54 S55 S56
Keyscan Stop Command
Switch Data Output Command
Switch Data
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Mode Data ML9228 has the seven function modes. The function mode is selected by the mode data (M0 to M2). The relation between function mode and mode data (M0 to M2) is as follows:
FUNCTION MODE 0 1 2 3 4 5 6 7 OPERATING MODE Segment Data for GRID1-3 Input Segment Data for GRID1 Input Segment Data for GRID2 Input Segment Data for GRID3 Input Digital Dimming Data Input Keyscan Stop Switch Data Output Sleep FUNCTION DATA M0 0 1 0 1 0 1 0 1 M1 0 0 1 1 0 0 1 1 M2 0 0 0 0 1 1 1 1
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Segment Data Input [Function Mode: 0 to 3] * ML9228 receives the segment data when function mode 0 to 3 are selected. * The same segment data is transferred to the 3 segment data latch correspond to GRID1 to 3 at the same time when the function mode 0 is selected. * The segment data is transferred to only one segment data latch that is selected by mode data, when the function mode is 1, 2 or 3 is selected. * Segment output (SEG1 to 82) becomes High level when the segment data (S1 to S82) is High level. [Data Format] Input Data Segment Data Mode Data
Bit Input Data 1 S1 2 S2
: : :
85 bits 82 bits 3 bits
3 S3 4 S4 --------------------79 80 81 S79 S80 S81 82 S82 83 84 85 M0 M1 M2 Mode Data (3 bits)
Segment Data (82 bits)
[Bit correspondence between segment output and segment data]
SEG n Segment SEG n Segment SEG n Segment SEG n Segment SEG n Segment SEG n Segment 1 data data data data data data
S1
2
S2
3
S3
4
S4
5
S5
6
S6
7
S7
8
S8
9
S9
10
S10
11
S11
12
S12
13
S13
14
S14
15
S15
16
S16
17
S17
18
S18
19
S19
20
S20
21
S21
22
S22
23
S23
24
S24
25
S25
26
S26
27
S27
28
S28
29
S29
30
S30
31
S31
32
S32
33
S33
34
S34
35
S35
36
S36
37
S37
38
S38
39
S39
40
S40
41
S41
42
S42
43
S43
44
S44
45
S45
46
S46
47
S47
48
S48
49
S49
50
S50
51
S51
52
S52
53
S53
54
S54
55
S55
56
S56
57
S57
58
S58
59
S59
60
S60
61
S61
62
S62
63
S63
64
S64
65
S65
66
S66
67
S67
68
S68
69
S69
70
S70
71
S71
72
S72
73
S73
74
S74
75
S75
76
S76
77
S77
78
S78
79
S79
80
S80
81
S81
82
S82
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Digital Dimming Data Input [Function Mode: 4] * ML9228 receives the digital dimming data when function mode 4 is selected. * The output duty changes in the range of 0/1024 (0%) to 1016/1024 (99.2%) for each grid. * The 10-bit digital dimming data is input from LSB. [Data Format] Input Data Digital Dimming Data Mode Data
Bit Input Data 1 D1 LSB 2 D2
: : :
13 bits 10 bits 3 bits
3 D3 4 D4 5 D5 6 D6 7 D7 8 D8 9 D9 10 D10 MSB 11 12 13 M0 M1 M2 Mode Data (3 bits)
Digital Dimming Data (10 bits)
(LSB) D1 D2 0 0 1 0
D3 0 0
D4 0 0
Dimming Data D5 D6 D7 0 0 0 0 0 0
D8 0 0
D9 0 0
(MSB) D10 0 0
Duty Cycle 0/1024 1/1024
1 0 1
1 0 0
1 0 0
0 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1 1 1
1015/1024 1016/1024 1016/1024
1
1
1
1
1
1
1
1
1
1
1016/1024
Keyscan Stop [Function Mode: 5] * ML9228 stops a key scanning when function mode 5 are selected. * To select this mode, the only mode data (M0 to M2) is needed. * The actual time lag range between receipt of the keyscan stop command and the ceasing of scanning is 2.4 s to 3.6 s [Input Data Format] Input Data Mode Data
Bit Input Data 83 M0
: :
84
3 bits 3 bits
85 M2
M1
Mode Data (3 bits)
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Switch Data Output [Function Mode: 6] * ML9228 output the switch data when function mode 6 is selected. * To select this mode, the only mode data (M0 to M2) is needed. * When ML9228 recieves this mode, the DATA I/O pin is changed to an output pin. * 30-bit switch data come out from the DATA I/O pin synchronizing with the rise edge of the clock. * When the CS pin is set at the low level, the DATA I/O pin returns to an input pin. * Contact Count bits are Q1 (LSB) to Q3 (MSB) [Input Data Format] Input Data Mode Data
Bit Input Data 83 M0
: :
84
3 bits 3 bits
85 M2
M1
Mode Data (3 bits)
[Output Data Format] Output Data 5 x 6 push switch Data
: :
30 bits 30 bits
6
S16
Bit 1 2 3 4 5 S11 S12 S13 S14 S15 Output Data Bit 13 14 15 16 17 S31 S32 S33 S34 S35 Output Data Bit 25 26 27 28 29 S51 S52 S53 S54 S55 Output Data Sij: i = ROW1 to 5, j = COL1 to 6 Sij = 1: Switch ON Sij = 0: Switch OFF
7
S21
8
S22
9
S23
10
S24
11
S25
12
S26
18
S36
19
S41
20
S42
21
S43
22
S44
23
S45
24
S46
30
S56
[5 x 6Push Switch] ROW1 COL1 COL2 COL3 COL4 COL5 COL6 ROW2 ROW3 ROW4 ROW5
=
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P-in/S-out shift resistor When the switch data output mode is selected and CS goes L, all the key data send to the shift resistor, and the up/down counter is reset and the INT signal goes "L".
CS C1 C2 C3 C4 C5 C6 Data I/O ROW1 CLOCK ROW4 ROW5 C1 C2 C3 C4 C5 C6 C1 C2 C3 C4 C5 C6
INT
When CS goes L, the up/down counter is reset and the INT goes "L".
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Keyscan Keyscanning is started only when depression or release of any key is detected in order to minimize noise caused by scanning signal. Then, keyscanning is continued until the keyscan stop mode is sent from a microcomputer. The INT pin goes to the high level at the completion of 1-cycle scanning after the keyscan start, so the (high level) signal sent from the INT pin can be used as an interrupt signal. [Keyscan Timing]
ROW 1
ROW 2 ROW 3
ROW 4
ROW 5 1 Cycle INT
Depress/Release
Keyscan stop mode is selected.
Note:
Keyscanning cannot be stopped by selecting the keyscan stop mode only once if: - keyscanning is started after depression or release of any key is detected, and then - a key is depressed or released again before the keyscan stop mode is selected. To stop keyscanning, it is required to select the keyscan stop mode once again.
Depress Depress Release
INT
Keyscan
Keyscan
Keyscan
CS
MODE5 MODE5 : Keyscan stop
MODE5
MODE5
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Sleep [Function Mode: 7] * ML9228 oscillation stops and segment display turns off when function mode 7 is selected. * key matrix is pushed, this mode will be canceled and it will usually become display mode. [Input Data Format] Input Data Mode Data
Bit Input Data 83 M0
: :
84
3 bits 3 bits
85 M2
M1
Mode Data (3 bits)
Wake up * Wake up by key press from COL6. Then, key scan is performed. * Wake up by CS assert(rising edge). Then, key scan does not carry out. * Oscillation restarts to accept normal operation. * Previous output for display data till updated by Each Mode. ROW1 COL1 COL2 COL3 COL4 COL5 COL6 If either of these keys is pushed, an oscillation will be started and it will usually return to operation. ROW2 ROW3 ROW4 ROW5
=
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OKI Semiconductor
VDD SEG1
VDISP
ML9228 SEG82 GRID1 GRID2 GRID3 S1 S2 S3 G1 G2 G3 S80 S81 S82
APPLICATION CIRCUITS
VDISP
VDD
5x6
ROW1 to 5
Key matrix
COL1 to 6
Triplex VFD Tube
BLANK
RESET
Ef
DUP/TRI
Circuit for the triplex VFD tube with 246 segments (3 Grid x 82 Anode)
Microcontroller
D-GND
GND
CS DATA I/O CLOCK
VDD
OSC0
L-GND
FEDL9228-01
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ML9228
GND
FEDL9228-01
OKI Semiconductor
ML9228
POWER SEQUENCE
* If the power sequence (please see below) recommended by Oki is not followed,it is possible to damage internal logic transistors. * Currently there is no definition for the time period between the point that VDD = 3.3V VDISP = 3.3V. * Oki recommends the following sequence.
18.0V
VDISP
3.3 V
VDD
2.0S
2.0S
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FEDL9228-01
OKI Semiconductor
ML9228
PACKAGE DIMENSIONS
(Unit: mm)
QFP128-P-1420-0.50-K
Mirror finish
5
Notes for Mounting the Surface Mount Type Package
Package material Lead frame material Pin treatment Package weight (g) Rev. No./Last Revised
Epoxy resin 42 alloy Solder plating (5m) 1.19 TYP. 4/Nov. 28, 1996
The surface mount type packages are very susceptible to heat in reflow mounting and humidity absorbed in storage. Therefore, before you perform reflow mounting, contact Oki's responsible sales person for the product name, package name, pin number, package code and desired mounting conditions (reflow method, temperature and times).
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FEDL9228-01
OKI Semiconductor
ML9228
REVISION HISTORY
Document No.
FEDL9228-01
Date
Oct. 20, 2004
Page Previous Current Edition Edition
Final edition 1
Description
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FEDL9228-01
OKI Semiconductor
ML9228
NOTICE 1. The information contained herein can change without notice owing to product and/or technical improvements. Before using the product, please make sure that the information being referred to is up-to-date. 2. The outline of action and examples for application circuits described herein have been chosen as an explanation for the standard action and performance of the product. When planning to use the product, please ensure that the external conditions are reflected in the actual circuit, assembly, and program designs. When designing your product, please use our product below the specified maximum ratings and within the specified operating ranges including, but not limited to, operating voltage, power dissipation, and operating temperature. Oki assumes no responsibility or liability whatsoever for any failure or unusual or unexpected operation resulting from misuse, neglect, improper installation, repair, alteration or accident, improper handling, or unusual physical or electrical stress including, but not limited to, exposure to parameters beyond the specified maximum ratings or operation outside the specified operating range. Neither indemnity against nor license of a third party's industrial and intellectual property right, etc. is granted by us in connection with the use of the product and/or the information and drawings contained herein. No responsibility is assumed by us for any infringement of a third party's right which may result from the use thereof. The products listed in this document are intended for use in general electronics equipment for commercial applications (e.g., office automation, communication equipment, measurement equipment, consumer electronics, etc.). These products are not authorized for use in any system or application that requires special or enhanced quality and reliability characteristics nor in any system or application where the failure of such system or application may result in the loss or damage of property, or death or injury to humans. Such applications include, but are not limited to, traffic and automotive equipment, safety devices, aerospace equipment, nuclear power control, medical equipment, and life-support systems. Certain products in this document may need government approval before they can be exported to particular countries. The purchaser assumes the responsibility of determining the legality of export of these products and will take appropriate and necessary steps at their own expense for these. No part of the contents contained herein may be reprinted or reproduced without our prior permission. Copyright 2004 Oki Electric Industry Co., Ltd.
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