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E2B0046-27-Y2 Semiconductor
Semiconductor MSM6794
DOT MATRIX LCD DRIVER WITH 128-CHANNEL RAM
This version: Nov. 1997 MSM6794 Previous version: Mar. 1996
GENERAL DESCRIPTION
The MSM6794 is a dot matrix graphic liquid crystal display LSI device to display bit maps. It drives an LCD panel for dot matrix graphic display under the control of a 4- or 8-bit microcomputer. All necessary functions for driving a bit map type LCD are built in on one chip. Therefore,by using the MSM6794, a bit map type dot matrix graphic liquid crystal display system can be implemented with a small number of chips. Since 1-bit data of the display RAM corresponds to the light-on/off of 1-dot of the LCD panel (bit map system), a flexible display, including kanji display, is possible. One chip comprises a graphic display system of a maximum of 12848 dots. This display can be expanded by using multiple chips. The MSM6794 uses CMOS process. Since it is an internal RAM type, the MSM 6794 features low power consumption, and is suited to display for battery-driven portable equipment.
FEATURES
* Segment outputs * Common outputs * Display duty * Bit map type internal RAM * Display data I/F * Standby function by program * LCD drive bias resistor (externally connected) * Built-in voltage multiplier circuit * LOGIC voltage * LCD driving voltage * Low current consumption * Number of pads : : : : : Maximum of 128 Maximum of 48 1/33, 1/41, 1/44, 1/48 6,144 bits (12848 bits) 8-bit parallel/serial switchable
: : : :
2.7 to 5.5V VBI 5 to 12V (positive voltage) Maximum of 10mA (in standby mode) 224
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Semiconductor
MSM6794
BLOCK DIAGRAM
SEG1
COM48 SEG128 COM1
LCD drive power supply V1, V3, V4, V6
Common driver
Segment driver Level shifter Data latch
2
LCD drive power supply V1, V2, V5, V6
2
Y decoder
VIN VC1 VC2 VS1 VS2 DT
Voltage multiplier circuit
6
RAM 128 x 48 bit display memory
MPX
6
Common counter Y address counter
6
X decoder
5 2
Memory input /output buffer 8
8
8-, 6-bit conversion circuit VDD1 to VDD4 VSS1 to VSS3 X address counter
5
X address register Y address register Control register Address register
8
8
6
DF LCDCK FLM M/S RESET CO OSC1 OSC2 OSC3 TEST1 TEST2 SI Timing generator
7 7
MPX
Clock frequency divider circuit
BUSY MPX MPX
8-bit Serial register
Decoder
SO
P/S
I/O control
SHT CS WR RD RS
Input/output buffer DB7 to DB0
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Semiconductor
MSM6794
ABSOLUTE MAXIMUM RATINGS
Parameter Supply voltage Bias voltage Voltage multiplication reference voltage Input voltage Power dissipation Storage temperature Symbol VDD VBI VIN VI PD TSTG Condition Ta=25C, VDD1-4-VSS1-3 Ta=25C,V1-V6 VIN-VSS1-3 *2 VIN-VSS1-3 *3 Ta=25C -- -- -0.3 to +14 -0.3 to +7 -0.3 to +4.6 -0.3 to VDD+0.3 *1 -55 to +150 V V V mW C V1, V6 VIN, VSS1-3 All Inputs -- -- Rating -0.3 to +7 Unit V Applicable Pins VDD1-4, VSS1-3
Ta : ambient temperature *1 Power dissipation depends on the heat radiation in a device attach condition. Set junction temperature to 150C or lower. *2 Ta = 25C; when doubler is used. *3 Ta = 25C; when tripler is used.
RECOMMENDED OPERATING CONDITIONS
Parameter Supply voltage Bias voltage Voltage multiplicatipon reference voltage Operating frequency Operating temperature Symbol VDD VBI VIN fop Top Condition VDD1-4-VSS1-3 V1-V6 VIN-VSS1-3 See Note 1 on p.6 2 -- 1 Range 2.7 to 5.5 5 to 12 1 to VDD 1 to 4 270 to 500 -25 to +85 Unit V V V kHz C Applicable Pins VDD1-4, VSS1-3 V1, V6 VIN, VSS1-3 OSC1 --
1 For bias potential, V1 has the highest potential and V6 has the lowest potential. Use V6 at the same potential as VSS1 to VSS3. 2 RC oscillation and external input clock frequency (when frequency dividing ratio is 1). For divided frequency operation, clock frequency after dividing must be within this range.
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MSM6794
ELECTRICAL CHARACTERISTICS
DC Characteristics (1)
Parameter "H" input voltage 1 "H" input voltage 2 "H" input voltage 3 "L" input voltage 1 "L" input voltage 2 "L" input voltage 3 "H" input current 1 "H" input current 2 "L" input current I "L" input current 2 OFF leakage current "H" output voltage 1 "H" output voltage 2 "L" output voltage 1 "L" output voltage 2 Multiplied voltage 1 Doubler output Multiplied voltage 2 Tripler output COM output resistance SEG output resistance Supply Current 1 Symbol VIH1 VIH2 VIH3 VIL1 VIL2 VIL3 IIH1 IIH2 IIL1 IIL2 Ioff VOH1 VOH2 VOL1 VOL2 VDB VTR RC RS Condition -- -- -- -- -- -- VI=VDD VI=VDD VI=0V VI=0V VI=VDD or 0V IO=-1.0mA IO=-1.0mA IO=1.0mA IO=1.0mA IO=-500A fosc=350kHz IO=-500A fosc=350kHz IO=50A IO=20A During display IDD1 External clock fosc = 350kHz During display Supply Current 2 IDD2 Internal oscillation fosc = 350kHz Supply Current 3 Oscillation frequency IDDS During standby Rf=18k fOSC Cf=56pF See Note 3 on p.6 292 350 437 kHz OSC1, OSC2, OSC3 -- -- 10 A VDD -- 360 700 A VDD -- -- 450 A VDD Min. 0.8VDD 0.8VDD 0.8VDD 0 0 0 -- -5 -5 -5 -5 0.9VDD 0.9VDD -- -- VINx2 -0.5 VINx3 -1.0 -- -- (VDD=2.7 to 4.5V, VBI=5 to 12V, Ta=-25 to +85C) Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. VDD VDD VDD 0.2VDD 0.2VDD 0.2VDD 5 5 -- 5 5 -- -- 0.1VDD 0.1VDD -- -- 10 20 Unit. V V V V V Unit. A A A A A V V V V V V k k Applicable Pin OSC1 DB0-7, LCDCK, FLM, DF Other input pins OSC1 DB0-7, LCDCK, FLM, DF Other input pins Input pins excluding DB0-7, LCDCK, FLM and DF DB0-7, LCDCK, FLM, DF Input pins excluding DB0-7, LCDCK, FLM and DF DB0-7, LCDCK, FLM, DF SO CO, LCDCK, FLM, DF, SO DB0 to DB7 CO, LCDCK, FLM, DF, SO DB0 to DB7 VS2 VS2 COM1 to COM48 SEG1 to SEG128
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Semiconductor DC Characteristics (2)
MSM6794
(VDD=4.5 to 5.5V, VBI=5 to 12V, Ta=-25 to +85C) Parameter "H" input voltage 1 "H" input voltage 2 "H" input voltage 3 "L" input voltage 1 "L" input voltage 2 "L" input voltage 3 "H" input current 1 "H" input current 2 "L" input current I "L" input current 2 OFF leakage current "H" output voltage 1 "H" output voltage 2 "L" output voltage 1 "L" output voltage 2 Multiplied voltage 1 Doubler output Multiplied voltage 2 Tripler output COM output resistance SEG output resistance Supply Current 1 Symbol VIH1 VIH2 VIH3 VIL1 VIL2 VIL3 IIH1 IIH2 IIL1 IIL2 Ioff VOH1 VOH2 VOL1 VOL2 VDB VTR RC RS Condition -- -- -- -- -- -- VI=VDD VI=VDD VI=0V VI=0V VI=VDD/0V IO=-1.5mA IO=-1.5mA IO=1.5mA IO=1.5mA IO=-500A fosc=350kHz IO=-500A fosc=350kHz IO=50A IO=20A During display External clock fosc = 350kHz During display Internal oscillation fosc=350kHz During standby Rf=22k Cf=56pF See Note 3 on p.6 Min. 0.8VDD 0.8VDD 0.8VDD 0 0 0 -- -5 -5 -5 -5 0.9VDD 0.9VDD -- -- VINx2 -0.5 VINx3 -1.0 -- -- Typ. -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- -- Max. VDD VDD VDD 0.2VDD 0.2VDD 0.2VDD 5 5 -- 5 5 -- -- 0.1VDD 0.1VDD -- -- 10 20 Unit V V V V V V A A A A A V V V V V V k k Applicable Pin OSC1 DB0-7, LCDCK, FLM, DF Other input pins OSC1 DB0-7, LCDCK, FLM, DF Other input pins Input pins excluding DB0-7, LCDCK, FLM and DF DB0-7, LCDCK, FLM, DF Input pins excluding DB0-7, LCDCK, FLM and DF DB0-7, LCDCK, FLM, DF SO CO, LCDCK, FLM, DF, SO DB0 to DB7 CO, LCDCK, FLM, DF, SO DB0 to DB7 VS2 VS2 COM1 to COM48 SEG1 to SEG128
IDD1
--
--
450
A
VDD
Supply Current 2
IDD2
--
360
700
A
VDD
Supply Current 3 Oscillation frequency
IDDS
--
--
10
A
VDD
fOSC
292
350
437
kHz
OSC1, OSC2, OSC3
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MSM6794
Notes: 1. Voltage multiplication reference voltage is = VDD maximum when the multiplied voltage is 12V or less. The voltage multiplication reference voltage is 4V maximum when the multiplied voltage is 12V or more (tripler output). Condition: fosc = 350kHz Voltage multiplier circuit configuration: connect as in the following diagram.
Voltage multiplication reference voltage 4.7F + VIN VC1 VC2 VS1 Doubler output Voltage multiplication reference voltage 4.7F + VC2 VS1 VIN VC1
+ 4.7F
Tripler output 4.7F
+
VS2 4.7F
+
VS2

2. If the multiplied voltage output and bias power supply are directly connected, the voltage multiplier circuit operation may malfunction due to bias power supply noise. A countermeasure for noise is necessary, such as inserting a series resistor to prevent noise from entering multiplied voltage output (VS1, VS2).
+ 4.7F 100 Tripler output 4.7F + VS2 VS1
3. RC oscillation circuit configuration: connect as in the following diagram.
OSC1 Cf Rf OSC2 Cf = 56pF 5 % Rf = 18k 2 % (VDD = 2.7 to 4.5V) Rf = 22k 2 % (VDD = 4.5 to 5.5V)
OSC3
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MSM6794
AC Characteristics
Parallel interface (1)
Parameter RD "H" level width RD "L" level width WR "H" level width WR "L" level width WR-RD "H" level width CS, RS setup time CS, RS hold time Write data setup time Write data hold time Read data output delay time Read data hold time External clock "H" level width External clock "L" level width RESET pulse width External clock rise time, fall time Symbol tWRH tWRL tWWH tWWL tWWRH tAS tAH tDSW tDHW tDDR tDHR tWCH tWCL tWRE tr, tf (VDD=2.7 to 4.5V, VBI=5 to 12V, Ta=-25 to +85C) Condition -- -- -- -- -- -- -- -- -- CL=50pF -- -- -- -- -- Min 200 200 200 200 200 50 10 50 20 -- 20 200 200 2.0 -- Max -- -- -- -- -- -- -- -- -- 170 -- -- -- -- 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s ns
Parallel interface (2)
(VDD=4.5 to 5.5V, VBI=5 to 12V, Ta=-25 to +85C) Parameter RD "H" level width RD "L" level width WR "H" level width WR "L" level width WR-RD "H" level width CS, RS setup time CS, RS hold time Write data setup time Write data hold time Read data output delay time Read data hold time External clock "H" level width External clock "L" level width RESET pulse width External clock rise time, fall time Symbol tWRH tWRL tWWH tWWL tWWRH tAS tAH tDSW tDHW tDDR tDHR tWCH tWCL tWRE tr, tf Condition -- -- -- -- -- -- -- -- -- CL=50pF -- -- -- -- -- Min 150 150 150 150 150 50 10 50 20 -- 20 150 150 2.0 -- Max -- -- -- -- -- -- -- -- -- 130 -- -- -- -- 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s ns
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Semiconductor
MSM6794
Parallel Interface Timing Diagram
CS
VIH VIL
-- --
RS
VIH VIL
-- --
tAS
tWWL
tAH
tAS
tAH
WR
VIH VIL
-- --
tWWH tWWRH tWRH tWRL
RD
VIH VIL
-- --
tDSW VIH DB0-DB7 VIL tWRE
tDHW
tDDR VOH VOL
tDHR
RESET VIL
--
tr
tf
tWCH
OSC1
VIH VIL
-- --
tWCL
VIH = 0.8VDD, VIL = 0.2VDD VOH = 0.9VDD, VOL = 0.1VDD
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Semiconductor Serial interface (1)
MSM6794
(VDD=2.7 to 4.5V, VBI=5 to 12V, Ta=-25 to +85C) Parameter CS, RS setup time CS, RS hold time S1 setup time S1 hold time SHT "H" pulse width SHT "L" pulse width SHT clock cycle time SO ON delay time SO output delay time SO OFF delay time BUSY delay time WR setup time WR "L" pulse width RESET pulse width External clock rise time, fall time Symbol tSAS tSAH tIS tIH tWSHH tWSHL tSYS tON tDS tOFF tBUSY tSHS tWWL tWRE tr, tf Condition -- -- -- -- -- -- -- CL=50pF CL=50pF -- CL=50pF -- -- -- -- Min 60 15 100 15 100 100 400 -- 0 -- -- 100 120 2.0 -- Max -- -- -- -- -- -- -- 200 200 50 200 -- -- -- 100 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s ns
Serial interface (2)
(VDD=4.5 to 5.5V, VBI=5 to 12V, Ta=-25 to +85C) Parameter CS, RS setup time CS, RS hold time S1 setup time S1 hold time SHT "H" pulse width SHT "L" pulse width SHT clock cycle time SO ON delay time SO output delay time SO OFF delay time BUSY delay time WR setup time WR "L" pulse width RESET pulse width External clock rise time, fall time Symbol tSAS tSAH tIS tIH tWSHH tWSHL tSYS tON tDS tOFF tBUSY tSHS tWWL tWRE t r, t f Condition -- -- -- -- -- -- -- CL=50pF CL=50pF -- CL=50pF -- -- -- -- Min 50 10 50 10 80 80 200 -- 0 -- -- 50 80 2.0 -- Max -- -- -- -- -- -- -- 100 100 20 100 -- -- -- 20 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns s ns
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Semiconductor
MSM6794
Serial Interface Timing Diagram
CS
VIH VIL VIH VIL VIH VIL
-- --
RS
-- --
tSAH
-- --
SI
tSAS VIH VIL
--
tIS
tIH
SHT
50%
--
tWSHL VIH VIL
--
tWSHH
tSHS
WR
tSYS
--
tON VOH VOL
-- --
tDS
tWWL
tBUSY
tOFF "Z"
SO
"Z"
tWRE
RESET VIL
--
tr
tf
OSC1
VIH VIL
-- --
VIH = 0.8VDD, VIL = 0.2VDD VOH = 0.9VDD, VOL = 0.1VDD
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Semiconductor
MSM6794
Serial Interface Input/Output Timing
Input timing
CS
RS
SHT
SI
D7
D6
D5
D4
D3
D2
D1
D0
WR
Output timing
CS
RS
SHT
SO
BUSY
D7
D6
D5
D4
D3
D2
D1
D0
BUSY
WR
For SO output, 8 bits after input of the WR pulse are valid.
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Semiconductor
MSM6794
FUNCTIONAL DESCRIPTION
Pin Functional Description *CS (Chip Select) Chip select input pin. "L" is for Select, "H" is for Unselect. Internal registers can be accessed only when this pin is at "L". When this pin is "H", the SO pin becomes high impedance. *WR (Write Enable) This is a write signal input pin when a parallel interface is used. Data is written to a register at the rising edge of a signal pulse. This becomes a latch signal input pin when a serial interface is used. This pin is normally "H". *RD (Read Enable) This is a read signal input pin when a parallel interface is used. Data can be read while the pulse is "L". This pin is normally "H". Set this pin to "H" or "L" when a serial interface is used. *RS (Register Select) Input pin to select register. Setting this pin to "L" selects the address register. Setting to "H" selects a register set by the address register. If this pin is changed from "H" to "L" while a serial interface is used, the SERW bit (D4 bit) of the address register is automatically reset to "0". *DB0 to DB7 (Data Buses 0 to 7) Data input/output pins for parallel interface. These pins are normally in high impedance status. When RD = "L", each register data is output. Leave this pin open when a serial interface is used. *SI (Serial Data Input) Data input pin for serial interface. Each register data and display data are read at the rising edge of SHT, and written to the register at the falling edge of WR. 8-bit data just before the rise of WR is valid data. Set this pin to "H" or "L" when a parallel interface is used. *SO (Serial Data Output) Data output pin for serial interface. Each register data is output synchronizing with the rise of SHT. For busy/non-busy data, busy ("H") is output after the rise of WR, and automatically becomes non-busy ("L") after a specified time. This pin is always in high impedance status when a parallel interface is used. *SHT (Shift Clock) Clock input pin for serial interface data input/output. Data is input synchronizing with the rise of the clock, and data is output synchronizing with the fall of the clock. This pin is normally in "H". Set this pin to "H" or "L" when a parallel interface is used. *P/S (Parallel/Serial Select) Input pin for selecting parallel interface or serial interface. Setting this pin to "L" selects parallel interface. Setting to "H" selects serial interface. Do not change the setting value after power is turned on. 12/34
Semiconductor
MSM6794
*LCDCK (LCD Clock) Input/output pin for display data latch clock. This pin is an output pin if master is specified and is an input pin if slave is specified. To use two or more MSM6794 devices, connect LCDCK of the master with LCDCK of the slave. *FLM (First Line Marker) Input/output pin for the first line marker. This pin is an output pin if master is specified, and is an input pin if slave is specified. To use two or more MSM6794 devices, connect FLM of the master with FLM of the slave. *DF (Display Frequency) Input/output pin for LCD alternating frame signals. This pin is an output pin if master is specified, and an input pin if slave is specified. To use two or more MSM6794 devices, connect DF of the master with DF of the slave. *OSC1 (Oscillation 1) Input pin for RC oscillation. Connecting the specified capacitor and resistor to this pin and the OSC2 and OSC3 pins creates an RC oscillation circuit. To generate an original oscillation clock externally, input the original oscillation clock to this pin. *OSC2, OSC3 (Oscillation 2, Oscillation 3) Output pins for RC oscillation. Connecting the specified capacitor and resistor to these pins and the OSC1 pin creates an RC oscillation circuit. To generate an original oscillation clock externally, leave these pins open.
OSC1 OSC2 OSC3
OSC1 OSC2 Open OSC3 Open
External clock
For RC oscillation circuit
For external clock input
Oscillation circuit diagram
M/S (Master/Slave) Input pin for switching between master and slave. Setting this pin to "L" sets this IC to the IC at the master side. Setting this pin to "H" sets this IC to the IC at the slave side. Do not change the setting value after power is turned on. CO (Clock Output) Output pin for original oscillation clock. The clock in the same phase as OSC1 is output. To use two or more MSM6794 devices, connect CO of the master with OSC1 of the slave.
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Semiconductor
MSM6794
RESET (Reset) Pin for reset signal input. Setting this pin to "L" sets initial status. For the status of each register and display after reset input, see "Status of Pins and Registers after Reset Input". TEST1, TEST2 (Test Signal 1, Test Signal 2) Test signal input pins. These pins are used by Oki to test. Set these pins to "L" permanently. SEG1 to SEG128 (Segment 1 to Segment 128) Segment signal output pins for driving LCD. Leave unused segment pins open. COM1 to COM48 (Common 1 to Common 48) Common signal output pins for driving LCD. Use COM1 to COM33 and leave COM34 to COM48 open for 1/33 duty. Use COM1 to COM41 and leave COM42 to COM48 open for 1/ 41 duty. Use COM1 to COM44 and leave COM45 to COM48 open for 1/44 duty. VDD1 to VDD4 Pins to connect the logic power supply. Connect these pins to positive pins of the power supply. VSS1 to VSS3 Pins to connect GND power supply. V1,V3, V4, V6 LCD power supply pins for the segment driver. Connect V6 to GND. V1, V2, V5, V6 LCD power supply pins for the common driver. Connect V6 to GND. DT (Doubler/Tripler Select) Input pin to select voltage multiplier circuit. Setting this pin to "L" selects tripler, and setting this pin to "H" selects doubler. Do not change the selection after power is turned on. VS1 Doubler voltage output pin. Voltage twice as high as voltage that is input from VIN is output from this pin. Connect a 4.7mF capacitor between this pin and the VSS1 to VSS3 pins to stabilize power supply. When doubler is used, connect this pin with VS2. Set this pin to GND level if the voltage multiplier circuit is not used. VS2 Multiplied voltage output pin. Multiplied voltage set by the DT pin is output from this pin. If tripler is used, connect a 4.7mF capacitor between this pin and the VSS1 to VSS3 pins to stabilize power supply. If doubler is used, connect this pin with VS1. Set this pin to GND level if the voltage multiplier circuit is not used. VC1, VC2 Capacitor connection pins for voltage multiplication. Connect a 4.7mF capacitor between the VC1 and VC2 pins. When an electrolytic capacitor is used, connect the VC2 pin to the positive side. Set these pins to GND level if the voltage multiplier circuit is not used. VIN Voltage multiplication reference voltage input pin. Voltage two or three times higher than voltage that is input to this pin is output from the VS2 pin. Set this pin to GND level if the voltage multiplier circuit is not used. 14/34
Semiconductor Registers
Register number 1 -- -- 0 0 1 1 0 -- -- 0 1 0 1 Register symbol -- AR DRAM YAD XAD FCR Register name Invalid 7 -- 6 -- D6 -- -- -- 5 -- D5 -- YAD FFS Data bit 4 -- D4 3 -- D3 2 -- D2 XAD
MSM6794
CS RS 1 0 0 0 0 0 -- 0 1 1 1 1
1 -- D1
0 -- D0
Address register BUSY STBY DISP SERW HZ Display data register D7 X address register Y address register Control register -- --
-- Register number
INC WLS
DUTY
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Semiconductor
MSM6794
Register Description
Address register (AR)
D7 BUSY D6 STBY D5 DISP D4 SERW D3 HZ D2 -- D1 D0
Register number
(1) D7 BUSY (Busy flag) 1: busy 0: ready This bit indicates that this IC is in internal processing. Reading/Writing display memory sets this bit to "1". This bit becomes busy for a period of a maximum of 8 clocks by reading/writing display memory. Registers other than this register cannot be read or written while this bit is "1". Setting the RESET pin to "L" also sets this bit to "1". This bit becomes "1" while the RESET pin is "L", and becomes "0" when the RESET pin becomes "H". In the case of a serial interface, the SO pin becomes high impedance if the RESET pin becomes "L". Therefore this bit cannot be read during a reset period. This bit is read only. Writing to this bit is invalid. (2) D6 STBY (Standby) 1: standby 0: normal This bit sets this IC to standby mode. This IC enters standby mode by writing "1" to this bit, and returns from standby mode to normal mode by writing "0" to this bit. This bit is set to normal status by setting the RESET pin to "L". Setting this bit to standby mode in a busy state may cause a malfunction. For details of standby mode, see "Pin status during Standby Operation and Register Status after Cancellation". (3) D5 DISP (Display on/off) 1: display on 0: display off This bit sets ON/OFF of the liquid crystal display connected to this IC. Writing "1" to this bit turns the liquid crystal display ON, and writing "0" turns it OFF. This bit is used to prevent a random display until the initialization of the display memory after power-on. This bit is set to display off status by setting the RESET pin to "L". (4) D4 SERW (Serial Data Read/Write) 1: writing registers other than address register is invalid 0: writing all registers is valid This bit limits writing to registers when a serial interface is used. Writing "1" to this bit disables writing to registers other than the address register, and writing "0" enables writing to all registers. This bit is a command to make registers read-only when a serial interface is used. When serial data is read from the SO pin, this pin disables writing to registers other than the address register, even if data is input to the SI pin. This bit is valid only when a serial interface is used. When a parallel interface is used, writing to this bit is invalid, and "0" is always read from this bit. This bit is set to write enable of all registers by setting the RESET pin to "L". This bit is automatically reset to "0" each time the RS pin is set from "H" to "L". 16/34
Semiconductor
MSM6794
(5) D3 HZ (high impedance) (SO pin output control) 1: high impedance 0: output enable This bit sets the status of the SO pin when a serial interface is used. Writing "1" to this bit sets the SO pin to a high impedance state, and writing "0" to this bit sets the SO pin to an output enable state. This bit is valid only when a serial interface is used. When a parallel interface is used, writing to this bit is invalid, and "0" is always read from this bit. This bit is set to a high impedance state by setting the RESET pin to "L". (6) D2 (Invalid Bit) Writing to this bit is invalid, and "0" is always read from this bit. (7) D1, D0 (Register Number) These bits select a register other than the address register. The relationship between each bit and each register is shown in the table below.
Code 0 1 2 3 D1 0 0 1 1 D0 0 1 0 1 Register Name Display data register X address register Y address register Control register
These bits are reset to (D1, D0) = (0, 0) (display data register select status) by setting the RESET pin to "L".
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Semiconductor Display data register (DRAM)
D7 -- D6 D5 D4 8-bit DATA 6-bit DATA D3 D2 D1
MSM6794
D0
This register is used to write or read display data to and from the liquid crystal display RAM. The contents of this register are written or read to and from the address set by the X address register and Y address register. The bit length of display data is selected by the WLS bit (D6 bit) of the control register. If 6-bit data is selected, writing to the D7 and D6 bit is invalid, and "0" is always read from these bits. D7 (D5 for 6-bit DATA) is MSB, and D0 is LSB. The content of this register does not change, even if the RESET pin is set to "L". X address register (XAR)
D7 D6 -- D5 D4 D3 D2 XAD D1 D0
This register is used to set the X address of the liquid crystal display RAM. If 8-bit data is selected by the WLS bit (D6 bit) of the control register, the addresses are 0 to15 (00H to 0FH). If 6-bit data is selected, the addresses are 0 to 21 (00H to 15H). If other addresses are set, operation is unpredictable. Writing to the D7 to D5 bits is invalid, and "0" is always read from these bits. This register is reset to "0" by setting the RESET pin to "L". Y address register (YAR)
D7 -- D6 D5 D4 D3 YAD D2 D1 D0
This register is used to set the Y address of the liquid crystal display RAM. If 1/48 duty is selected by DUTY bits (D1, D0 bits) of the control register, the address set value is 0 to 47 (00H to 2FH). If 1/44 duty is selected, the address set value is 0 to 43 (00H to 2BH). If 1/41 duty is selected, the address set value is 0 to 40 (00H to 28H), and if 1/33 duty is selected, the address set value is 0 to 32 (00H to 20H). If other values are set, operation is unpredictable. Writing to D7 and D6 bits is invalid, and "0" is always read from these bits. This register is reset to "0" by setting the RESET pin to "L".
18/34
Semiconductor Control register (FCR)
D7 INC D6 WLS D5 -- D4 D3 FFS D2 D1
MSM6794
D0 DUTY
(1) D7 INC (Address Increment Direction) 1: X direction 0: Y direction This bit sets the address increment direction of the display RAM. The address of the display RAM is automatically incremented by 1 by writing data to the display data register. Writing "1" to this bit sets the X address increment, and writing "0" to this bit sets the Y address increment. For details of address increment, see "X, Y Address Counter Auto Increment". The value of this register does not change, even if the RESET pin is set to "L". (2) D6 WLS (Word Length Select) 1: 6 bits 0: 8 bits This bit selects the read/write word length to the display RAM. Writing "1" to this bit sets read/write data to the display RAM in 6 bit units, and writing "0" to this bit sets read/write data to the display RAM in 8 bit units. Select the word length according to the character font to be used. The value of this register does not change, even if the RESET pin is set to "L". (3) D5 (Invalid Bit) Writing to this bit is invalid. "0" is always read from this bit. (4) D4 to D2 FFS (Frame Frequency Select) This bit selects the internal clock frequency dividing ratio to the original oscillation frequency. Correspondence between each bit and each frequency dividing ratio is shown in the table below.
Code 0 1 2 3 4 5 6 7 D4 0 0 0 0 1 1 1 1 D3 0 0 1 1 0 0 1 1 D2 0 1 0 1 0 1 0 1 Frequency Dividing Ratio 1 1/2 1/3 1/4 1/6 1/8 TEST TEST
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MSM6794
When the original oscillation frequency is 350kHz and the frequency dividing ratio is 1, the frame frequency is about 80Hz. When the display data register is written/read, the busy time is a maximum of 8 original oscillation clocks. If the original oscillation frequency is increased to shorten the busy time, the frame frequency increases in proportion to the original oscillation frequency. In this case the frequency dividing ratio must be changed so that the frame frequency falls in the range of 60 to 100Hz. For details on the relation between original oscillation frequency and frame frequency, see "Original Oscillation Frequency and Frame Frequency". (D4, D3, D2) = (1, 1, 0) and (1, 1, 1) are combinations which Oki uses for testing. If these combinations are used by the user, the operation of this IC is unpredictable. The value of this register does not change even if the RESET pin is set to "L". Once frame frequency is set after power is turned on, the value cannot be changed. To change the frame frequency, set it again according to the power-on flowchart. See "Power-on Flowchart". (5) D1, D0 DUTY (Display Duty Select) These bits select the display duty. Correspondence between each bit and display duty is shown in the table below.
Code 0 1 2 3 D1 0 0 1 1 D0 0 1 0 1 DUTY 1/48 1/44 1/41 1/33
The value of this register does not change, even if the RESET pin is set to "L". Once display duty is set after power is turned on, the value cannot be changed. To change display duty, set it again according to the power-on flowchart. See "Power-on Flowchart".
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Semiconductor
MSM6794
Status of Pins and Registers After Reset Input
The following tables show pin and register status after reset input.
Pin OSC2, 3 CO SO DF FLM LCDCK Status Clock output or oscillation status Clock output High impedance "H" (master), high impedance (slave) "L" (master), high impedance (slave) "L" (master), high impedance (slave)
Register Address register Display data register X address register Y address register Control register
Status HZ = "1", other bits are reset to "0". Display data is held Reset to "0" Reset to "0". No change from status before inputting reset
Pin Status during Standby Operation and Register Status after Cancellation
The following tables show pin status during standby operation and register status after cancellation.
Pin OSC2 OSC3 CO SO DF FLM LCDCK Status "L" "H" "L" High impedance "H" (master), high impedance (slave) "L" (master), high impedance (slave) "L" (master), high impedance (slave)
Register Address register Display data register X address register Y address register Control register
Status STBY = "0", other bits maintain data before standby Maintains data before standby Reset to "0" Reset to "0" Maintains data before standby
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Semiconductor
MSM6794
X , Y Address Counter Auto Increment
RAM for the liquid crystal display of the MSM6794 has an X address counter and Y address counter, and both have an auto increment function. Writing/reading display data increments either X or Y address counter. The INC bit (D7 bit) of the control register selects X or Y address to be incremented. (When X address is selected:) Address count cycle of X address counter changes depending on word length: 8- or 6-bit. If the word length is 8-bit, X address is counted in a 0 to 15 range. If the word length is 6-bit, X address is counted in a 0 to 21 range. When the maximum value of an X address count value (15 for an 8-bit word length, and 21 for a 6-bit word length) returns to "0", the Y address count value is also automatically incremented. (When Y address is selected:) The address count of Y address counter changes depending on the display duty: 1/33, 1/41, 1/44 or 1/48. If the display duty is 1/33, Y address is counted in a 0 to 32 range. If the display duty is 1/41, Y address is counted in a 0 to 40 range. If the display duty is 1/44, Y address is counted in a 0 to 43 range. If the display duty is 1/48, Y address is counted in a 0 to 47 range. When the maximum value of a Y address count value (32 for display duty 1/33, 40 for display duty 1/41, 43 for display duty 1/44, and 47 for display duty 1/48) returns to "0", the X address count value is also automatically incremented. (Note) If an address other than the count cycle is set at X or Y address counter, count operation becomes abnormal. 1. Example of X address increment (8-bit word length, 1/33 duty)
X address 0 0 1 2 13 14 15 0 1 1 2
Y address
2. Example of Y address increment (8-bit word length, 1/33 duty)
X address 0 1 15 0
Y address
32
30 31 0 32
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MSM6794
Display Screen and Memory Address
The MSM6794 includes a bit map type display RAM (48 128 bit). Display data is written to display memory with MSB as (Xn, Yn) address, and LSB as (Xn+7, Yn) address, as shown in Figure 1. Writing "1" to display memory turns the light on, and writing "0" turns the light off. The address assignment of memory address changes depending on the selection of word length: 8 bits or 6 bits. The memory address is 0 to 15 for 8 bits per word, and 0 to 21 for 6 bits per word. When X address is 21 with 6 bits per word, the display memory is 2 bits. 2 bits (D5, D4) from MSB of data display are written to memory, with the remaining 4 bits (D3 to D0) becoming invalid.
SEG128 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8
COM1 COM2 128 x 48 dot LCD panel
COM48 X direction
X127
Address assignment for 6 bits/word 15 0 1
(8 bits) (6 bits) (2 bits)
Y0 Y1
Y direction
MSB
Y47
Figure 1. Correspondence between display screen and memory
Address assignment for 8 bits/word 0123 0 1
X0 X1 X2 X3 X4 X5 X6 X7
10101001
LSB
RAM for 128 x 48 bit display
0123
21
47
47
Figure 2. Display memory address 23/34
Semiconductor
MSM6794
Power-on Flowchart (Serial Interface)
Power on
Reset input
5s, external or power-on reset
Set CS = "L"
Chip enable
Set RS = "L", AR
D7 D6 D5 D4 D3 D2 D1 D0 * 1 0 0 0 * 1 1 (Standby setting, FCR select, SO output enable)
Set RS = "H", FCR
Select duty according to specification. Set FFS, WLS, INC.
Set RS = "L", AR
D7 D6 D5 D4 D3 D2 * 0 0 0 0 * (Standby release, DRAM select)
D1 0
D0 0
Set RS = "H". Input display data.
Wait for 8 OSC clocks
Note: This wait is a wait during busy period. To detect busy by SO, wait until the busy output is set from "H" to "L".
NO
Initial screen data input complete?
YES Set RS = "L", AR D7 * D6 0 D5 1 D4 0 D3 0 D2 * D1 D0 X X Arbitrary
(DISP ON) Normal operation
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MSM6794
STBY Setting and Cancellation Flowchart
Normal operation
Check for BUSY data
Confirm non-busy.
NO
Non-busy?
YES Set RS = "L", AR D7 * D6 1 D5 0 D4 0 D3 0 D2 * D1 X D0 X
Arbitrary (Standby setting)
Standby status
Set RS = "L", AR
D7 *
D6 0
D5 0
D4 0
D3 0
D2 *
D1 X
D0 X
Arbitrary (Standby release) Wait until oscillation stabilizes
Wait until voltage multiplier circuit stabilizes
Set RS = "L", AR
D7 *
D6 0
D5 1
D4 0
D3 0
D2 *
D1 X
D0 X
Arbitrary (DISP ON) Normal operation
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Semiconductor
MSM6794
Original Oscillation Frequency and Frame Frequency
Frame frequency calculation For 1/33, 1/44, 1/48 DUTY: (Original oscillation clock cycle) (1/frequency dividing ratio) 4224 = frame cycle ................ Formula 1 For 1/41 DUTY: (Original oscillation clock cycle) (1/frequency dividing ratio) 4264 = frame cycle ................ Formula 2 Frame frequency can be calculated by the above formulas. Example 1) For original oscillation 350 [kHz], frequency dividing ratio 1/1, and 1/33 duty specification: By formula 1, frame cycle Tf = 1 /(350103) 1 4224 = 12.1 [ms] Therefore, frame frequency = 82.9 [Hz] Example 2) For original oscillation 1 [MHz], frequency dividing ratio 1/3, 1/41 duty specification: By formula 2, frame cycle Tf = 1 /(1106) 3 4264 = 12.8 [ms] Therefore, frame frequency = 78.2 [Hz] Original oscillation frequency and BUSY time When RAM data is written or read, data processing time (BUSY time) occurs. BUSY time is a maximum of [(original oscillation clock cycle) 8]. As the original oscillation frequency increases, BUSY time becomes shorter (not influenced by the frequency dividing ratio). By increasing the original oscillation frequency, BUSY time can be made shorter in proportion. In this case frame frequency also increases. So, set the frequency dividing ratio so that frame frequency reaches a frequency close to the frame frequency to be used.
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Semiconductor
MSM6794
LCD Drive Power Supply
COM output example (COM1) V1 V2 V3 V4 V5 V6
1 line
1 frame SEG output example V1 V2 V3 V4 V5 V6 Light ON/light OFF
Light ON Light OFF
COM DRV input power supply : V1, V2, V5, V6 SEG DRV input power supply : V1, V3, V4, V6
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Semiconductor
MSM6794
APPLICATION CIRCUITS
Application example (1) (1/48 duty, serial interface, voltage multiplier circuit (tripler) used, single chip)
LCD panel
: 8 characters x 2 lines (16 x 16 dots) Kanji Alphabet : 21 characters x 1 line (5 x 7 dots) Cursor : 4 lines
Temperature compensation and stabilization circuit
COM 48 lines VIN 4.7F VC1 VC2 VS1 VS2 C1 to C48
SEG 128 lines S1 to S128 VDD OSC1 OSC2 OSC3 CO TEST1 TEST2 56pF OPEN 22k
VCC
4.7F 4.7F Bias generation circuit
V1 V2 V3 V4 V5 V6 VSS M/S P/S DB7 to DB0 DT
MSM6794
100k RESET 1F
LCDCK
SHT
OPEN
OPEN
PORT
FLM
WR
RD
CS
RS
SO
SI
DF
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Semiconductor Application example (2) (1/33 duty, parallel interface, voltage multiplier circuit unused, single chip)
MSM6794
LCD panel
Kanji : 8 characters x 2 lines (16 x 16 dots) Symbol : 128 x 1 line
Temperature compensation and stabilization circuit
VIN VC1 VC2 VS1 VS2
OPEN 15 C1 to C33 C34 to C48
COM 33 lines
SEG 128 lines S1 to S128 VDD OSC1 OSC2 OSC3 CO TEST1 TEST2 56pF OPEN 22k
VCC
Bias generation circuit
V1 V2 V3 V4 V5 V6 VSS M/S P/S DB7 to DB0 DT
MSM6794
100k RESET 1F
LCDCK
SHT
8
OPEN
OPEN
PORT
FLM
WR
RD
CS
RS
SO
SI
DF
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LCD panel (SEG) 256 (COM) 48 OPEN SEG 128 lines S1 to S128 VDD OCS1 OCS2 OCS3 CO TEST1 TEST2 OPEN VDD OCS1 OCS2 56pF OCS3 22kW CO TEST1 TEST2 VS2 C1 to C48
Kanji : 16 characters 2 lines (16 16 dots) Alphabet : 42 characters 1 line (5 7 dots) Cursor : 4 lines
Semiconductor
COM 48 lines SEG 128 lines S1 to S128
VCC
C1 to C48
Temperature compensation and stabilization circuit
4.7F
4.7F
VIN VC1 VC2 VS1
VIN VC1 VC2 VS1
4.7F
VS2
Bias generation circuit
V1 V2 V3 V4 V5
MSM6794 (MASTER)
RESET
V1 V2 V3 V4 V5
MSM6794 (SLAVE)
100kW RESET 1F
Application example (3) (1/48 duty, serial interface, 2 chips used, cascade connection)
DB7 to DB0 WR RD RS SI
CS
SO
SHT DF
LCDCK FLM
DB7 to DB0 CS
WR
RD
RS
SI
SO
SHT
LCDCK OPEN
DF
V6 VSS DT M/S P/S V6 VSS DT M/S P/S
OPEN
PORT
FLM
MSM6794
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Semiconductor
MSM6794
Interface Connection Example
For serial interface (only control signals are described)
(Master)
(Slave)
SHT
SHT
WR
WR
CS
RS
SO
CS
SO
SO (M) SO (S) SI PORT SHT CS (M) CS (S) WR RS
Master and slave control operation Connect as in the above diagram. The master side and slave side can be selected by setting CS to "L" respectively. Rise or fall the CS signal level after confirming NON-BUSY. Example of continuous writing of RAM data (all master addresses AE all slave addresses):
RAM write start
CS(M) = "L", CS(S) = "L", write start address setting
CS(M) = "L", CS(S) = "H", master side data write
Master END address data write completed
CS(M) = "H", CS(S) = "L", slave side data write
Slave END address data write completed
RAM write completed
SI
RS
SI
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Semiconductor
MSM6794
PAD CONFIGURATION (TOP VIEW)
Pad Layout
166 165 109 108
224 1
48 49
Pad Coordinates
Pad No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 Pad Name X(m) Y(m) V6 V4 V3 V1 VDD1 VDD2 OSC1 OSC2 OSC3 CO VSS1 VSS2 RESET SO SI SHT PS CS WR RD RS DB7 DB6 DB5 DB4 -3377 -3784 -3257 -3784 -3137 -3784 -3017 -3784 -2897 -3784 -2777 -3784 -2647 -3784 -2453 -3784 -2284 -3784 -2215 -3784 -1962 -3784 -1842 -3784 -1712 -3784 -1519 -3784 -1317 -3784 -1186 -3784 -1066 -3784 -946 -3784 -826 -3784 -706 -3784 -586 -3784 -404 -3784 -235 -3784 -67 -3784 -103 -3784 Pad No. 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 Pad Name X(m) Y(m) DB3 DB2 DB1 DB0 TEST1 TEST2 M/S FLM DF LCDCK DT VDD3 VSS3 VS1 VS2 VC2 VIN VC1 VDD4 V1 V2 V5 V6 C48 C47 271 440 609 778 697 -3784 -3784 -3784 -3784 -3784 Pad No. 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 Pad Name X(m) Y(m) C46 C45 C44 C43 C42 C41 C40 C39 C38 C37 C36 C35 C34 C33 C32 C31 C30 C29 C28 C27 C26 C25 C24 C23 C22 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 -3306 -3186 -3066 -2946 -2826 -2706 -2586 -2466 -2346 -2226 -2106 -1986 -1866 -1746 -1626 -1506 -1386 -1266 -1146 -1026 -906 -786 -666 -546 -426
1098 -3784 1218 -3784 1399 -3784 1568 -3784 1737 -3784 1937 -3784 2057 -3784 2177 -3784 2297 -3784 2417 -3784 2537 -3784 2657 -3784 2777 -3784 2897 -3784 3017 -3784 3137 -3784 3257 -3784 3377 -3784 4058 -3546 4058 -3426
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MSM6794
Pad No. 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
Pad Name X(m) Y(m) C21 C20 C19 C18 C17 C16 C15 C14 C13 C12 C11 C10 C9 C8 C7 C6 C5 C4 C3 C2 C1 S128 S127 S126 S125 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 4058 -306 -186 -66 54 174 294 414 534 654 774 894 1014 1134 1254 1374 1494 1614 1734 1854 1974 2094 2214 2334 2454 2574
Pad No. 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125
Pad Name X(m) Y(m) S124 S123 S122 S121 S120 S119 S118 S117 S116 S115 S114 S113 S112 S111 S110 S109 S108 S107 S106 S105 S104 S103 S102 S101 S100 4058 4058 4058 4058 4058 4058 4058 4058 3332 3212 3092 2972 2852 2732 2612 2492 2372 2252 2132 2012 1892 1772 1652 1532 1412 2694 2814 2934 3054 3174 3294 3414 3534 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824
Pad No. 126 127 128 129 130 131 132 133 134 135 136 137 138 139 140 141 142 143 144 145 146 147 148 149 150
Pad Name X(m) Y(m) S99 S98 S97 S96 S95 S94 S93 S92 S91 S99 S89 S88 S87 S86 S85 S84 S83 S82 S81 S80 S79 S78 S77 S76 S75 1292 1172 1052 932 812 692 572 452 332 212 93 -28 -147 -267 -387 -507 -627 -747 -867 -987 -1107 -1277 -1347 -1467 -1587 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824 3824
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Semiconductor
MSM6794
Pad No. 151 152 153 154 155 156 157 158 159 160 161 162 163 164 165 166 167 168 169 170 171 172 173 174 175
Pad Name X(m) Y(m) S74 S73 S72 S71 S70 S69 S68 S67 S66 S65 S64 S63 S62 S61 S60 S59 S58 S57 S56 S55 S54 S53 S52 S51 S50 -1707 3824 -1827 3824 -1947 3824 -2067 3824 -2187 3824 -2307 3824 -2427 3824 -2547 3824 -2667 3824 -2787 3824 -2907 3824 -3207 3824 -3147 3824 -3267 3824 -3387 3824 -4058 3534 -4058 3414 -4058 3294 -4058 3174 -4058 3054 -4058 2934 -4058 2814 -4058 2694 -4058 2574 -4058 2454
Pad No. 176 177 178 179 180 181 182 183 184 185 186 187 188 189 190 191 192 193 194 195 196 197 198 199 200
Pad Name X(m) Y(m) S49 S48 S47 S46 S45 S44 S43 S42 S41 S40 S39 S38 S37 S36 S35 S34 S33 S32 S31 S30 S29 S28 S27 S26 S25 -4058 2334 -4058 2214 -4058 2094 -4058 1974 -4058 1854 -4058 1734 -4058 1614 -4058 1494 -4058 1374 -4058 1254 -4058 1134 -4058 1014 -4058 -4058 -4058 -4058 -4058 -4058 -4058 -4058 -4058 894 774 654 534 414 294 174 54 -66
Pad No. 201 202 203 204 205 206 207 208 209 210 211 212 213 214 215 216 217 218 219 220 221 222 223 224
Pad Name X(m) Y(m) S24 S23 S22 S21 S20 S19 S18 S17 S16 S15 S14 S13 S12 S11 S10 S9 S8 S7 S6 S5 S4 S3 S2 S1 -4058 -4058 -4058 -666 -786 -906
-4058 -1026 -4058 -1146 -4058 -1266 -4058 -1386 -4058 -1506 -4058 -1626 -4058 -1746 -4058 -1866 -4058 -1986 -4058 -2106 -4058 -2226 -4058 -2346 -4058 -2466 -4058 -2586 -4058 -2706 -4058 -2826 -4058 -2946 -4058 -3066 -4058 -3186 -4058 -3306 -4058 -3426
-4058 -186 -4058 -306 -4058 -426 -4058 -546
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