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PLL650-06
Network LAN Clock
FEATURES
* * * * * * * *
*
PIN CONFIGURATION
XIN XOUT GND 50MHz/FS* 1 2 3 4 8 7 6 5 VDD GND 75MHz+/66MHz+ VDD
Full CMOS output swing with 40-mA output drive capability. 25-mA output drive at TTL level. Advanced, low power, sub-micron CMOS processes. 25MHz fundamental crystal or clock input. One output fixed at 50MHz One selectable frequency output of 66.6 or 75MHz (with Double Drive Strength output). Zero PPM synthesis error in all clocks. Ideal for Network switches. 3.3V operation. Available in 8-Pin 150mil SOIC.
PLL650-06
*: bi-directional pin
+ : double strength output
DESCRIPTION
The PLL 650-06 is a low cost, low jitter, and high performance clock synthesizer. Using PhaseLink's proprietary analog Phase Locked Loop techniques, this device can produce one 50MHz output clock and one selectable 75MHz or 66.6MHz output clock from a single low cost 25.0MHz crystal. This makes the PLL650-06 ideal for networking applications.
FREQUENCY TABLE
FS 0 1 Pin 6 75MHz 66.6MHz
BLOCK DIAGRAM
50MHz XIN XOUT
XTAL OSC
Control Logic
FS 1 75MHz/66MHz
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 1
PLL650-06
Network LAN Clock
PIN DESCRIPTIONS
Name
XIN XOUT 50MHz/FS 75MHz / 66MHz VDD GND
Number
1 2 4 6 5, 8 3, 7
Type
I I B O P P
Description
25MHz fundamental crystal input (20pF CL parallel resonant). Crystal connection pin. 50MHz outputs. This pin latches the FS input value at power-up. It has a 60k internal pull up resistor. 75MHz or 66.6MHz outputs with double drive strength. The output frequency is determined by the value of FS (see pin 4). 3.3V power supply. Ground.
FUNCTIONAL DESCRIPTION Selectable spread spectrum and output frequencies
The PLL650-06 provides selectable output frequencies. Selection is made by connecting the selector pin to a logical "zero" or "one", or by leaving it not connected (internal pull-up) according to the frequency selection table shown on page 1. Pin 4 (FS) is a bi-directional pin used to select the output frequency of pin 6 (75MHz or 66.6MHz) according to the Frequency Selection Table on page 1. The description of how to connect this bi-directional pin follows in the next paragraph.
Connecting a bi-directional pin
A bi-directional pin serves as input upon power-up, and as output as soon as the inputs have been latched. The value of the input is latched-in upon power-up. Depending on the pin (see pin description), the input can be tri-level or a standard two-level. Unlike unidirectional pins, bi-directional pins cannot be connected directly to GND or VDD in order to set the input to "0" or "1", since the pin also needs to serve as output. In the case of two level input pins, an internal pull-up resistor is present. This allows a default value to be set when no external pull down resistor is connected between the pin and GND (by definition, a tri-level input has a the default value of "M" (mid) if it is not connected). In order to connect a bi-directional pin to a non-default value, the input must be connected to GND or VDD through an external pull-down/pull-up resistor. Note: when the output load presents a low impedance in comparison to the internal pull-up resistor, the internal pull-up resistor may not be sufficient to pull the input up to a logical "one", and an external pull-up resistor may be required. For bi-directional inputs, the external loading resistor between the pin and GND has to be sufficiently small (compared to the internal pull-up resistor) so that the pin voltage be pulled below 0.8V (logical "zero"). In order to avoid loading effects when the pin serves as output, the value of the external pull-down resistor should however be kept as large as possible. In general, it is recommended to use an external resistor of around one sixth to one quarter of the internal pull-up resistor (see Application Diagram). Note: when the output is used to drive a load presenting an small resistance between the output pin and VDD, this resistance is in essence connected in parallel to the internal pull-up resistor. In such a case, the external pull-down resistor may have to be dimensioned smaller to guarantee that the pin voltage will be low enough achieve the desired logical "zero". This is particularly true when driving 74FXX TTL components.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 2
PLL650-06
Network LAN Clock
APPLICATION DIAGRAM
Internal to chip VDD
External Circuitry
Rup Power Up Reset
R RB
Output
EN
Bi-directional pin
Clock Load
Latched Input
Latch
RUP/4
Jumper options
NOTE: Rup=60k . R starts from 1 to 0 while RB starts from 0 to 1.
Electrical Specifications
1. Absolute Maximum Ratings PARAMETERS
Supply Voltage Input Voltage, dc Output Voltage, dc Storage Temperature Ambient Operating Temperature* Junction Temperature Lead Temperature (soldering, 10s) ESD Protection, Human Body Model
SYMBOL
VDD VI VO TS TA TJ
MIN.
-0.5 -0.5 -65 -40
MAX.
4.6 VDD+0.5 VDD+0.5 150 85 125 260 2
UNITS
V V V C C C C kV
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. * Note: Operating Temperature is guaranteed by design for all parts (COMMERCIAL and INDUSTRIAL), but tested for COMMERCIAL grade only.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 3
PLL650-06
Network LAN Clock
2. AC Specifications PARAMETERS
Input Frequency Output Rise Time Output Fall Time Duty Cycle Max. Absolute Jitter Max. Jitter, cycle to cycle
CONDITIONS
0.8V to 2.0V with no load 2.0V to 0.8V with no load @ 50% VDD Short term
MIN.
10
TYP.
25
MAX.
27 1.5 1.5 55 80
UNITS
MHz ns ns % ps ps
45
50 150
3. DC Specifications PARAMETERS
Operating Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Input High Voltage Input Low Voltage Output High Voltage Output Low Voltage Output High Voltage At CMOS Level Operating Supply Current Short-circuit Current Nominal output current* Nominal output current* Internal pull-up resistor Internal pull-up resistor
SYMBOL
VDD VIH VIL VIH VIL VIH VIL VOH VOL VOH IDD IS Iout Iout Rup Rup
CONDITIONS
MIN.
2.97
TYP.
VDD /2 VDD /2
MAX.
3.63 VDD /2 - 1 0.5
UNITS
V V V V V V V V V V
For all Tri-level input For all Tri-level input For all normal input For all normal input IOH = -25mA IOL = 25mA IOH = -8mA No Load CMOS output level TTL output level Pins 5,7 Pin 2
VDD -0.5 2 0.8 2.4 0.4 VDD -0.4 35 35 20 50 40 25 60 120
mA mA mA mA k k
*: Output strengths are doubled (i.e. min. CMOS level is 70mA, typ. CMOS level is 80mA) on pin 6 (output for 75MHz or 66.6MHz)
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 4
PLL650-06
Network LAN Clock
PACKAGE INFORMATION
8 PIN ( dimensions in mm )
Narrow SOIC Symbol A A1 B C D E H L e Min. 1.47 0.10 0.33 0.19 4.80 3.80 5.80 0.38 1.27 BSC Max. 1.73 0.25 0.51 0.25 4.95 4.00 6.20 1.27 A 1 e B A C L D E H
ORDERING INFORMATION
For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991
PART NUMBER
The order number for this device is a combination of the following: Device number, Package type and Operating temperature range
PLL650-06 S C
PART NUMBER TEMPERATURE C=COMMERCIAL I=INDUSTRAL PACKAGE TYPE S=SOIC
Order Number PLL650-06SC-R PLL650-06SC
Marking P650-06SC P650-06SC
Package Option SOIC - Tape and Reel SOIC - Tube
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 09/03/04 Page 5

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