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Product Specification
PE3336
Product Description
Peregrine's PE3336 is a high performance integer-N PLL capable of frequency synthesis up to 3000 MHz. The superior phase noise performance of the PE3336 makes it ideal for applications such as LMDS / MMDS / WLL basestations and demanding terrestrial systems. The PE3336 features a 10/11 dual modulus prescaler, counters and a phase comparator as shown in Figure 1. Counter values are programmable through either a serial or parallel interface and can also be directly hard wired. The PE3336 Phase Locked-Loop is optimized for terrestrial applications. It is manufactured on Peregrine's UltraCMOSTM process, a patented variation of silicon-oninsulator (SOI) technology on a sapphire substrate, offering the performance of GaAs with the economy and integration of conventional CMOS. 3000 MHz UltraCMOSTM Integer-N PLL for Low Phase Noise Applications Features
* 3000 MHz operation * /10/11 dual modulus prescaler * Internal phase detector * Serial, parallel or hardwired
programmable
* Pin compatible with PE3236 * Ultra-low phase noise * Available in 44-lead PLCC and
7x7 mm 48-lead QFN package
Figure 1. Block Diagram
Fin Fin
Prescaler 10 / 11
Main Counter 13
fp
D(7:0) 8 Sdata Pre_en M(6:0) A(3:0) R(3:0) fr
Primary 20-bit 20 Latch
Secondary 20-bit Latch
20 20
20 16
Phase Detector
PD_U PD_D
6
6 fc
R Counter
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PE3336
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. (44-lead PLCC) Pin No. (48-lead QFN) Pin Name
S_WR 13 7 D4 M4 Sdata 14 8 D5 M5 Sclk 15 9 D6 M6 FSELS 16 10 D7 Pre_en 17 11 GND FSELP 18 12 A0 Direct Serial E_WR 19 13 Parallel A1 M2_WR 20 14 A2 Smode 21 15 A3 22 23 24 25 26 27 16 17,18 19 20 21 22 Bmode VDD M1_WR A_WR Hop_WR Fin Direct Serial, Parallel Direct ALL ALL Parallel Parallel Serial, Parallel ALL Input Input Input Input (Note 1) Input Input Input Input Direct Parallel Input Input Input Input Input Parallel Direct Serial Parallel Direct ALL Parallel Input Input Input Input Input Input Parallel Direct Serial Parallel Direct Serial Input Input Input Input Input Input
Interface Mode
Serial
Type
Description
Serial load enable input. While S_WR is "low", Sdata can be serially clocked. Primary register data are transferred to the secondary register on S_WR or Hop_WR rising edge. Parallel data bus bit4 M Counter bit4 Binary serial data input. Input data entered MSB first. Parallel data bus bit5. M Counter bit5. Serial clock input. Sdata is clocked serially into the 20-bit primary register (E_WR "low") or the 8-bit enhancement register (E_WR "high") on the rising edge of Sclk. Parallel data bus bit6. M Counter bit6. Selects contents of primary register (FSELS=1) or secondary register (FSELS=0) for programming of internal counters while in Serial Interface Mode. Parallel data bus bit7 (MSB). Prescaler enable, active "low". When "high", Fin bypasses the prescaler. Ground. Selects contents of primary register (FSELP=1) or secondary register (FSELP=0) for programming of internal counters while in Parallel Interface Mode. A Counter bit0 (LSB). Enhancement register write enable. While E_WR is "high", Sdata can be serially clocked into the enhancement register on the rising edge of Sclk. Enhancement register write. D[7:0] are latched into the enhancement register on the rising edge of E_WR. A Counter bit1. M2 write. D[3:0] are latched into the primary register (R[5:4], M [8:7]) on the rising edge of M2_WR. A Counter bit2. Selects serial bus interface mode (Bmode=0, Smode=1) or Parallel Interface Mode (Bmode=0, Smode=0). A Counter bit3 (MSB). Selects direct interface mode (Bmode=1). Same as pin 1. M1 write. D[7:0] are latched into the primary register (Pre_en, M[6:0]) on the rising edge of M1_WR. A write. D[7:0] are latched into the primary register (R[3:0], A [3:0]) on the rising edge of A_WR. Hop write. The contents of the primary register are latched into the secondary register on the rising edge of Hop_WR. Prescaler input from the VCO. 3.0 GHz max frequency.
Input
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PE3336
Product Specification
Figure 2. Pin Configurations (Top View)
GND GND GND Enh V DD LD R3 R2 R1 R0 fr
GND GND GND GND Enh VDD LD R3 R2 R1 R0
6
D0, M0 D1, M1 D2, M2 D3, M3 VDD VDD S_WR, D4, M4 Sdata, D5, M5 Sclk, D6, M6 FSELS, D 7, Pre_en GND
5
4
3
2
1
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
fc VDD_f c PD_U PD_D VDD Cext VDD Dout VDD_f p fp GND
D0, M0 D1, M1 D2, M2 D3, M3 VDD VDD S_W R, D4, M4 Sdata, D5, M5 Sclk, D6, M6 FSELS, D7, Pre_en GND
48 47 46 45 44 43 42 41 40 39 38 37
7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
1 2 3 4 5 6 7 8 9 10 11
fr
36 35 34 33 32 31 30 29 28 27 26 25
fc VDD_fc NC PD_U PD_D GND VDD Cext VDDE Dout VDD_fp fp
FSELP, A0 12
13 14 15 16 17 18 19 20 21 22 23 24
E_WR, A1 M2_WR, A2 Smode, A3 Bmode VDD VDD M1_WR A_WR Hop_WR Fin Fin GND
Table 1. Pin Descriptions
Pin No. (44-lead PLCC)
1 2 3 4 5 6 7
FSELP, A0
E_WR, A1
44-lead PLCC
(48-lead QFN)
43 44 45 46 47 48 1
M2_WR, A2
Pin No.
Smode, A3
Bmode
VDD
M1_WR
VDD R0 R1 R2 R3 GND D0 M0 D1
A_WR
Pin Name
Hop_WR
Fin
Fin
48-lead QFN
Interface Mode
ALL Direct Direct Direct Direct ALL Parallel Direct Parallel Direct Parallel Direct Parallel Direct ALL ALL
Type
(Note 1) Input Input Input Input (Note 1) Input Input Input Input Input Input Input Input (Note 1) (Note 1)
Description
Power supply input. Input may range from 2.85 V to 3.15 V. Bypassing recommended. R Counter bit0 (LSB). R Counter bit1. R Counter bit2. R Counter bit3. Ground. Parallel data bus bit0 (LSB). M Counter bit0 (LSB). Parallel data bus bit1. M Counter bit1. Parallel data bus bit2. M Counter bit2. Parallel data bus bit3. M Counter bit3. Same as pin 1. Same as pin 1.
8
2 M1 D2
9
3 M2 D3
10 11 12
4 M3 5 6 VDD VDD
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Document No. 70-0033-02 UltraCMOSTM RFIC Solutions
PE3336
Product Specification
Table 1. Pin Descriptions (continued)
Pin No. (44-lead PLCC)
28 29 30
Pin No. (48-lead QFN)
23 24 25
Pin Name
Fin GND fp
Interface Mode
ALL ALL ALL
Type
Description
Prescaler complementary input. A bypass capacitor should be placed as close as possible to this pin and be connected in series with a 50 resistor directly to the ground plane. Ground.
Input
Output
Monitor pin for main divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding V DD pin 31. VDD for fp. Can be left floating or connected to GND to disable the fp output. Data Out. The MSEL signal and the raw prescaler output are available on Dout through enhancement register programming. Same as pin 1. Logical "NAND" of PD_U and PD_D terminated through an on chip, 2 k series resistor. Connecting Cext to an external capacitor will low pass filter the input to the inverting amplifier used for driving LD. Same as pin 1. PD_D is pulse down when fp leads fc. PD_U is pulse down when fc leads fp.
31
26
VDD-fp
ALL Serial, Parallel ALL
(Note 1)
32 33
27 28
Dout VDD
Output (Note 1)
34
29
Cext
ALL
Output
35 36 37 38
30 32 33 35
VDD PD_D PD_U VDD-fc
ALL ALL ALL ALL
(Note 1) Output
(Note 1)
VDD for fc can be left floating or connected to GND to disable the fc output. Monitor pin for reference divider output. Switching activity can be disabled through enhancement register programming or by floating or grounding VDD pin 38. Ground. Ground.
39 40 41 42 43
36 31,37 38,39 40 41 42 34
fc GND GND fr LD Enh NC
ALL ALL ALL ALL ALL Serial, Parallel ALL
Output
Input Output
Reference frequency input. Lock detect and open drain logical inversion of CEXT. When the loop is in lock, LD is high impedance, otherwise LD is a logic low ("0"). Enhancement mode. When asserted low ("0"), enhancement register bits are functional. No connection.
44 N/A Note 1:
Input
All VDD pins are connected by diodes and must be supplied with the same positive voltage level. VDD-fp and VDD-fp are used to power the fp and fc outputs and can alternatively be left floating or connected to GND to disable the fp and fc outputs.
Note 2:
All digital input pins have 70 k pull-down resistors to ground.
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PE3336
Product Specification
Table 2. Absolute Maximum Ratings
Symbol
VDD VI II IO Tstg
Table 4. ESD Ratings
Units
V V Note 1: mA mA C Periodically sampled, not 100% tested. Tested per MILSTD-883, M3015 C2
Parameter/Conditions
Supply voltage Voltage on any input DC into any input DC into any output Storage temperature
Min
-0.3 -0.3 -10 -10 -65
Max
4.0 VDD +10 +10 150
Symbol
VESD
Parameter/Conditions
ESD voltage (Human Body
Level
1000
Units
V
Electrostatic Discharge (ESD) Precautions When handling this UltraCMOSTM device, observe the same precautions that you would use with other ESD-sensitive devices. Although this device contains circuitry to protect it from damage due to ESD, precautions should be taken to avoid exceeding the specified rating in Table 4. Latch-Up Avoidance Unlike conventional CMOS devices, UltraCMOSTM devices are immune to latch-up.
Table 3. Operating Ratings
Symbol
VDD TA
Parameter/Conditions
Supply voltage Operating ambient
Min
2.85 -40
Max
3.15 85
Units
V C
Table 5. DC Characteristics: VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified
Symbol
IDD Prescaler disabled Prescaler enabled Digital Inputs: All except fr, R0, Fin, Fin VIH VIL IIH IIL High level input voltage Low level input voltage High level input current Low level input current VDD = 2.85 to 3.15 V VDD = 2.85 to 3.15 V VIH = VDD = 3.15 V VIL = 0, VDD = 3.15 V -1 0.7 x VDD 0.3 x VDD +70 V V A A
Parameter
Operational supply current;
Conditions
VDD = 2.85 to 3.15 V
Min
Typ
10 19
Max
Units
mA
26
mA
Reference Divider input: fr IIHR IILR High level input current Low level input current VIH = VDD = 3.15 V VIL = 0, VDD = 3.15 V -100 +100 A A
R0 Input (Pull-up Resistor): R0 IIHRO IILRO High level input current Low level input current VIH = VDD = 3.15 V VIL = 0, VDD = 3.15 V -5 +5 A A
Counter and phase detector outputs: fc, fp, PD_D, PD_U VOLD VOHD Output voltage LOW Output voltage HIGH Iout = 6 mA Iout = -3 mA VDD - 0.4 0.4 V V
Lock detect outputs: Cext, LD VOLC VOHC VOLLD Output voltage LOW, Cext Output voltage HIGH, Cext Output voltage LOW, LD Iout = 100 mA Iout = -100 mA Iout = 6 mA VDD - 0.4 0.4 0.4 V V V
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PE3336
Product Specification
Table 6. AC Characteristics: VDD = 3.0 V, -40 C < TA < 85 C, unless otherwise specified
Symbol
fClk tClkH tClkL tDSU tDHLD tPW tCWR tCE tWRC tEC tMDO
Parameter
Serial data clock frequency Serial clock HIGH time Serial clock LOW time Sdata set-up time after Sclk rising edge, D[7:0] set-up time to M1_WR, M2_WR, A_WR, E_WR rising edge Sdata hold time after Sclk rising edge, D[7:0] hold time to M1_WR, M2_WR, A_WR, E_WR rising edge S_WR, M1_WR, M2_WR, A_WR, E_WR pulse width Sclk rising edge to S_WR rising edge. S_WR, M1_WR, M2_WR, A_WR falling edge to Hop_WR rising edge Sclk falling edge to E_WR transition S_WR falling edge to Sclk rising edge. Hop_WR falling edge to S_WR, M1_WR, M2_WR, A_WR rising edge E_WR transition to Sclk rising edge MSEL data out delay after Fin rising edge
Conditions
Min
Max
10
Units
MHz ns ns ns ns ns ns ns ns ns
Control Interface and Latches (see Figures 3, 4, 5)
30 30 10 10 30 30 30 30 30 CL = 12 pf 8
ns
Main Divider (Including Prescaler) Fin PFin Operating frequency Input level range External AC coupling 500 -5 3000 5 MHz dBm
Main Divider (Prescaler Bypassed) Fin PFin Reference Divider fr Pfr Vfr Phase Detector fc Note 1: Note 2: Note 3: Comparison frequency (Note 1) 20 MHz Operating frequency Reference input power Input sensitivity (Note 1) Single ended input External AC coupling (Note 3) (Note 2) -2 0.5 100 10 MHz dBm VP-P Operating frequency Input level range External AC coupling 50 -5 300 5 MHz dBm
Parameter is guaranteed through characterization only and is not tested. Running at low frequencies (< 10 MHz sinewave), the device will still be functional but may cause phase noise degradation. Inserting a lownoise amplifier to square up the edges is recommended at lower input frequencies. CMOS logic levels may be used if DC coupled. For optimum phase noise performance, the reference input falling edge rate should be faster than 80mV/ns.
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Document No. 70-0033-02 UltraCMOSTM RFIC Solutions
PE3336
Product Specification
Functional Description The PE3336 consists of a prescaler, counters, a phase detector and control logic. The dual modulus prescaler divides the VCO frequency by either 10 or 11, depending on the value of the modulus select. Counters "R" and "M" divide the reference and prescaler output, respectively, by integer values stored in a 20-bit register. An additional counter ("A") is used in the modulus select logic. The phase-frequency detector generates up and down frequency control signals. The control logic includes a selectable chip interface. Data can be written via serial bus, parallel bus, or hardwired direct to the pins. There are also various operational and test modes and lock detect.
Figure 3. Functional Block Diagram
fr
R Counter (6-bit)
fc
D(7:0) Sdata Control Pins
Control Logic
R(5:0) M(8:0) A(3:0)
Phase Detector
PD_U PD_D
Cext
2k
Modulus Select
Fin Fin
10/11 Prescaler
M Counter (9-bit)
fp
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PE3336
Product Specification
Main Counter Chain The main counter chain divides the RF input frequency, Fin, by an integer derived from the user defined values in the "M" and "A" counters. It is composed of the 10/11 dual modulus prescaler, modulus select logic, and 9-bit M counter. Setting Pre_en "low" enables the 10/11 prescaler. Setting Pre_en "high" allows Fin to bypass the prescaler and powers down the prescaler. The output from the main counter chain, fp, is related to the VCO frequency, Fin, by the following equation:
fp = Fin / [10 x (M + 1) + A] where A M + 1, 1 M 511 (1)
Register Programming Parallel Interface Mode Parallel Interface Mode is selected by setting the Bmode input "low" and the Smode input "low". Parallel input data, D[7:0], are latched in a parallel fashion into one of three, 8-bit primary register sections on the rising edge of M1_WR, M2_WR, or A_WR per the mapping shown in Table 7 on page 10. The contents of the primary register are transferred into a secondary register on the rising edge of Hop_WR according to the timing diagram shown in Figure 4. Data are transferred to the counters as shown in Table 7 on page 10. The secondary register acts as a buffer to allow rapid changes to the VCO frequency. This double buffering for "ping-pong" counter control is programmed via the FSELP input. When FSELP is "high", the primary register contents set the counter inputs. When FSELP is "low", the secondary register contents are utilized. Parallel input data, D[7:0], are latched into the enhancement register on the rising edge of E_WR according to the timing diagram shown in Figure 4. This data provides control bits as shown in Table 8 on page 10 with bit functionality enabled by asserting the Enh input "low". Serial Interface Mode Serial Interface Mode is selected by setting the Bmode input "low" and the Smode input "high". While the E_WR input is "low" and the S_WR input is "low", serial input data (Sdata input), B0 to B19, are clocked serially into the primary register on the rising edge of Sclk, MSB (B0) first. The contents from the primary register are transferred into the secondary register on the rising edge of either S_WR or Hop_WR according to the timing diagram shown in Figures 4-5. Data are transferred to the counters as shown in Table 7 on page 10. The double buffering provided by the primary and secondary registers allows for "ping-pong" counter control using the FSELS input. When FSELS is "high", the primary register contents set the counter inputs. When FSELS is "low", the secondary register contents are utilized. While the E_WR input is "high" and the S_WR
Document No. 70-0033-02 UltraCMOSTM RFIC Solutions
When the loop is locked, Fin is related to the reference frequency, fr, by the following equation:
Fin = [10 x (M + 1) + A] x (fr / (R+1)) where A M + 1, 1 M 511 (2)
A consequence of the upper limit on A is that Fin must be greater than or equal to 90 x (fr / (R+1)) to obtain contiguous channels. Programming the M Counter with the minimum value of "1" will result in a minimum M Counter divide ratio of "2". When the prescaler is bypassed, the equation becomes:
Fin = (M + 1) x (fr / (R+1)) where 1 M 511 (3)
In Direct Interface Mode, main counter inputs M7 and M8 are internally forced low. Reference Counter The reference counter chain divides the reference frequency, fr, down to the phase detector comparison frequency, fc. The output frequency of the 6-bit R Counter is related to the reference frequency by the following equation:
fc = fr / (R + 1) where 0 R 63 (4)
Note that programming R equal to "0" will pass the reference frequency, fr, directly to the phase detector. In Direct Interface Mode, R Counter inputs R4 and R5 are internally forced low ("0").
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PE3336
Product Specification
input is "low", serial input data (Sdata input), B0 to B7, are clocked serially into the enhancement register on the rising edge of Sclk, MSB (B0) first. The enhancement register is double buffered to prevent inadvertent control changes during serial loading, with buffer capture of the serially entered data performed on the falling edge of E_WR according to the timing diagram shown in Figure 5. After the falling edge of E_WR, the data provide control bits as shown in Table 8 with bit functionality enabled by asserting the Enh input "low".
Direct Interface Mode Direct Interface Mode is selected by setting the Bmode input "high". Counter control bits are set directly at the pins as shown in Table 7. In Direct Interface Mode, main counter inputs M7 and M8, and R Counter inputs R4 and R5 are internally forced low ("0").
Table 7. Primary Register Programming
Interface Mode Parallel Enh 1 Bmode 0 Smode 0 R5 R4 M8 M7 Pre_en M6 M5 M4 M3 M2 M1 M0 R3 R2 R1 R0 A3 A2 A1 A0
M2_WR rising edge load D3 D2 B1 0 D1 B2 0 D0 B3 0 D7 B4 Pre_en D6 B5 M6
M1_WR rising edge load D5 B6 M5 D4 B7 M4 D3 B8 M3 D2 B9 M2 D1 B10 M1 D0 B11 M0 D7 B12 R3 D6 B13 R2
A_WR rising edge load D5 B14 R1 D4 B15 R0 D3 B16 A3 D2 B17 A2 D1 B18 A1 D0 B19 A0
Serial* Direct
1 1
0 1
1 X
B0 0
*Serial data clocked serially on Sclk rising edge while E_WR "low" and captured in secondary register on S_WR rising edge.
MSB (first in)
(last in) LSB
Table 8. Enhancement Register Programming
Interface Mode Parallel Serial* Enh 0 0 Bmode X X Smode 0 1 Reserved D7 B0 Reserved D6 B1 Reserved D5 B2 Power down Counter load MSEL output D2 B5 Prescaler output D1 B6 fc, fp OE D0 B7 E_WR rising edge load D4 D3 B3 B4
*Serial data clocked serially on Sclk rising edge while E_WR "high" and captured in the double buffer on E_WR falling edge.
MSB (first in)
(last in) LSB
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PE3336
Product Specification
Figure 4. Parallel Interface Mode Timing Diagram
tDSU
tDHLD
D [7 : 0]
tPW tCWR tWRC
M1_WR M2_WR A_WR E_WR
tPW
Hop_WR
Figure 5. Serial Interface Mode Timing Diagram
Sdata
E_WR
tEC tCE
Sclk
S_WR
tDSU tDHLD tClkH tClkL tCWR tPW tWRC
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Document No. 70-0033-02 UltraCMOSTM RFIC Solutions
PE3336
Product Specification
Enhancement Register The functions of the enhancement register bits are shown below with all bits active "high".
Table 9. Enhancement Register Bit Functionality
Bit Function
Bit 0 Bit 1 Bit 2 Bit 3 Bit 4 Bit 5 Bit 6 Bit 7 Reserved** Reserved** Reserved** Power down Counter load MSEL output Prescaler output fp, fc OE Power down of all functions except programming interface. Immediate and continuous load of counter programming as directed by the Bmode and Drives the internal dual modulus prescaler modulus select (MSEL) onto the Dout output. Drives the raw internal prescaler output onto the Dout output. fp, fc outputs disabled.
Description
** Program to 0
Phase Detector The phase detector is triggered by rising edges from the main Counter (fp) and the reference counter (fc). It has two outputs, PD_U, and PD_D. If the divided VCO leads the divided reference in phase or frequency (fp leads fc), PD_D pulses "low". If the divided reference leads the divided VCO in phase or frequency (fc leads fp), PD_U pulses "low". The width of either pulse is directly proportional to phase offset between the two input signals, fp and fc. The phase detector gain is equal to 2.7 V / 2 , which numerically yields 0.43 V / radian. PD_U and PD_D drive an active loop filter which controls the VCO tune voltage. PD_U pulses result in an increase in VCO frequency; PD_D pulses result in a decrease in VCO frequency (for a positive Kv VCO). A lock detect output, LD is also provided, via the pin Cext. Cext is the logical "NAND" of PD_U and PD_D waveforms, which is driven through a series 2 kohm resistor. Connecting Cext to an external shunt capacitor provides low pass filtering of this signal. Cext also drives the input of an internal inverting comparator with an open drain output. Thus LD is an "AND" function of PD_U and PD_D.
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PE3336
Product Specification
Handling Requirements
All surface mount products which do not meet Level 1 moisture sensitivity requirements are processed through dry bake and pack procedure. The necessary data is recorded on the caution label of each shipment. Both packages for the PE3335 are moisture sensitivity Level 3. Level 3 Caution Label The caution label should contain the following information for Level 3 devices: 1. Calculated shelf life in sealed bag: 12 months at <40 C and <90% relative humidity (RH) 2. Peak package body temperature is 225 C. 3. After bag is opened, devices that will be subjected to reflow solder or other high temperature process must a) Be mounted within 168 hours of factory conditions <30 C/60% RH, or b) Be stored at <10% RH 4. Devices require bake, before mounting, if: a) Humidity Indicator Card is > 10% when read at 23 5 C b) 3a or 3b are not met 5. If baking is required, devices may be baked for 48 hours at 125 +5/-0 C Note: If device containers cannot be subjected to high temperature or shorter bake times are desired, reference IPC/JEDEC-J-STD-033 for bake procedure. Level and Body temperature defined by: IPC/JEDEC-J-STD-020 For Dry Bake Procedures, see: IPC/JEDEC-J-STD-033 Operator must observe ESD precautions per ESD Control Procedure and Parts Handling and shipping Procedure.
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Document No. 70-0033-02 UltraCMOSTM RFIC Solutions
PE3336
Product Specification
Figure 6. Package Drawing
48-lead QFN
7.00 -B3.50
INDEX AREA 3.50 X 3.50 3.50 0.25 C -A-
0.10 C
2
0.08 C 0.020 0.20 REF EXPOSED PAD & TERMINAL PADS
0.80
SEATING -CPLANE
0.30 0.50
5.00 5.25 2.50 2.63
12 13 24 25
0.18
7.00 5.50 TYP
0.23
2.50 2.63
1 48 36 37
0.23
2.75 TYP
0.18
DETAIL A 0.50 TYP 0.23 0.10
5.00 5.25
EXPOSED PAD
7.00
2
CAB
1
1. DIMENSION APPLIES TO METALLIZED TERMINAL AND IS MEASURED BETWEEN 0.25 AND 0.30 FROM TERMINAL TIP. 2. COPLANARITY APPLIES TO THE EXPOSED HEAT SINK SLUG AS WELL AS THE TERMINALS.
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PE3336
Product Specification
Figure 7. Package Drawing
44-lead PLCC
0.6900.005 0.6530.003 0.010 X 45 0.045 X 45
4* 0.6900.005 0.6530.003
1*
R0.025
PIN 1 0.050
0.020 MIN.
SURFACE MOUNT POINT 0.610 0.020
3*
2* 0.050
DETAIL
A
BOTTOM VIEW
0.027 (WIDTH OF LEAD SLOT)
*EJECT PIN POSITION O0.040 0.070 0.070 0.010 SEE DETAIL A 0.180 MAX. 0.004 50X 45 DIMENSIONS ARE IN INCHES TOLERANCES ARE 0.004
Table 10. Ordering Information
Order Code
3336-21 3336-22 3336-23 3336-24 3336-00 3336-01
Part Marking
PE3336 PE3336 PE3336 PE3336 PE3336EK PE3336EK
Description
PE3336-44PLCC-27A PE3336-44PLCC-500C PE3336-48QFN 7x7 mm-52A PE3336-48QFN 7x7 mm-2000C PE3336-44PLCC-EVAL KIT PE3336-48QFN 7x7 mm-EK
Package
44-lead PLCC 44-lead PLCC 48-lead QFN 48-lead QFN Evaluation Kit Evaluation Kit
Shipping Method
27 units / Tube 500 units / T&R 52 units / Tube 2000 units / T&R 1 / Box 1 / Box
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Document No. 70-0033-02 UltraCMOSTM RFIC Solutions
PE3336
Product Specification
Sales Offices
The Americas Peregrine Semiconductor Corporation
9450 Carroll Park Drive San Diego, CA 92121 Tel 858-731-9400 Fax 858-731-9499
North Asia Pacific Peregrine Semiconductor K.K.
5A-5, 5F Imperial Tower 1-1-1 Uchisaiwaicho, Chiyoda-ku Tokyo 100-0011 Japan Tel: +81-3-3502-5211 Fax: +81-3-3502-5213
Europe Peregrine Semiconductor Europe
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Data Sheet Identification
Advance Information
The product is in a formative or design stage. The data sheet contains design target specifications for product development. Specifications and features may change in any manner without notice. The information in this data sheet is believed to be reliable. However, Peregrine assumes no liability for the use of this information. Use shall be entirely at the user's own risk. No patent rights or licenses to any circuits described in this data sheet are implied or granted to any third party. Peregrine's products are not designed or intended for use in devices or systems intended for surgical implant, or in other applications intended to support or sustain life, or in any application in which the failure of the Peregrine product could create a situation in which personal injury or death might occur. Peregrine assumes no liability for damages, including consequential or incidental damages, arising out of the use of its products in such applications. The Peregrine name, logo, and UTSi are registered trademarks and UltraCMOS and HaRP are trademarks of Peregrine Semiconductor Corp.
Preliminary Specification
The data sheet contains preliminary data. Additional data may be added at a later date. Peregrine reserves the right to change specifications at any time without notice in order to supply the best possible product.
Product Specification
The data sheet contains final data. In the event Peregrine decides to change the specifications, Peregrine will notify customers of the intended changes by issuing a DCN (Document Change Notice).
Document No. 70-0033-02 www.psemi.com
(c)2005 Peregrine Semiconductor Corp. All rights reserved. Page 15 of 15

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