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Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
FEATURES
* Dual device * Low on-state resistance * Fast switching * Low profile surface mount package
SYMBOL
d1 d2
QUICK REFERENCE DATA VDS = 100 V ID = 3 A RDS(ON) 90 m (VGS = 10 V)
s2
g1 s1
g2
GENERAL DESCRIPTION
Dual N-channel enhancement mode field-effect transistor in a plastic envelope using 'trench' technology. Applications:* Motor and relay drivers * d.c. to d.c. converters The PHKD3NQ10T is supplied in the SOT96-1 (SO8) surface mounting package.
PINNING
PIN 1 2 3 4 5,6 7,8 DESCRIPTION source 1 gate 1 source 2 gate 2 drain 2 drain 1
SOT96-1
8 7 6 5
pin 1 index
1
2
3
4
LIMITING VALUES
Limiting values in accordance with the Absolute Maximum System (IEC 134) SYMBOL VDS VDGR VGS ID ID IDM Ptot Tstg, Tj PARAMETER Continuous drain-source voltage Drain-gate voltage Gate-source voltage Drain current per MOSFET CONDITIONS Tj = 25 C to 150C Tj = 25 C to 150C; RGS = 20 k MIN. - 65 MAX. 100 100 20 3 2.4 2.2 1.7 12 2 1.3 150 UNIT V V V A A A A A W W C
Ta = 25 C, t 10 s Ta = 70 C, t 10 s Drain current per MOSFET (both Ta = 25 C, t 10 s MOSFETs conducting) Ta = 70 C, t 10 s Drain current (pulse peak value per Ta = 25 C MOSFET) Total power dissipation Ta = 25 C, t 10 s Ta = 70 C, t 10 s Storage & operating temperature
THERMAL RESISTANCES
SYMBOL PARAMETER Rth j-a Rth j-a Thermal resistance junction to ambient Thermal resistance junction to ambient CONDITIONS Surface mounted on FR4 board, t 10 sec; either or both MOSFETs conducting Surface mounted on FR4 board; either or both MOSFETs conducting TYP. 150 MAX. 62.5 UNIT K/W K/W
August 1999
1
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
ELECTRICAL CHARACTERISTICS
Tj= 25C, per MOSFET unless otherwise specified SYMBOL PARAMETER V(BR)DSS VGS(TO) RDS(ON) IGSS IDSS Qg(tot) Qgs Qgd td on tr td off tf Ld Ls Ciss Coss Crss Drain-source breakdown voltage Gate threshold voltage CONDITIONS VGS = 0 V; ID = 250 A; Tj = -55C VDS = VGS; ID = 1 mA Tj = 150C Tj = -55C Drain-source on-state VGS = 10 V; ID = 1.5 A resistance Gate source leakage current VGS = 20 V; VDS = 0 V Zero gate voltage drain VDS = 100 V; VGS = 0 V; current Total gate charge Gate-source charge Gate-drain (Miller) charge Turn-on delay time Turn-on rise time Turn-off delay time Turn-off fall time Internal drain inductance Internal source inductance Input capacitance Output capacitance Feedback capacitance ID = 3 A; VDD = 80 V; VGS = 10 V Tj = 150C Tj = 150C MIN. 100 89 2 1.1 TYP. MAX. UNIT 3 70 10 0.05 21 2.5 8 6 12 20 10 2.5 5 633 103 61 4 6 90 216 100 10 100 V V V V V m m nA A A nC nC nC ns ns ns ns nH nH pF pF pF
VDD = 50 V; RD = 15 ; VGS = 10 V; RG = 5.6 Resistive load Measured from drain lead to centre of die Measured from source lead to source bond pad VGS = 0 V; VDS = 20 V; f = 1 MHz
REVERSE DIODE LIMITING VALUES AND CHARACTERISTICS
Tj = 25C, per MOSFET unless otherwise specified SYMBOL PARAMETER IS ISM VSD trr Qrr Continuous source diode current Pulsed source diode current Diode forward voltage Reverse recovery time Reverse recovery charge CONDITIONS Ta = 25 C, t 10 s IF = 2 A; VGS = 0 V IF = 2 A; -dIF/dt = 100 A/s; VGS = 0 V; VR = 25 V MIN. TYP. MAX. UNIT 0.8 55 135 2 12 1.2 A A V ns nC
August 1999
2
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
Normalised Power Derating, PD (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 Ambient temperature, Ta (C) 125 150
100
Transient thermal impedance, Zth j-a (K/W) D = 0.5
10
0.2 0.1 0.05 0.02 single pulse P D D = tp/T
1
tp
0.1 T 0.01 1E-06 1E-05 1E-04 1E-03 1E-02 1E-01 1E+00 1E+01
Pulse width, tp (s)
Fig.1. Normalised power dissipation. PD% = 100PD/PD 25 C = f(Ta)
Fig.4. Transient thermal impedance. Zth j-a = f(t); parameter D = tp/T
Drain Current, ID (A) VGS = 10V 5 4 3 2 1 0 0 0.2 0.4 0.6 0.8 1 1.2 1.4 Drain-Source Voltage, VDS (V) 1.6 1.8 2 4.8 V 8V 6V Tj = 25 C 5V 5.4 V 5.2 V
Normalised Current Derating, ID (%) 100 90 80 70 60 50 40 30 20 10 0 0 25 50 75 100 Ambient temperature, Ta (C) 125 150
6
4.6 V 4.4 V
Fig.2. Normalised continuous drain current. ID% = 100ID/ID 25 C = f(Ta); VGS 10 V
Peak Pulsed Drain Current, IDM (A)
Fig.5. Typical output characteristics, Tj = 25 C. ID = f(VDS)
100
0.2
Drain-Source On Resistance, RDS(on) (Ohms) 4.6V 4.8V 5V 5.2 V 5.4 V 6V 8V VGS = 10V Tj = 25 C 0 1 2 3 4 Drain Current, ID (A) 5 6
RDS(on) = VDS/ ID 10
0.18
tp = 10 us 100 us 1 ms
0.16 0.14 0.12 0.1 0.08 0.06 0.04 0.02
1 10 ms D.C. 0.1 100 ms
0.01 0.1 1 10 100 Drain-Source Voltage, VDS (V) 1000
0
Fig.3. Safe operating area ID & IDM = f(VDS); IDM single pulse; parameter tp
Fig.6. Typical on-state resistance, Tj = 25 C. RDS(ON) = f(ID)
August 1999
3
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
Drain current, ID (A) 6 VDS > ID X RDS(ON) 5 4 3 150 C 2 Tj = 25 C 1 0 0 1 2 3 4 5 6 Gate-source voltage, VGS (V)
4.5 4 3.5 3 2.5 2 1.5 1 0.5 0
Threshold Voltage, VGS(TO) (V) maximum typical
minimum
-60
-40
-20
0
20
40
60
80
100 120 140 160 180
Junction Temperature, Tj (C)
Fig.7. Typical transfer characteristics. ID = f(VGS)
Transconductance, gfs (S) VDS > ID X RDS(ON)
Fig.10. Gate threshold voltage. VGS(TO) = f(Tj); conditions: ID = 1 mA; VDS = VGS
Drain current, ID (A)
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
1.0E-01
1.0E-02
Tj = 25 C
1.0E-03
150 C
minimum typical
1.0E-04 maximum 1.0E-05
1.0E-06
0 1 2 3 4 Drain current, ID (A) 5 6
0
0.5
1 1.5 2 2.5 3 3.5 Gate-source voltage, VGS (V)
4
4.5
5
Fig.8. Typical transconductance, Tj = 25 C. gfs = f(ID)
Normalised On-state Resistance 2.9 2.7 2.5 2.3 2.1 1.9 1.7 1.5 1.3 1.1 0.9 0.7 0.5 -60 -40 -20 0 20 40 60 80 100 120 140 160 180 Junction temperature, Tj (C)
Fig.11. Sub-threshold drain current. ID = f(VGS); conditions: Tj = 25 C; VDS = VGS
10000
Capacitances, Ciss, Coss, Crss (pF)
1000
Ciss
100
Coss
Crss 10 0.1 1 10 Drain-Source Voltage, VDS (V) 100
Fig.9. Normalised drain-source on-state resistance. RDS(ON)/RDS(ON)25 C = f(Tj)
Fig.12. Typical capacitances, Ciss, Coss, Crss. C = f(VDS); conditions: VGS = 0 V; f = 1 MHz
August 1999
4
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
Source-Drain Diode Current, IF (A) Gate-source voltage, VGS (V) 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 0 ID = 3A Tj = 25 C VDD = 20 V 4 150 C 3 VDD = 80 V 2 1 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 Gate charge, QG (nC) 0 0.1 0.2 0.3 0.4 0.5 0.6 0.7 0.8 0.9 1 1.1 1.2 Source-Drain Voltage, VSDS (V) Tj = 25 C 6 VGS = 0 V 5
Fig.13. Typical turn-on gate-charge characteristics. VGS = f(QG)
Fig.14. Typical reverse diode current. IF = f(VSDS); conditions: VGS = 0 V; parameter Tj
August 1999
5
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
MECHANICAL DATA
SO8: plastic small outline package; 8 leads; body width 3.9 mm SOT96-1
D
E
A X
c y HE vMA
Z 8 5
Q A2 A1 pin 1 index Lp 1 e bp 4 wM L detail X (A 3) A
0
2.5 scale
5 mm
DIMENSIONS (inch dimensions are derived from the original mm dimensions) UNIT mm inches A max. 1.75 0.069 A1 0.25 0.10 A2 1.45 1.25 A3 0.25 0.01 bp 0.49 0.36 c 0.25 0.19 D (1) 5.0 4.8 0.20 0.19 E (2) 4.0 3.8 0.16 0.15 e 1.27 0.050 HE 6.2 5.8 L 1.05 Lp 1.0 0.4 Q 0.7 0.6 v 0.25 0.01 w 0.25 0.01 y 0.1 0.004 Z (1) 0.7 0.3 0.028 0.012
0.010 0.057 0.004 0.049
0.019 0.0100 0.014 0.0075
0.244 0.039 0.028 0.041 0.228 0.016 0.024
8 0o
o
Notes 1. Plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT96-1 REFERENCES IEC 076E03S JEDEC MS-012AA EIAJ EUROPEAN PROJECTION
ISSUE DATE 95-02-04 97-05-22
Fig.15. SOT96 surface mounting package.
Notes 1. This product is supplied in anti-static packaging. The gate-source input must be protected against static discharge during transport or handling. 2. Refer to Integrated Circuit Packages, Data Handbook IC26. 3. Epoxy meets UL94 V0 at 1/8".
August 1999
6
Rev 1.000
Philips Semiconductors
Product specification
Dual N-channel TrenchMOSTM transistor
PHKD3NQ10T
DEFINITIONS
Data sheet status Objective specification Product specification Limiting values Limiting values are given in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of this specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. (c) Philips Electronics N.V. 1999 All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, it is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent or other industrial or intellectual property rights. This data sheet contains target or goal specifications for product development. This data sheet contains final product specifications. Preliminary specification This data sheet contains preliminary data; supplementary data may be published later.
LIFE SUPPORT APPLICATIONS
These products are not designed for use in life support appliances, devices or systems where malfunction of these products can be reasonably expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
August 1999
7
Rev 1.000

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