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PI6C21200
1:12 Clock Driver for Intel PCI-Express Chipsets
Features
* Twelve Pairs of PCI-Express Differential Clocks (HCSL compatible signaling) * Low skew < 50ps * Low jitter < 50ps * Output Enable for all outputs * Outputs tristate control via SMBus * Power Management Control * Programmable PLL Bandwidth * PLL or Fan out operation * Gear Ratio supporting different output frequencies * 3.3V Operation * 56-pin Packages (Pb-Free & Green): - TSSOP (A56) and SSOP (V56)
Description
PI6C21200 is a high-speed, low-noise PCI-Express differential clock buffer designed to be a companion with PI6C410B clock synthesizer. The device distributes twelve copies of the differential SRC clock coming from PI6C410B. The output frequency can be ratioed to offer a derivative frequency from the input frequency. Each differential output is controlled by individual OE pin, except OUT10 and OUT11 are sharing one OE_10#_11# pin. The clock outputs are controlled by input selection of SA_0, SA_1, SA_2 via SMBus, SCLK and SDA.
Block Diagram
OE [0:10]# VTT_PWRGD# / PWRDWN SCLK SDA SA_[0:1] SA_2 / PLLBypress# SRC SCR#
Pinout Diagram
Output Control
HIGH_BW# SRC_IN SRC_IN# SA_0 OE_0# OUT0 OUT0# OE_1# OUT1 OUT1# VDD VSS OUT2 OUT2# OE_2# OUT3 OUT3# OE_3# OUT4 OUT4# OE_4# VDD VSS OUT5 OUT5# OE_5# SA_1 SDA 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 VDD_A VSS_A IREF OE_10#_11# OUT11 OUT11# VDD VSS OUT10 OUT10# FS_A VTT_PWRGD# / PWRDWN OE_9# OUT9 OUT9# OE_8# OUT8 OUT8# VDD VSS OUT7 OUT7# OE_7# OUT6 OUT6# OE_6# SA_2 /PLLBypass# SCL
OUT0 OUT0# OUT1 OUT1# OUT2 OUT2# OUT3 OUT3# OUT4 OUT4# OUT5 OUT5# OUT6 OUT6#
SMBus Controller
HIGH_BW#
PLL
OUT7 OUT7# OUT8 OUT8# OUT9 OUT9# OUT10 OUT10# OUT11 OUT11#
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Pin Descriptions
Pin Name PLL_BW# SRC & SRC# OUT[0:9] & OUT[0:9]# OUT[10:11] & OUT[10:11]# OE_[0:9]# OE_10#_11# SA_[0:1] SA_2 / PLLBYPASS# SCLK SDA IREF FS_A VTT_PWRGD# / PWRDWN VDD VSS VSS_A VDD_A Type Input Input Output Output Input Input Input Input Input I/O Input Input Input Power Ground Ground Power Pin Number 1 2, 3 6, 7, 9, 10, 13, 14, 16, 17, 19, 20, 24, 25, 32, 33, 35, 36, 39, 40, 42, 43 47, 48, 51, 52 5, 8, 15, 18, 21, 26, 31, 34, 41, 44 53 4, 27 30 29 28 54 46 45 11, 22, 38, 50 12, 23, 37, 49 55 56 Descriptions 3.3V LVTTL input for selecting the PLL bandwidth. (High = Low BW) 0.7V Differential SRC input from PI6C410B clock synthesizer 0.7V Differential outputs, geared to the ratio of input clock. Can be configured to be 1:1 ratio. 0.7V Differential outputs, geared to the ratio of input clock same as OUT[0:9]. Can be configured to be 1:1 ratio. 3.3V LVTTL input for enabling outputs, active low. Control each OUT[0:9] pair. 3.3V LVTTL input for enabling outputs, active low. Control each OUT[10:11] pair. 3.3V LVTTL input for selecting the SMBus address 3.3V LVTTL input for selecting fan-out of PLL operation, and SMBus address. 0 = PLL Bypass, 1 = PLL mode SMBus compatible SCLOCK input SMBus compatible SDATA External resistor connection to set the differential output current 3.3V LVTTL inputs for CPU frequency selection 0 = above 200 MHz, 1 = below 200 MHz 3.3V LVTTL input for Power Down operation, active high 3.3V Power Supply for Outputs Ground for Outputs Ground for PLL 3.3V Power Supply for PLL
Serial Data Interface (SMBus)
PI6C21200 is a slave only SMBus device that supports random byte read and write indexed block read and write protocol using a single 7-bit address and read/write bit as shown below.
SMBus Address Selection by SA_[0:2]
SA_2/ PLLBypass# 0 0 0 0 1 1 1 1 SA_1 0 0 1 1 0 0 1 1 SA_0 0 1 0 1 0 1 0 1 SMBus Address D0 D2 D4 D6 D8 DA DC DE PLL Mode Bypass Bypass Bypass Bypass PLL PLL PLL PLL
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Indexed Block Read and Write Protocol
Block Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29:36 37 38:45 46 .... .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 Bits '00000000' Stand for block operation Acknowledge from slave Byte Count from master - 8 bits Acknowledge from slave Datat byte 0 from master - 8 bits Acknowledge from slave Datat byte 1 from master - 8 bits Acknowledge from slave Data bytes from master/Acknowledge Data byte N - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20 21:27 28 29 30:37 38 39:46 47 48:55 56 .... .... .... .... Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 Bits '00000000' Stand for block operation Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Byte count from slave - 8 bits Acknowledge from host Data byte 0 from slave - 8 bits Acknowledge from host Data byte 1 from slave - 8 bits Acknowledge from host Data bytes from slave/Acknowledge Data byte N from slave - 8 bits Acknowledge from host - 38 bits Stop Block Read Protocol Description
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Random Byte Read and Write Protocol
Byte Write Protocol Bit 1 2:8 9 10 11:18 19 20:27 28 29 Start Slave address - 7 bits Write = 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed. Acknowledge from slave Data byte from master - 8 bits Acknowledge from slave Stop Description Bit 1 2:8 9 10 11:18 19 20:27 21:27 28 29 30:37 38 39 Start Slave address - 7 bits Write - 0 Acknowledge from slave Command Code - 8 bits '100xxxxx' stands for byte operation, bits[6:0] of the command code represents the offset of the byte to be accessed. Acknowledge from slave Repeat start Slave address - 7 bits Read = 1 Acknowledge from slave Data byte from slave - 8 bits Acknowledge from master - 38 bits Stop Byte Read Protocol Description
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Data Byte 0: Control Register
Bit 0 1 2 3 4 5 6 7 Descriptions FSB Gear Ratio SMBus FSB Gear Ratio SMBus FSB Gear Ratio SMBus FSB Gear Ratio SMBus FS_A PI6C410B latched input Reserved Group of 2 gear ratio select 1 = 1:1, 0 = Gear Raito Group of 10 gear ratio select 1 = 1:1, 0 = Gear Raito Type RW RW RW RW RW RW RW RW Power Up Condition 1 Depends on FS_A pin(1) 0 Depends on FS_A pin(1) Latch 1 1 1 OUT[10:11], OUT[10:11]# OUT[0:9], OUT[0:9]# Output(s) Affected
Note: 1. When FS_A = 1, Bit 1 = 0 and Bit 3 = 1; When FS_A = 0, Bit 1 = 1 and Bit 3 = 0
Data Byte 1: Control Register
Bit 0 1 2 3 4 5 6 7 OUTPUTS enable 1 = Enabled 0 = Hi-Z Descriptions Type RW RW RW RW RW RW RW RW Power Up Condition 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled Output(s) Affected OUT0, OUT0# OUT1, OUT1# OUT2, OUT2# OUT3, OUT3# OUT4, OUT4# OUT5, OUT5# OUT6, OUT6# OUT7, OUT7#
Data Byte 2: Control Register
Bit 0 1 2 3 4 5 6 Descriptions OUTPUTS enable 1 = Enabled 0 = Hi-Z Reserved PLL/BYPASS# 0 = Fanout,1 = PLL PLL Bandwidth 0 = High Bandwidth, 1 = Low Bandwidth Outputs current select at PWRDWN = 1 1 = 2 x IREF, 0 = HiZ Type RW RW RW RW RW RW RW 1 = PLL 1 = Low OUT[0:11], OUT[0:11]# OUT[0:11], OUT[0:11]# Power Up Condition 1 = Enabled 1 = Enabled 1 = Enabled 1 = Enabled Output(s) Affected OUT8, OUT8# OUT9, OUT9# OUT10, OUT10# OUT11, OUT11#
7
RW
1
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Data Byte 3: Control Register
Bit 0 1 2 3 4 5 6 7 Descriptions OE_0#, 1 = Disable (Hi-Z), 0 = Enable OE_1#, 1 = Disable (Hi-Z), 0 = Enable OE_2#, 1 = Disable (Hi-Z), 0 = Enable OE_3#, 1 = Disable (Hi-Z), 0 = Enable OE_4#, 1 = Disable (Hi-Z), 0 = Enable OE_5#, 1 = Disable (Hi-Z), 0 = Enable OE_6#, 1 = Disable (Hi-Z), 0 = Enable OE_7#, 1 = Disable (Hi-Z), 0 = Enable Type R R R R R R R R Power Up Condition Depends on state of pin Depends on state of pin Depends on state of pin Depends on state of pin Depends on state of pin Depends on state of pin Depends on state of pin Depends on state of pin Output(s) Affected OUT0, OUT0# OUT1, OUT1# OUT2, OUT2# OUT3, OUT3# OUT4, OUT4# OUT5, OUT5# OUT6, OUT6# OUT7, OUT7#
Data Byte 4: Control Register
Bit 0 1 2 3 4 5 6 7 Descriptions OE_8#, 1 = Disable (Hi-Z), 0 = Enable OE_9#, 1 = Disable (Hi-Z), 0 = Enable OE_10#_11#, 1 = Disable (Hi-Z), 0 = Enable Reserved Reserved Readback - PLLBypass input Readback - HIGH_BW# input Readback - FS_A input Type R R R R R R R R Latch value of pin at power up Latch value of pin at power up Latch value of pin at power up Power Up Condition Depends on state of pin at power up Depends on state of pin at power up Depends on state of pin at power up Output(s) Affected OUT8, OUT8# OUT9, OUT9# OUT[10:11], OUT[10:11]#
Data Byte 5: Pericom ID Register
Bit 0 1 2 3 4 5 6 7 Revision Code Pericom ID Descriptions Type R R R R R R R R Power Up Condition 0 0 0 0 0 0 0 0 Output(s) Affected NA NA NA NA NA NA NA NA
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Data Byte 6: Device ID Register
Bit 0 1 2 3 4 5 6 7 Device ID 0 Device ID 1 Device ID 2 Device ID 3 Device ID 4 Device ID 5 Device ID 6 Device ID 7 Descriptions Type R R R R R R R R Power Up Condition 0 0 1 1 0 0 0 0 Output(s) Affected NA NA NA NA NA NA NA NA
Data Byte 7: Byte Counter Register
Bit 0 1 2 3 4 5 6 7 Descriptions BC0 - Writing to the register configures how many bytes will be read back BC1 - Writing to the register configures how many bytes will be read back BC2 - Writing to the register configures how many bytes will be read back BC3 - Writing to the register configures how many bytes will be read back BC4 - Writing to the register configures how many bytes will be read back BC5 - Writing to the register configures how many bytes will be read back BC6 - Writing to the register configures how many bytes will be read back BC7 - Writing to the register configures how many bytes will be read back Type RW RW RW RW RW RW RW RW Power Up Condition 1 1 1 0 0 0 0 0 Output(s) Affected NA NA NA NA NA NA NA NA
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Programmable Gear Ratio - Output Frequency
FS_A Bit 3 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SMBus Byte 0 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input M 3 5 12 2 5 8 3 4 6 1 5 4 3 2 3 1 Output N 1 2 5 1 3 5 2 3 5 1 6 5 4 3 5 2 Gear Ratio (N/M) 0.333 0.400 0.417 0.500 0.600 0.625 0.667 0.750 0.833 1.000 1.200 1.250 1.333 1.500 1.667 2.000 200 NA NA NA 100.0 120.0 125.0 133.3 150.0 166.7 200.0 240.0 250.0 266.7 300.0 333.3 400.0 CPU Input Frequency (MHz) 266.7 NA 106.7 111.1 133.3 160.0 166.7 177.8 200.0 222.2 266.7 320.0 333.3 NA 400.0 444.4 NA 320 106.7 128.0 133.3 160.0 192.0 200.0 213.3 240.0 NA 320.0 384.0 400.0 NA 480.0 NA NA 333.3 111.1 133.3 138.9 166.7 200.0 208.3 222.2 NA NA 333.3 400.0 416.6 NA NA NA NA 400 133.3 160.0 166.7 200.0 240.0 NA 266.7 NA NA 400.0 480.0 500.0 NA NA NA NA
Note: 1. Line in BOLD is power-up default for FS_A = 0 for Pericom Semiconductor's PI6C410B.
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Programmable Gear Ratio - Output Frequency -- Continued
FS_A Bit 3 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 SMBus Byte 0 Bit 2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 Bit 1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 Bit 0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Input M 3 5 12 2 5 8 3 5 6 1 5 4 3 2 3 1 Output N 1 2 5 1 3 5 2 4 5 1 6 5 4 3 5 2 Gear Ratio (N/M) 0.333 0.400 0.417 0.500 0.600 0.625 0.667 0.800 0.833 1.000 1.200 1.250 1.333 1.500 1.667 2.000 100 NA NA NA 50.0 60.0 62.5 66.7 80.0 NA 100.0 120.0 125.0 133.3 150.0 166.7 200.0 CPU Input Frequency (MHz) 133.3 NA 53.3 55.6 66.7 80.0 83.3 88.9 106.7 111.1 133.3 160.0 166.7 177.8 200.2 222.2 266.7 160 53.3 64.0 66.7 80.0 96.0 100.0 106.7 128.0 133.3 160.0 192.0 200.0 213.3 240.0 266.7 320.0 166.67 55.6 66.7 69.4 83.3 100.0 104.2 111.1 133.3 138.9 166.7 200.0 208.3 222.2 250.0 277.8 333.3 200 66.7 80.0 83.3 100.0 120.0 NA 133.3 160.0 166.7 200.0 240.0 NA 266.7 300.0 333.3 400.0
Note: 1. Line in BOLD is power-up default for FS_A = 0 for Pericom Semiconductor's PI6C410B.
Functionality
VTT_PWRGD# / PWRDWN 0 1 OUT Normal 2 x IREF or Float OUT# Normal Low OE# pin 0 0 1 1 OE (SMBus bit) 1 0 1 0 OUT Normal Hi-Z Hi-Z Hi-Z OUT# Normal Hi-Z Hi-Z Hi-Z
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Power Down (PWRDWN assertion)
PWRDWN OUT OUT#
Figure 1. Power down sequence
Power Down (PWRDWN De-assertion)
Tstable < 1ms
PWRDWN
OUT OUT# Tdrive_PWRDWN < 300US, >200mV
Figure 2. Power down de-assert sequence
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Current-mode output buffer characteristics of OUT[0:11], OUT[0:11]#
VDD (3.3V 5%) Slope ~ 1/RO RO IOUT ROS IOUT VOUT = 1.2V max 0V 1.2V
Figure 3. Simplified diagram of current-mode output buffer
Differential Clock Buffer Characteristics
Symbol RO ROS VOUT Minimum 3000 unspecified N/A Maximum N/A unspecified 850mV
Current Accuracy
Symbol IOUT
Note: 1. INOMINAL refers to the expected current based on the configuration of the device.
Conditions VDD = 3.30 5%
Configuration RREF = 475 1% IREF = 2.32mA
Load Nominal test load for given configuration
Min. -12% INOMINAL
Max. +12% INOMINAL
Differential Clock Output Current
Board Target Trace/Term Z 100 differential Reference R, Iref = VDD/(3xRr) RREF= 475 1%, IREF = 2.32mA Output Current IOH = 6 x Iref VOH @ Z 0.7V @ 50
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Absolute Maximum Ratings (Over operating free-air temperature range)
Symbol VDD_A VDD VIH VIL Ts VESD Parameters 3.3V Core Supply Voltage 3.3V I/O Supply Voltage Input High Voltage Input Low Voltage Storage Temperature ESD Protection -0.5 -65 2000 150 C V Min. -0.5 -0.5 Max. 4.6 4.6 4.6 V Units
Note: 1. Stress beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device.
DC Electrical Characteristics (VDD = 3.35%, VDD_A = 3.3 5%)
Symbol VDD_A VDD VIH VIL IIK VOH VOL IOH CIN COUT LPIN IDD ISS ISS TA Parameters 3.3V Core Supply Voltage 3.3V I/O Supply Voltage 3.3V Input High Voltage 3.3V Input Low Voltage Input Leakage Current 3.3V Output High Voltage 3.3V Output Low Voltage Output High Current Input Pin Capacitance Output Pin Capacitance Pin Inductance Power Supply Current Power Down Current Power Down Current Ambient Temperature VDD = 3.465V, FCPU = 400 MHz Driven outputs Tristate outputs 0 0 < VIN < VDD IOH = -1mA IOL = 1mA IOH = 6 x IREF, IREF = 2.32mA 12.2 15.6 3 5 6 7 375 90 24 70 C mA VDD Condition Min. 3.135 3.135 2.0 VSS - 0.3 -5 2.4 0.4 Max. 3.465 3.465 VDD + 0.3 0.8 +5 A V mA pF nH V Units
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets AC Switching Characteristics (VDD = 3.35%, VDD_A = 3.3 5%)
Symbol Trise / Tfall Trise / Tfall Parameters Rise and Fall Time (measured between 0.175V to 0.525V) Rise and Fall Time Variation Rise/Fall Matching Tpd Tskew Tskew Tjitter VHIGH VLOW VCROSS VCROSS TDC PLL Mode Non-PLL Mode Output-to-Output Skew OUT [9:0] or OUT [10:11] Output-to-Output Skew OUT [9:0] to OUT [10:11] Cycle-to-Cycle Jitter Voltage High including overshoot Voltage Low including undershoot Absolute crossing poing voltages Total Variation of Vcross over all edges Duty Cycle 45 660 -150 250 550 100 55 % 3 50 75 50 850 mV ps Min 125 Max. 525 75 10 250 ps % ps ns 4 4 4 3 3 3 3 4 Units Notes 3 3 3
Notes: 3. Measurement taken from Single Ended waveform. 4. Measurement taken from Differential waveform. 5. Test configuration is RS = 33.2, Rp = 49.9, and 2pF.
Configuration Test Load Board Termination
Rs 33 5% PI6C21200
Clock TLA Clock# TLB
Rs 33 5% 2pF 5%
475 1%
Rp 49.9 1%
Rp 49.9 1%
2pF 5%
Note: 1. TLA and TLB are 3" transmission lines.
Figure 4. Configuration test load board termination
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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Packaging Mechanical: 56-Pin, 240-mil wide TSSOP (A)

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PI6C21200 1:12 Clock Driver for Intel PCI-Express Chipsets Packaging Mechanical: 56-Pin, 400-mil wide SSOP (V)
56
.291 .299 7.39 7.59
.396 .416 10.06 10.56
Gauge Plane
.010 0.25
1
.02 .04 0.51 1.01
.720 18.29 .730 18.54
.008 0.20 Nom.
.015 0.381 x 45 .025 0.635
.110 2.79 Max
.025 BSC 0.635
X.XX DENOTES DIMENSIONS X.XX IN MILLIMETERS
.008 .0135 0.20 0.34
0-8
.008 0.20 .016 0.40
Ordering Information:
Ordering Code PI6C21200AE PI6C21200VE Packaging Code A V Package Type 56-Pin, 240-mil wide, 0.5mm pitch TSSOP, Pb-Free and Green 56-Pin, 400-mil wide, 0.65mm pitch SSOP, Pb-Free and Green
Pericom Semiconductor Corporation * 1-800-435-2336 * www.pericom.com
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