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21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16835
18-Bit Universal Bus Driver with 3-State Outputs
Product Features
Very high-speed, low-noise universal bus driver with embedded resistor outputs Meets PC133 SDRAM Registered DIMM specification Implements output impedance control for low-noise and heavy-load applications Fast Propagation Delay: 2.5ns max. for 50pF test load VCC = 3.3V or 2.5V or 1.8V Packages available: 56-pin 240 mil wide plastic TSSOP (A) 56-pin 173 mil wide plastic TVSOP (K)
Product Description
Pericom Semiconductor's PI74AVC series of logic circuits are produced using the Company's advanced 0.35 micron CMOS technology, achieving industry leading speed. The 18-bit PI74AVC16835 universal bus driver is designed for 1.8V to 3.6V Vcc operation. Data flow from A to Y is controlled by Output Enable (OE). The device operates in the transparent mode when LE is HIGH. The A data is latched if CLK is held at a high or low logic level. If LE is LOW, the A-bus is stored in the latch/flip-flop on the low-to-high transition of CLK. When OE is HIGH, the outputs are in the highimpedance state. The PI74AVC16835 bus driver is designed to drive an array of 133 MHz synchronous memory chips, with minimal undershoot/ overshoot noise, and to meet the input signal rise/fall time requirement of memory chips. The output drivers of this part have an embedded series-resistor. For DIMM module design, no external series termination resistors near the buffer drivers or any other termination resistors are required. This feature simplifies DIMM module layout design, and results in cost savings.
Product Pin Configuration
NC NC Y1 GND Y2 Y3 VCC Y4 Y5 Y6 GND Y7 Y8 Y9 Y10 Y11 Y12 GND Y13 Y14 Y15 VCC Y16 Y17 GND Y18 OE LE
1 2 3 4 5 6 7 8 9 10 11 12 13 56-Pin 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28
56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
GND NC A1 GND A2 A3 VCC A4 A5 A6 GND A7 A8 A9 A10 A11 A12 GND A13 A14 A15 VCC A16 A17 GND A18 CLK GND
A56 K56
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PS8373D
08/03/99
Product Pin Description
Pin Name OE LE CLK A Y GND VCC Description Output Enable Input (Active LOW) Latch Enable Clock Input Data Input Data Output Ground Power
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PI74AVC16835 18-Bit Universal Bus Driver w/3-State Outputs
Logic Block Diagram
27
Truth Table(1)
Inputs OE H LE X H H L L L L CLK X X X H L A X L H L H X X Outputs Y Z L H L H Yo(2) Yo(3)
OE
CLK
30
L L
28 LE 54
L L
A1
1D C1 CLK 3 Y1
L L
TO 17 OTHER CHANNELS
Note: 1 H = High Signal Level L = Low Signal Level Z = High Impedance = Transition LOW-to-HIGH X = Irrelevant 2. Output level before the indicated steady-state input conditions were established, provided that CLK is HIGH before LE goes LOW. 3. Output level before the indicated steady-state input conditions were established.
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PS8373D
08/03/99
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PI74AVC16835 18-Bit Universal Bus Driver w/3-State Outputs
Maximum Ratings
(Above which the useful life may be impaired. For user guidelines, not tested.) Storage Temperature ............................................................................................................. 65C to +150C Ambient Temperature with Power Applied ............................................................................ 40C to +85C Supply Voltage Range, VCC ............................................................................................................................................................................... 0.5V to +4.6V Input Voltage Range, VI(1) .................................................................................................................................................................................... 0.5V to +4.6V Voltage range applied to any output in the high-impedance or power-off state, VO(1) ........... 0.5V to +4.6V Voltage range applied to any output in the high or low state, VO(1,2) ............................... 0.5V to VCC +0.5V Input clamp current, IIK (VI <0) ............................................................................................................. 50mA Output clamp current, IOK (VO <0) ........................................................................................................ 50mA Continuous output current, IO ................................................................................................................ 50mA Continuous current through each VCC or GND .................................................................................... 100mA Package thermal impedance, JA(3): A (TSSOP) package .................................................................... 81C/W K (TVSOP) package .................................................................... 86C/W Note: 1. Input and output negative voltage ratings may be exceeded if the input and output current ratings are observed. 2. Output positive voltage rating may be exceeded up to 4.6V maximum if the output current rating is observed. 3. Package thermal impedance is calculated in accordance with JESD 51. Stresses greater than those listed under MAXIMUM RATINGS may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
3
PS8373D
08/03/99
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PI74AVC16835 18-Bit Universal Bus Driver w/3-State Outputs
Recommended Operating Conditions(1)
Parame te rs VCC D e s cription Supply Voltage Te s t Conditions O perating Data Retention O nly VCC = 1.2V VIH High- level Input Voltage VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VCC = 1.2V VIL Low- level Input Voltage VCC = 1.65V to 1.95V VCC = 2.3V to 2.7V VCC = 3V to 3.6V VIN VOUT Input Voltage O utput Voltage Active State 3- State VCC = 1.65V to 1.95V IOHS High- level O utput Current (2) VCC = 2.3V to 2.7V VCC = 3V to 3.6V VCC = 1.65V to 1.95V IOLS Low- level O utput Current (2) VCC = 2.3V to 2.7V VCC = 3V to 3.6V t/v TA Input transition rise or fall rate O perating Free- Air Temperature VCC = 1.65V to 3.6V - 40 0 0 0 M in. 1.65 1.2 VCC 0.65 x VCC 1.7 2 GND 0.35 x VCC 0.7 0.8 3.6 VCC 3.6 -4 -8 - 12 4 8 12 5 85 ns/V C mA V M ax. 3.6 Units
Note: 1. Unused control inputs must be held HIGH or LOW to prevent them from floating. 2. Dynamic drive is greater than standard output drive of IOH = 24mA and IOL = 24mA
4
PS8373D
08/03/99
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PI74AVC16835 18-Bit Universal Bus Driver w/3-State Outputs
Typ.(2)
DC Electrical Characteristics (Over the Operating Range, TA = -40C to +85C, VCC = 3.3V 10%)
Parame te rs IOHS = 100A VOH IOHS = 4mA IOHS = 8mA IOHS = 12mA IOLS = 100A VOL IOLS = 4mA IOLS = 8mA IOLS = 12mA II IOFF IOZ(3) ICC Control Inputs CI Data Input VI = VCC or GND Control Inputs VI = VCC or GND VI = 0 or 3.6V VO = VCC or GND VI = VCC or GND OE = VCC IO = 0 Te s t Conditions VIH or VIL VIH = 1.07V VIH = 1.7V VIH = 2V VIH or VIL VIL = 0.57V VIL = 0.7V VIL = 0.8V VCC(1) 1.65 to 3.6 1.65 2.3 3.0 1.65 to 3.6 1.65 2.3 3.0 3.6 0 3.6 3.6 2.5 3.3 2.5 3.3 VO = VCC or GND 2.5 3.3 4.5 4.5 4.0 4.0 6.5 6.5 pF M in. VCC - 0.2 1.2 1.75 2.3 0.2 0.45 0.55 0.7 2.5 10 10 40 A V M ax. Units
CO
Outputs
Notes: 1. For Max. or Min. conditions, use appropriate value specified under Electrical Characteristics for the applicable device type. 2. Typical values are measured at +25C. 3. For I/O ports, the IOZ includes the input leakage current.
Timing Requirements over Operating Range
Parame te rs fCLOCK tW Pulse Duration tSU Setup time tH Hold time De s cription Clock Frequency LE High CLK High or Low Data before CLK Data before LE, CLK High or Low Data after CLK Data after LE, CLK High or Low 2.0 2.0 1.4 1.4 1.0 1.0 VCC = 1.8 V 0.15V M in. M ax. 150 1.2 1.2 1.2 1.2 0.8 0.8 VCC = 2.5V 0.2V M in. M ax. 150 1.0 1.0 1.0 1.0 0.6 0.6 ns VCC = 3.3V 0.3V M in. M ax. 150 MHz Units
5
PS8373D
08/03/99
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PI74AVC16835 18-Bit Universal Bus Driver w/3-State Outputs
Switching Characteristics Over Recommended Operating Free-Air Temperature Range Unless otherwise noted, see Figures 3 through 5.
Parame te r fmax A tpd LE CLK ten tDIS OE OE Y From (Input) To (Output) VCC = 1.8V 0.15V M in. 150 1.0 1.0 1.0 1.5 1.5 4.5 5.0 4.5 5.5 5.0 M ax. VCC = 2.5V 0.2V M in. 150 0.8 0.8 0.8 1.0 1.0 3.0 3.3 3.0 4.5 4.5 M ax. VCC = 3.3V(1) 0.3V M in. 150 0.7 0.7 0.7 1.0 1.0 2.4 2.5 2.5 4.0 4.0 M ax.
Units MHz
ns
Note 1. Load at 50pF and 500.
Operating Characteristics, TA = 25C
Parame te rs Cpd Power dissipation capacitance O utputs Enabled O utputs Disabled Te s t Conditions CL = 0, f = 10 MHz VCC = 1.8V Typ. 45 23 VCC = 2.5V Typ. 48 25 VCC = 3.3V Typ. 52 28 Units
pF
6
PS8373D
08/03/99
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16835 18-Bit Universal Bus Driver w/3-State Outputs
Parameter Measurement Information (VCC = 1.8V 0.15V)
R1 500 2 x VCC Open GND
TEST tpd tPLZ/tPZL tPHZ/tPZH
S1 Ope n 2 x VCC GND
From Output Under Test
CL=30pF
(See Note A)
1k
Load Circuit
tW
Timing Input tsu Data Input
VCC/2
VCC
VCC/2
0V th VCC
VCC/2
VCC Input
VCC/2 VCC/2
0V
0V
Voltage Waveforms Pulse Duration
Output Control
(Low-level enabling)
Voltage Waveforms Setup and Hold Times
VCC
VCC VCC/2 tPZL VCC/2 tPZH VCC/2 VCC/2 tPLZ 0V VCC VOL +0.15V VOL tPHZ VOH VOH -0.15V 0V
Input
Vcc/2
Vcc/2 0V
Output Waveform 1 S1 at 2 x VSS
(see Note B)
tPLH
tPLH
VOH
Output
Vcc/2
Vcc/2 VOL
Output Waveform 2 S1 at GND
(see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Notes:
A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tr 2ns, tr 2ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as tdis. G. tPLH and tPHL are the same as tdis.
Figure 3. Load Circuit and Voltage Waveforms
7
PS8373D
08/03/99
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PI74AVC16835 18-Bit Universal Bus Driver w/3-State Outputs
Parameter Measurement Information (VCC = 2.5V 0.2V)
500 S1 2 x VCC Open GND
From Output Under Test
TEST tpd tPLZ/tPZL tPHZ/tPZH
S1 Ope n 2 x VCC GND
CL=30pF
(See Note A)
500
Load Circuit
tW
Timing Input tsu Data Input
VCC/2
VCC
VCC/2
VCC Input
VCC/2 VCC/2
0V th VCC
VCC/2
0V
Voltage Waveforms Pulse Duration
Output Control
(Low-level enabling)
0V
Voltage Waveforms Setup and Hold Times
VCC
VCC VCC/2 tPZL VCC/2 tPZH VCC/2 VCC/2 tPLZ 0V VCC VOL +0.15V VOL tPHZ VOH VOH -0.15V 0V
Input
Vcc/2
Vcc/2 0V
Output Waveform 1 S1 at 2 x VSS
(see Note B)
tPLH
tPLH
VOH
Output
Vcc/2
Vcc/2 VOL
Output Waveform 2 S1 at GND
(see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Notes:
A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tr 2ns, tr 2ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as tdis. G. tPLH and tPHL are the same as tdis.
Figure 4. Load Circuit and Voltage Waveforms
Pericom Semiconductor Corporation 2380 Bering Drive * San Jose, CA 95131 * 1-800-435-2336 * Fax (408) 435-1100 * http://www.pericom.com
8
PS8373D 08/03/99
21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321 21098765432121098765432109876543210987654321210987654321098765432109876543212109876543210987654321098765432121098765432109876543210987654321
PI74AVC16835 18-Bit Universal Bus Driver w/3-State Outputs
Parameter Measurement Information (VCC = 3.3V 0.3V)
2 x VCC Open GND
From Output Under Test
500
S1
TEST tpd tPLZ/tPZL tPHZ/tPZH
S1 Ope n 2 x VCC GND
CL=50pF
(See Note A)
500
Load Circuit
tW
Timing Input tsu Data Input
VCC/2
VCC
VCC/2
VCC Input
VCC/2 VCC/2
0V th VCC
VCC/2
0V
Voltage Waveforms Pulse Duration
Output Control
(Low-level enabling)
0V
Voltage Waveforms Setup and Hold Times
VCC VCC/2 tPZL VCC/2 tPZH VCC/2 VCC/2 tPLZ 0V VCC VOL +0.3V VOL tPHZ VOH VOH -0.3V 0V
VCC
Input
Vcc/2
Vcc/2 0V
Output Waveform 1 S1 at 2 x VSS
(see Note B)
tPLH
tPLH
VOH
Output
Vcc/2
Vcc/2 VOL
Output Waveform 2 S1 at GND
(see Note B)
Voltage Waveforms Propagation Delay Times
Voltage Waveforms Enable and Disable Times
Notes:
A. CL includes probe and jig capacitance. B. Waveform 1 is for an output with internal conditions such that the output is LOW except when disabled by the output control. Waveform 2 is for an output with internal conditions such that the output is HIGH except when disabled by the output control. C. All input pulses are supplied by generators having the following characteristics: PRR 10 MHz, ZO = 50, tr 2ns, tr 2ns. D. The outputs are measured one at a time with one transition per measurement. E. tPLZ and tPHZ are the same as tdis. F. tPZL and tPZH are the same as tdis. G. tPLH and tPHL are the same as tdis.
Figure 5. Load Circuit and Voltage Waveforms
9
PS8373D
08/03/99

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