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(Preliminary)PL611s-26
1.8V-3.3V PicoPLL TM Programmable Clock
FEATURES
* Advanced One Time Programmable (OTP) PLL design * Programmable PLL or direct oscillation operation * Very low Jitter and Phase Noise (30-70ps Pk-Pk typical) * Output Frequency up to o 133MHz @ 1.8V operation o 166MHz @ 2.5V operation o 200MHz @ 3.3V operation * Reference Input Frequency: 1MHz to 200MHz * Accepts >0.1V reference signal input voltage * Low current consumption, <10 A when PDB is activated * One programmable I/O pin can be configured as Output Enable (OE),Power Down (PDB) input or an additional clock output (CLK1). * Frequency Switching (FSEL) capability * Single 1.8V, 2.5V, or 3.3V 10% power supply * Operating temperature range from -40C to 85C * Available in 6-pin SOT23 and DFN GREEN/RoHS compliant packaging
DESCRIPTION
The PL611s-26 is a general purpose frequency synthesizer and a member of PhaseLink's PicoPLL TM product family. Designed to fit in a small 6-pin DFN or 6-pin SOT package for high performance applications, the PL611s-26 offers very low phase noise, jitter, and power consumption, while offering up to 2 clock outputs.. The Frequency Switching (FSEL) capability of PL611s-26 allows for programming two sets of frequencies, while the power down feature of PL611s-26, when activated, allows the IC to consume less than 10 A of power. PL611s-26's programming flexibility allows generating any output using Reference input signal.
BLOCK DIAGRAM
FIN
FREF
R-Counter (8-bit) M-Counter (11-bit) Phase Detector Charge Pump Loop Filter
F VCO = F REF * (2 * M/R)
VCO
FOUT = F VCO / (2 * P)
Programmable Function
P-Counter (5-bit)
CLK0 FSEL
Programming Logic
OE, PDB, CLK1
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 1
(Preliminary)PL611s-26
1.8V-3.3V PicoPLL TM Programmable Clock
KEY PROGRAMMING PARAMETERS
CLK Output Frequency FOUT = FREF * M / (R * P) Where M = 11 bit R = 8 bit P = 5 bit CLK0 = FOUT, FREF or FREF / (2*P) CLK1 = FREF, FREF/2, CLK0 or CLK0/2 Output Drive Strength Three optional drive strengths to choose from: * Low: 4mA * Std: 8mA (default) * High: 16mA Programmable Input/Output One output pin can be configured as: * OE - input * PDB - input * CLK1 - output
PACKAGE PIN CONFIGURATION AND DESCRIPTION
OE, PDB, CLK1 FIN OE,PDB,CLK1 GND 1 2 3 6 5 4 FSEL VDD CLK0 GND FIN
1 2 3
6 5 4
CLK0 VDD FSEL
PL611s-26 L611s-26
DFNDFN-6L
(2.0mmx1.3mmx0.6mm) mmx1 mmx0 mm)
SOT23SOT23-6L 23
(3.0mmx3.0mmx1.35mm) mmx3 mmx1 35mm) mm
PIN DESCRIPTION
Name Pin Assignment DFN Pin# SOT Pin # Type Description
This programmable I/O pin can be configured as an Output Enable (OE) input, Power Down input (PDB) or CLK1 Clock output. This pin has an internal 60K pull up resistor (OE and PDB functions only). 2 1 I/O Pin State 0 1 (default) GND FIN 3 1 2 3 P I OE Disable CLK Normal mode PDB Power Down Mode Normal mode
OE, PDB, CLK1
FSEL
6
4
I
GND connection Reference input pin Frequency Switching Input pin. This pin has an internal 60K resistor. FSEL State 0 1 (default) Frequency 2 Frequency 1
pull up
VDD CLK0
5 4
5 6
P O
VDD connection Programmable Clock Output
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 2
(Preliminary)PL611s-26
1.8V-3.3V PicoPLL TM Programmable Clock
FUNCTIONAL DESCRIPTION
PL611s-26 is a highly featured, very flexible, advanced programmable PLL design for high performance, lowpower, small form-factor applications. The PL611s-26 accepts a reference clock input of 1MHz to 200MHz and is capable of producing two outputs up to 200MHz. This flexible design allows the PL611s-26 to deliver any PLL generated frequency, FREF (Ref Clk) frequency or FREF /(2*P) to CLK0 and/or CLK1. Some of the design features of the PL611s-26 are mentioned below: PLL Programming The PLL in the PL611s-26 is fully programmable. The PLL is equipped with an 8-bit input frequency divider (R-Counter), and an 11-bit VCO frequency feedback loop divider (M-Counter). The output of the PLL is transferred to a 5-bit post VCO divider (PCounter). The output frequency is determined by the following formula [FOUT = FREF * M / (R * P) ]. Clock Output (CLK0) CLK0 is the main clock output. The PL611s-26 can also be programmed to provide a second clock output, CLK1, on the programmable I/O pin (see OE/PDB/CLK1 pin description below). The output of CLK0 can be configured as the PLL output (F VCO /(2*P)), FREF (Ref Clk Frequency) output, or FREF/(2*P) output. The output drive level can be programmed to Low Drive (4mA), Standard Drive (8mA) or High Drive (16mA). The maximum output frequency is determined by the power supply voltage as shown below: Clock Output (CLK1) The CLK1 feature allows the PL611s-26 to have an additional clock output. This output can be programmed to one of the following: FREF - Reference (Ref Clk ) Frequency FREF / 2 CLK0 CLK0 / 2 Frequency Select (FSEL) The Frequency Select (FSEL) feature allows the PL611s-26 to switch between two pre-programmed outputs allowing the device "On the Fly" frequency switching. The FSEL pin incorporates a 60k pull up resistor giving a default condition of logic "1". Output Enable (OE) The Output Enable feature allows the user to enable and disable the clock output(s) by toggling the OE pin. The OE pin incorporates a 60k pull up resistor giving a default condition of logic "1". Power-Down Control (PDB) The Power Down (PDB) feature allows the user to put the PL611s-26 into "Sleep Mode". When activated (logic `0'), PDB `Disables the PLL, the oscillator circuitry, counters, and all other active circuitry. In Power Down mode the IC consumes <10 A of power. The PDB pin incorporates a 60k pull up resistor giving a default condition of logic "1".
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 3
(Preliminary)PL611s-26
1.8V-3.3V PicoPLL TM Programmable Clock
ELECTRICAL SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS PARAMETERS
Supply Voltage Range Input Voltage Range Output Voltage Range Soldering Temperature (Green package) Data Retention @ 85C Storage Temperature Ambient Operating Temperature*
SYMBOL
VDD VI VO
MIN.
MAX.
7 VDD+0.5 VDD+0.5 260 150 85
UNITS
V V V C Year C C
-0.5 -0.5 -0.5
10
TS
-65 -40
Exposure of the device under conditions beyond the limits specified by Maximum Ratings for extended periods may cause permanent damage to the device and affect product reliability. These conditions represent a stress rating only, and functional operations of the device at these or any other conditions above the operational limits noted in this specification is not implied. *Operating temperature is guaranteed by design. Parts are tested to commercial grade only.
AC SPECIFICATIONS
PARAMETERS
@ VDD =3.3V Input (FIN) Frequency Input (FIN) Signal Amplitude Input (FIN) Signal Amplitude Output Frequency Settling Time Output Enable Time @ VDD =2.5V @ VDD =1.8V Internally AC coupled (High Frequency) Internally AC coupled (Low Frequency) 3.3V <50MHz, 2.5V <40MHz, 1.8V <15MHz @ VDD =3.3V @ VDD =2.5V @ VDD =1.8V At power-up (after VDD increases over 1.62V) OE Function; Ta=25 C, 15pF Load 1 0.9 0.1
CONDITIONS
MIN.
TYP.
MAX.
200 166 133 VDD VDD 200 166 133 2 10
UNITS
MHz Vpp Vpp MHz MHz MHz ms ns ms ns ns % ps
PDB Function; Ta=25 C, 15pF Load Output Rise Time 15pF Load, 10/90% VDD, High Drive, 3.3V Output Fall Time 15pF Load, 90/10% VDD, High Drive, 3.3V Duty Cycle VDD /2 Period Jitter,Pk-to-Pk* With capacitive decoupling between VDD and (measured from 10,000 samples) GND. * Note: Jitter performance depends on the programming parameters.
45
1.2 1.2 50 70
2 1.7 1.7 55
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 4
(Preliminary)PL611s-26
1.8V-3.3V PicoPLL TM Programmable Clock
DC SPECIFICATIONS
PARAMETERS
Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic, with Loaded CMOS Outputs Supply Current, Dynamic with Loaded CMOS Outputs Stand By Current, with Loaded Outputs Operating Voltage Output Low Voltage Output High Voltage Output Current, Low Drive Output Current, Standard Drive Output Current, High Drive
SYMBOL
IDD IDD IDD IDD VDD VOL VOH IOSD IOSD IOHD
CONDITIONS
@ VDD =3.3V, 27MHz, load=15pF @ VDD =2.5V, 27MHz, load=15pF @ VDD =1.8V, 27MHz, load=15pF When PDB=0
MIN.
TYP.
5.5 3.8 1.8*
MAX.
UNITS
mA mA mA
<10 1.62 3.63 0.4
A V V V mA mA mA
IOL = +4mA Standard Drive IOH = -4mA Standard Drive VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V VOL = 0.4V, VOH = 2.4V
VDD - 0.4 4 8 16
* Note: Please contact PhaseLink, if super low-power is required.
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 5
(Preliminary)PL611s-26
1.8V-3.3V PicoPLL TM Programmable Clock
LAYOUT RECOMMENDATIONS
The following guidelines are to assist you with a performance optimized PCB design: - Keep all the PCB traces to the PL611s-26 as short as possible, as well as keeping all other traces as far away from it as possible. - Place a 0.01 F~0.1 F decoupling capacitor between VDD and GND, on the component side of the PCB, close to the VDD pin. It is not recommended to place this component on the backside of the PCB. Going through vias will reduce the signal integrity, causing additional jitter and phase noise. - It is highly recommended to keep the VDD and GND traces as short as possible. - When connecting long traces (> 1 inch) to a CMOS output, it is important to design the traces as a transmission line or `stripline', to avoid reflections or ringing. In this case, the CMOS output needs to be matched to the trace impedance. Usually `striplines' are designed for 50 impedance and CMOS outputs usually have lower than 50 impedance so matching can be achieved by adding a resistor in series with the CMOS output pin to the `stripline' trace. - Please contact PhaseLink for additional information on how to design outputs driving long traces or for the Gerber files for the PL611s-26 eval board shown.
DFN-6L Evaluation Board
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 6
(Preliminary)PL611s-26
1.8V-3.3V PicoPLL TM Programmable Clock
PACKAGE DRAWINGS (GREEN PACKAGE COMPLIANT)
SOT23-6L Dimension in MM Min. Max. 1.05 1.35 0.05 0.15 1.00 1.20 0.30 0.50 0.08 0.20 2.80 3.00 1.50 1.70 2.60 3.0 0.35 0.55 0.95 BSC
Symbol A A1 A2 b c D E H L e DFN-6L
E
H
D
A2 A A1 e b C L
D1
Symbol A A1 A3 b e D E D1 E1 L
Dimension in MM Min. Max. 0.50 0.60 0.00 0.05 0.152 0.152 0.15 0.25 0.40BSC 1.25 1.35 1.95 2.05 0.75 0.85 0.95 1.05 0.20 0.30
b
e Pin 6 ID Chamfer E1 E
D
L Pin1 Dot A A1
A3
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 7
(Preliminary)PL611s-26
1.8V-3.3V PicoPLL TM Programmable Clock
ORDERING INFORMATION (GREEN PACKAGE COMPLIANT)
For part ordering, please contact our Sales Department: 47745 Fremont Blvd., Fremont, CA 94538, USA Tel: (510) 492-0990 Fax: (510) 492-0991 PART NUMBER The order number for this device is a combination of the following: Part number, Package type and Operating temperature range
PL611s-26-XXX X X X
PART NUMBER
3 DIGIT ID Code * (will be assigned at programming time) PACKAGE TYPE G=DFN-6L T=SOT23-6L Part/Order Number PL611s-26-XXXGC-R PL611s-26-XXXTC-R
NONE= TUBE R=TAPE and REEL TEMPERATURE C=COMMERCIAL I = INDUSTRIAL Marking XXX 26XXX Package Option 6-Pin DFN (Tape and Reel) 6-Pin SOT23 (Tape and Reel)
Note: `XXX' designates marking identifier that, at times, could be independent of the part number. Please consult your PhaseLink sales for marking information.
PhaseLink Corporation, reserves the right to make changes in its products or specifications, or both at any time without notice. The information furnished by Phaselink is believed to be accurate and reliable. However, PhaseLink makes no guarantee or warranty concerning the accuracy of said information and shall not be responsible for any loss or damage of whatever nature resulting from the use of, or reliance upon this product. LIFE SUPPORT POLICY: PhaseLink's products are not authorized for use as critical components in life support devices or systems without the express written approval of the President of PhaseLink Corporation.
Solder reflow profile available at www.phaselink.com/QA/solderingGreen.pdf
47745 Fremont Blvd., Fremont, California 94538 Tel (510) 492-0990 Fax (510) 492-0991 www.phaselink.com Rev 12/12/06 Page 8

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