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MITSUBISHI SEMICONDUCTOR MITSUBISHI SEMICONDUCTOR
PS11014 PS11014
FLAT-BASE TYPE FLAT-BASE TYPE INSULATED TYPE INSULATED TYPE
PS11014
INTEGRATED FUNCTIONS AND FEATURES
* Converter bridge for 3 phase AC-to-DC power conversion. * Circuit for dynamic braking of motor regenerative energy. * 3-phase IGBT inverter bridge configured by the latest 3rd. generation IGBT and diode technology. * Inverter output current capability IO (Note 1): Type Name PS11014 100% load 5.0A (rms) 150% over load 7.5A (rms), 1min
(Note 1) : The inverter output current is assumed to be sinusoidal and the peak current value of each of the above loading cases is defined as : IOP = IO x 2
INTEGRATED DRIVE, PROTECTION AND SYSTEM CONTROL FUNCTIONS:
* For inverter side upper-leg IGBTs : Drive circuit, High voltage isolated high-speed level shifting, Short circuit protection (SC). Bootstrap circuit supply scheme (single drive power supply) and Under voltage protection (UV). * For inverter side lower-leg IGBTs : Drive circuit, Short circuit protection (SC). Control supply circuit under- & over- voltage protection (OV/UV). System over temperature protection (OT). Fault output signaling circuit (FO) and Current limit warning signal output (CL). * For Brake circuit IGBT : Drive circuit * Warning and Fault signaling : FO1 : Short circuit protection for lower-leg IGBTs and Input interlocking against spurious arm shoot-through. FO2 : N-side control supply abnormality locking (OV/UV). FO3 : System over-temperature protection (OT). CL : Warning for inverter current overload condition * For system feedback control : Analogue signal feedback reproducing actual inverter output phase currents (3). * Input Interface : 5V CMOS/TTL compatible, Schmitt trigger input, and Arm-Shoot-Through interlock protection.
APPLICATION Acoustic noise-less 0.75kW/AC200V class 3 phase inverter and other motor control applications
PACKAGE OUTLINES
4-R2 0.5 V6
56 7 8 91011121314151617181920212223
Terminals Assignment: 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 CBU+ CBU- CBV+ CBV- CBW+ CBW- GND NC VDH CL FO1 FO2 FO3 CU CV CW UP VP WP UN 21 VN 22 WN 23 Br
12 3 4
2424
24
5
94.2 1
82 0.8
50
V 0.5
2 0.3
2-4
2-R4 5.08 0.3 ! 9 = 45.72 0.8
31 32 33 34 35 36 37 38 39 40
1.2 V Control Pin top portion details
0~0.8
(16.25)
31 32 33 34 35 36 37 38 39 40
R S T P1 P2 N B U V W
V 0.6
29
22.6
5
8.5
20.4 1
12
27 1
V Main terminal top portion details 0.8
0.5 0
3.5
LABEL 54 0.5 62 1
0.3
0~0.8
0.35MAX
0.4
12
0.5 0
0.5
0.6
0.5 0.03
(Fig. 1)
Jan . 2000
MITSUBISHI SEMICONDUCTOR
PS11014
FLAT-BASE TYPE INSULATED TYPE
INTERNAL FUNCTIONS BLOCK DIAGRAM
C3 ; 3.3F or more, tight tolerance, temp-compensated electrolytic type (Note : the value may change depending on the type PWM control scheme used in the applied system) C4 ; 2F R-category ceramic condenser for noise filtering.
CBW- CBW+ C4,C3 CBU- CBU+ CBV- CBV+
Application Specific Intelligent Power Module P2 Brake resistor connection, B Inrush prevention P1 circuit, etc. AC200V line input R S T Z C N
Z : Surge absorber. C : AC filter (Ceramic condenser 2.2~6.5nF) [Note : Additionally an appropriate Line-to line surge absorber circuit maybe necessary depending on the application environment].
Protection Circuit
Level shifter
Drive Circuit
U V W
M
T.S.
AC 200V line output
Current sensing circuit Trig signal conditioning
Drive Curcuit FO Logic
Protection circuit
Control supply fault sense
C2 C2 ; 3.3F or more
GND VDH (15V line) Note 1) To prevent chances of signal oscillation, an RC coupling at each output is recommended. (see also Fig.10) Note 2) By virtue of integrating an application specific type HVIC inside the module, direct coupling to CPU, without any opto or transformer isolation ispossible. (see also Fig.10) Note 3) All these outputs are open collector type. Each signal line should be pulled up to plus side of the 5V power supply with approximately 5.1k resistance. (see also Fig.10) Note 4) The wiring between power DC link capacitor and P/N terminals should be as short as possible to protect the ASIPM against catastrophic high surge voltage. For extra precaution, a small film type snubber capacitor (0.1~0.22F, high voltage type) is recommended to be mounted close to these P and N DC powerinput pins.
CUCVCW Analogue signal output corresponding to each phase current (5V line) Note 1)
UPVPWPUN VNWN Br CL FO1 FO2 FO3 Each phase input (PWM) Fault output (5V line) Note 2) (5V line) Note 3)
(Fig. 2)
MAXIMUM RATINGS (Tj = 25C) INVERTER PART (Including Brake Part)
Item Supply voltage VCC(surge) Supply voltage (surge) VP or VN VP(S) or VN(S) IC(ICP) IC(ICP) IF(IFP) Symbol VCC Condition Applied between P2-N Ratings 450 500 600 600 15 (30) 4 (8) 4 (8) Unit V V V V A A A
Applied between P2-N, Surge-value Applied between P-U, V, W, Br or U, V, W, Each output IGBT collector-emitter static voltage Br-N Each output IGBT collector-emitter Applied between P-U, V, W, Br or U, V, W, switching surge voltage Br-N Each output IGBT collector current TC = 25C Brake IGBT collector current Brake diode anode current Note: "( )" means IC peak value
CONVERTER PART
Symbol VRRM Ea IO IFSM I2t Item Repetitive peak reverse voltage Recommended AC input voltage DC output current Surge (non-repetitive) forward current I2t for fusing Condition Ratings 800 220 25 196 160 Unit V V A A A 2s
3 rectifying circuit 1 cycle at 60Hz, peak value non-repetitive Value for one cycle of surge current
CONTROL PART
Symbol VDH, VDB VCIN VFO IFO VCL ICL ICO Supply voltage Input signal voltage Fault output supply voltage Fault output current Current-limit warning (CL) output voltage CL output current Analogue current signal output current Item Condition Applied between VDH-GND, CBU+-CBU-, CBV+-CBV-, CBW+-CBW- Applied between UP * VP * WP * UN * VN * WN * Br-GND Applied between FO1 * FO2 * FO3-GND Sink current of FO1 * FO2 * FO3 Applied between CL-GND Sink current of CL Sink current of CU * CV * CW Ratings 20 -0.5 ~ 7.5 -0.5 ~ 7 15 -0.5 ~ 7 15 1 Unit V V V mA V mA mA
Jan. 2000
MITSUBISHI SEMICONDUCTOR
PS11014
FLAT-BASE TYPE INSULATED TYPE
TOTAL SYSTEM
Symbol Tj Tstg TC Viso -- Item Junction temperature Storage temperature Module case operating temperature Isolation voltage Mounting torque Condition (Note 2) -- (Fig. 3) 60 Hz sinusoidal AC applied between all terminals and the base plate for 1 minute. Mounting screw: M3.5 Ratings -20 ~ +125 -40 ~ +125 -20 ~ +100 2500 0.78 ~ 1.27 Unit C C C Vrms kg*cm
Note 2) The item defines the maximum junction temperature for the power elements (IGBT/Diode) of the ASIPM to ensure safe operation. However, these power elements can endure junction temperature as high as 150C instantaneously . To make use of this additional temperature allowance, a detailed study of the exact application conditions is required and, accordingly, necessary information is requested to be provided before use.
CASE TEMPERATURE MEASUREMENT POINT (3mm from the base surface)
TC
(Fig. 3)
THERMAL RESISTANCE
Symbol Rth(j-c)Q Rth(j-c)F Junction to case Thermal Rth(j-c)QB Resistance Rth(j-c)FB Rth(j-c)FR Rth(c-f) Contact Thermal Resistance Item Inverter IGBT (1/6) Inverter FWDi (1/6) Brake IGBT Brake FWDi Converter Di (1/6) Case to fin, thermal grease applied (1 Module) Condition Min. -- -- -- -- -- -- Ratings Typ. -- -- -- -- -- -- Max. 2.8 3.9 5.8 6.0 4.3 0.044 Unit C/W C/W C/W C/W C/W C/W
ELECTRICAL CHARACTERISTICS (Tj = 25C, VDH = 15V, VDB = 15V unless otherwise noted)
Symbol VCE(sat) VEC VCE(sat)Br VFBr IRRM VFR ton tc(on) toff tc(off) trr FWD reverse recovery time Short circuit endurance (Output, Arm, and Load, Short Circuit Modes) Switching SOA Item Collector-emitter saturation voltage FWDi forward voltage Brake IGBT Collector-emitter saturation voltage Brake diode forward voltage Condition VDH = VDB = 15V, Input = ON, Tj = 25C, IC = 15A Tj = 25C, IC = -15A, Input = OFF VDH = 15V, Input = ON, Tj = 25C, IC = 4A Tj = 25C, IF = 4A, Input = OFF Min. -- -- -- -- -- -- 0.3 -- -- -- -- Ratings Typ. -- -- -- -- -- -- 0.6 0.2 1.1 0.4 0.1 Max. 2.9 2.9 3.5 2.9 8 1.5 1.5 0.6 1.8 1.0 -- Unit V V V V mA V s s s s s
Converter diode reverse current VR = VRRM, Tj = 125C Tj = 25C, IF = 10A Converter diode voltage 1/2 Bridge inductive load, Input = ON Switching times VCC = 300V, Ic = 15A, Tj = 125C VDH = 15V, VDB = 15V Note : ton, toff include delay time of the internal control circuit VCC 400V, Input = ON (one-shot) Tj = 125C start 13.5V VDH = VDB 16.5V VCC 400V, Tj 125C, Ic < IOL(CL) operation level, Input = ON 13.5V VDH = VDB 16.5V
* No destruction * FO output by protection operation * No destruction * No protecting operation * No FO output
Jan . 2000
MITSUBISHI SEMICONDUCTOR
PS11014
FLAT-BASE TYPE INSULATED TYPE
ELECTRICAL CHARACTERISTICS (Tj = 25C, VDH = 15V, VDB = 15V unless otherwise noted)
Symbol IDH Vth(on) Vth(off) Ri fPWM txx tdead tint VCO Item Circuit current Input on threshold voltage Input off threshold voltage Input pull-up resistor PWM input frequency Allowable input on-pulse width Allowable input signal dead time for blocking arm shoot-through Input inter-lock sensing Condition VDH = 15V, VCIN = 5V Min. -- 0.8 2.5 -- 2 1 2.2 -- 1.87 0.77 2.97 -- -- 4.0 -- -5 -- 14.05 -- -- (Fig. 7) (Note 5) 23.2 100 -- 11.05 11.55 18.00 TC = -20C ~ +100C Tj 125C 16.50 10.0 10.5 -- -- -- Ratings Typ. -- 1.4 3.0 150 -- -- -- 65 2.27 1.17 3.37 15 -- -- 1.1 -- 3 17.30 -- 1 43.0 110 90 12.00 12.50 19.20 17.50 11.0 11.5 10 -- 1 Max. 150 2.0 4.0 -- 20 500 -- 100 2.57 1.47 3.67 -- 0.7 -- -- 5 -- 20.80 1 -- 62.0 120 -- 12.75 13.25 20.15 18.65 12.0 12.5 -- 1 -- Unit mA V V k kHz s s ns V V V mV V V V % s A A mA A C C V V V V V V s A mA
Integrated between input terminal-VDH TC 100C, Tj 125C (Note 3) VDH = 15V, TC = -20C ~ +100C Relates to corresponding input (Except brake part) TC = -20C ~ +100C Relates to corresponding input (Except brake part) Ic = 0A Ic = IOP(200%) Ic = -IOP(200%) VDH = 15V TC = -20C ~ +100C (Fig. 4)
Analogue signal linearity with VC+(200%) output current VC-(200%) Offset change area vs temperature |VCO| VC+ Analogue signal output voltage limit VC- VC(200%) Analogue signal over all linear variation rCH td(read) IOL ICL(H) ICL(L) SC OT OTr UVDH UVDHr OVDH OVDHr UVDB UVDBr tdV IFO(H) IFO(L) Supply circuit under & over voltage protection Analogue signal data hold accuracy Analogue signal reading time Current limit warning (CL) operation level Idle Active Short circuit over current trip level Trip level Over temperature protection Reset level Signal output current of CL operation Trip level Reset level Trip level Reset level Trip level Reset level Filter time Idle Active
VDH = 15V, TC = -20C ~ +100C Ic > IOP(200%), VDH = 15V (Fig. 4) |VCO-VC(200%)| Correspond to max. 500s data hold period only, Ic = IOP(200%) (Fig. 5) After input signal trigger point VDH =15V, TC = -20C ~ +100C Open collector output Tj = 25C VDH =15V (Fig. 8) (Note 4)
Fault output current
Open collector output
(Note 3) : (a) Allowable minimum input on-pulse width : This item applies to P-side circuit only. (b) Allowable maximum input on-pulse width : This item applies to both P-side and N-side circuits excluding the brake circuit. (Note4) : CL output : The "current limit warning (CL) operation circuit outputs warning signal whenever the arm current exceeds this limit. The circuit is reset automatically by the next input signal and thus, it operates on a pulse-by-pulse scheme. (Note5) : The short circuit protection works instantaneously when a high short circuit current flows through an internal IGBT rising up momentarily. The protection function is, thus meant primarily to protect the ASIPM against short circuit distraction. Therefore, this function is not recommended to be used for any system load current regulation or any over load control as this might, cause a failure due to excessive temperature rise. Instead, the analogue current output feature or the over load warning feature (CL) should be appropriately used for such current regulation or over load control operation. In other words, the PWM signals to the ASIPM should be shut down, in principle, and not to be restarted before the junction temperature would recover to normal, as soon as a fault is feed back from its FO1 pin of the ASIPM indicating a short circuit situation.
RECOMMENDED CONDITIONS
Symbol VCC VDH, VDB Item Supply voltage Control supply voltage Condition Applied across P2-N terminals Applied between VDH-GND, CBU+-CBU-, CBV+-CBV-, CBW+-CBW- Ratings 400 (max.) 151.5 1 (max.) 0 ~ 0.3 Using application circuit Using application circuit 4.8 ~ 5.0 2 ~ 20 2.2 (min.) Unit V V V/s V V kHz s
Jan. 2000
VDH, VDB Supply voltage ripple VCIN(on) Input on voltage VCIN(off) Input off voltage fPWM PWM Input frequency tdead Arm shoot-through blocking time
MITSUBISHI SEMICONDUCTOR
PS11014
FLAT-BASE TYPE INSULATED TYPE
Fig. 4 OUTPUT CURRENT ANALOGUE SIGNALING LINEARITY
5
Fig. 5 OUTPUT CURRENT ANALOGUE SIGNALING "DATA HOLD" DEFINITION
VC
VC- 4 min
max VC-(200%)
VDH=15V TC=-20~100C
500s
0V
VC0
3
VC(V)
VCH(5s) VCH(505s)-VCH(5s) VCH(5s)
VCH(505s)
2
VC+(200%)
rCH=
1
Analogue output signal data hold range
VC+
0 -400 -300 -200 -100
0
100 200 300 400
Note ; Ringing happens around the point where the signal output voltage changes state from "analogue" to "data hold" due to test circuit arrangement and instrumentational trouble. Therefore, the rate of change is measured at a 5 s delayed point.
Real load current peak value.(%)(Ic=Io! 2)
(Fig. 4)
Fig. 6 INPUT INTERLOCK OPERATION TIMING CHART
Input signal VCIN(p) of each phase upper arm Input signal VCIN(n) of each phase lower arm 0V Gate signal Vo(p) of each phase upper arm (ASIPM internal) Gate signal Vo(n) of each phase upper arm (ASIPM internal) Error output FO1 0V
0V
0V 0V
Note : Input interlock protection circuit ; It is operated when the input signals for any upper-arm / lower-arm pair of a phase are simultaneously in "LOW" level. By this interlocking, both upper and lower IGBTs of this mal-triggered phase are cut off, and "FO" signal is outputted. After an "input interlock" operation the circuit is latched. The "FO" is reset by the high-to-low going edge of either an upper-leg, or a lower-leg input, whichever comes in later.
Fig. 7 TIMING CHART AND SHORT CIRCUIT PROTECTION OPERATION
Input signal VCIN of each phase upper arm Short circuit sensing signal VS
0V 0V
SC delay time
Gate signal Vo of each phase upper arm(ASIPM internal) Error output FO1
0V 0V
Note : Short circuit protection operation. The protection operates with "FO" flag and reset on a pulse-by-pulse scheme. The protection by gate shutdown is given only to the IGBT that senses an overload (excluding the IGBT for the "Brake").
Jan . 2000
MITSUBISHI SEMICONDUCTOR
PS11014
FLAT-BASE TYPE INSULATED TYPE
Fig. 8 INVERTER OUTPUT ANALOGUE CURRENT SENSING AND SIGNALING TIMING CHART
N-side IGBT Current
off
N-side FWDi Current
VCIN V(hold) IC
on on off
0
+ICL
(VS)
0
-ICL
t(hold) Ref
VC
0 off
VCL
on
Delay time td(read)
Fig. 9 START-UP SEQUENCE
Normally at start-up, Fo and CL output signals will be pulled-up High to Supply voltage (OFF level); however, FO1 output may fall to Low (ON) level at the instant of the first ON input pulse to an N-Side IGBT. This can happen particularly when the boot-strap capacitor is of large size. FO1 resetting sequence (together with the boot-strap charging sequence) is explained in the following graph
Fig. 10 RECOMMENDED I/O INTERFACE CIRCUIT
5V
ASIPM
5.1k R
DC-Bus voltage Control voltage supply Boot-strap voltage N-Side input signal P-Side input signal Brake input signal FO1 output signal
VPN 0 VDH 0 VDB VCIN(N)
0 on
PWM starts a)
UP,VP,WP,UN,VN,WN,Br
R
CPU
10k 0.1nF 0.1nF
F01,F02,F03,CL CU,CV,CW GND(Logic)
b)
VCIN(P) on VCIN(Br) on FOI
on
a) Boot-strap charging scheme : Apply a train of short ON pulses at all N-IGBT input pins for adequate charging (pulse width = approx. 20s number of pulses =10 ~ 500 depending on the boot-strap capacitor size) b) FO1 resetting sequence: Apply ON signals to the following input pins : Br Un/Vn/Wn Up/Vp/Wp in that order.
Jan. 2000

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