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Preliminary 0
Features
CLK_REQ_OUT
SiW3500
ULTIMATEBLUE
ADDRESS BUS
* RF System on Chip (SoC) for Bluetooth wireless technology combining a 2.4 GHz transceiver, baseband processor, and protocol stack ROM. * Bluetooth specification V1.2 qualified including mandatory and optional functions such as AFH and eSCO. * Manufactured using standard 0.18-micron CMOS process technology. * UART based Host Control Interface (HCI) transport layer supports standard and 3-wire modes. * Direct conversion RF architecture improves receiver-blocking performance. * I/O voltage supply can range from 1.62 V to 3.63 V. * -85 dBm receiver sensitivity and +2 dBm transmitter power typical performance specifications. * Integrated analog and digital voltage regulators simplify system design. * 50 RF I/O does not need any additional external impedance matching components. * Flexible reference clock source options including crystal or direct input from the host platform. * Internal temperature compensated transmitter and receiver circuits deliver consistent performance from -40 to +85C. * On-chip ROM software storage with patch capability.
RF_I/O
PLL Control
Clock Distribution LNA
Voltage Regulators and Power Distribution
Optional flash interface
ADC 0 90 Internal 50-Ohm Match Network ADC PLL Synthesizer Power Control 0 90 DRIVER DAC Aux ADC DAC GFSK Modem Bluetooth Link Controller
ARM7TDMI(R) Processor
CS, OE and WE
UART Multi Function I/Os Audio CODEC Interface
CLK_REQ_IN XTAL_P/CLK
VBATT_ANA
CHG_PUMP
VBATT_DIG
Data SRAM
Firmware ROM
Block Diagram
Product Description
The UltimateBlue SiW3500TM is a RF System On Chip (SoC) that combines a 2.4 GHz transceiver, baseband processor, and protocol stack software for Bluetooth(R) wireless technology. Due to its low power CMOS process, the SiW3500 is ideally suited for applications such as mobile phones, audio headsets, and other embedded products. The SiW3500 integrates an ARM7TDMI processor for software execution from either internal ROM or external FLASH memory. The standard SiW3500 ROM contains the Bluetooth lower layer stack software including the HCI transport driver. The SiW3500 is packaged in a 6 x 6 Pb-Free 96-VFBGA that meets RoHS (Green) requirements. Known Good Die (KGD) is available for special applications.
Applications
* Mobile phones and smart phones. * Bluetooth audio headset. * Bluetooth hands-free kit.
Ordering Information
SiW3500 UltimateBlue
Optimum Technology Matching(R) Applied
Si BJT Si Bi-CMOS GaInP/HBT GaAs HBT SiGe HBT GaN HEMT GaAs MESFET Si CMOS SiGe Bi-CMOS
RF Micro Devices, Inc. 7628 Thorndike Road Greensboro, NC 27409, USA Tel (336) 664 1233 Fax (336) 664 0454 http://www.rfmd.com
60 0066 R00Hrf SiW3500 Radio Processor DS
November 8, 2004
DATA BUS
VCC_OUT
VBB_OUT
XTAL_N
VTUNE
VDD_P
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SiW3500
Radio Features
* * * * * *
Preliminary
RF System on Chip (SoC) for Bluetooth wireless technology combining a 2.4 GHz transceiver, baseband processor, and protocol stack ROM. Bluetooth specification V1.2 qualified including mandatory and optional functions such as AFH and eSCO. Manufactured using standard 0.18 m CMOS process technology. UART based Host Control Interface (HCI) transport layer supports standard and 3-wire modes. Direct conversion RF architecture improves receiver-blocking performance. I/O voltage supply can range from 1.62 V to 3.63 V.
* -85 dBm receiver sensitivity and +2 dBm transmitter power typical performance specifications. * * * * * * * * Integrated analog and digital voltage regulators simplify system design. 50 RF I/O does not need any additional external impedance matching components. Flexible reference clock source options including crystal or direct input from the host platform. Internal temperature compensated transmitter and receiver circuits deliver consistent performance from -40 to +85C. On-chip ROM software storage with patch capability. Hardware based GFSK MODEM and packet processing contributes to lower system current consumption with minimal software overhead. ARM7TDMI processor efficiently executes all protocol stack and application software. Software execution from either internal ROM or external FLASH memory. The SiW3500 features a ROM patch mechanism that allows substituting small portions of ROM code with code either downloaded from the host or stored in external EEPROM. Extensive multi function I/Os allow flexible product configurations. Auxiliary analog-to-digital converter (ADC) is available for applications such as battery level detection. Full-featured lower layer Bluetooth protocol stack software up to the host interface (HCI).
Baseband Features
* * *
Standard Protocol Stack Features
* Bluetooth 1.2 qualified including mandatory and optional features such as AFH, extended SCO, faster connections, and LMP improvements. * Full Bluetooth connection capabilities with support for piconet and scatternet modes and device scanning during SCO connection. * Able to establish up to 3 SCO connections simultaneously. * * * Supports low power connection states such as hold, sniff, and park modes with selectable sniff intervals. Full support of Bluetooth test modes for use during production. Verified HCI command level compatibility with multiple upper layer stack software.
Additional Protocol Stack Features
* Proprietary channel assessment algorithm provides fast and accurate determination of occupied channel for use in AFH mode. * In addition to AFH, UltimateBlue Coexistence Technology is part of the baseline protocol stack. UltimateBlue coexistence minimizes interference to 802.11b/g products.
* The Channel Quality Driven Data Rate (CQDDR) feature optimizes data transfer in noisy or weak signal environments. * Full selection of upper layer protocol stack software and profiles available for license and customization.
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60 0066 R00Hrf SiW3500 Radio Processor DS
Preliminary
SiW3500
ROM Features SiW3500
HCI
SiW3500
Headset
Protocol Stack
Lower stack up to HCI UltimateBlue Coexistence Upper Stack (L2CAP, SDP, RFCOMM) Programming Interface (API)
[ [
- -
[ [ [ [ [ [
Profiles
Headset Profile (HSP) Hands Free Profile (HFP) - -
[ = Included in SiW3500 ROM External System Interfaces
Host HCI Transport (UART) The high speed UART interface provides the physical transport between the SiW3500 and the application host for the transfer of Bluetooth data compliant with the Bluetooth specification. The table below shows the supported configurations. The default baud rate is 115,200 bps and can be set depending on the product. SiW3500 Radio Processor HCI UART Parameters
Number of data bits Parity bit Stop bit Flow control Host flow-off response requirement from the SiW3500 SiW3500 IC flow-off response requirement from host Supported baud rates 8 No parity 1 stop bit RTS/CTS 8 bytes 2 bytes 9.6k, 19.2k, 38.4k, 57.6k, 115.2k, 230.4k, 460.8k, 500k, 921.6k, 1M, 1.5M, 2M
Required Host Setting
Host HCI Transport (3-Wire UART) To reduce the number of signals and to increase the reliability of the HCI UART interface, a 3-wire UART protocol is available in the SiW3500. The protocol is compliant with the Bluetooth specification H:5 transport and backwards compatible with the BCSP 3-wire UART protocol. Selection between H:4 UART, H:5 UART, and BCSP UART is done automatically by the SiW3500. SiW3500 Radio Processor HCI 3-Wire UART Parameters
Number of data bits Parity bit Stop bit Error detection Sleep modes 8 Even 1 stop bit SLIP and checksum Shallow and deep
Required Host Setting
Audio Codec Interface The SiW3500 supports direct interface to an external audio CODEC or PCM host device. The interface provides the following configurations: * * * * Standard PCM clock rates from 64 kHz to 2.048 MHz with multi-slot handshakes and synchronization. Supports either master or slave mode. Supports any PCM data size up to 16 bits. Compatible with Motorola SSI mode. 14-39
60 0066 R00Hrf SiW3500 Radio Processor DS
SiW3500
*
Preliminary
Configuration of the CODEC interface is done by the firmware during boot-up by reading non-volatile memory (NVM) parameters. Multi-function I/Os (MFPs) Up to 8 (eight) multi-function I/O ports are available in the SiW3500. The table below identifies the I/Os and their usage. Multi Function I/O Number
MFP[0] MFP[1] MFP[2] MFP[3] MFP[4] MFP[5] MFP[6] MFP[7]
Possible Usage Configuration
General purpose. CLOCK_REQ_IN, HOST_WAKEUP, General purpose. Address A[18], SYNC_CLOCK, AUX_RTS, General purpose. FREQ_SEL[3], SYNC_DATA, General purpose. FREQ_SEL[1], General purpose. FREQ_SEL[2], General purpose. AUX_RXD, General purpose. AUX_CTS, TX_RX_SWITCH, General purpose.
External Memory Interface The SiW3500 does not require additional memory for standard below HCI protocol functions. An external memory interface is available for execution of protocol stack software from FLASH memory if desired. If external FLASH memory will be used, the read access time of the device must be 100 ns or less. Auxiliary UART The SiW3500 can be configured and enabled with an auxiliary UART port. This UART port can be used for debug depending on the application software. Signal
AUX_TXD AUX_RXD AUX_CTS AUX_RTS TX Data RX Data Clear To Send Request To Send
Description
External Power Amplifier Interface The SiW3500 supports the use of an external power amplifier for +20 dBm designs. When enabled, these signals provide an integrated interface for the control of an external PA. Signal
IDAC TX_RX_SWITCH
Description
Power control to external PA. This output provides a variable current source that can be used to control the external PA. Leave unconnected if not used Output signal used to indicate the state of the radio. This could be used as a direction control for the PA. The polarity is programmable with the default set as: Low = Transmit; High = Receive.
Power Management The HOST_WAKEUP and EXT_WAKE signals are used for power management control of the SiW3500. HOST_WAKEUP is an output signal used to indicate Bluetooth activity to the host. EXT_WAKE is an input signal used by the host to wake up the SiW3500 from sleep mode. For control of the reference clock source, CLOCK_REQ_IN and CLOCK_REQ_OUT can be made available to turn on/off an external reference clock source. General-Purpose Analog to Digital Converter (ADC) The SiW3500 incorporates a general-purpose ADC that can be enabled to sample external analog voltage. The ADC has an 8-bit resolution. External EEPROM Controller and Interface This interface is intended for communication to an optional EEPROM when using the SiW3500 in ROM mode. The 14-40 60 0066 R00Hrf SiW3500 Radio Processor DS
Preliminary
SiW3500
EEPROM is not required for configurations with external flash. The EEPROM is the non-volatile memory (NVM) in the system and contains the system configuration parameters such as the Bluetooth device address, the CODEC type, as well as other parameters. These default parameters are set at the factory, and some parameters will change depending on the system configuration. Optionally, the memory parameters can be downloaded from the host processor at boot up eliminating the need for EEPROM. Please consult the Application Support team for details. The EEPROMs should have a serial I2C interface with a minimum size of 2 Kbits and 16-byte page write buffer capabilities.
General System Requirements
System Reference Clock The SiW3500 chip can use either an external crystal or a reference clock as the system clock input. A partial list of supported frequencies (in MHz) includes: 9.6, 12, 12.8, 13, 14.4, 15.36, 16, 16.8, 19.2, 19.68, 19.8, 26, 32, 38.4, and 48. For other frequencies, please contact Applications Support. The system reference crystal/clock must have an accuracy of 20 PPM or better to meet the Bluetooth specification. Low Power Clock For the Bluetooth low power clock, a 32.768 kHz crystal can be used to drive the SiW3500 oscillator circuit, or alternatively, a 32.768 kHz reference clock signal can be used instead of a crystal. If the lowest power consumption is not required during low-power modes such as sniff, hold, park, and idle modes, the 32.768 kHz crystal may be omitted in the design. If the 32.768 kHz clock source is used, the clock source should be connected to the CLK32_IN pin and must meet the following requirements: * For AC-coupled via 100 pF or greater (peak-to-peak voltage): 400 mVP-P < CLK32_IN < VDD_C For DC-coupled: CLK32_IN minimum peak voltage < VIL CLK32_IN maximum peak voltage > VIH Where VIL = 0.3 * VDD_C Where VIH = 0.7 * VDD_C For both cases, the signal is not to exceed: -0.3 V < CLK32_IN < VDD_C + 0.3 V
*
*
Power Supply Description The SiW3500 operates at 1.8 V core voltage for internal analog and digital circuits. The chip has internal analog and digital voltage regulators simplifying power supply requirements to the chip. The internal voltage regulators can be supplied directly from a battery or from other system voltage sources. Optionally, the internal regulators can be bypassed if 1.8 V regulated source is available on the system. Function
Regulator input pin Regulator output pin
Internal Analog Regulator
VBATT_ANA = 2.3 to 3.63 V VCC_OUT = 1.8 V
Internal Digital Regulator
VBATT_DIG = 2.3 to 3.63 V VDD_C = 1.8 V
Internal Regulator Used Function
Circuit voltage supply pin
Analog Core Circuits
VCC = 1.8 V
Digital Core Circuits
VDD_C = 1.8 V
Internal Regulator Bypassed
Note: Both regulators can be bypassed if external regulation is desired. When bypassing the analog regulator, the VBATT_ANA and VCC_OUT pins must be tied together and the external analog voltage (1.8 V) should be applied to the VBATT_ANA pin. When bypassing the digital regulator, the VBATT_DIG pin should be left unconnected and the external digital voltage (1.8 V) should be applied to VBB_OUT pin.
The power for the I/Os is taken from two separate sources (VDD_P and VDD_P_ALT). They can range from 1.62 to 3.63 60 0066 R00Hrf SiW3500 Radio Processor DS 14-41
SiW3500
Preliminary
Volts to maintain compatibility with a wide range of peripheral devices. Please check the pin list for the exact pins that are powered from the VDD_P and VDD_P_ALT sources. RF I/O Description The SiW3500 employs single-ended RF input and output pins for reduced external components. In typical Class 2 (0 dBm nominal) applications, no external matching components are necessary.
On-Chip Memory
The SiW3500 Radio Processor integrates both SRAM and ROM. The ROM is pre-programmed with Bluetooth protocol stack software (HCI software) and boot code that executes automatically upon reset. The boot code serves to control the boot sequence as well as to direct the execution to the appropriate memory for continued operation.
Configuration Selection
Reference Frequency Selection The SiW3500 is designed to operate with multiple reference frequencies. During boot, specific frequency select I/O pins are sampled to determine the default reference frequency. The reference frequency setting will be set according to the following table: FREQ_SEL3 (MFP[3])
0 0 0 0 0 0 0 0 1 1 1 1 1 0 0 0 0 1 1 1 1 0 1 1 1 1
FREQ_SEL2 (MFP[5])
0 0 1 1 0 0 1 1 X 0 0 1 1
FREQ_SEL1 (MFP[4])
0 1 0 1 0 1 0 1 X 0 1 0 1
FREQ_SEL0 (ADC_IN)
Frequency
15.36 MHz 19.2 MHz 19.44 MHz 19.68 MHz 19.8 MHz 26 MHz 38.4 MHz Do not program frequency (leave as ref/2 and set according to system parameters). 32 MHz 32 MHz 12 MHz 13 MHz 14.4 MHz
Application Software Memory Selection The SiW3500 can support application (protocol stack) software execution from internal ROM or external FLASH memory. To run from internal ROM, pins D[9] and D[10] must be connected together as shown in the application circuit section of this document (Application Circuit). To run from external flash memory, the flash must be connected as shown in the application circuit diagram and contain valid application code. If the external memory does not have valid program data, the device enters a download mode in which a valid program may be loaded into the external memory through a sequence of commands over the HCI transport layer.
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60 0066 R00Hrf SiW3500 Radio Processor DS
Preliminary
Pin Description
SiW3500
The following table provides detailed listings of pin descriptions arranged by functional groupings. Name Radio (Power from VCC)
RF_IO TX_BIAS VTUNE CHG_PUMP XTAL_N XTAL_P/CLK IDAC ADC_IN VREFN_CAP VREFP_CAP Analog Analog Analog Analog Analog Analog Analog Analog Analog Analog A2 A4 A6 F1 B7 A7 B1 J2 C2 C1 RF signal. Input and output. Internal transmitter driver bias. Pin for reference PLL loop filter, only used if reference frequency is not integer multiples of 4 MHz. Pin for RF loop filter. System clock crystal negative input. If a reference clock is used, this pin should be left unconnected. System clock crystal positive input or reference clock input. Power control to external power amplifier. This output provides a variable current source that can be used to control the external power amp. Leave unconnected if not used. Analog to digital converter input or FREQ_SEL_(0). Decoupling capacitor for internal A/D converter voltage reference. Decoupling capacitor for internal A/D converter voltage reference.
Pad Type
Ball
Description
Low Power Oscillator and Reset (Power from VDD_P_ALT)
CLK32K_IN CLK32K_OUT RESET_N Analog Analog CMOS input L1 K1 G1 For crystal or external clock input (32.768 kHz). Drive for crystal. System level reset (active low).
Power Control Interface (Power from VDD_P)
PWR_REG_EN AUX_TXD CMOS bi-directional CMOS bi-directional G2 G9 CLOCK_REQ_OUT control line for external TCXO by default, or can be used as enable for an external voltage regulator. Programmable active high or active low. Auxiliary UART serial port output.
Multi-function (MFP) I/O (Power from VDD_P)
MFP [0] MFP [1] MFP [2] MFP [3] MFP [4] MFP [5] MFP [6] MFP [7] CMOS bi-directional CMOS bi-directional CMOS bi-directional CMOS bi-directional CMOS bi-directional CMOS bi-directional CMOS bi-directional CMOS bi-directional F3 J1 L6 F10 B9 C8 C7 C6 Multi-function I/O port. Multi-function I/O port. Multi-function I/O port. Multi-function I/O port. Multi-function I/O port. Multi-function I/O port. Multi-function I/O port. Multi-function I/O port.
PCM Interface (Power from VDD_P_ALT)
PCM_IN PCM_OUT PCM_CLK PCM_SYNC CMOS bi-directional CMOS bi-directional CMOS bi-directional CMOS bi-directional H3 L2 K3 K2 PCM data output from SiW3500. PCM data input to SiW3500. PCM synchronous data clock to the remote device. Normally an output. Input for slave mode. PCM synchronization data strobe to the remote device. Normally an output. Input for slave mode.
Table 1. SiW3500 Radio Processor Pin List
60 0066 R00Hrf SiW3500 Radio Processor DS
14-43
SiW3500
Name
UART_RXD UART_TXD UART_CTS UART_RTS EXT_WAKE
Preliminary
Pad Type Ball
G3 L4 H2 H1 C5 UART receive data. UART transmit data. UART flow control clear to send. UART flow control ready to send. Wake up signal from host.
Description
UART Interface (Power from VDD_P_ALT)
CMOS input CMOS output CMOS input CMOS output CMOS input
External Memory Interface (power from VDD_P)
A[17] A[16] A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1] D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8] D[7] D[6] D[5] D[4] D[3] D[2] D[1] D[0] OE_N WE_N/EEPROM_WP FCS_N E11 J11 L5 F11 B8 K6 L7 A10 H11 A11 B11 K9 K7 C10 K10 D10 L11 A9 C9 B10 E10 K5 G11 G10 H9 K4 J9 K8 J6 J5 F9 J4 H10 L10 A8 J10
Address lines. Note: A[17] and A[16] can be used to support an optional external serial EEPROM when using the internal ROM in place of the external Flash memory.
CMOS output
Data lines.
CMOS bi-directional
Note: Connect D[9] to D[10] to use internal ROM.
CMOS output CMOS output CMOS output
Output enable for external memory (active low). Write enable for external memory (active low). Chip select for external memory (active low).
Power and Ground
VBATT_ANA VBATT_DIG VCC_OUT VDD_P VDD_C Power Power Power Power Power D3 L9 D1 D11 K11 C11 L8 Positive supply to internal analog voltage regulator. Positive supply to internal digital voltage regulator. Regulated output from internal analog voltage regulator. Positive supply for external memory interface and some digital I/Os. Positive supply for digital circuitry or output of internal digital voltage.
Table 1. SiW3500 Radio Processor Pin List (Continued)
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60 0066 R00Hrf SiW3500 Radio Processor DS
Preliminary
Name Pad Type Ball
A1 B6 C4 E1 E3 J8 E9 L3 J3 A3 A5 B2 B3 B4 B5 C3 D2 E2 F2 D9 J7
SiW3500
Description
VCC
Power
Positive supply for RF and analog circuitry.
VSS_P VDD_P_ALT VSS_P_ALT
GND Power Ground
Ground connections for VDD_P. Positive supply for UART, CODEC, and other digital I/Os. Ground connection for VDD_P_ALT.
GND
GND
Ground connections for RF and analog circuitry.
Table 1. SiW3500 Radio Processor Pin List (Continued)
60 0066 R00Hrf SiW3500 Radio Processor DS
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SiW3500
System Specifications Absolute Maximum Ratings
Parameter
VDD_C VCC VDD_P, VDD_P_ALT VBATT_ANA VBATT_DIG TST RFMAX
Preliminary
Description
Digital circuit supply voltage Analog circuit supply voltage I/O supply voltage Analog regulator supply voltage Digital regulator supply voltage Storage temperature Maximum RF input level
Min
-0.3 -0.3 -0.3 -0.3 -0.3 -55 -
Max
3.63 3.63 3.63 3.63 3.63 +125 +5
Unit
V V V V V C dBm
Note: Absolute maximum ratings indicate limits beyond which the useful life of the device may be impaired or damage may occur.
Recommended Operating Conditions
Parameter
TOP TEOP VBATT_ANA VBATT_DIG VCC VDD_C VDD_P , VDD_P_ALT
Description
Operating temperature (industrial grade) Extended operating Unregulated supply voltage into internal analog regulator Unregulated supply voltage into internal digital regulator Regulated supply voltage directly into analog circuits Regulated supply voltage directly into digital circuits Digital interface I/O supply voltage temperature1
Min
-40 -40 2.3 2.3 1.71 1.62 1.62
Max
+85 +105 3.63 3.63 1.89 1.98 3.63
Unit
C C V V V V V
1.The extended operating temperature range applies to special order devices qualified for extended operating range. Please contact factory for details.
ESD Rating
Symbol
ESD ESD protection - all pins
Description
Rating
2000 V
Note: This device is a high performance RF integrated circuit with an ESD rating of 2,000 volts (HBM conditions per Mil-Std-883, Method 3015). Handling and assembly of this device should only be done using appropriate ESD controlled processes.
Electrical Characteristics
Symbol
VIL VIH VOL VOH IOH IOL IILI Input low voltage Input high voltage Output low voltage Output high voltage Output high current Output low current Input leakage current
DC Specification (TOP =+25C, VDD_P =3.0V) Description Min.
GND-0.1 0.7 VDD_P GND 0.8
.V DD_P .
Typ
- - - - 1 1 1
Max.
0.3 . VDD_P VDD_P 0.2 . VDD_P VDD_P - - -
Unit
V V V V mA mA A
- - -
AC Characteristics (TOP =+25C, VDD_P =3.0V, CLOAD =15pF) Symbol Description
tr tf Rise time Fall time
Typ
5 5
Max.
11 8
Unit
ns ns
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60 0066 R00Hrf SiW3500 Radio Processor DS
Preliminary
Current Consumption (TOP =+25C, VBATT =3.0V using internal regulators) Operating Mode Average
Standby Continuous transmit* Continuous receive* Parked slave, 1.28 sec. interval Inquiry scan, 1.28 sec interval Page scan, 1.28 sec. interval ACL connection, sniff mode, 40 ms interval ACL data transfer 723 kbps TX, 57 kbps RX SCO connection, HV3 packets 40 48 54 90 440 560 1.3 42 22
SiW3500
Max
80 55 60 - - - - - -
Unit
A mA mA A A A mA mA mA
*Note: Continuous transmit and receive currents are measured in operating modes where there is no activity in baseband digital circuits.
Digital Regulator Specification (TOP = 25C) Parameter
Output voltage Line regulation Load regulation Dropout voltage Output maximum current Quiescent current Ripple rejection (I OUT = 10 mA) (I OUT = 0 mA, VBATT_DIG = 2.3 V to 3.63 V) (I OUT = 3 mA to 80 mA) (I OUT = 10 mA) Maximum supplied current while maintaining regulation Off current f RIPPLE = 400 Hz
Description
Min
1.62 - - - - - -
Typ
1.80 8.0 9.0 - - 10 40
Max
1.98 - - 250 80 - -
Unit
V mV mV mV mA A dB
Radio Specification Parameter
VCO Operating Range PLL lock time Frequency Average tune time
Description
Min
2402 -
Typ
- 60
Max
2480 100
Unit
MHz s
Receiver Specification1 (VBATT =3.3V, VCC =internal analog regulator output, TOP = 25C)
Parameter
Receiver sensitivity Maximum usable signal C/I co-channel (0.1% BER) C/I 1 MHz (0.1% BER) C/I 2 MHz (0.1% BER) C/I 3 MHz (0.1% BER) BER < 0.1% BER < 0.1% Co-channel selectivity Adjacent channel selectivity 2nd adjacent channel selectivity 3rd adjacent channel selectivity Fc/3 Fc/2 Out-of-band blocking2 2 * Fc/3 30 MHz - 2000 MHz 2000 MHz - 2399 MHz 2498 MHz - 3000 MHz 3000 MHz - 12.75 GHz
Description
Min
- -10 - - - - -23 -25 -45 -10 -27 -27 -10
Typ
-85 0 +8.0 -4.0 -38.0 -43.0 - - - - - - -
Max
-78 - +10.0 -3.0 -35.0 -40.0 - - - - - - -
Unit
dBm dBm dB dB dB dB dBm dBm dBm dBm dBm dBm dBm
60 0066 R00Hrf SiW3500 Radio Processor DS
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SiW3500
Parameter
Intermodulation Receiver spurious emission
Preliminary
Description Min
-39 - -
Typ
-36 - -
Max
- -57 -47
Unit
dBm dBm dBm
Max interferer level to maintain 0.1% BER, interference signals at 3 and 6 MHz offset. 30 MHz to 1 GHz 1 GHz to 12.75 GHz
1. Measured into the chip with 50 source and no bandpass filter. 2. Out-of-band blocking guaranteed by design.
Transmitter Specification1 (VBATT =3.3V, VCC =internal analog regulator output, TOP = 25C)
Parameter
Output RF transmit power Modulation Characteristics2 Initial carrier frequency accuracy Carrier frequency drift 20 dB occupied bandwidth In-band spurious emission - One slot packet Two slot packet Five slot packet Max drift rate Test per Bluetooth specification 2 MHz offset >3 MHz offset 30 MHz to 1 GHz, operating mode 30 MHz to 1 GHz, idle mode Out-of-band spurious emission 1 GHz to 12.75 GHz, operating mode 1 GHz to 12.75 GHz, idle mode 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz
Description
At maximum power output level f1avg f2max (For at least 99.9% of all f2max) f1avg/ f2avg
Min
-2 140 115 0.8 -75 -25 -40 -40 - - - - - - - - - -
Typ
+2 155 - - - - - - - - - - - - - - - -
Max
+5 175 - - +75 +25 +40 +40 20 1000 -40 -60 -55 -57 -50 -47 -62 -47
Unit
dBm kHz kHz kHz kHz kHz kHz kHz kHz/50 s kHz dBm dBm dBm dBm dBm dBm dBm dBm
1. Measured into the chip with 50 source and no bandpass filter. 2. Modulation characteristics as measured per test TRM/CA/07/C as defined in the Bluetooth test specification.
Industrial Temperature Performance1 (VBATT=2.3 - 3.63V, VCC =internal analog regulator output, TOP = -40 to +85C) Parameter
Receiver sensitivity Output RF transmit power Modulation Characteristics2 Initial carrier frequency accuracy - One slot packet Two slot packet Five slot packet Max drift rate Bluetooth specification 2 MHz offset >3 MHz offset BER<0.1% At maximum power output level f1avg f2max (For at least 99.9% of all f2max) f1avg/ f2avg
Description
Min
- -4 140 115 0.8 -75 -25 -40 -40 - - - -
Typ
-85 +2 155 - - - - - - - - - -
Max
-75 +6 175 - - +75 +25 +40 +40 20 1000 -40 -60
Unit
dBm dBm kHz kHz kHz kHz kHz kHz kHz kHz/50 s kHz dBm dBm
Carrier frequency drift
20 dB occupied bandwidth In-band spurious emission
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60 0066 R00Hrf SiW3500 Radio Processor DS
Preliminary
Parameter Description
30 MHz to 1GHz, operating mode 30 MHz to 1GHz, idle mode Out-of-band spurious emission 1 GHz to 12.75 GHz, operating mode 1 GHz to 12.75 GHz, idle mode 1.8 GHz to 1.9 GHz 5.15 GHz to 5.3 GHz
SiW3500
Min
- - - - - -
Typ
- - -70 - - -
Max
-55 -57 -50 -47 -62 -47
Unit
dBm dBm dBm dBm dBm dBm
1. Measured into the chip with 50 impedance and no bandpass filter. Industrial temperature performance guaranteed by design. 2. The modulation characteristic is measured as per test TRM/CA/07/C defined in the Bluetooth Test Specification.
Analog Voltage Supply Requirements The SiW3500 processor is designed for use with its own internal low noise analog voltage regulator. This configuration is recommended for all applications. When necessary, the internal analog regulator can be bypassed. In situations where bypassing the internal analog regulator is required, the supply voltage to the analog circuit must satisfy the following requirements to preserve the RF performance characteristics. Parameter
VCC Minimum load current Minimum ripple rejection Output noise External regulator current At 400Hz Integrated 10 Hz to 80 kHz noise
Description
Analog supply voltage to all VCC input pins
Min
1.71 80 40 -
Max
1.89 - - 22
Unit
V mA dB mV RMS
External Reference Requirements It is possible to provide a number of reference frequencies that are typical in most cellular phones directly into ball B7 (XTAL_P/CLK) of the device. Refer to "System Reference Clock" on page 41 for a list of supported reference frequencies. Parameter
100 Hz offset Phase noise 1 kHz offset 10 kHz offset AC amplitude Drive level DC levela
Description
Min
- - - 0.5 0.3
Max
-100 -120 -140 VCC VCC
Unit
dBc/Hz dBc/Hz dBc/Hz VP-P V
a.If DC-coupled, the external reference signal voltage must stay within this range at all times.
Reference Crystal Requirements Many reference frequencies are supported by the device. If a crystal is used as the reference frequency source, the typical required parameters are listed below: Parameter
Drive level ESR CO CL CM - Effective serial resistance Holder Load capacitance2 capacitance3
1
Description
Min
- - - - -
Typ
- - 3 12 6
Max
0.3 150 5 18 -
Unit
mW pF pF fF
Motional capacitance
1. For 32 MHz crystal. 2. If DC-coupled, the external reference signal voltage must stay within this range at all times. 3. The actual values for CO and CL are dependent on the crystal manufacturer and can be compensated for by an internal crystal calibration capability.
60 0066 R00Hrf SiW3500 Radio Processor DS
14-49
CHG_PUMP
VREFP_CAP
VREFN_CAP
XTAL_N
B7 Y1 DSX321SL 3 1
A3 A5 B2 B3 B4 B5 C3 D2 D9 E2 F2 J7 E9 J8 J3
GND GND GND GND GND GND GND GND GND GND GND GND
XTAL_P/CLK
A7
VSS_P VSS_P VSS_P_ALT
E11 J11 L5 F11 B8 K6 L7 A10 H11 A11 B11 K9 K7 C10 K10 D10 L11
VCC_OUT VCC VCC VCC VCC VCC
D1 A1 B6 C4 E1 E3
A[17]/EEPROM_SCL A[16]/EEPROM_SDA A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1]
VBATT
VBATT_ANA VBATT_DIG
D3 L9
(INTERNAL ROM CONFIGURATION)
Application Circuit Internal ROM Version
Connect D[9] to D[10] to select internal ROM mode.
A9 C9 B10 E10 K5 G11 G10 H9 K4 J9 K8 J6 J5 F9 J4 H10
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]/PIO[3] D[7]/PIO[7] D[6]/PIO[6] D[5]/PIO[5] D[4]/PIO[4] D[3] D[2] D[1] D[0]
VDD_C VDD_C
C11 L8
A8 J10 WE_N/EEPROM_WP L10 FCS_N OE_N
VDD_P VDD_P VDD_P_ALT
D11 K11 VDD_P L3
HOST INTERFACE
14-50
Antenna
C2 1uF C9 C7 8.2pF C8 180pF C3 1.5pF 22pF C10 0.1uF C2 F1 B1 A6 A2 A4 IDAC RF_IO VTUNE TX_BIAS R1 47K L1 2.2nH C4 18pF U1 C5 18pF
SiW3500
60 0066 R00Hrf SiW3500 Radio Processor DS
L2 18nH C11 0.1uF C1 PWR_REG_EN G2 ADC_IN J2 EXT_WAKE UART_RXD UART_TXD UART_CTS UART_RTS AUX_TXD G9 PCM_CLK PCM_SYNC PCM_IN PCM_OUT K3 K2 H3 L2 C5 G3 L4 H2 H1
SiW3500
CLK32K_IN CLK32K_OUT K1 MFP[0] MPF[1] MFP[2] MFP[3] MFP[4] MFP[5] MFP[6] MFP[7] F3 J1 L6 F10 B9 C8 C7 C6 L1
C6 1uF C1 0.1uF
RESET_N G1
Preliminary
A3 A5 B2 B3 B4 B5 C3 D2 D9 E2 F2 J7 E9 J8 J3
GND GND GND GND GND GND GND GND GND GND GND GND
VSS_P VSS_P VSS_P_ALT
H1 H6
GND GND
SiW3500
B3 C3 D3 C4 D4
NC NC NC NC NC
A17 A16 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0
B2 E6 D6 C6 A6 B6 D5 C5 A5 B5 A2 C2 D2 B1 A1 C1 D1 E1
E11 J11 L5 F11 B8 K6 L7 A10 H11 A11 B11 K9 K7 C10 K10 D10 L11
A[17]/EEPROM_SCL A[16]/EEPROM_SDA A[15] A[14] A[13] A[12] A[11] A[10] A[9] A[8] A[7] A[6] A[5] A[4] A[3] A[2] A[1]
DQ15 DQ14 DQ13 DQ12 DQ11 DQ10 DQ9 DQ8 DQ7 DQ6 DQ5 DQ4 DQ3 DQ2 DQ1 DQ0 WE CE OE
G6 F5 G5 F4 G3 F3 G2 F2 E5 H5 E4 H4 H3 E3 H2 E2 A4 F1 G1
A9 C9 B10 E10 K5 G11 G10 H9 K4 J9 K8 J6 J5 F9 J4 H10 A8 J10 L10
D[15] D[14] D[13] D[12] D[11] D[10] D[9] D[8]/PIO[3] D[7]/PIO[7] D[6]/PIO[6] D[5]/PIO[5] D[4]/PIO[4] D[3] D[2] D[1] D[0] WE_N/EEPROM_WP FCS_N OE_N
HOST INTERFACE
60 0066 R00Hrf SiW3500 Radio Processor DS
C2 1uF
Application Circuit External Flash Version
Preliminary
SiW3500
14-51
C9 L2 18nH C11 0.1uF C1 VREFN_CAP C10 0.1uF C2 VREFP_CAP F1 B1 IDAC A6 VTUNE 180pF R1 47K CHG_PUMP
Antenna
C7 8.2pF
C8 22pF L1 2.2nH A2 RF_IO A4 TX_BIAS XTAL_N
C3 1.5pF
C4 18pF
U1 B7
3
Y1 DSX321SL 1
MFP[2]
XTAL_P/CLK
A7
C5 18pF
Note: For 4M Flash, use MPF[2] for A17 pin
(EXTERNAL FLASH CONFIGURATION)
U2 RY/BY# VCC BYTE# RESET# 2M or 4M FLASH F6 A3 C12 0.1uF B4 G4
VCC_OUT VCC VCC VCC VCC VCC
D1 A1 B6 C4 E1 E3
VBATT
VBATT_ANA VBATT_DIG
D3 L9
VDD_C VDD_C
C11 L8
C6 1uF D11 K11 L3
VDD_P VDD_P VDD_P_ALT
VDD_P
PWR_REG_EN
CLK32K_OUT
VDD_P
C1 0.1uF
AUX_TXD
RESET_N
CLK32K_IN
EXT_WAKE
UART_RXD UART_TXD UART_CTS UART_RTS
PCM_CLK PCM_SYNC PCM_IN PCM_OUT K3 K2 H3 L2
ADC_IN J2
MFP[0] MPF[1] MFP[2] MFP[3] MFP[4] MFP[5] MFP[6] MFP[7]
L1
K1
C5
G2
G9
G3 L4 H2 H1
G1
F3 J1 L6 F10 B9 C8 C7 C6
SiW3500
VFBGA I/O Configuration (Top View)
1 A B C D E F G H J K L
VCC
Preliminary
2
RF_IO
3
GND
4
TX_ BIAS
5
GND
6
VTUNE
7
XTAL_ P/CLK
8
WE_N
9
D[15]
10
A[10]
11
A[8]
IDAC
GND
GND
GND
GND
VCC
XTAL_N
A[13]
MFP[4]
D[13]
A[7]
VREF P_CAP
VREF N_CAP
GND
VCC
EXT_ WAKE
MFP[7]
MFP[6]
MFP[5]
D[14]
A[4]
VDD_C
VCC_ OUT
GND
VBATT_ ANA
GND
A[2]
VDD_P
VCC
GND
VCC
VSS_P
D[12]
A[17]
CHG_ PUMP
GND
MFP[0]
D[2]
MFP[3]
A[14]
RESET_ N
PWR_ REG_ EN
UART_ RXD
AUX_ XTD
D[9]
D[10]
UART_ RTS
UART_ CTS
PCM_IN
D[8]
D[0]
A[9]
MFP[1]
ADC_IN
VSS_P_ ALT
D[1]
D[3]
D[4]
GND
VSS_P
D[6]
FCS_N
A[16]
CLK_ 32K_ OUT
PCM_ SYNC
PCM_ CLK
D[7]
D[11]
A[12]
A[5]
D[5]
A[6]
A[3]
VDD_P
CLK_ 32K_ IN
PCM_ OUT
VDD_ P_ALT
UART_ TXD
A[15]
MFP[2]
A[11]
VDD_C
VBATT_ DIG
OE_N
A[1]
1
2
3
4
5
6
7
8
9
10
11
14-52
60 0066 R00Hrf SiW3500 Radio Processor DS
Preliminary
Packaging and Product Marking
Package Drawing
SiW3500
Green package, 96-Pin, 6 mm x6 mm, VFBGA Drawing and Dimensions
Symbol A A1 A2 A3 b D E e D1 E1
Min 0.8 0.2
Max 1.0 0.3 0.22 REF 0.45 REF 0.25 0.35 6 BSC 6 BSC 0.5 BSC 5 BSC 5 BSC
Notes: 1. Dimension b is measured at the maximum solder ball diameter, parallel to datum plane Z.
2. Datum Z is defined by the spherical crowns of the solder balls. 3. Parallelism measurement shall exclude any effect of mark on top surface of package. 4. All dimensions are in millimeters. 5. VFBGA green package solder ball material: 95.5% Sn, 4% Ag, 0.5% Cu.
60 0066 R00Hrf SiW3500 Radio Processor DS
14-53
SiW3500
Product Marking
96-Pin, VFBGA Drawing
Pin 1 Corner
Preliminary
Pin 1 Bar
SIW
4 Digit Date Code
XXXXXXXX LLLLL YYWW ARM
Trace Code
Ordering Information
Part Number
SIW3500GIG1 SIW3500GIG1-T13 SiW3500DIF1 SiW3500DIF1-T13
1Industrial 2 For
Operational Temperature Range1
Industrial Industrial Industrial Industrial
Package
96-pin VFBGA, green package 96-pin VFBGA, green package Known good die green package
2,
Ordering Quantity
429 pcs. per tray 2500 on 13" reel Waffle pack 2,500 on 13" reel
Known good die2, green package
temperature range: -40C to +85C.
additional technical details about known good die, please refer to RF Micro Devices document 60 0071 SiW3500DIF Bumped Die Manufacturing Notes.
The information in this publication is believed to be accurate and reliable. However, no responsibility is assumed by RF Micro Devices for its use, nor for any infringement of patents, or other rights of third parties, resulting from its use. No license is granted by implication or otherwise under any patent or patent rights of RF Micro Devices, Inc. RF Micro Devices reserves the right to change component circuitry, recommended application circuitry and specifications at any time without prior notice. RF MICRO DEVICES(R), RFMD(R), Optimum Technology Matching(R), Enabling Wireless ConnectivityTM, UltimateBlueTM, and the SiW product name prefix are trademarks of RFMD, LLC. BLUETOOTH is a trademark owned by Bluetooth SIG, Inc., U.S.A. and licensed for use by RF Micro Devices, Inc. Manufactured under license from ARM Limited. ARM, ARM7TDMI and the ARM logo are the registered trademarks of ARM Limited in the EU and other countries. All other trade names, trademarks and registered trademarks are the property of their respective owners.
14-54 of 54
60 0066 R00Hrf SiW3500 Radio Processor DS

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