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SPL61A
80KB LCD Controller/Driver
AUG. 13, 2001 Version 1.2
SUNPLUS TECHNOLOGY CO. reserves the right to change this documentation without prior notice. Information provided by SUNPLUS TECHNOLOGY CO. is believed to be accurate and reliable. However, SUNPLUS TECHNOLOGY CO. makes no warranty for any errors which may appear in this document. Contact SUNPLUS TECHNOLOGY CO. to obtain the latest version of device specifications before placing your order. No responsibility is assumed by SUNPLUS TECHNOLOGY CO. for any infringement of patent or other rights of third parties which may result from its use. In addition, SUNPLUS products are not authorized for use as critical components in life support devices/ systems or aviation devices/systems, where a malfunction or failure of the product may reasonably be expected to result in significant injury to the user, without the express written approval of Sunplus.
SPL61A
Table of Contents
PAGE
1. GENERAL DESCRIPTION.......................................................................................................................................................................... 3 2. BLOCK DIAGRAM ...................................................................................................................................................................................... 3 3. FEATURES.................................................................................................................................................................................................. 3 4. SIGNAL DESCRIPTIONS ........................................................................................................................................................................... 4 5. FUNCTIONAL DESCRIPTIONS.................................................................................................................................................................. 5 5.1. ROM AREA ........................................................................................................................................................................................... 5 5.2. MAP OF MEMORY AND I/OS .................................................................................................................................................................... 5 5.3. OPERATING STATES ............................................................................................................................................................................... 5 5.4. SPEECH AND MELODY............................................................................................................................................................................ 5 5.5. LCD CONTROLLER/DRIVER.................................................................................................................................................................... 6 5.6. VOLTAGE DOUBLER/REGULATOR ............................................................................................................................................................ 6 5.7. PWM OUTPUT....................................................................................................................................................................................... 6 5.8. ASYNCHRONOUS SERIAL INTERFACE ...................................................................................................................................................... 6 5.9. LOW VOLTAGE DETECTION ..................................................................................................................................................................... 6 5.10. WATCH DOG TIMER (WDT) ................................................................................................................................................................. 7 5.11. MASK OPTIONS................................................................................................................................................................................... 7 6. ELECTRICAL SPECIFICATIONS ............................................................................................................................................................... 8 6.1. ABSOLUTE MAXIMUM RATINGS ............................................................................................................................................................... 8 6.2. DC CHARACTERISTICS........................................................................................................................................................................... 8 7. APPLICATION CIRCUITS........................................................................................................................................................................... 9 7.1. 640 POINTS LCD DRIVER, 40 SEGMENTS X 16 COMMONS, 32768 MASK OPTION X'TAL ........................................................................ 9 7.2. 640 POINTS LCD DRIVER, 40 SEGMENTS X 16 COMMONS, 32768 MASK OPTION R-OSCILLATOR ......................................................... 10 7.3. SERIAL COMMUNICATIONS BETWEEN TWO SPL61AS..............................................................................................................................11 8. PACKAGE/PAD LOCATIONS ................................................................................................................................................................... 12 8.1. PAD ASSIGNMENT ............................................................................................................................................................................... 12 8.2. ORDERING INFORMATION ..................................................................................................................................................................... 12 8.3. PAD LOCATIONS.................................................................................................................................................................................. 13 9. DISCLAIMER............................................................................................................................................................................................. 14 10. REVISION HISTORY ................................................................................................................................................................................. 15
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AUG. 13, 2001 Version: 1.2
SPL61A
80KB LCD CONTROLLER/DRIVER
1. GENERAL DESCRIPTION
The SPL61A, an 8-bit CMOS single chip microprocessor, contains RAM, ROM, I/Os, interrupt/wakeup controller, 8-bit PWM audio output, UART and automatic display controller/driver for LCD. With a dual channel PWM driver, attractive sound effects can be generated easily. between two chips. A built-in UART speeds up data transmission Furthermore, a software controllable standby The great
3. FEATURES
! Built-in 8-bit processor 496 bytes SRAM 80K bytes ROM Max. operating speed: 3.0MHz @ 2.6V CPU clock is software programmable, can be 1/2, 1/4, 1/8 or 1/16 of R-oscillator's clock frequency Key wake-up Provide 8 interrupt sources ! Asynchronous serial interface Supports bit rates up to 115.2 Kbps ! Programmable LCD driver Up to 40 segments, up to 16 commons, maximum 640 dots 1/4 or 1/5 bias capability 1/8, 1/12 or 1/6 duty 80 bytes dedicated LCD RAM LCD com/seg driving strength can be adjusted to
switch is also built-in to save power consumption.
amount of ROM can be used to store both program and audio data. (The speech duration is approximately 18 seconds at 7KHz sampling rate by using 4-bit ADPCM). The SPL61A is designed with state-of-the-art technology to fulfill the requirements of LCD applications especially hand-held products.
2. BLOCK DIAGRAM
ROSC X32I X32O
compromise the display quality and current consumption Built-in voltage doubler and voltage regulator to generate
8 I/O P O R T
4 4
OSC GEN
8-BIT PROCESSOR
TIME BASE & INTERRUPT LOGIC
Watchdog Timer
IOCD3 - 0(I/O)
VLCD for LCD driver 16-level VLCD adjustable (3.3V - 4.8V) ! Power saving SLEEP mode ! Low voltage detector 2.6V and 2.4V detection ! Peripherals 8 I/O pins (IOEF3 - 0, IOCD3 - 0) 4 I/O pins shared with LCD segments (mask option) Extra 2 I/O pins (IOEF5 - 4) when UART is not used (mask option) Extra 2 I/O pins (IOEF7 - 6) when LCD is in 1/8 or 1/12 duty (mask option) Built-in 32.768KHz oscillator circuit for real time clock function Built-in R-oscillator (only one resistor is needed) Internal time base generator Two 16-bit reloadable timer/counters 8-bit resolution, 2-channel PWM outputs (can drive speaker or buzzer directly) Watchdog Timer for reliable operation ! Wide operating voltage: 2.4V - 3.6V @ 1.0MHz 3.6V - 5.5V @ 1.0MHz ! Low-power consumption: 1mA typical @ 3.0V, FCPU = 1.0MHz <1A typical standby current @ 3.0V
IOEF3 - 0(I/O)
80K BYTES ROM
496 BYTES SRAM
TWO 16 BITS AUTO RELOAD TIMERS
AUDP
P W M
AUDN
VOLTAGE DETECTOR
U A R T
80 BYTE LCD RAM
TxD/IOEF4
RxD/IOEF5
REGULATOR
DOUBLER
40 SEGMENTS x 16 COMMONS LCD DRIVER
40
16
SEG39 - 0
COM15 - 0
Note1: IOAB3 - 0 can be enabled by mask option from Segment 39 - 36. Each I/O(segment) can be mask optioned individually. Note2: TxD and RxD can be optioned to IOEF5 - 4 when UART is not used.
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SPL61A
4. SIGNAL DESCRIPTIONS
Mnemonic SEG39 - 37 SEG36 SEG35 - 0 COM15 - 14 COM13 - 0 IOEF3 - 0 IOCD3 - 0 RxD TxD ROSC RESET AUDP AUDN X32I X32O TEST VLCD HVLCD CUP1 CUP2 VDD VSS AVDD AVSS PIN No. 79 - 81 1 7 - 42 67 - 68 56 - 43 71 - 74 75 - 78 69 70 66 60 2 4 63 62 61 64 59 58 57 65 6 3 5 P P P P Power supply voltage input Ground reference Analog power Analog ground reference I O I P P P 32.768KHz crystal input or connect to VDD through a resistor (option) 32.768KHz crystal output Test input LCD voltage. enabled. LCD voltage generation. Charge pump capacitor interconnection pins Connect to VSS through a capacitor if voltage doubler is enabled. Connect to VSS through a capacitor if voltage regulator is I/O I/O I O I I O O LCD driver common output. IOEF7 - 6. COM15 - 14 can be optioned to Port EF is a bi-directional I/O port. Type O LCD driver segment output. IOAB3 - 0. Description SEG39 - 36 can be optioned to
Port AB is a bi-directional I/O port.
Port EF is a bi-directional I/O port, can be software programmed as wake up I/O. Port CD is a bi-directional I/O port. UART input. UART output. Can be optioned to IOEF5 Can be optioned to IOEF4
ROSC input, connect to VDD through a resistor System reset input, low active. PWM audio output
LCD voltage generation.
Legend: I = Input, O = Output, P = Power
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SPL61A
5. FUNCTIONAL DESCRIPTIONS
5.1. ROM Area
SPL61A is a large ROM based micro-controller with 640 dots LCD driver. The large ROM can be defined as program ROM, LCD To fonts and audio data continuously without any limitation. In operating state, all modules (CPU, 32768 oscillator, There are If timer/counter, LCD driver...) are activated. The halt/standby
state is entered by writing to SLEEP register ($09).
access the ROM area, users should first program the BANK SELECT Register ($07) and then access the bank#1 or bank#2 by addressing the higher bank address, data. $8000 - $FFFF, to fetch
four wake-up sources in SPL61A: port IOEF wake-up, TIMR0 wake-up, 4Hz/8Hz/16Hz/32Hz wake-up and 2Hz/1Hz wake-up. continues in the operating state. When in standby, all modules will be shut down, and RAM and I/Os remain in their previous states. The current consumption is In halt state, minimized in standby. By writing to SLEEP register but keeps any wake-up event occurs, execution of the next instruction
5.2. Map of Memory and I/Os
*I/O PORT: PORT IOAB $0002 PORT IOCD $0003 PORT IOEF $0004 I/O AB_CTRL $0001 I/O CD_CTRL $0000 I/O EF_CTRL $0006 *NMI SOURCE: INT1 ( from TIMER 1 ) *INT SOURCE: INT0 ( from TIMER 0 ) INT1 ( from TIMER 1 ) 2 KHz T2 Hz ( 2Hz / 1 Hz) T16 Hz ( 4Hz/8Hz/16Hz/32Hz ) 128 Hz EXT INT ( from IOCD0 pin ) UART $13FFF $14000 $17FFF $07FFF $08000 $0FFFF $10000 $0003F $00040 $000FF $00100 $0022F $00300 $0037F $00400 $007FF $00800 * MEMORY MAP $00000 H/W registers , I/Os WORKING SRAM(192 bytes) SRAM for STACK and Data Storage (304bytes) LCD Buffer ( 80 bytes) SUNPLUS TEST PROGRAM
32768 oscillator running, the system is in halt state. overflow) to generate a wake-up.
CPU clock is halted while it waits for an event (key press, timer The 32768 related modules (timer/counter, LCD driver...) may remain active in the halt state. Following figure is a state diagram for the SPL61A.
Write to SLEEP register, 32768 oscillator OFF OPERATING STANDBY Wake-up or user reset
, te r gis re N P rO EE ato SL cill to os rite 68 W 327 et es
USER's PROGRAM DATA AREA ROM BANK
u eak W
ROM BANK #1
po ru
rr se
UNUSED
HALT
ROM BANK #2
State Diagram of SPL61A Note: $7FFA - $7FFF in ROM bank#0, and $FFFA - $FFFF in bank#1 - 2 are reserved for reset vectors. $7FF2 - $7FF7 in bank#0, and $FFF2 - $FFF7 in bank#1 - 2 are reserved for testing.
5.4. Speech and Melody
Since SPL61A provides large ROM and wide range of CPU operating speed, it is the most appropriate IC for speech and melody synthesis. For speech synthesis, SPL61A provides Users several timer interrupts for precise sampling frequency.
5.3. Operating States
The SPL61A supports three operating states: standby, halt, and operating. Following table shows the differences between the three operating states.
can record or synthesize the sound and digitize it into the ROM. The sound then can be played back in the sequence assigned by users' programs. Several algorithms are recommended for high fidelity and good compression of sound: such as PCM and
Operating CPU 32768 oscillator LCD driver ON ON ON
Halt OFF ON ON/OFF
Standby OFF OFF OFF
ADPCM. For melody synthesis, SPL61A provides the dual tone mode. Once in the dual tone mode, users only need to program the tone frequency of each channel by writing to timer/counter TM0 and TM1, and set the envelope of each channel. The hardware will toggle the tone wave automatically without users' care.
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SPL61A
5.5. LCD Controller/Driver
SPL61A contains total of 640 dots LCD controller and driver. Programmers can set the LCD configuration (bias, duty, voltage doubler) by writing to LCD control register ($20). filling the LCD buffer with appropriate data. Once the LCD configuration is initialized, the desired pattern can be displayed by The LCD driver can also operate during sleep by keeping 32768 oscillator running. The LCD driver in SPL61A is designed to fit most LCD specifications. It can either be programmed as 1/4 or 1/5 bias Baud Rate(bps) 1200 2400 4800 9600 19200 38400 51200 57600 102400 115200 Min. Frosc(Hz) 24000 48000 96000 192000 384000 768000 1024000 1152000 2048000 2304000 and the duty is also programmable as 1/8, 1/12, or 1/16 duty. The UART supports clock auto calibration. 115.2kbps are available. If this clocking
scheme is selected, standard baud rates from 1.2kbps to The baud rate is selected by writing to The supported standard baud rate control registers $2E and $2F. required are shown in the following table.
baud rates and their minimum R-oscillator clock frequency
5.6. Voltage Doubler/Regulator
SPL61A also contains a built-in voltage doubler and a voltage regulator. (HVLCD) The voltage regulator provides a reference voltage for voltage doubler to generate VLCD (by Users can get desired VLCD by changing the
charge-pumping).
output reference voltage (writing to $23) of the voltage regulator. By enabling the voltage doubler and regulator, users can get a stable VLCD that will not be affected by VDD. in the following table. The three possible configurations of voltage doubler and regulator are shown
If the auto calibration clocking scheme is not selected, users can Doubler OFF ON OFF ON VLCD VDD (not regulated) 2*VDD (not regulated) N/A 3.3V - 4.8V adjustable get desired baud rates by writing appropriate values to prescaler registers, $2C and $2D. obtained this way. Non-standard baud rates can be When using non-calibration mode, one should
Regulator OFF OFF ON ON
aware that the frequency of R-oscillator may alter due to manufacturing process variations, supply voltage, operating temperature and tolerance of external R components used.
5.7. PWM Output
Internally, SPL61A has one pair of PWM outputs with two sound channels. individually. circuit. Each channel can be set to play speech or tone SPL61A uses Pulse Width Modulation that could
5.9. Low Voltage Detection
The SPL61A provides a 2.6V/2.4V voltage detector to detect a low voltage event. Users can turn on 2.6V detection and read bit1 of In port $24 periodically to monitor if VDD is lower than 2.6V.
directly drive speaker or buzzer without any buffer or amplification
addition, if 2.4V detection is turned on and VDD drops below 2.4V, after a SLEEP command is issued, system will shut down all activities(LCD bias, LCD display, 32768 oscillator) and enters standby to reduce current consumption. This low voltage power Users
5.8. Asynchronous Serial Interface
SPL61A supports 1-channel UART for serial communications. supports bit rates up to 115.2kbps. It UART operation is controlled
down can be awakened by a PEF0 key change or RESET. change function.
can use this feature to implement low battery check/battery
by UART command registers $29 and $2A. Configurations such as Tx/Rx interrupt, parity check, parity even/odd and clock source can be set in command registers. by Rx and Tx. received or transmitted. Two interrupts are generated
VDD < 2.4V and SLEEP OPERATING STANDBY
The Rx or Tx interrupt asserts when a byte is By reading the status register $2A,
users can tell whether the interrupt is generated by Rx or Tx. Framing, overrun and parity errors are detected as each byte is received. All error status can be read from status register $2A.
Port EF0 Key wake-up or user reset
State Diagram of Low Voltage Power Down
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SPL61A
5.10. Watch Dog Timer (WDT)
An on chip watchdog timer is available on SPL61A. The WDT is If the designed for recovering from system abnormal operation. system after 1 second.
5.11.3. TxD/RxD select
1). TxD as UART transmit output, RxD as UART receive input 2). TxD as I/O port EF4, RxD as I/O port EF5
system is hanged, WDT will generate a system reset to restart If WDT is enabled, the WDT should be The WDT Note that the WDT only works
5.11.4. Port EF Bit7 - 0 with 600K pull-low
1). Each bit can be optioned to Enable/Disable individually.
cleared every 0.5 seconds to avoid accidental reset. can be cleared by writing to $0F. when 32768Hz clock is available.
5.11.5. I/O and LCD driver 5.11. Mask Options 5.11.1. 32768 oscillator
1). X'TAL 2). R-oscillator 1). COM15 -14 can be optioned to IOEF7 - 6 when LCD mode is 1/8 duty or 1/12 duty. 2). SEG39 - 36 can be optioned to IOAB3 - 0 individually.
5.11.2. Watchdog timer
1). Enable 2). Disable
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SPL61A
6. ELECTRICAL SPECIFICATIONS
6.1. Absolute Maximum Ratings
Characteristics DC Supply Voltage Input Voltage Range Operating Temperature Storage Temperature
conditions see AC/DC Electrical Characteristics.
Symbol V+ VIN TA TSTO
Ratings < 7.0V -0.5V to V+ + 0.5V 0 to +60 -50 to +150
For normal operational
Note: Stresses beyond those given in the Absolute Maximum Rating table may cause operational errors or damage to the device.
6.2. DC Characteristics
Characteristics Symbol Limit Min. 2.4 3.6 Typ. 1.0 1.0 -20 -40 25 50 Max. 3.6 5.5 2.0 Unit V V mA A mA mA mA mA Test Condition For 2-battery For 3-batter FCPU = 1.0MHz @ 3.0V, no load VDD = 3.0V, 32768Hz OFF VDD = 3.0V, VOH = 2.5V VDD = 3.0V, VOH = 2.0V VDD = 3.0V, VOL = 0.5V VDD = 3.0V, VOL = 1.0V VDD = 2.6V - 5.0V VLCD Variation VLCD_VAR 0.2 V VLCD = 4.5V LCD bias strength = $04, no LCD panel applied Input High Level Input Low Level Output High Current (I/O) Output Sink Current (I/O) OSC Resistor CPU Clock VIH VIL IOH 2.0 -800 0.8 V V A A ohm MHz VDD = 3.0V VDD = 3.0V VDD = 3.0V VOH = 2.4V VDD = 3.0V VOL = 0.8V FOSC2 = 2.0MHz @ 3.0V FCPU = FOSC2 /2 @ 2.6V
Operating Voltage Operating Current Standby Current Audio Output Current
VDD IOP ISTBY IOH
Audio Output Current
IOL
IOL ROSC FCPU
-
1000 220K -
3.0
Note1: VLCD variation is subject to change due to the variation of process, temperature, supply voltage and loadings. Note2: When voltage regulator and voltage doubler are enabled, VDD should be lower than VLCD to prevent forward biasing the p-n junction of I/O's output PMOS.
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AUG. 13, 2001 Version: 1.2
SPL61A
7. APPLICATION CIRCUITS
7.1. 640 Points LCD Driver, 40 Segments X 16 Commons, 32768 Mask Option X'TAL
C6
VDD 220F
VDD
HVLCD VLCD CUP1 CUP2 IOEF0 IOEF1 IOEF2 IOEF3
0.1
BUZZER SPEAKER
Note1: IOEF4, IOEF5 are shared with TxD, RxD(UART), if UART is not used, these two pins can be used as I/O ports Note2: These capacitors must be connected if voltage doubler and voltage regulator are used. Note3: Wire route path from capacitors (C6 - 1) to chip should be as close as possible.
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TEST AUDP AVDD AUDN AVSS SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1
Note2
0.1 F
0.1 F
C3
C4 0.1 F
C5
SPL61A
SEG [ 39 : 0 ]
9
KEY
Note1
MODULE LCD
TxD/IOEF4 RxD/IOEF5
TxD RxD RESET
IOCD3 IOCD2 IOCD1 IOCD0 RESET ROSC X32I X32O VDD
0.1
COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0
COM [ 15 : 0 ]
C1 32768Hz
200pF
VSS
RSYS
20pF
20pF
C2
VDD
VDD
0.1
AUG. 13, 2001 Version: 1.2
SPL61A
7.2. 640 Points LCD Driver, 40 Segments X 16 Commons, 32768 Mask Option R-Oscillator
C6
VDD 220F
VDD
0.1
BUZZER SPEAKER
Note1: IOEF4, IOEF5 are shared with TxD, RxD(UART), if UART is not used, these two pins can be used as I/O ports Note2: These capacitors must be connected if voltage doubler and voltage regulator are used. Note3: Wire route path from capacitors (C6 - 1) to chip should be as close as possible.
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TEST AUDP AVDD AUDN AVSS SEG39 SEG38 SEG37 SEG36 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 HVLCD VLCD CUP1 CUP2 IOEF0 IOEF1 IOEF2 IOEF3 Note1 TxD/IOEF4 RxD/IOEF5 IOCD3 IOCD2 IOCD1 IOCD0 RESET X32I X32O ROSC VDD Note2
0.1 F
C3 0.1 F
0.1 F
C4
C5
SPL61A
SEG [ 39 : 0 ]
10
KEY TxD RxD
RESET 0.1
200PF
R32768
C1
VSS COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 COM14 COM15 SEG0 COM [ 15 : 0 ] MODULE LCD
RSYS
VDD
200PF
C2
VDD
AUG. 13, 2001 Version: 1.2
0.1
SPL61A
7.3. Serial Communications between two SPL61As
VDD 200P 20pF 20pF
VDD 200P 20pF 20pF
R VDD
R
VDD
X32I
X32O
ROSC
X32I
ROSC
X32O
VDD
TxD
RxD
VDD
VSS
SPL61A
RxD TxD
SPL61A
VSS
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SPL61A
8. PACKAGE/PAD LOCATIONS
8.1. PAD Assignment
Chip Size: 3190m x 2620m This IC substrate should be connected to VSS
Note1: Chip size included scribe line. Note2: The 0.1F capacitor between VDD and VSS should be placed to IC as close as possible.
8.2. Ordering Information
Product Number SPL61A-nnnnV-C
Note1: Code number (nnnnV) is assigned for customer. Note2: Code number (nnnn = 0000 - 9999); version (V = A - Z).
Package Type Chip form
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8.3. PAD Locations
PAD No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 PAD Name SEG36 AUDP AVDD AUDN AVSS VSS SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18 SEG17 SEG16 SEG15 SEG14 SEG13 SEG12 SEG11 SEG10 SEG9 SEG8 SEG7 SEG6 SEG5 SEG4 SEG3 SEG2 SEG1 X -1420 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1416 -1401 -1261 -1133 -1013 -893 -773 -653 -533 -413 -293 -173 -53 67 187 307 427 547 667 787 907 1027 1147 1276 Y 1110 905 785 665 545 440 320 200 80 -40 -160 -280 -400 -520 -640 -760 -880 -1000 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 -1131 PAD No. 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 PAD Name SEG0 COM0 COM1 COM2 COM3 COM4 COM5 COM6 COM7 COM8 COM9 COM10 COM11 COM12 COM13 CUP2 CUP1 HVLCD RESET TEST X32O X32I VLCD VDD ROSC COM15 COM14 RXD TXD IOEF3 IOEF2 IOEF1 IOEF0 IOCD3 IOCD2 IOCD1 IOCD0 SEG39 SEG38 SEG37 X 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1416 1276 1156 1036 916 796 666 539 404 277 142 15 -120 -247 -382 -509 -641 -768 -911 -1038 -1166 -1293 Y -1131 -986 -851 -724 -601 -481 -361 -241 -121 -1 119 239 359 479 599 721 849 984 1129 1129 1129 1129 1129 1129 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110 1110
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9. DISCLAIMER
The information appearing in this publication is believed to be accurate. Integrated circuits sold by Sunplus Technology are covered by the warranty and patent indemnification provisions stipulated in the terms of sale only. SUNPLUS makes no warranty, express, statutory implied or by description regarding the information in this publication or FURTHERMORE, SUNPLUS MAKES NO WARRANTY OF SUNPLUS reserves the right to halt production or alter the specifications and regarding the freedom of the described chip(s) from patent infringement. MERCHANTABILITY OR FITNESS FOR ANY PURPOSE. prices at any time without notice. publication are current before placing orders.
Accordingly, the reader is cautioned to verify that the data sheets and other information in this Products described herein are intended for use in normal commercial applications. Please note that application circuits
Applications involving unusual environmental or reliability requirements, e.g. military equipment or medical life support equipment, are specifically not recommended without additional processing by SUNPLUS for such applications. illustrated in this document are for reference purposes only.
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10. REVISION HISTORY
Date MAR. 01, 1999 MAY. 28, 1999 Revision # 0.1 0.2 Original 1. Renew to a new document format 2. Modify ROM Size: 72K Bytes -> 80K Bytes 3. Modify SRAM Size: 704 Bytes -> 496 Bytes 4. Modify "5.2 Map of Memory and I/Os" 5. Add "5.3 Operating States" 6. Add "5.6 Voltage Doubler/Regulator" 7. Add "5.8 Asynchronous Serial Interface" 8. Add "8.3. Serial Communications Between Two SPL61As" DEC. 03, 1999 1.0 1. Delete "PRELIMINARY" 2. Renew to a new document format JUN. 01, 2001 1.1 1. Correct "8.1 640 Points LCD Driver, 40 Segments X 16 Commons, 32768 Mask Option X'TAL" RESET switch 0.1F capacitor. 2. Add "Note: The 0.1F capacitor between VDD and VSS..." 3. Renew to a new document format AUG. 13, 2001 1.2 1. Correct chip size 2. Add Note1 in the "8.1 PAD Assignment" 3. Renew to a new document format 12 12 11 8 Description Page
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