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| ST10R172L 16-BIT LOW VOLTAGE ROMLESS MCU DATASHEET s High Performance 16-bit CPU q q q q q q q q CPU Frequency: 0 to 50 MHz 40ns instruction cycle time at 50-MHz CPU clock 4-stage pipeline Register-based design with multiple variable register banks Enhanced boolean bit manipulation facilities Additional instructions to support HLL and operating systems Single-cycle context switching support 1024 bytes on-Chip special function register area 1KByte on-chip RAM Up to 16 MBytes linear address space for code and data (1 MByte with SSP used) Programmable external bus characteristics for different address ranges 8-bit or 16-bit external data bus Multiplexed or demultiplexed external address/data buses Five programmable chip-select signals Hold and hold-acknowledge bus arbitration support Dedicated pins O SC P.6 P.4 XSSP P.1 P.0 W DT PLL ST10 CO RE DPRAM Interrupt Controller &PEC ASC P.3 GPT1/2 P.5 PW M P.7 Po.2 s Memory Organisation q q q s External Memory Interface q q Two multi-functional general purpose timer units with 5 timers Clock Generation via on-chip PLL, or via direct or prescaled clock input Synchronous/asynchronous High-speed-synchronous serial port SSP s Serial Channels q q q q q q s s s Up to 77 general purpose I/O lines No bootstrap loader Electrical Characteristics q q s s One Channel PWM Unit Fail Safe Protection q q Programmable watchdog timer Oscillator Watchdog s q q 5V Tolerant I/Os 5V Fail-Safe Inputs (Port 5) Power: 3.3 Volt +/-0.3V Idle and power down modes C-compilers, macro-assembler packages, emulators, evaluation boards, HLLdebuggers, simulators, logic analyser disassemblers, programming boards 100-Pin Thin Quad Flat Pack (TQFP) Rev. 1.2 s Interrupt q Support q q 8-channel interrupt-driven single-cycle data transfer facilities via peripheral event controller (PEC) 16-priority-level interrupt system with 17 sources, sample-rate down to 40 ns s s Timers Package q March 2001 1/68 1 Table of Contents 1 PIN DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 2 FUNCTIONAL DESCRIPTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 3 MEMORY MAPPING . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 4 CENTRAL PROCESSING UNIT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 5 INTERRUPT AND TRAP FUNCTIONS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 5.1 INTERRUPT SOURCES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 5.2 HARDWARE TRAPS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 6 PARALLEL PORTS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 7 EXTERNAL BUS CONTROLLER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 8 PWM MODULE . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 9 GENERAL PURPOSE TIMERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.1 GPT1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 9.2 GPT2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 10 SERIAL CHANNELS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 11 WATCHDOG TIMER . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 12 SYSTEM RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 13 POWER REDUCTION MODES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 14 SPECIAL FUNCTION REGISTERS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 15 ELECTRICAL CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.1 ABSOLUTE MAXIMUM RATINGS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 15.2 DC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 68 2/68 1 Table of Contents 15.3 AC CHARACTERISTICS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 15.3.1 Cpu Clock Generation Mechanisms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 15.3.2 Memory Cycle Variables . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 15.3.3 Multiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 15.3.4 Demultiplexed Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 15.3.5 CLKOUT and READY/READY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 15.3.6 External Bus Arbitration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 15.3.7 External Hardware Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 15.3.8 Synchronous Serial Port Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 16 PACKAGE MECHANICAL DATA . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 17 ORDERING INFORMATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 68 3/68 ST10R172L - PIN DESCRIPTION 1 P5.12/T6IN P5.11/T5EUD P5.10/T6EUD P7.3/POUT3 P7.2 P7.1 P7.0 P2.11/EX3IN P2.10/EX2IN P2.9/EX1IN P2.8/EX0IN P6.7/BREQ P6.6/HLDA P6.5/HOLD P6.4/CS4 P6.3/CS3 P6.2/CS2 P6.1/CS1 P6.0/CS0 NMI RSTOUT RSTIN VDD VSS P1H.7/A15 100999897969594939291908988878685848382818079787776 P 5.13/T5IN P 5.14/T4E D U P 5.15/T2E D U V SS X L1 TA X L2 TA V DD P 3.0 P 3.1/T6O T U P 3.2/C P A IN P 3.3/T3O T U P 3.4/T3E D U P 3.5/T4IN P 3.6/T3IN P 3.7/T2IN P 3.8 P 3.9 P 3.10/TxD 0 P 3.11/R 0 xD P 3.12/BH /W H ER P 3.13 P 3.15/C O T LK U P 4.0/A 16 P 4.1/A 17 P 4.2/A 18 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 P .6/A 1H 14 P .5/A 1H 13 P .4/A 1H 12 P .3/A 1H 11 P .2/A 1H 10 V SS V DD P .1/A 1H 9 P .0/A 1H 8 P 1L.7/A 7 P 1L.6/A 6 P 1L.5/A 5 P 1L.4/A 4 P 1L.3/A 3 P 1L.2/A 2 P 1L.1/A 1 P 1L.0/A 0 P .7/A 15 0H D P .6/A 14 0H D P .5/A 13 0H D P .4/A 12 0H D P .3/A 11 0H D P .2/A 10 0H D P .1/A 9 0H D P .0/A 8 0H D PIN DESCRIPTION ST10R172L 26272829303132333435363738394041424344454647484950 P4.3/A19 VSS VDD P4.4/A20/SSPCE1 P4.5/A21/SSPCE0 P4.6/A22/SSPDAT P4.7/A23/SSPCLK RD W R/W RL READY/READY ALE EA VDD VSS P0L.0/AD0 P0L.1/AD1 P0L.2/AD2 P0L.3/AD3 P0L.4/AD4 P0L.5/AD5 P0L.6/AD6 P0L.7/AD7 VDD VSS RPD Figure 1 TQFP-100 pin configuration (top view) 4/68 1 ST10R172L - PIN DESCRIPTION Pin Number (TQFP) Input (I) Output (O) P5.10 -P5.15 98-100 1- 3 98 I I I 5S 5S 5S Function 6-bit input-only port with Schmitt-Trigger characteristics. Port 5 pins also serve as timer inputs: P5.10 T6EUD GPT2 Timer T6 Ext.Up/Down Ctrl.Input GPT2 Timer T5 Ext.Up/Down Ctrl.Input GPT2 Timer T6 Count Input GPT2 Timer T5 Count Input GPT1 Timer T4 Ext.Up/Down Ctrl.Input GPT1 Timer T2 Ext.Up/Down Ctrl.Input P5.11 Symbol 99 I Kind1) 5S T5EUD 100 1 2 I I I 5S 5S 5S P5.12 P5.13 P5.14 T6IN T5IN T4EUD 3 I 5S P5.15 T2EUD XTAL1 5 I 3T XTAL1: Input to the oscillator amplifier and internal clock generator Output of the oscillator amplifier circuit. To clock the device from an external source, drive XTAL1, while leaving XTAL2 unconnected. Observe minimum and maximum high/low and rise/fall times specified in the AC Characteristics. XTAL2 6 O 3T XTAL2: Table 1 Pin definitions 5/68 1 ST10R172L - PIN DESCRIPTION Pin Number (TQFP) Input (I) Output (O) P3.0 - P3.13 P3.15 8-21 22 I/O I/O 5T 5T 9 10 O I 5T 5T Function A 15-bit (P3.14 is missing) bidirectional I/O port. Port 3 is bitwise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. Port 3 outputs can be configured as push/ pull or open drain drivers. The following pins have alternate functions: P3.1 P3.2 T6OUT CAPIN GPT2 Timer T6 toggle latch output GPT2 Register CAPREL capture input GPT1 Timer T3 toggle latch output GPT1 Timer T3 ext.up/down ctrl.input GPT1 Timer T4 input for count/gate/ reload/capture GPT1 Timer T3 count/gate input GPT1 Timer T2 input for count/gate/ reload/capture ASC0 clock/data output (asyn./syn.) ASC0 data input (asyn.) or I/O (syn.) Ext. Memory High Byte Enable Signal Ext. Memory High Byte Write Strobe System clock output (=CPU clock) P3.3 P3.4 P3.5 Symbol 11 12 13 O I I Kind1) 5T 5T 5T T3OUT T3EUD T4IN 14 15 I I 5T 5T P3.6 P3.7 T3IN T2IN 18 19 20 O I/O O O 5T 5T 5T 5T 5T P3.10 P3.11 P3.12 TxD0 RxD0 BHE WRH 22 O P3.15 CLKOUT Table 1 Pin definitions 6/68 1 ST10R172L - PIN DESCRIPTION Pin Number (TQFP) Input (I) Output (O) P4.0- P4.7 23-26 29-32- I/O 5T 23 ... 26 29 O ... O O O 5T ... 5T 5T 5T 5T 5T 5T 5T 5T 5T 5T Function An 8-bit bidirectional I/O port. Port 8 is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 4 can be used to output the segment address lines for external bus configuration. P4.0 ... P4.3 P4.4 A16 ... A19 A20 SSPCE1 P4.5 A21 SSPCE0 P4.6 A22 SSPDAT P4.7 A23 SSPCLK Least Significant Segment Addr. Line ... Segment Address Line Segment Address Line Chip Enable Line 1 Segment Address Line SSPChip Enable Line 0 Segment Address Line SSP Data Input/Output Line Most Significant Segment Addr. Line SSP Clock Output Line External Memory Read Strobe. RD is activated for every external instruction or data read access. External Memory Write Strobe. In WR-mode, this pin is activated for every external data write access. In WRL-mode, this pin is activated for low byte data write accesses on a 16-bit bus, and for every data write access on an 8-bit bus. See WRCFG in the SYSCON register for mode selection. Ready Input. Active level is programmable. When the Ready function is enabled, the selected inactive level at this pin during an external memory access will force the insertion of memory cycle time waitstates until the pin returns to the selected active level. Polarity is programmable. Symbol 30 O O 31 O I/O 32 O O RD 33 O WR/ WRL 34 O READY/ READY 35 I Kind1) 5T 5T Table 1 Pin definitions 7/68 1 ST10R172L - PIN DESCRIPTION Pin Number (TQFP) Input (I) Output (O) ALE 36 O 5T EA 37 I 5T PORT0: P0L.0- P0L.7, P0H.0 P0H.7 41 - 48 51 - 58 I/O 5T Function Address Latch Enable Output. Can be used for latching the address into external memory or an address latch in the multiplexed bus modes. External Access Enable pin. Low level at this pin during and after reset forces the ST10R172L to begin instruction execution out of external memory. A high level forces execution out of the internal ROM. The ST10R172L must have this pin tied to `0'. PORT0 has two 8-bit bidirectional I/O ports P0L and P0H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. For external bus configuration, PORT0 acts as address (A) and address/data (AD) bus in multiplexed bus modes and as the data (D) bus in demultiplexed bus modes. Demultiplexed bus modes Data Path Width: P0L.0 - P0L.7: P0H.0 - P0H.7: 8-bit D0 - D7 I/O 16-bit D0 - D7 D8 - D15 Multiplexed bus modes Data Path Width: P0L.0 - P0L.7: P0H.0 - P0H.7: 8-bit AD0 - AD7 A8 - A15 16-bit AD0 - AD7 AD8 - AD15 PORT1 has two 8-bit bidirectional I/O ports P1L and P1H. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into highimpedance state. PORT1 acts as a 16-bit address bus (A) in demultiplexed bus modes and also after switching from a demultiplexed bus mode to a multiplexed bus mode. Symbol PORT1: P1L.0- P1L.7, P1H.0 P1H.7 59- 66 67, 68 71-76 I/O Kind1) 5T Table 1 Pin definitions 8/68 1 ST10R172L - PIN DESCRIPTION Pin Number (TQFP) Input (I) Output (O) RSTIN 79 I 5T RSTOUT 80 O 5T NMI 81 I 5S P6.0P6.7 82-89 I/O 5T 82 ... 86 87 O ... O I 5T ... 5T 5T Function Reset Input with Schmitt-Trigger characteristics. Resets the device when a low level is applied for a specified duration while the oscillator is running. An internal pullup resistor enables power-on reset using only a capacitor connected to VSS. With a bonding option, the RSTIN pin can also be pulled-down for 512 internal clock cycles for hardware, software or watchdog timer triggered resets Internal Reset Indication Output. This pin is set to a low level when the part is executes hardware-, software- or watchdog timer reset. RSTOUT remains low until the EINIT (end of initialization) instruction is executed. Non-Maskable Interrupt Input. A high to low transition at this pin causes the CPU to vector to the NMI trap routine. If it is not used, NMI should be pulled high externally. An 8-bit bidirectional I/O port. Port 6 is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 6 outputs can be configured as push/pull or open drain drivers. The following Port 6 pins have alternate functions: P6.0 ... P6.4 P6.5 CS0 ... CS4 HOLD Chip Select 0 Output ... Chip Select 4 Output External Master Hold Request Input (Master mode: O, Slave mode: I) Hold Acknowledge Output Bus Request Output P6.6 P6.7 Symbol 88 89 I/O O Kind1) 5T 5T HLDA BREQ Table 1 Pin definitions 9/68 1 ST10R172L - PIN DESCRIPTION Pin Number (TQFP) Input (I) Output (O) P2.8 - P2.11 90 - 93 I/O 5T 90 ... 93 P7.0 - P7.3 94 - 97 I ... I I/O 5T ... 5T 5T Function Port 2 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 2 outputs can be configured as push/pull or open drain drivers. The following Port 2 pins have alternate functions: P2.8 ... P2.11 EX0IN ... EX3IN Fast External Interrupt 0 Input ... Fast External Interrupt 3 Input Port 7 is a 4-bit bidirectional I/O port. It is bit-wise programmable for input or output via direction bits. For a pin configured as input, the output driver is put into high-impedance state. Port 7outputs can be configured as push/pull or open drain drivers. The following Port 7 pins have alternate functions: P7.3 Symbol 97 RPD 40 O I/O Kind1) 5T 5T POUT3 PWM (Channel 3) Output Input timing pin for the return from powerdown circuit and power-up asynchronous reset. Digital supply voltage. VDD 7, 28, 38, 49, 69, 78 4, 27, 39, 50, 70, 77 - PO VSS - PO Digital ground. Table 1 Pin definitions 1) The following I/O kinds are used. Refer to ELECTRICAL CHARACTERISTICS on page 31 for a detailed description. PO: Power pin 3T: 3 V tolerant pin (voltage max. respect to Vss is -0.5 to VDD + 0.5) 5V: 5 V tolerant pin (voltage max. respect to Vss is -0.5 to 5.5 only if chip is powered) 5S: 5 V tolerant and fail-safe pin (-0.5-5.5 max. voltage w.r.t. Vss even if chip is not powered). 10/68 1 ST10R172L - FUNCTIONAL DESCRIPTION 2 FUNCTIONAL DESCRIPTION ST10R172L architecture combines the advantages of both RISC and CISC processors with an advanced peripheral subsystem. The following block diagram overviews the different onchip components and the internal bus structure. I/O CS(4:0) HOLD HLDA BREQ I/O A(23:16), SSPCLK, SSPDAT, SSPCE(1:0) EA, ALE, RD, WR/WRL, READY, NMI, RSTIN, RSTOUT dedicated pins I/O I/O, D(7:0) D(15:8), D(7:0) I/O A(15:8), AD(7:0) A(15:0) AD(15:8), AD(7:0) Port 6 8-bit Port 4 8-bit Port 1 2x8-bit Port 0 2x8-bit XTAL1 OSC XTAL2 PLL WDT XSSP 4-bit 1KByte DPRAM ST10 CORE Interrupt Controller & PEC ASC GPT1/2 PWM Port 3 15-bit Port 5 6-bit Port 7 4-bit Port 2 4-bit I/O CLKOUT, BHE/WRH, RxD0, TxD0, T2IN, T3IN, T4IN, T3EUD, T3OUT, CAPIN, T6OUT I T2EUD, T4EUD, T5IN, T6IN, T5EUD, T6EUD I/O POUT3 I/O EXIN(3:0) Figure 2 Block diagram 11/68 1 ST10R172L - MEMORY MAPPING 3 MEMORY MAPPING The ST10R172L is a ROMless device, the internal RAM space is 1 KByte. The RAM address space is used for variables, register banks, the system stack, the PEC pointers (in 00'FCE0h - 00'FCFFh) and the bit-addressable space (in 00'FD00h - 00'FDFFh). RAM/SFR 00'EFFFh 256 Byte 00'EF00h XSSP 00'FFFFh 00'F000h Data Page 3 00'FFFFh 00'FF3Fh 00'FF20h 00'FE3Fh 00'FE20h 00'FE00h SFR Area (reserved) External memory 00'F000h RAM Data Page 2 00'FA00h 00'8000h 1K-Byte Data Page 1 internal memory Block 1 00'4000h 00'F200h 00'FF3Fh 00'FF20h 00'1FFFh 8K-byte 00'0000h System Segment 0 64 K-Byte Data Page 0 Block 0 00'0000h DPRAM / SFR Area 4 K-Byte 00'F03Fh 00'F020h 00'F000h ESFR Area (reserved) Figure 3 Memory map 12/68 1 ST10R172L - CENTRAL PROCESSING UNIT 4 CENTRAL PROCESSING UNIT The main core of the CPU contains a 4-stage instruction pipeline, a separate multiply and divide unit, a bit-mask generator and a barrel shifter. Most instructions can be executed in one machine cycle requiring 40ns at 50MHz CPU clock. The CPU includes an actual register context consisting of 16 wordwide GPRs physically located in the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be accessed by the CPU. The number of register banks is only restricted by the available internal RAM space. For easy parameter passing, one register bank may overlap others. A system stack of up to 1024 bytes is provided as a storage for temporary data. The system stack is allocated in the on-chip RAM area, and it is accessed by the CPU via the stack pointer (SP) register. Two separate SFRs, STKOV and STKUN, are compared against the stack pointer value during each stack access to detect stack overflow or underflow. CPU 16 SP STKOV STKUN Exec. Unit Instr. Ptr Instr. Reg 4-Stage Pipeline PSW SYSCON BUSCON 0 BUSCON 1 BUSCON 2 BUSCON 3 BUSCON 4 Data Pg. Ptrs MDH MDL Mul./Div.-HW Bit-Mask Gen. R15 Internal General Purpose ALU 16-Bit Barrel-Shift Context Ptr ADDRSEL 1 ADDRSEL 2 ADDRSEL 3 ADDRSEL 4 Code Seg. Ptr. R0 IDX0 QX0 QR0 IDX1 QX1 QR1 Registers RAM 1KByte R15 16 R0 Figure 4 CPU block diagram 13/68 1 ST10R172L - INTERRUPT AND TRAP FUNCTIONS 5 INTERRUPT AND TRAP FUNCTIONS The architecture of the ST10R172L supports several mechanisms for fast and flexible response to the service requests that can be generated from various sources, internal or external to the microcontroller. Any of these interrupt requests can be programmed to be serviced, either by the Interrupt Controller or by the Peripheral Event Controller (PEC). In a standard interrupt service, program execution is suspended and a branch to the interrupt service routine is performed. For a PEC service, just one cycle is `stolen' from the current CPU activity. A PEC service is a single, byte or word data transfer between any two memory locations, with an additional increment of either the PEC source or the destination pointer. An individual PEC transfer counter is decremented for each PEC service, except in the continuous transfer mode. When this counter reaches zero, a standard interrupt is performed to the corresponding source-related vector location. PEC services are very well suited, for example, to the transmission or reception of blocks of data. The ST10R172L has 8 PEC channels, each of which offers fast interrupt-driven data transfer capabilities. A separate control register which contains an interrupt request flag, an interrupt enable flag and an interrupt priority bitfield, exists for each of the possible interrupt sources. Via its related register, each source can be programmed to one of sixteen interrupt priority levels. Once having been accepted by the CPU, an interrupt service can only be interrupted by a higher priority service request. For standard interrupt processing, each of the possible interrupt sources has a dedicated vector location. Fast external interrupt inputs are provided to service external interrupts with high precision requirements. These fast interrupt inputs, feature programmable edge detection (rising edge, falling edge or both edges). Software interrupts are supported by means of the `TRAP' instruction in combination with an individual trap (interrupt) number. 14/68 1 ST10R172L - INTERRUPT AND TRAP FUNCTIONS 5.1 Interrupt Sources Request Flag CC8IR CC9IR CC10IR CC11IR T2IR T3IR T4IR T5IR T6IR CRIR S0TIR S0TBIR S0RIR S0EIR PWMIR XP1IR XP3IR Enable Flag CC8IE CC9IE CC10IE CC11IE T2IE T3IE T4IE T5IE T6IE CRIE S0TIE S0TBIE S0RIE S0EIE PWMIE XP1IE XP3IE Interrupt Vector CC8INT CC9INT CC10INT CC11INT T2INT T3INT T4INT T5INT T6INT CRINT S0TINT S0TBINT S0RINT S0EINT PWMINT XP1INT XP3INT Vector Location 60h 64h 68h 6Ch 88h 8Ch 90h 94h 98h 9Ch A8h 11Ch ACh B0h FCh 104h 10Ch Trap Number 18h 19h 1Ah 1Bh 22h 23h 24h 25h 26h 27h 2Ah 47h 2Bh 2Ch 3Fh 41h 43h Source of Interrupt or PEC Service Request External Interrupt 0 External Interrupt 1 External Interrupt 2 External Interrupt 3 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 GPT2 Timer 6 GPT2 CAPREL Register ASC0 Transmit ASC0 Transmit Buffer ASC0 Receive ASC0 Error PWM Channel 3 SSP Interrupt PLL Unlock Table 2 List of possible interrupt sources, flags, vector and trap numbers 15/68 1 ST10R172L - INTERRUPT AND TRAP FUNCTIONS 5.2 Hardware traps Exceptions or error conditions that arise during run-time are called Hardware Traps. Hardware traps cause immediate non-maskable system reaction similar to a standard interrupt service (branching to a dedicated vector table location). The occurrence of a hardware trap is additionally signified by an individual bit in the trap flag register (TFR). Except when another higher prioritized trap service is in progress, a hardware trap will interrupt any actual program execution. In turn, hardware trap services can not normally be interrupted by standard or PEC interrupts. The following table shows all of the possible exceptions or error conditions that can arise during run-time: Vector Location Trap Number Trap Priority Exception Condition Reset Functions: Hardware Reset Software Reset Watchdog Timer Overflow Class A Hardware Traps: Non-Maskable Interrupt Stack Overflow Stack Underflow Class B Hardware Traps: Undefined opcode Protected instruction fault Trap Flag Trap Vector RESET RESET RESET 00'0000h 00'0000h 00'0000h 00h 00h 00h III III III NMI STKOF STKUF NMITRAP STOTRAP STUTRAP 00'0008h 00'0010h 00'0018h 02h 04h 06h II II II UNDOPC PRTFLT BTRAP BTRAP BTRAP BTRAP BTRAP 00'0028h 00'0028h 00'0028h 00'0028h 00'0028h [2Ch - 3Ch] 0Ah 0Ah 0Ah 0Ah 0Ah [0Bh - 0Fh] I I I I I Illegal word operand access ILLOPA Illegal instruction access Illegal external bus access Reserved Software Traps TRAP Instruction ILLINA ILLBUS Any [00'0000h Any Current - 00'01FCh] [00h - 7Fh] CPU steps of 4h Priority Table 3 Exceptions or error conditions 16/68 1 ST10R172L - PARALLEL PORTS 6 PARALLEL PORTS The ST10R172L provides up to 77 I/O lines organized into 7 input/output ports and one input port. All port lines are bit-addressable, and all input/output lines are individually (bit-wise) programmable as inputs or outputs by direction registers. The I/O ports are true bidirectional ports which are switched to high impedance state when configured as inputs. The output drivers of three I/O ports can be configured (pin by pin) for push/pull operation or open-drain operation by control registers. During the internal reset, all port pins are configured as inputs. All port lines have programmable alternate input or output functions associated with them. PORT0 and PORT1 may be used as address and data lines when accessing external memory, while Port 4 outputs the additional segment address bits A23/19/17...A16 in systems where segmentation is enabled to access more than 64 KBytes of memory. Port 6 provides optional bus arbitration signals (BREQ, HLDA, HOLD) and chip select signals. Port 3 includes alternate functions of timers, serial interfaces, the optional bus control signal BHE and the system clock output (CLKOUT). Port 5 is used for timer control signals. Port 2 lines can be used as fast external interrupt lines. Port 7 includes alternate function for the PWM signal. All port lines that are not used for these alternate functions may be used as general purpose I/O lines. 7 EXTERNAL BUS CONTROLLER All external memory accesses are performed by the on-chip External Bus Controller which can be programmed either to single chip mode when no external memory is required, or to the following external memory access modes: 16-bit data, demultiplexed 16-bit data, multiplexed 8-bit data, multiplexed 8-bit data, demultiplexed 16-/18-/20-/24-bit addresses 16-/18-/20-/24-bit addresses 16-/18-/20-/24-bit addresses 16-/18-/20-/24-bit addresses In the demultiplexed bus modes, addresses are output on PORT1 and data is input/output on PORT0/P0L, respectively. In the multiplexed bus modes both addresses and data use PORT0 for input/output. Memory cycle time, memory tri-state time, length of ALE and read write delay are programmable so that a wide range of different memory types and external peripherals can be used. Up to 4 independent address windows can be defined (via ADDRSELx / BUSCONx register pairs) to access different resources with different bus characteristics. These address windows are arranged hierarchically where BUSCON4 overrides BUSCON3 etc. All accesses to locations not covered by these 4 address windows are controlled by BUSCON0. Up to 5 external CS signals (4 windows plus default) can be generated to reduce external glue logic. Access to very slow memories is supported by the READY function. A HOLD/HLDA protocol is available for bus arbitration so that external resources can be shared with other bus masters. In slave mode, the slave controller can be connected to another master controller without glue logic. For applications which require less than 16 MBytes 17/68 1 ST10R172L - PWM MODULE of external memory space, the address space can be restricted to 1 MByte, 256 KByte or to 64 KByte. 8 PWM MODULE A 1-channel Pulse Width Modulation (PWM) Module operates on channel 3. The pulse width modulation module can generate up to four PWM output signals using edge-aligned or centrealigned PWM. In addition, the PWM module can generate PWM burst signals and single shot outputs. The table below shows the PWM frequencies for different resolutions. The level of the output signals is selectable and the PWM module can generate interrupt requests. Mode 0 edge aligned CPU clock/1 CPU clock/64 Mode 1 center aligned CPU clock/1 CPU clock/64 Resolution 20ns 1.28ns Resolution 20ns 1.28ns 8-bit 195.3 KHz 3.052KHz 8-bit 97.66KHz 1.525Hz 10-bit 48.83KHz 762.9Hz 10-bit 24.41KHz 381.5 Hz 12-bit 12.21KHz 190.7Hz 12-bit 6.104KHz 95.37Hz 14-bit 3.052KHz 47.68Hz 14-bit 1.525KHz 23.84Hz 16-bit 762.9Hz 11.92Hz 16-bit 381.5Hz 0Hz Table 4 PWM unit frequencies and resolution at 50MHz CPU clock 18/68 1 ST10R172L - GENERAL PURPOSE TIMERS 9 GENERAL PURPOSE TIMERS The GPTs are flexible multifunctional timer/counters used for time-related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation or pulse multiplication. The GPT unit contains five 16-bit timers, organized in two separate modules, GPT1 and GPT2. Each timer in each module may operate independently in a number of different modes, or may be concatenated with another timer of the same module. 9.1 GPT1 Each of the three timers T2, T3, T4 of the GPT1 module can be configured individually for one of four basic modes of operation: timer, gated timer, counter mode and incremental interface mode. In timer mode, the input clock for a timer is derived from the CPU clock, divided by a programmable prescaler. In counter mode, the timer is clocked in reference to external events. Pulse width or duty cycle measurement is supported in gated timer mode where the operation of a timer is controlled by the `gate' level on an external input pin. For these purposes, each timer has one associated port pin (TxIN) which serves as gate or clock input. Table 5 GPT1 timer input frequencies, resolution and periods lists the timer input frequencies, resolution and periods for each pre-scaler option at 50MHz CPU clock. This also applies to the Gated Timer Mode of T3 and to the auxiliary timers T2 and T4 in Timer and Gated Timer Mode The count direction (up/down) for each timer is programmable by software or may additionally be altered dynamically by an external signal on a port pin (TxEUD). In Incremental Interface Mode, the GPT1 timers (T2, T3, T4) can be directly connected to the incremental position sensor signals A and B by their respective inputs TxIN and TxEUD. Direction and count signals are internally derived from these two input signals so that the contents of the respective timer Tx corresponds to the sensor position. The third position sensor signal TOP0 can be connected to an interrupt input. Timer T3 has output toggle latches (TxOTL) which changes state on each timer over-flow/ underflow. The state of this latch may be output on port pins (TxOUT) e. g. for time out monitoring of external hardware components, or may be used internally to clock timers T2 and T4 for measuring long time periods with high resolution. In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 is captured into T2 or T4 in response to a signal at their associated input pins (TxIN). Timer T3 is reloaded with the contents of T2 or T4 triggered either by an external signal or by a selectable state transition of its toggle latch T3OTL. When both T2 and T4 are configured to alternately reload T3 on opposite state transitions of T3OTL with the low and high times of a PWM signal, this signal can be constantly generated without software intervention. 19/68 1 ST10R172L - GENERAL PURPOSE TIMERS Timer input selection FCPU=50MHz 000b Prescaler Factor Input Frequency Resolution Period 8 001b 16 010b 32 1.5625 MHz 640ns 41.94ms 011b 64 781 KHz 1.28 us 83.88ms 100b 128 391 KHz 2.56 us 168ms 101b 256 195 KHz 5.12 us 336ms 110b 512 97.5 KHz 111b 1024 48.83 KHz 6.25 MHz 3.125 MHz 160ns 10.49ms 320ns 20.97ms 10.24 us 20.48 us 672ms 1.342s Table 5 GPT1 timer input frequencies, resolution and periods T2E UD U/D GPT1 Timer T2 n C PU Clock T2IN 2 n=3...10 T2 Mode Reload Capture Interrupt Request CPU C lock 2n n=3...10 T3 Mode G PT1 Timer T3 U/D T3O TL T3OUT T3EUD T3IN T4 T4IN CPU Clock Capture Reload Mode 2n n=3...10 GPT1 Timer T4 U/D Interrupt Request Interrupt Request T4EU D Figure 5 GPT1 block diagram 20/68 1 ST10R172L - GENERAL PURPOSE TIMERS 9.2 GPT2 The GPT2 module provides precise event control and time measurement. It includes two timers (T5, T6) and a capture/reload register (CAPREL). Both timers can be clocked with an input clock derived from the CPU clock via a programmable prescaler or with external signals. The count direction (up/down) for each timer is programmable by software or altered dynamically by an external signal on a port pin (TxEUD). Concatenation of the timers is supported by the output toggle latch (T6OTL) of timer T6, which changes its state on each timer overflow/underflow. The state of T6OTL may be used to clock timer T5, or may be output on a port pin T6OUT. The overflows/underflows of timer T6 reload the CAPREL register. The CAPREL register captures the contents of T5 based on an external signal transition on the corresponding port pin (CAPIN), and timer T5 may optionally be cleared after the capture procedure. This allows absolute time differences to be measured or pulse multiplication to be performedwithout software overhead. Timer input selection FCPU=50MHz 000b Prescaler Factor Input Frequency Resolution Period 4 001b 8 010b 16 011b 32 1.563 MHz 640ns 41.94ms 100b 64 781 KHz 1.28 us 83.88ms 101b 128 391 KHz 2.56 us 167.7ms 110b 256 195 KHz 5.12 us 335.5ms 111b 512 97.6 KHz 10.24 us 671ms 12.5 MHz 6.25 MHz 3.125 MHz 80ns 5.24ms 160ns 10.49ms 320ns 20.97ms Table 6 GPT2 timer input frequencies, resolution and periods 21/68 1 ST10R172L - SERIAL CHANNELS T5EUD CPU Clock T5IN U/D 2n n=2...9 T5 Mode GPT2 Tim T5 er Clear Capture Interrupt Request CAPIN GPT2 CAPREL Reload Toggle FF GPT2 Tim T6 er U/D T6EUD Interrupt Request Interrupt Request T6IN CPU Clock T6 2n n=2...9 Mode T60TL T6OUT Figure 6 GPT2 block diagram 10 SERIAL CHANNELS Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a Synchronous Serial Port (SSP). ASC0 A dedicated baud rate generator sets up standard baud rates without oscillator tuning. 3 separate interrupt vectors are provided for transmission, reception, and erroneous reception. In asynchronous mode, 8- or 9-bit data frames are transmitted or received, preceded by a start bit and terminated by one or two stop bits. For multiprocessor communication, a mechanism to distinguish address from data bytes has been included (8-bit data + wake up bit mode). In synchronous mode, the ASC0 transmits or receives bytes (8 bits) synchronously to a shift clock which is generated by the ASC0. The ASC0 always shifts the LSB first. A loop back option is available for testing purposes. A number of optional hardware error detection capabilities have been included to increase the reliability of data transfers. A parity bit can be generated automatically on transmission, or checked on reception. Framing error detection recognizes data frames with missing stop bits. An overrun error is generated if the last character received was not read out of the receive buffer register at the time the reception of a new character is complete.The table below lists 22/68 1 ST10R172L - SERIAL CHANNELS various commonly used baud rates together with the required reload values and the deviation errors compared to the intended baudrate. S0BRS = `0', fCPU = 50MHz Baud Rate Deviation Error (Baud) 1562500 56000 38400 19200 9600 4800 2400 1200 600 190 0.0% +3.3% +1.7% +0.5% +0.5% +0.2% 0.0% 0.0% 0.0% +0.4% / 0.0% / -0.4% / -0.8% / -0.8% / -0.1% / -0.1% / -0.1% / -0.1% / 0.0% /+0.4% Reload Value 0000H / 0000H 001AH / 001BH 0027H / 0028H 0050H / 0051H 00A1H/ 00A2H 0144H / 0145H 028AH / 028BH 0515H / 0516H 0A2BH / 0A2CH 1FFFH / 1FFFH S0BRS = `1', f CPU = 50MHz Baud Rate Deviation Error (Baud) 1041666 56000 38400 19200 9600 4800 2400 1200 600 75 127 0.0% +3.3% +0.5% +0.5% +0.5% 0.0% 0.0% 0.0% 0.0% 0.0% +0.1% / 0.0% / -2.1% / -3.1% /-1.4% / -0.5% / -0.5% / -0.2% / -0.1% / -0.1% / 0.0% Reload Value 0000H / 0000H 0011H / 0012H 001AH / 001BH 0035H / 0036H 006BH / 006CH 00D8H / 00D9H 01B1H / 01B2H 0363H / 0364H 06C7H / 06C8H 363FH / 3640H / +0.1% 1FFFH / 1FFFH Table 7 Commonly used baud rates, required reload values and deviation errors SSP transmits 1...3 bytes or receives 1 byte after sending 1...3 bytes synchronously to a shift clock which is generated by the SSP. The SSP can start shifting with the LSB or with the MSB and is used to select shifting and latching clock edges, and clock polarity. Up to two chip select lines may be activated in order to direct data transfers to one or both of two peripheral devices. When the SSP is enabled, the four upper pins of Port4 can not be used as general purpose IO. Note that the segment address selection done via the system start-up configuration during reset has priority and overrides the SSP functions on these pins. SSPCKS Value 000 001 010 SSP clock = CPU clock divided by 2 SSP clock = CPU clock divided by 4 SSP clock = CPU clock divided by 8 Synchronous baud rate 25 MBit/s 12.5 MBit/s 6.25 MBit/s Table 8 Synchronous baud rate and SSPCKS reload values 23/68 1 ST10R172L - WATCHDOG TIMER SSPCKS Value 011 100 101 110 111 SSP clock = CPU clock divided by 16 SSP clock = CPU clock divided by 32 SSP clock = CPU clock divided by 64 SSP clock = CPU clock divided by 128 SSP clock = CPU clock divided by 256 Synchronous baud rate 3.13 MBit/s 1.56 MBit/s 781 KBit/s 391 KBit/s 195 KBit/s Table 8 Synchronous baud rate and SSPCKS reload values 11 WATCHDOG TIMER The Watchdog Timer is a fail-safe mechanism which limits the malfunction time of the controller. The Watchdog Timer is always enabled after device reset and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. In this way, the chip's start-up procedure is always monitored. The software must be designed to service the Watchdog Timer before it overflows. If, due to hardware or software related failures, the software fails to maintain the Watchdog Timer, it will overflow generating an internal hardware reset and pulling the RSTOUT pin low to reset external hardware components. The Watchdog Timer is a 16-bit timer, clocked with the system clock divided either by 2 or by 128. The high byte of the Watchdog Timer register can be set to a pre-specified reload value (stored in WDTREL) in order to allow further variation of the monitored time interval. Each time it is serviced by the application software, the high byte of the Watchdog Timer is reloaded. The table below shows the watchdog time range which for a 50MHz CPU clock rounded to 3 significant figures. Prescaler for fCPU 2 (WDTIN = `0') 10.24 s 2.62 ms 128 (WDTIN = `1') 655 s 168 ms Reload value in WDTREL FFH 00H Table 9 Watchdog timer range 24/68 1 ST10R172L - SYSTEM RESET 12 SYSTEM RESET The following type of reset are implemented on the ST10R172L: Asynchronous hardware reset: Asynchronous reset does not require a stabilized clock signal on XTAL1 as it is not internally resynchronized, it resets the microcontroller into its default reset state. Asynchronous reset is required on chip power-up and can be used during catastrophic situations. The rising edge of the RSTIN pin is internally resynchronized before exiting the reset condition, therefore, only the entry to hardware reset is asynchronous. Synchronous hardware reset (warm reset): A warm synchronous hardware reset is triggered when the reset input signal RSTIN is latched low and Vpp pin is high. The I/Os are immediately (asynchronously) set in high impedance, RSTOUT is driven low. After RSTIN negation is detected, a short transition period elapses, during which pending internal hold states are cancelled and any current internal access cycles are completed, external bus cycles are aborted. Then, the internal reset sequence is active for 1024 TCL (512 CPU clock cycles). During this reset sequence, if bit BDRSTEN was previously set by software (bit 3 in SYSCON register), RSTIN pin is driven low and internal reset signal is asserted to reset the microcontroller in its default state. Note that after all reset sequence, bit BDRSTEN is cleared. After the reset sequence has been completed, the RSTIN input is sampled. When the reset input signal is active at that time the internal reset condition is prolonged until RSTIN becomes inactive. Software reset: The reset sequence can be triggered at any time by the protected instruction SRST (software reset). This instruction can be executed deliberately within a program, e.g. to leave bootstrap loader mode, or on a hardware trap that reveals a system failure. As for a synchronous hardware reset, if bit BDRSTEN was previously set by software (bit 3 in SYSCON register), the reset sequence lasts 1024 TCL (512 CPU clock cycles), and drives the RSTIN pin low. Watchdog timer reset: When the watchdog timer is not disabled during the initialization or serviced regularly during program execution it will overflow and trigger the reset sequence. Unlike hardware and software resets, the watchdog reset completes a running external bus cycle if this bus cycle does not use READY, or if READY is sampled active (low) after the programmed waitstates. When READY is sampled inactive (high) after the programmed waitstates the running external bus cycle is aborted. Then the internal reset sequence is started. The watchdog reset cannot occur while the ST10R172L is in bootstrap loader mode. Bidirectional reset: The bidirectional reset is activated by setting bit BDRSTEN (bit 3 in SYSCON register). This reset makes the watchdog timer reset and software reset externally visible. It is active for the duration of an internal reset sequences caused by a watchdog timer reset and software reset. Therefore, the bidirectional reset transforms an internal watchdog timer reset or software reset into an external hardware reset with a minimum duration of 1024 TCL. 25/68 1 ST10R172L - POWER REDUCTION MODES 13 POWER REDUCTION MODES Two different power reduction modes with different levels of power reduction can be entered under software control. In Idle mode the CPU is stopped, while the peripherals continue their operation. Idle mode can be terminated by any reset or interrupt request. In Power Down mode both the CPU and the peripherals are stopped. Power Down mode can now be configured by software in order to be terminated only by a hardware reset or by an external interrupt source on fast external interrupt pins. All external bus actions are completed before Idle or Power Down mode is entered. However, Idle or Power Down mode is not entered if READY is enabled, but has not been activated (driven low for negative polarity, or driven high for positive polarity) during the last bus access. 14 SPECIAL FUNCTION REGISTERS The following table lists all ST10R172L SFRs in alphabetical order. Bit-addressable SFRs are marked with the letter "b" in column "Name". SFRs within the Extended SFR-Space (ESFRs) are marked with the letter "E" in column "Physical Address". An SFR can be specified by its individual mnemonic name. Depending on the selected addressing mode, an SFR can be accessed by its physical address (using the Data Page Pointers), or by its short 8-bit address (without using the Data Page Pointers). Physical Address FE18h FE1Ah FE1Ch FE1Eh b b b b b FF0Ch FF14h FF16h FF18h FF1Ah FE4Ah b FF88h 8-Bit Description Address 0Ch 0Dh 0Eh 0Fh 86h 8Ah 8Bh 8Ch 8Dh 25h C4h Address Select Register 1 Address Select Register 2 Address Select Register 3 Address Select Register 4 Bus Configuration Register 0 Bus Configuration Register 1 Bus Configuration Register 2 Bus Configuration Register 3 Bus Configuration Register 4 GPT2 Capture/Reload Register EX0IN Interrupt Control Register Reset Value 0000h 0000h 0000h 0000h 0XX0h 0000h 0000h 0000h 0000h 0000h 0000h Name ADDRSEL1 ADDRSEL2 ADDRSEL3 ADDRSEL4 BUSCON0 BUSCON1 BUSCON2 BUSCON3 BUSCON4 CAPREL CC8IC Table 10 Special functional registers 26/68 1 ST10R172L - SPECIAL FUNCTION REGISTERS Name CC9IC CC10IC CC11IC CP CRIC CSP DP0L DP0H DP1L DP1H DP2 DP3 DP4 DP6 DP7 DPP0 DPP1 DPP2 DPP3 EBUSCON b EXICON IDCHIP IDMANUF IDMEM IDPROG MDC b b b b b b b b b b b b b b b Physical Address FF8Ah FF8Ch FF8Eh FE10h FF6Ah FE08h F100h F102h F104h F106h FFC2h FFC6h FFCAh FFCEh FFD2h FE00h FE02h FE04h FE06h F10Eh F1C0h F07Ch F07Eh F07Ah F078h FF0Eh E E E E E E E E E E 8-Bit Description Address C5h C6h C7h 08h B5h 04h 80h 81h 82h 83h E1h E3h E5h E7h E9h 00h 01h 02h 03h 87H E0h 3Eh 3Fh 3Dh 3Ch 87h EX1IN Interrupt Control Register EX2IN Interrupt Control Register EX3IN Interrupt Control Register CPU Context Pointer Register GPT2 CAPREL Interrupt Control Register CPU Code Segment Pointer Register (read only) P0L Direction Control Register P0h Direction Control Register P1L Direction Control Register P1h Direction Control Register Port 2 Direction Control Register Port 3 Direction Control Register Port 4 Direction Control Register Port 6 Direction Control Register Port 7 Direction Control Register CPU Data Page Pointer 0 Register (10 bits) CPU Data Page Pointer 1 Register (10 bits) CPU Data Page Pointer 2 Register (10 bits) CPU Data Page Pointer 3 Register (10 bits) Extended BUSCON register External Interrupt Control Register Device Identifier Register Manufacturer/Process Identifier Register On-chip Memory Identifier Register Programming Voltage Identifier Register CPU Multiply Divide Control Register Reset Value 0000h 0000h 0000h FC00h 0000h 0000h 00h 00h 00h 00h -0--h 0000h 00h 00h -0h 0000h 0001h 0002h 0003h 0000h 0000h 1101h 0201h 0000h 0000h 0000h Table 10 Special functional registers 27/68 1 ST10R172L - SPECIAL FUNCTION REGISTERS Name MDH MDL ODP2 ODP3 ODP6 ODP7 ONES P0L P0H P1L P1H P2 P3 P4 P5 P6 P7 PECC0 PECC1 PECC2 PECC3 PECC4 PECC5 PECC6 PECC7 PP3 b b b b b b b b b b b b b b Physical Address FE0Ch FE0Eh F1C2h F1C6h F1CEh F1D2h FF1Eh FF00h FF02h FF04h FF06h FFC0h FFC4h FFC8h FFA2h FFCCh FFD0h FEC0h FEC2h FEC4h FEC6h FEC8h FECAh FECCh FECEh F03Eh E E E E E 8-Bit Description Address 06h 07h E1h E3h E7h E9h 8Fh 80h 81h 82h 83h E0h E2h E4h D1h E6h E8h 60h 61h 62h 63h 64h 65h 66h 67h 1Fh CPU Multiply Divide Register - High Word CPU Multiply Divide Register - Low Word Port 2 Open Drain Control Register Port 3 Open Drain Control Register Port 6 Open Drain Control Register Port 7 Open Drain Control Register Constant Value 1's Register (read only) Port 0 Low Register (Lower half of PORT0) Port 0 High Register (Upper half of PORT0) Port 1 Low Register (Lower half of PORT1) Port 1 High Register (Upper half of PORT1) Port 2 Register (4 bits) Port 3 Register Port 4 Register (8 bits) Port 5 Register (read only) Port 6 Register (8 bits) Port 7Register (4 bits) PEC Channel 0 Control Register PEC Channel 1 Control Register PEC Channel 2 Control Register PEC Channel 3 Control Register PEC Channel 4 Control Register PEC Channel 5 Control Register PEC Channel 6 Control Register PEC Channel 7 Control Register PWM Module Period Register 3 Reset Value 0000h 0000h -0--h 0000h 00h -0h FFFFh 00h 00h 00h 00h -0--h 0000h 00h XXXXh 00h -0h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h Table 10 Special functional registers 28/68 1 ST10R172L - SPECIAL FUNCTION REGISTERS Name PSW PW3 PWMCON0 b PWMCON1 b PWMIC RP0H S0BG S0CON S0EIC S0RBUF S0RIC S0TBIC S0TBUF S0TIC SP SSPCON0 SSPCON1 SSPRTB SSPTBH STKOV STKUN SYSCON T2 T2CON T2IC b b b b b b b b b b b Physical Address FF10h FE36h FF30h FF32h F17Eh F108h FEB4h FFB0h FF70h FEB2h FF6Eh F19Ch FEB0h FF6Ch FE12h EF00h EF02h EF04h EF06h FE14h FE16h FF12h FE40h FF40h FF60h X X X X E 8-Bit Description Address 88h 1Bh 98h 99h E E BFh 84h 5Ah D8h B8h 59h B7h CEh 58h B6h 09h --------0Ah 0Bh 89h 20h A0h B0h CPU Program Status Word PWM Module Pulse Width Register 3 PWM Module Control Register 0 PWM Module Control Register 1 PWM Module Interrupt Control Register Reset Value 0000h 0000h 0000h 0000h 0000h System Start-up Configuration Register (Rd. only) XXh Serial Channel 0 baud rate generator reload reg Serial Channel 0 Control Register Serial Channel 0 Error Interrupt Control Register Serial Channel 0 receive buffer reg. (rd only) Serial Channel 0 Receive Interrupt Control Reg. Serial Channel 0 transmit buffer interrupt control reg Serial Channel 0 transmit buffer register (wr only) 0000h 0000h 0000h XXh 0000h 0000h 00h Serial Channel 0 Transmit Interrupt Control Regis- 0000h ter CPU System Stack Pointer Register SSP Control Register 0 SSP Control Register 1 SSP Receive/Transmit Buffer SSP Transmit Buffer High CPU Stack Overflow Pointer Register CPU Stack Underflow Pointer Register CPU System Configuration Register GPT1 Timer 2 Register GPT1 Timer 2 Control Register GPT1 Timer 2 Interrupt Control Register FC00h 0000h 0000h XXXXh XXXXh FA00h FC00h 0xx0h1) 0000h 0000h 0000h Table 10 Special functional registers 29/68 1 ST10R172L - SPECIAL FUNCTION REGISTERS Name T3 T3CON T3IC T4 T4CON T4IC T5 T5CON T5IC T6 T6CON T6IC TFR WDT WDTCON XP1IC XP3IC ZEROS b b b b b b b b b b b b Physical Address FE42h FF42h FF62h FE44h FF44h FF64h FE46h FF46h FF66h FE48h FF48h FF68h FFACh FEAEh FFAEh F18Eh F19Eh FF1Ch E E 8-Bit Description Address 21h A1h B1h 22h A2h B2h 23h A3h B3h 24h A4h B4h D6h 57h D7h C7h CFh 8Eh GPT1 Timer 3 Register GPT1 Timer 3 Control Register GPT1 Timer 3 Interrupt Control Register GPT1 Timer 4 Register GPT1 Timer 4 Control Register GPT1 Timer 4 Interrupt Control Register GPT2 Timer 5 Register GPT2 Timer 5 Control Register GPT2 Timer 5 Interrupt Control Register GPT2 Timer 6 Register GPT2 Timer 6 Control Register GPT2 Timer 6 Interrupt Control Register Trap Flag Register Watchdog Timer Register (read only) Watchdog Timer Control Register SSP Interrupt Control Register PLL unlock Interrupt Control Register Constant Value 0's Register (read only) Reset Value 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 0000h 000xh2) 0000h 0000h 0000h Table 10 Special functional registers Note Note 1. The system configuration is selected during reset. 2. Bit WDTR indicates a watchdog timer triggered reset. 30/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS 15 15.1 * * * * * * * * * ELECTRICAL CHARACTERISTICS Absolute Maximum Ratings Ambient temperature under bias (TA): ......................................................-40C to +85 C Storage temperature (TST):....................................................................... - 65 to +150 C Voltage on VDD pins with respect to ground (VSS):..................................... - 0.5 to +4.0 V Voltage on any pin with respect to ground (VSS): ................................ -0.5 to VDD +0.5 V Voltage on any 5V tolerant pin with respect to ground (VSS): .......................-0.5 to 5.5 V Voltage on any 5V fail-safe pin with respect to ground (VSS): .......................-0.5 to 5.5 V Input current on any pin during overload condition: .................................. -10 to +10 mA Absolute sum of all input currents during overload condition: .............................|100 mA| Power dissipation:.....................................................................................................1.0 W Note Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not guaranteed. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. During overload conditions (VIN>VDD or VIN 31/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS Remarks on 5 volt tolerant (5T) and 5 volt fail-safe (5S) pins The 5V tolerant input and output pins can sustain an absolute maximum external voltage of 5.5V. However, signals on unterminated bus lines might have overshoot above 5.5V, presenting latchup and hot carrier risks. While these risks are under evaluation, observe the following security recommendations: * * Maximum peak voltage on 5V tolerant pin with respect to ground (VSS)= +6 V If the ringing of the external signal exceeds 6V, then clip the signal to the 5V supply. Power supply failure condition The power supply failure condition is a state where the chip is NOT supplied but is connected to active signal lines. There are several cases: * * * * 3.3V external lines on 3.3V (3T) pin on the non powered chip: ...............NOT Acceptable 3.3V external lines on 5V tolerant (5T) pin on the non powered chip: ............. Acceptable The 5V tolerant buffer do not leak: external signals not altered. No reliability problem. 3.3V external lines on 5V fail-safe (5S) pin on the non powered chip: ............ Acceptable The 5V tolerant buffer do not leak: external signals not altered. No reliability problem. 5.5V external lines on 5V tolerant (5T) pin on the non powered chip: ............. Acceptable For VERY SHORT times only: the buffers do not leak (external signals not altered) but there is a fast degradation of the gate oxides in the buffers. The total maximum time under this stress condition is 2 days. This limits this configuration to short power-up/down sequences. For 10 year life time, the maximum duty factor is 1/1800 allowing e.g. a maximum stress duration of 48 seconds per day. * * * 5.5V external lines on 5V fail-safe (5S) pin on the non powered chip: ............ Acceptable 6V transient signals on 5V tolerant (5T) pin on the non powered chip: ...NOT Acceptable 6V transient signals on 5V fail-safe (5S) pin on the non powered chip:.......... Acceptable 32/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS 15.2 DC Characteristics VSS = 0 V VDD = 3.3V 0.3V Reset active TA = -40C to +85 C Limit Values Parameter Symbol min. Input low voltage Input high voltage (all except RSTIN and XTAL1) Input high voltage RSTIN, RPD Input high voltage XTAL1 Output low voltage (ALE, RD, WR, BHE, CLKOUT, RSTIN,RSTOUT, CSX) Output low voltage (all other outputs) Output high voltage ALE, RD, WR, BHE, CLKOUT, RSTIN,RSTOUT, CSX) Output high voltage1) (all other outputs) Input leakage current (3T pins) Input leakage current (5T, 5S pins) RSTIN pull-up resistor 2) Read/Write pullup current3) Read/Write pullup current3 ALE pulldown current3 ALE pulldown current3 Port 6 (CS) pullup current3 Port 6 (CS) pullup current3 max. 0.8 V V V V V - - - - Unit Test Condition VIL VIH VIH1 VIH2 VOL SR SR SR SR CC - 0.3 2.0 0.6 VDD 0.7 VDD - VDD + 0.3 VDD + 0.3 VDD + 0.3 0.4 IOL = 4 mA VOL1 VOH CC CC - 2.4 0.4 - V V IOL1 = 2 mA IOH = -4 mA VOH1 IOZ IOZ1 CC 2.4 - V A A A k A A A A A A IOH = - 2mA 0 V - - 10 10 1007) RRST IRWH 4) IRWL5) IALEL4 IALEH5 IP6H4 IP6L 5 CC 20 - -500 40 - - -500 300 -40 - - 500 -40 - VIN = 0 V VOUT = 2.4 V VOUT = 0.4 V VOUT = 0.4 V VOUT = 2.4 V VOUT = 2.4 V VOUT = 0.4 V Table 11 DC characteristics 33/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS Limit Values Parameter Symbol min. PORT0 configuration current3 max. -4 - 500 20 10 A A A A pF VIN = V IHmin VIN = V ILmax VOUT = V DD 0 V < VIN < VDD Unit Test Condition IP0H4 IP0L 5 - -50 100 CC CC - - RPD pulldown current2 XTAL1 input current Pin capacitance6) (digital inputs/outputs) Power supply current IRPD5 IIL CIO ICC IID f = 1 MHz TA = 25 C fCPU in [MHz] 7)) RSTIN = VIH1 fCPU in [MHz] 7 - 15 + 2.5 * fCPU 10 + 0.9 * fCPU 200 mA Idle mode supply current - mA Power-down mode supply current I 8 PD - A VDD = 3.6 V 9 Table 11 DC characteristics 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the resulting voltage comes from the external circuitry. 2) This specification is only valid during reset, or interruptible power-down mode, after reception of an external interrupt signal that will wake up the CPU. 3) This specification is only valid during reset, hold or adapt-mode. Port 6 pins are only affected if they are used for CS output and the open drain function is not enabled. 4) The maximum current may be drawn while the signal line remains inactive. 5) The minimum current must be drawn in order to drive the signal line active. 6) Not 100% tested, guaranteed by design characterization. 7) Supply current is a function of operating frequency as illustrated in Figure 7 on page 35. This parameter is tested at V DDmax and 50 MHz CPU clock with all outputs disconnected and all inputs at VIL or V IH with an infinite execution of NOP instruction fetched from external memory (16-bit demux bus mode, no waitstates, no memory tri-state waitstates, normal ALE). 8) Typical value at 25C = 20A. 9) This parameter is tested including leakage currents. All inputs (including pins configured as inputs) at 0 V to 0.1 V or at VDD - 0.1 V to VDD, VREF = 0 V, all outputs (including pins configured as outputs) disconnected. 34/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS Supply/idle current [mA] 200 ICCmax 150 100 IIDmax 15 10 20 30 40 50 f CPU [MHz] Figure 7 Supply/idle current vs operating frequency 35/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS 15.3 AC Characteristics Test conditions * * * * * Input pulse levels: ........................................................................................... 0 to +3.0 V Input rise and fall times (10%-90%):........................................................................ 2.5 ns Input timing reference levels: ................................................................................. +1.5 V Output timing reference levels: .............................................................................. +1.5 V Output load: ................................................................................................... seeFigure 9 3V 90% 1.5V 10% 2.5ns Figure 8 Input waveforms timing ref. points 90% 1.5V 10% 2.5 ns 0V ~ 3.3 V IOL = 1m A From output under test Vref CL = 50pF A IOH = 1m VOH 1.5V VOL timing reference points 1.5V Figure 9 Output load circuit waveform 36/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS ~ 3.3 V IOL = 5 m A From output under test Vref CL = 5 pF IOH = 5 m A VOH VLOAD VOL VLOAD +0.15 V VLOAD - 0.15 V timing reference points VOH - 0.15 V VOL + 0.15 V For timing purposes a port pin is no longer floating when a 150 mV change from load voltage occurs, but begins to float when a 150 mV change from the loaded VOH/VOL level occurs. CL is 5 pF for floating measurements only. Figure 10 Float waveforms 37/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.1 Cpu Clock Generation Mechanisms ST10R172L internal operation is controlled by the CPU clock f CPU. Both edges of the CPU clock can trigger internal (e.g. pipeline) or external (e.g. bus cycles) operations. The external timing (AC Characteristics) specification therefore depends on the time between two consecutive edges of the CPU clock, called "TCL" (see figure below). The CPU clock signal can be generated by different mechanisms. The duration of TCLs and their variation (and also the external timing) depends on the f CPU generation mechanism. This must be considered when calculating ST10R172L timing. The CPU clock generation mechanism is set during reset by the logic levels on pins P0.15-13 (P0H.7-5). Phase Locked Loop Operation (PLL factor=4) fXTAL fCPU TCL TCL Direct Clock Drive fXTAL fCPU TCL TCL Prescaler Operation fXTAL fCPU TCL TCL Figure 11 CPU clock generation mechanisms External clock input range 1050MHz 2.5 to 12.5 MHz 3.33 to 16.66 MHz 5 to 25 MHz P0.15-13 (P0H.7-5) CPU frequency fCPU = f XTAL * F Notes 1 1 1 1 1 0 1 0 1 FXTAL * 4 FXTAL * 3 FXTAL * 2 Default configuration Table 12 CPU clock generation mechanisms 38/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS P0.15-13 (P0H.7-5) CPU frequency fCPU = f XTAL * F External clock input range 1050MHz 2 to 10 MHz 1 to 50 MHz 6.66 to 33.33 MHz 2 to 100 MHz 4 to 20 MHz Notes 1 0 0 0 0 0 1 1 0 0 0 1 0 1 0 FXTAL * 5 FXTAL * 1 FXTAL * 1.5 FXTAL / 2 FXTAL * 2.5 Direct drive 1) CPU clock via 2:1 prescaler Table 12 CPU clock generation mechanisms 1) The maximum depends on the duty cycle of the external clock signal. The maximum input frequency is 25 MHz when using an external crystal oscillator, but higher frequencies can be applied with an external clock source. Prescaler operation Set when pins P0.15-13 (P0H.7-5) equal '001' during reset, the CPU clock is derived from the internal oscillator (input clock signal) by a 2:1 prescaler. The frequency of fCPU is half the frequency of fXTAL and the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the period of the input clock fXTAL . The timings listed in the AC characteristics that refer to TCLs therefore can be calculated using the period of fXTAL for any TCL. Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. Direct drive When pins P0.15-13 (P0H.7-5) equal '011' during reset, the on-chip phase locked loop is disabled and the CPU clock is driven from the internal oscillator with the input clock signal. The frequency of fCPU directly follows the frequency of fXTAL so the high and low time of fCPU (i.e. the duration of an individual TCL) is defined by the duty cycle of the input clock fXTAL. The TCL timing below must be calculated using the minimum possible TCL which can be calculated by the formula: TCL min = 1 f XTAL x DCmin ( DC = duty cycle ) For two consecutive TCLs the deviation caused by the duty cycle of fXTAL is compensated so the duration of 2TCL is always 1/fXTAL. Therefore, the minimum value TCLmin has to be used only once for timings that require an odd number of TCLs (1,3,...). Timings that require an even number of TCLs (2,4,...) may use the formula: 2TCL = 1 fXTAL . 39/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS Note The address float timings in Multiplexed bus mode (t11 and t45 ) use TCL max = 1 f XTAL x DC max instead of TCL min . Note that if the bit OWDDIS in SYSCON register is cleared, the PLL runs on its free-running frequency and delivers the clock signal for the Oscillator Watchdog. If bit OWDDIS is set, then the PLL is switched off. Oscillator Watchdog (OWD) When the clock option selected is direct drive or direct drive with prescaler, in order to provide a fail safe mechanism in case of a loss of the external clock, an oscillator watchdog is implemented as an additional functionality of the PLL circuitry. This oscillator watchdog operates as follows: After a reset, the Oscillator Watchdog is enabled by default. To disable the OWD, set bit 4 of SYSCON register OWDDIS. When the OWD is enabled, the PLL runs on its free-running frequency and increments the Oscillator Watchdog counter. On each transition of the XTAL1 pin, the Oscillator Watchdog is cleared. If an external clock failure occurs, then the Oscillator Watchdog counter overflows (after 16 PLL clock cycles). The CPU clock signal will be switched to the PLL free-running clock signal, and the Oscillator Watchdog Interrupt Request (XP3INT) is flagged. The CPU clock will not switch back to the external clock even if a valid external clock exits on XTAL1 pin. Only a hardware reset can switch the CPU clock source back to direct clock input. When the OWD is disabled, the CPU clock is always fed from the oscillator input and the PLL is switched off to decrease power supply current. Phase locked loop For all other combinations of pins P0.15-13 (P0H.7-5) during reset the on-chip phase locked loop is enabled and provides the CPU clock. The PLL multiplies the input frequency by the factor F which is selected via the combination of pins P0.15-13 (i.e. fCPU = fXTAL * F). With every F'th transition of fXTAL the PLL circuit synchronizes the CPU clock to the input clock. In this way, fCPU is constantly adjusted so it is locked to fXTAL. The slight variation causes a jitter of fCPU which affects individual TCL duration.Therefore, AC characteristics that refer to TCLs must be calculated using the minimum possible TCL. The actual minimum value for TCL depends on the jitter of the PLL. As the PLL constantly adjusts its output frequency, it corresponds to the applied input frequency (crystal or oscillator). The relative deviation for periods of more than one TCL is lower than for one single TCL. For a period of N * TCL the minimum value is computed using the corresponding deviation DN: TCL min = TCL NOM x ( 1 - D N 100 ) D N = ( 4 - N 15 ) [ % ] 40/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS where N = number of consecutive TCLs and 1 N 40. So for a period of 3 TCLs (i.e. N = 3): D 3 = 4 - 3 15 = 3,8% and 3TCL min = 3TCL NOM x ( 1 - 3,8 100 ) = 3TCL NOM x 0,962 ( 36.07nsec @fcpu=50MHz ) PLL jitter is an important factor for bus cycles using waitstates and for the operation of timers, serial interfaces, etc. For slower operations and longer periods (e.g. pulse train generation or measurement, lower baudrates, etc.) the deviation caused by the PLL jitter is negligible. Max.jitter [% ] This formula is valid for 1 2 4 8 16 32 N Figure 12 Approximated maximum PLL jitter 41/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.2 Memory Cycle Variables The timing tables below use three variables derived from the BUSCONx registers and represent programmed memory cycle characteristics. Table 13 describes how these variables are computed. Description ALE Extension Memory Cycle Time Waitstates Memory Tristate Time Symbol Values TCL * tA tC tF Table 13 Memory cycle variables 42/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.3 Multiplexed Bus VDD = 3.3 V 0.3 V VSS = 0 V TA = -40C to +85 C CL = 50 pF ALE cycle time = 6 TCL + 2tA + tC + tF (60 ns at 50-MHz CPU clock without waitstates) Parameter Symbol Max. CPU Clock = 50 MHz min. max. - - - - - - 51 151 - - 5 + tC 15 + tC 15 + t A + tC 20 + 2tA + tC Variable CPU Clock 1/2TCL = 1 to 50 MHz min. TCL - 3 + t A TCL - 7 + t A TCL - 5 + t A TCL - 5 + t A TCL - 5 + t A -5 + tA - max. - - - - - - 51 TCL + 51 - - 2TCL - 15 + tC 3TCL - 15 + tC 3TCL - 15 + tA + tC 4TCL - 20 + 2tA + t C Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns 43/68 ALE high time Address (P1, P4), BHE setup to ALE t5 t6 CC 7 + t A CC 3 + t A CC 5 + t A CC 5 + t A CC 5 + t A CC -5 + tA CC - Address (P0) setup to ALE t6m Address hold after ALE ALE falling edge to RD, WR (with RW-delay) ALE falling edge to RD, WR (no RW-delay) Address float after RD, (with RW-delay) 1 1) t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 t17 Address float after RD, (no RW-delay) CC - - RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in CC 13 + t C CC 23 + t C SR - 2TCL - 7+ tC 3TCL - 7 + tC - SR - - SR - - Address to valid data in SR - - Table 14 Multiplexed bus 1 ST10R172L - ELECTRICAL CHARACTERISTICS Parameter Symbol Max. CPU Clock = 50 MHz min. max. - 15 + tF2 - - - - 3 + tA - 13 + t C + 2tA Variable CPU Clock 1/2TCL = 1 to 50 MHz min. 0 - max. - 2TCL - 5 + tF2 - - - - 3 + tA - 3TCL - 17 + tC + 2tA 4TCL - 17 + tC + 2tA - - - - 31 TCL + 31 Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns Data hold after RD rising edge Data float after RD rising edge 12)) t18 t19 t22 t23 t25 SR SR 0 - Data valid to WR Data hold after WR ALE rising edge after RD, WR CC 13 + t C CC 13 + t F CC 10 + t F CC 10 + t F CC -7 + tA CC 3 + tA SR - 2TCL - 7 + tC 2TCL - 7+ tF 2TCL - 10 + tF 2TCL - 10 + tF -7 + tA TCL - 7 + tA - Address hold after RD, WR t27 Latched CS setup to ALE Unlatched CS setup to ALE Latched CS low to Valid Data In t38 t38u t39 Unlatched CS low to Valid t39u Data In Latched CS hold after RD, t40 WR Unlatched CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW delay) ALE fall. edge to RdCS, WrCS (no RW delay) Address float after RdCS (with RW delay) delay)1 1 SR - 23 + t C + 2tA - CC 20 + t F CC 10 + t F CC 7 + t A CC -3 + tA CC - - - - - 31 131 3TCL - 10 + tF 2TCL - 10 + tF TCL - 3 + t A -3 + tA - t40u t42 t43 t44 t45 Address float after RdCS (no RW CC - - Table 14 Multiplexed bus 44/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS Parameter Symbol Max. CPU Clock = 50 MHz min. max. 3 + tC 13 + tC - - - - 13 + tF2 - - Variable CPU Clock 1/2TCL = 1 to 50 MHz min. - max. 2TCL - 17 + tC 3TCL - 17 + tC - - - - 2TCL - 7 + tF2 - - Unit ns ns ns ns ns ns ns ns ns 45/68 RdCS to Valid Data In (with RW delay) RdCS to Valid Data In (no RW delay) RdCS, WrCS Low Time (with RW delay) RdCS, WrCS Low Time (no RW delay) Data valid to WrCS Data hold after RdCS Data float after RdCS 1 2 Address hold after RdCS, WrCS Data hold after WrCS t46 t47 t48 t49 t50 t51 t52 t54 t56 SR - SR - - CC 13 + t C CC 23 + t C CC 10 + t C SR SR 0 - 2TCL - 7+ tC 3TCL - 7+ tC 2TCL - 10 + tC 0 - 2TCL - 10 + tF 2TCL - 10 + tF CC 10 + t F CC 10 + t F Table 14 Multiplexed bus 1) Output loading is specified using Figure 10 (CL = 5 pF). 2) This delay assumes that the following bus cycle is a multiplexed bus cycle. If next bus cycle is demultiplexed, refer to demuxultiplexed equivalent AC timing. 1 ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT t5 ALE t16 t25 t38u CSx t38 t39u t40 t39 t40u t6 A23-A16 (A15-A8) BHE t17 Address t27 t16 Read Cycle BUS P0 t6m Address t7 t18 Data In Address t8 RD t10 t14 t12 t19m t13 t9 Write Cycle BUS P0 Address t11 t15 Data Out t23 t8 WR, WRL, WRH t22 t12 t13 t9 Figure 13 External memory cycle: multiplexed bus, with/without read/write delay, normal ALE 46/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT t5 ALE t16 t25 t38u t38 t39u t39 t40u t40 CSx t6d/b A23-A16 (A15-A8) BHE Read Cycle t17 Address t27 t6m BUS P0 Address t7 Data In t8 t9 RD t10 t11 t14 t15 t12 t18 t19m Write Cycle BUS P0 Address t13 Data Out t23 t8 t9 WR WRL, WRH t10 t11 t22 t13 t12 Figure 14 External memory cycle: multiplexed bus, with/without read/write delay, extended ALE 47/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT t5 ALE t16 t25 t6b/d A23-A16 (A15-A8) BHE t17 Address t27 t16 Read Cycle BUS P0 t6m Address t7 t51 Data In Address t42 RdCSx t44 t46 t48 t52m t49 t43 Write Cycle BUS P0 Address t45 t47 Data Out t56 t42 WrCSx t50 t48 t49 t43 Figure 15 External memory cycle: multiplexed bus, with/without read/write delay, normal ALE, read/write chip select 48/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT t5 ALE t16 t25 A23-A16 (A15-A8) BHE t6d/b t17 Address t54 Read Cycle t6m BUS P0 Address t7 Data In t42 t43 RdCSx t44 t45 t46 t48 t47 t49 t18 t19m Write Cycle BUS P0 Address Data Out t42 t43 WR WRL, WRH t44 t45 t50 t56 t48 t49 Figure 16 External memory cycle: multiplexed bus, with/without read/write delay, extended ale, read/write chip select 49/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.4 Demultiplexed Bus VDD = 3.3 V 0.3 V VSS = 0 V TA = -40C to +85 C CL = 50 pF ALE cycle time = 4 TCL + 2tA + tC + tF (40 ns at 50 MHz CPU clock without waitstates) Max CPU Clock 50MHz Parameter Symbol min. ALE high time Address (P1, P4), BHE setup to ALE Address setup to RD, WR (with RW-delay) Address setup to RD, WR (no RW-delay) RD, WR low time (with RW-delay) RD, WR low time (no RW-delay) RD to valid data in (with RW-delay) RD to valid data in (no RW-delay) ALE low to valid data in max. - - - - - - 5 + tC 15 + tC Variable CPU Clock 1/2TCL = 1 to 50 MHz min. TCL - 3 + tA TCL - 7 + tA max. - - Unit ns ns ns ns ns ns ns ns ns ns ns ns 2 t5 t6 t80 t81 t12 t13 t14 t15 t16 t17 t18 t20 CC CC CC CC CC CC SR 7 + tA 3 + tA 13 + 2tA 3 + 2tA 13 + tC 23 + tC - 2TCL - 7 + 2tA - TCL - 7 + 2tA 2TCL - 7 + tC 3TCL - 7 + tC - - - - 2TCL - 15 + tC 3TCL - 15 + tC 3TCL - 15 + tA + tC 4TCL - 20 + 2tA + tC - 2TCL - 5 + tF + 2tA - TCL - 5 + tF + 2tA 2TCL - 7 + tC - 2 SR - - SR - 15 + tA + tC - 20 + 2tA + - Address to valid data in SR - tC Data hold after RD rising edge Data float after RD rising edge (with RW-delay) 1) 2) SR SR 0 - - 15 + tF + 2tA2 0 - Data float after RD rising edge (no RW-delay) Data valid to WR 12 t21 SR - 5 + tF + 2tA 2 ns t22 CC 13 + tC - ns Table 15 Demultiplexed bus 50/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS Max CPU Clock 50MHz Parameter Symbol min. Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR max. - - - Variable CPU Clock 1/2TCL = 1 to 50 MHz min. TCL - 5 + tF -5 + tF 0 (no tF) -9+ tF (tF>0) max. - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns 51/68 t24 t26 t28 CC CC CC 5 + tF -5 + tF 0 (no tF) -9+tF (tF>0) Address hold after WRH t28h CC t38 CC -1 (no tF) -8 +tF (t F>0) - -1 (no tF) -8 + tF (tF>0) - Latched CS setup to ALE -7 + tA 3 + tA - 3 + tA - 13 + tC + 2tA 23 + tC + 2tA - - -7 + tA TCL - 7 + tA - 3 + tA - 3TCL - 17 + tC + 2tA 4TCL - 17 + tC + 2tA - - Unlatched CS setup to ALE t38u CC Latched CS low to Valid Data In Unlatched CS low to Valid Data In Latched CS hold after RD, WR t39 SR t39u SR t41 CC - - 3 + tF 0 (no tF) -7 +tF (t F>0) TCL - 7 + tF 0 (no tF) -7 + tF (tF>0) Unlatched CS hold after RD, t41u CC WR Address setup to RdCs, WrCs (with RW-delay) Address setup to RdCs, WrCs (no RW-delay) RdCS to Valid Data In (with RW-delay) RdCS to Valid Data In (no RW-delay) RdCS, WrCS Low Time (with RW-delay) RdCS, WrCS Low Time (no RW-delay) Data valid to WrCS t82 t83 t46 t47 t48 t49 t50 CC CC SR SR CC CC CC 13 + 2tA 3 + 2tA - - 11 + tC 21 + tC 13 + tC - - 3 + tC 13 + tC - - - 2TCL - 7 + 2tA - TCL - 7 + 2tA - - 2TCL - 9 + tC 3TCL - 9 + tC 2TCL - 7 + tC - 2TCL - 17 + tC ns 3TCL - 17 + tC ns - - - Table 15 Demultiplexed bus 1 ST10R172L - ELECTRICAL CHARACTERISTICS Max CPU Clock 50MHz Parameter Symbol min. Data hold after RdCS Data float after RdCS (with RW-delay) 12 Variable CPU Clock 1/2TCL = 1 to 50 MHz min. 0 - max. - 2TCL - 7 + tF + 2tA TCL - 7 + tF + 2tA 2 2 max. - 13 + tF + 2 2tA t51 t53 SR SR 0 - ns ns Data float after RdCS (no RW-delay)1 2 t68 t55 t57 SR - 3 + tF+ 2tA2 - - - -5 + tF TCL - 7 + tF ns Address hold after RdCS, WrCS Data hold after WrCS CC CC -5 + tF 3 + tF - - ns ns Table 15 Demultiplexed bus 1) Output loading is specified using Figure 10 with CL = 5 pF. 2) This delay assumes that the following bus cycle is a demultiplexed bus cycle and that the data bus will only be driven externally when the RD or RdCs signal becomes active. RWdelay and tA refer to the following bus cycle. If the following bus cycle is a muxtiplexed bus cycle, refer to equivalent multiplexed AC timing (which are still applicable due to automatic insertion an idle state (2TCL) when switching from Demultiplexed to Multiplexed Bus Mode. 52/68 1 Unit ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT t5 ALE t16 t26 t38u t38 t39u t39 CSx t41 t41u t6 A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 t17 Address t28, t28h t18 Data In t80 t81 t14 t15 t20d t21d RD t12 t13 Write Cycle P0 BUS (D15-D8) D7-D0 Data Out t80 t81 t22 t24 WR(L), WRH t12 t13 Figure 17 External memory cycle: demultiplexed bus, with/without read/write delay, normal ALE 53/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT t5 ALE t16 t26 t38u t38 t39u t39 t6 t41 t41u CSx A23-A16 (A15-A8) BHE t17 Address t28,t28h Read Cycle P0 BUS (D15-D8) D7-D0 t18 Data In t80 t81 RD t14 t15 t21d t20d t12 t13 Write Cycle P0 BUS (D15-D8) D7-D0 Data Out t80 t81 t22 t24 WR(L), WRH t12 t13 Figure 18 External memory cycle: demultiplexed bus, with/without read/write delay, extended ALE 54/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT t5 ALE t16 t6 t26 t17 Address t55 A23-A16 (A15-A8) BHE Read Cycle P0 BUS (D15-D8) D7-D0 t51 Data In t82 t83 t46 t47 t53d t68d RdCsx t48 t49 Write Cycle P0 BUS (D15-D8) D7-D0 Data Out t82 t83 t50 t57 WrCSx t48 t49 Figure 19 External memory cycle: demultiplexed bus, with/without read/write delay, normal ALE, read/write chip select 55/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT t5 ALE A23-A16 (A15-A8) BHE t16 t17 Address t26 t6 t55 Read Cycle P0 BUS (D15-D8) D7-D0 t51 Data In t82 t83 RdCSx t46 t47 t68d t53d t48 t49 Write Cycle P0 BUS (D15-D8) D7-D0 Data Out t82 t83 t50 t57 WrCSx t48 t49 Figure 20 External memory cycle: demultiplexed bus, no read/write delay, extended ALE, read/write chip select 56/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.5 CLKOUT and READY/READY VDD = 3.3 V 0.3 V VSS = 0 V TA = -40C to +85 C Max. CPU Clock = 50 MHz min. CLKOUT cycle time CLKOUT high time CLKOUT low time CLKOUT rise time1) CLKOUT fall time1 CLKOUT rising edge to ALE falling edge Synchronous READY setup time to CLKOUT Synchronous READY hold time after CLKOUT Asynchronous READY low time Asynchronous READY setup time2) Asynchronous READY hold time 2 CL = 50 pF Parameter Symbol Variable CPU Clock 1/2TCL = 1 to 50 MHz min. 2TCL TCL - 5 TCL - 5 - - -3 + tA 9 0 2TCL + 7 9 max. 2TCL - - 31 31 5 + tA - - - - Unit ns ns ns ns ns ns ns ns ns ns ns ns 3 max. 20 - - 31 31 5 + tA - - - - t29 t30 t31 t32 t33 t34 t35 t36 t37 t58 t59 CC 20 CC 5 CC 5 CC - CC - CC -3 + tA SR 9 SR 0 SR 27 SR 9 SR 0 - 0 - Async. READY hold time t60 after RD, WR high (Demultiplexed Bus)3)2 SR 0 0 + 2tA+ tc+ tF 3 0 TCL - 10 + 2tA+ tc+ tF Table 16 CLKOUT and READY/READY 1) Measured between 0.3 and 2.7 volts 2) These timings assure recognition at a specific clock edge for test purposes only. 3) Demultiplexed bus is the worst case. For multiplexed bus, 2TCL should be added to the maximum values. This adds even more time for deactivating READY. 2tA and tC refer to the following bus cycle, tF refers to the current bus cycle. 57/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS Running cycle 1) READY waitstate MUX/Tristate 6) CLKOUT t32 t30 t34 t33 t31 t29 7) ALE Command RD, WR 2) t35 Sync t36 t35 3) t36 READY 3) t58 Async t59 3) 5) t58 3) t59 t60 4) READY t35 3) t37 t36 t35 3) t36 Sync READY t58 Async t59 3) t58 3) 5) t59 t60 4) READY t37 see 6) Figure 21 CLKOUT and READY/READY 1 2 3 Cycle as programmed, including MCTC waitstates (Example shows 0 MCTC WS). The leading edge of the respective command depends on RW-delay. READY (or READY) sampled HIGH (resp. LOW) at this sampling point generates a READY controlled waitstate, READY (resp. READY) sampled LOW (resp. HIGH) at this sampling point terminates the currently running bus cycle. READY (resp. READY) may be deactivated in response to the trailing (rising) edge of the corresponding command (RD or WR). If the Asynchronous READY (or READY) signal does not fulfill the indicated setup and hold times with respect to CLKOUT (e.g. because CLKOUT is not enabled), it must fulfill t 37 in order to be safely synchronized. This is guaranteed, if READY is removed in response to the command (see Note 4)). 4 5 58/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS 6 Multiplexed bus modes have a MUX waitstate added after a bus cycle, and an additional MTTC waitstate may be inserted here. For a multiplexed bus with MTTC waitstate this delay is 2 CLKOUT cycles, for a demultiplexed bus without MTTC waitstate this delay is zero. The next external bus cycle may start here. 7 59/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.6 External Bus Arbitration VDD = 3.3 V 0.3 V VSS = 0 V TA = -40C to +85 C CL = 50 pF Parameter Symbol Max. CPU Clock = 50 MHz min. max. - 10 10 15 15 15 15 Variable CPU Clock 1/2TCL = 1 to 50 MHz min. 15 - - - -3 - -3 max. - 10 10 15 15 15 15 Unit ns ns ns ns ns ns ns HOLD input setup time to CLKOUT CLKOUT to HLDA high or BREQ low delay CLKOUT to HLDA low or BREQ high delay CSx release CSx drive Other signals release Other signals drive t61 t62 t63 t64 t65 t66 t67 SR 15 - - - -3 - -3 CC CC CC CC CC CC Table 17 External bus arbitration 60/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT t61 HOLD t63 HLDA 1) t62 BREQ 2) t64 3) CSx (On P6.x) t66 Other Signals 1) Figure 22 External bus arbitration, releasing the bus 1 2 3 The ST10R172L will complete the running bus cycle before granting bus access. This is the first opportunity for BREQ to become active. The CS outputs will be resistive high (pullup) after t64. 61/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS CLKOUT 2) t61 HOLD t62 HLDA t62 BREQ t62 1) t63 t65 CSx (On P6.x) t67 Other Signals Figure 23 External bus arbitration, (regaining the bus) 1 This is the last chance for BREQ to trigger the regain-sequence indicated. Even if BREQ is activated earlier, the regain-sequence is initiated by HOLD going high. Please note that HOLD may also be de-activated without the ST10R172L requesting the bus. The next ST10R172L driven bus cycle may start here. 2 62/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.7 External Hardware Reset VDD = 3.3 V 0.3 V VSS = 0 V TA = -40C to +85 C CL = 50 pF Variable CPU Clock 1/2TCL = 1 to 50 MHz min. 4 TCL + 10 4 1024 max. - 16 1024 Unit ns TCL TCL TCL ns TCL ns ns TCL ns 63/68 Parameter Symbol Max. CPU Clock = 50 MHz min. max. - 16 1024 Sync. RSTIN low time1) RSTIN low to internal reset sequence start internal reset sequence, (RSTIN internally pulled low) t70 t71 t72 SR CC 50 4 1024 CC RSTIN rising edge to inter- t73 nal reset condition end PORT0 system start-up configuration setup to RSTIN rising edge 2)) PORT0 system start-up configuration hold after RSTIN rising edge Bus signals drive from internal reset end RSTIN low to signals release CC 4 100 6 - 4 100 6 - t74 SR t75 SR 1 6 1 6 t76 t77 CC 0 - 8 1500 20 50 8 - 0 - 8 1500 20 50 8 - CC ALE rising edge from inter- t78 nal reset condition end Async. RSTIN low time1 CC t79 SR Table 18 External hardware reset 1) On power-up reset, the RSTIN pin must be asserted until a stable clock signal is available (about 10...50 ms to allow the on-chip oscillator to stabilize) and until System Start-up Configuration is correct on PORT0 (about 50 s for internal pullup devices to load 50 pF from VILmin to VIHmin). 2) The value of bits 0 (EMU), 1 (ADAPT), 13 to 15 (Clock Configuration) are loaded during hardware reset as long as internal reset signal is active, and have an immediate effect on the system. 1 ST10R172L - ELECTRICAL CHARACTERISTICS 1) t792) RSTIN t73 t76 Internal Reset Signal ALE t78 RD, WR 3) t74 t75 4) PORT0 PORT1 (Demux Bus) RSTOUT 5) Other IOs 6) t77 Figure 24 External asynchronous hardware reset (power-up reset): Vpp low 1 2 3 The ST10R172L is reset in its default state asynchronously with RSTIN. The internal RAM content may be altered if an internal write access is in progress. On power-up, RSTIN must be asserted t79 after a stabilized CPU clock signal is available. Internal pullup devices are active on the PORT0 lines, so - input level is high if the respective pin is left open - or is low if the respective pin is connected to an external pulldown device. The ST10R172L starts execution here at address 00'0000h. RSTOUT stays active until execution of the EINIT (end of initialization) instruction. Activation of the IO pins is controlled by software 4 5 6 64/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS . t70 RSTIN t722) t711) Internal Reset Signal ALE 3) t73 t76 t78 RD, WR 4) t74 t75 5) PORT0 PORT1 (Demux Bus) RSTOUT 6) Other IOs 7) t77 Figure 25 External synchronous hardware reset (warm reset): Vpp high 1 2 3 4 The pending internal hold states are cancelled and the current internal access cycle (if any) is completed. RSTIN pulled low by internal device during internal reset sequence. The reset condition may ends here if RSTIN pin is sampled high after t72. Internal pullup devices are active on the PORT0 lines. Their input level is high if the respective pin is left open, or is low if the respective pin is connected to an external pulldown device by resistive high (pullup) after t64 . The ST10R172L starts execution here at address 00'0000h. RSTOUT stays active until execution of the EINIT (End of Initialization) instruction. Activation of the IO pins is controlled by software. 5 6 7 65/68 1 ST10R172L - ELECTRICAL CHARACTERISTICS 15.3.8 Synchronous Serial Port Timing VCC = 3.3 V 0.3 V VSS = 0 V TA = -40C to +85 C Max. Baudrate Parameter Symbol = 25 MBd min. SSP clock cycle time SSP clock high time SSP clock low time SSP clock rise time SSP clock fall time CE active before shift edge CE inactive after latch edge Write data valid after shift edge Write data hold after shift edge Write data hold after latch edge Read data active after latch edge max. 40 - - 3 3 - 47 7 - 25 - - - CL = 50 pF Variable Baudrate = 0.2 to 25 MBd min. max. 512 TCL - - 3 3 - ns ns ns ns ns ns ns ns ns ns ns ns ns t200 CC t201 CC t202 CC t203 CC t204 CC t205 CC t206 CC t207 CC t208 CC t209 CC t210 SR SR 40 13 13 - - 13 33 - 0 15 27 15 0 4 TCL t200/2 - 7 t200/2 - 7 - - t200/2 - 7 t200 - 7 - 0 t200 + 7 7 - t200/2 - 5 t200/2 + 7 15 0 t200/2 + 5 - - - Read data setup time before latch edge t211 Read data hold time after latch edge t212 SR Table 19 Synchronous serial port timing 66/68 1 Unit ST10R172L - ELECTRICAL CHARACTERISTICS t200 1) t202 t201 2) SSPCLK t203 t205 SSPCEx t204 t206 3) t207 SSPDAT 1st Bit t207 2nd Bit t208 t207 t209 Last Bit Figure 26 SSP write timing 1) 2) SSPCLK t206 SSPCEx 3) t210 t209 SSPDAT last Wr. Bit t211 1st.In Bit t212 Lst.In Bit Figure 27 SSP read timing 1 2 3 The transition of shift and latch edge of SSPCLK is programmable. This figure uses the falling edge as shift edge (drawn bold). The bit timing is repeated for all bits to be transmitted or received. The active level of the chip enable lines is programmable. This figure uses an active low CE (drawn bold). At the end of a transmission or reception the CE signal is disabled in single transfer mode. In continuous transfer mode it remains active. 67/68 1 ST10R172L - PACKAGE MECHANICAL DATA 16 PACKAGE MECHANICAL DATA Dim Min A A2 D D1 D3 E E1 E3 e 15.75 13.90 1.35 15.75 13.90 mm Typ Max 1.60 1.40 16.00 14.00 12.00 16.00 14.00 12.00 0.50 Number of Pins 16.25 14.10 0.620 0.547 1.45 16.25 14.10 0.053 0.620 0.547 Min inches Typ Max 0.063 0.055 0.630 0.551 0.472 0.630 0.551 0.472 0.020 0.640 0.555 0.057 0.640 0.555 ND NE N 25 25 100 Figure 28 Package outline TQFP100 (14 x 14 mm) 17 ORDERING INFORMATION Sales type ST10R172LT1 ST10R172LT6 Temperature range 0C to 70C TQFP100 (14x 14) -40C to +85 C Package Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without the express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c)2001 STMicroelectronics - All Rights Reserved. Purchase of I2C Components by STMicroelectronics conveys a license under the Philips I2C Patent. Rights to use these components in an I2C system is granted provided that the system conforms to the I2C Standard Specification as defined by Philips. STMicroelectronics Group of Companies Australia - Brazil - China - Finland - France - Germany - Hong Kong - India - Italy - Japan - Malaysia - Malta - Morocco - Singapore - Spain Sweden - Switzerland - United Kingdom - U.S.A. http://www.st.com 68/68 1 |
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