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| STSJ2NM60 N-CHANNEL 600V - 2.8 - 2A PowerSO-8 Zener-Protected MDmeshTM POWER MOSFET TYPE STSJ2NM60 s s s s VDSS 600 V RDS(on) < 3.2 ID 2A s s TYPICAL RDS(on) = 2.8 HIGH dv/dt AND AVALANCHE CAPABILITIES IMPROVED ESD CAPABILITY LOW INPUT CAPACITANCE AND GATE CHARGE LOW GATE INPUT RESISTANCE TIGHT PROCESS CONTROL AND HIGH MANUFACTORING YIELDS PowerSO-8 DESCRIPTION The MDmeshTM is a new revolutionary MOSFET technology that associates the Multiple Drain process with the Company's PowerMESHTM horizontal layout. The resulting product has an outstanding low on-resistance, impressively high dv/dt and excellent avalanche characteristics. The adoption of the Company's proprietary strip technique yields overall dynamic performance that is significantly better than that of similar completition's products. INTERNAL SCHEMATIC DIAGRAM APPLICATIONS The MDmeshTM family is very suitable for increase the power density of high voltage converters allowing system miniaturization and higher efficiencies. ABSOLUTE MAXIMUM RATINGS Symbol VDS VDGR VGS ID Parameter Drain-source Voltage (VGS = 0) Drain-gate Voltage (RGS = 20 k) Gate- source Voltage Drain Current (continuous) at TC = 25C Drain Current (continuous) at TA = 25C (1) Drain Current (continuous) at TC = 100C Drain Current (pulsed) Total Dissipation at TC = 25C Total Dissipation at TA = 25C (1) Derating Factor (1) dv/dt (3) Tstg Tj August 2002 Peak Diode Recovery voltage slope Storage Temperature Max. Operating Junction Temperature DRAIN CONTACT ALSO ON THE BACKSIDE Value 600 600 30 2 0.37 1.26 8 70 3 0.02 15 - 65 to 150 Unit V V V A A A A W W W/C V/ns C IDM (2) PTOT PTOT 1/8 STSJ2NM60 THERMAL DATA Rthj-c Rthj-amb Tj Tstg Thermal Resistance Junction-case Max Thermal Resistance Junction-ambient Max (1) Max. Operating Junction Temperature Storage Temperature 1.78 42 150 - 65 to 150 C/W C/W C C ELECTRICAL CHARACTERISTICS (TCASE = 25 C UNLESS OTHERWISE SPECIFIED) OFF Symbol V(BR)DSS IDSS IGSS Parameter Drain-source Breakdown Voltage Zero Gate Voltage Drain Current (VGS = 0) Gate-body Leakage Current (VDS = 0) Test Conditions ID = 1 mA, VGS = 0 VDS = Max Rating VDS = Max Rating, TC = 125 C VGS = 20V Min. 600 1 10 5 Typ. Max. Unit V A A A ON (1) Symbol VGS(th) RDS(on) Parameter Gate Threshold Voltage Static Drain-source On Resistance Test Conditions VDS = VGS, ID = 250A VGS = 10 V, ID = 1 A Min. 3 Typ. 4 2.8 Max. 5 3.2 Unit V DYNAMIC Symbol gfs (4) Ciss Coss Crss RG Parameter Forward Transconductance Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Input Resistance f=1 MHz Gate DC Bias = 0 Test Signal Level = 20mV Open Drain Test Conditions VDS > ID(on) x RDS(on)max, ID = 2 A VDS = 25 V, f = 1 MHz, VGS = 0 Min. Typ. 1.4 160 67 4 3.5 Max. Unit S pF pF pF 2/8 STSJ2NM60 ELECTRICAL CHARACTERISTICS (CONTINUED) SWITCHING ON Symbol td(on) tr Qg Qgs Qgd Parameter Turn-on Delay Time Rise Time Total Gate Charge Gate-Source Charge Gate-Drain Charge Test Conditions VDD = 300 V, ID = 1 A RG = 4.7 VGS = 10 V (see test circuit, Figure 3) VDD = 480 V, ID = 2 A, VGS = 10 V Min. Typ. 13 8 6 1.8 3.3 8.4 Max. Unit ns ns nC nC nC SWITCHING OFF Symbol tr(Voff) tf tc Parameter Off-Voltage Rise Time Fall Time Cross-Over Time Test Conditions VDD = 480 V, ID = 2 A, RG = 4.7, VGS = 10 V (see test circuit, Figure 3) Min. Typ. 12 25 30 Max. Unit ns ns ns SOURCE DRAIN DIODE Symbol ISD ISDM (2) VSD (4) trr Qrr IRRM trr Qrr IRRM Note: 1. 2. 3. 4. Parameter Source-drain Current Source-drain Current (pulsed) Forward On Voltage Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Reverse Recovery Time Reverse Recovery Charge Reverse Recovery Current Test Conditions Min. Typ. Max. 2 8 Unit A A V ns nC A ns nC A ISD = 2 A, VGS = 0 ISD = 2, di/dt = 100A/s, VDD = 100 V, Tj = 25C (see test circuit, Figure 5) ISD = 2, di/dt = 100A/s, VDD = 100 V, Tj = 150C (see test circuit, Figure 5) 516 516 2 808 890 2.2 1.5 When mounted on 1inch FR4 Board, 2oz of Cu, t 10 sec. Pulse width limited by safe operating area ISD<3.3A, di/dt<400A/s, VDD Symbol BVGSO Parameter Gate-Source Breakdown Voltage Test Conditions Igs= 1mA (Open Drain) Min. 30 Typ. Max. Unit V PROTECTION FEATURES OF GATE-TO-SOURCE ZENER DIODES The built-in back-to-back Zener diodes have specifically been designed to enhance not only the device's ESD capability, but also to make them safely absorb possible voltage transients that may occasionally be applied from gate to source. In this respect the Zener voltage is appropriate to achieve an efficient and cost-effective intervention to protect the device's integrity. These integrated Zener diodes thus avoid the usage of external components. 3/8 STSJ2NM60 Output Characteristics Transfer Characteristics Transconductance Static Drain-source On Resistance Gate Charge vs Gate-source Voltage Capacitance Variations 4/8 STSJ2NM60 Normalized Gate Thereshold Voltage vs Temp. Normalized On Resistance vs Temperature Source-drain Diode Forward Characteristics Normalized BVDSS vs. Temperature 5/8 STSJ2NM60 Fig. 1: Unclamped Inductive Load Test Circuit Fig. 2: Unclamped Inductive Waveform Fig. 3: Switching Times Test Circuit For Resistive Load Fig. 4: Gate Charge test Circuit Fig. 5: Test Circuit For Inductive Load Switching And Diode Recovery Times 6/8 STSJ2NM60 PowerSO-8TM MECHANICAL DATA mm. MIN. 0.1 0.65 0.35 0.19 0.25 4.8 5.8 1.27 3.81 2.79 3.8 0.4 4.0 1.27 0.6 8 (max.) 0.14 0.015 TYP MAX. 1.75 0.25 1.65 0.85 0.48 0.25 0.5 45 (typ.) 5.0 6.2 0.188 0.228 0.050 0.150 0.110 0.157 0.050 0.023 0.196 0.244 0.025 0.013 0.007 0.010 0.003 MIN. inch TYP. MAX. 0.068 0.009 0.064 0.033 0.018 0.010 0.019 DIM. A a1 a2 a3 b b1 C c1 D E e e3 e4 F L M S 7/8 STSJ2NM60 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. (c) The ST logo is a registered trademark of STMicroelectronics (c) 2002 STMicroelectronics - Printed in Italy - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan - Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. (c) http://www.st.com 8/8 |
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