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| Micrel SynergyTM High-Speed Products 3.3V 1:4 CLOCK DISTRIBUTION DESCRIPTION ClockWorksTM SY100EL15L ClockWorksTM SY100EL15L FEATURES s s s s s s s s 3.3V power supply 50ps output-to-output skew Low power Synchronous enable/disable Multiplexed clock input 75K internal input pull-down resistors ESD protection of 2000V Available in 16-pin SOIC package PIN CONFIGURATION/BLOCK DIAGRAM VCC 16 EN SCLK CLK CLK VBB 15 14 13 1 D Q 0 12 11 SEL VEE 10 9 1 Q0 2 Q0 3 Q1 4 Q1 5 Q2 6 Q2 7 Q3 8 The SY100EL15L is a low skew 1:4 clock distribution IC designed explicitly for low skew clock distribution applications. The device can be driven by either a differential or single-ended ECL or, if positive power supplies are used, PECL input signal. If a single-ended input is to be used the VBB output should be connected to the CLK input and bypassed to ground via a 0.01F capacitor. The VBB output is designed to act as the switching reference for the input of the EL15 under singleended input conditions. As a result, this pin can only source/sink up to 0.5mA of current. The EL15 features a multiplexed clock input to allow for the distribution of a lower speed scan or test clock along with the high speed system clock. When LOW (or left open and pulled LOW by the input pull-down resistor) the SEL pin will select the differential clock input. The common enable (EN) is synchronous so that the outputs will only be enabled/disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/ disabled as can happen with an asynchronous control. The internal flip flop is clocked on the falling edge of the input clock, therefore all associated specification limits are referenced to the negative edge of the clock input. When both differential inputs are left open, CLK input will pull down to VEE and CLK input will bias around VCC/2. Q3 SOIC TOP VIEW PIN NAMES Pin CLK SCLK EN SEL VBB Q0-3 Function Differential Clock Inputs Synchronous Clock Input Synchronous Enable Clock Select Input Reference Output Differential Clock Outputs TRUTH TABLE CLK L H X X X SCLK X X L H X SEL L L H H X EN L L L L H Q L H L H L* * On next negative transition of CLK or SCLK (c) 1999 Micrel Rev.: A Amendment: /0 1 Issue Date: December 1999 Micrel ClockWorksTM SY100EL15L ABSOLUTE MAXIMUM RATINGS(1) Symbol VEE VI IOUT Power Supply (VCC = 0V) Input Voltage (VCC = 0V) Output Current -Continuous -Surge TA Operating Temperature Range 50 100 -40 to +85 mA C Rating Value -8.0 to 0 0 to -6.0 Unit VDC VDC NOTES: 1. Absolute maximum rating, beyond which, device life may be impaired, unless otherwise specified on an individual data sheet. 2. Parametric values specified at: 3 volt Power Supply Range 100EL15L Series -3.0V to -3.8V. DC ELECTRICAL CHARACTERISTICS VEE = 3.3V 10%; VCC = GND(1) TA = -40C Symbol VOH VOL VOHA VOLA VIH VIL IIH IIL IEE VBB Parameter Output HIGH Output LOW Output HIGH Output LOW Voltage(2) Voltage(2) Voltage(3) Voltage(3) Min. -1085 -1830 -1095 -- -1165 -1810 -- CLK Power Supply Current Output Reference Voltage 0.5 -300 -- -1.38 Max. -880 -1555 -- -1555 -880 -1475 150 -- -- 35 -1.26 TA = 0C Min. -1025 -1810 -1035 -- -1165 -1810 -- 0.5 -300 -- -1.38 Max. -880 -1620 -- -1610 -880 -1475 150 -- -- 35 -1.26 Min. -1025 -1810 -1035 -- -1165 -1810 -- 0.5 -300 -- -1.38 TA = +25C Typ. -955 -1705 -- -- -- -- -- -- 25 -- Max. -880 -1620 -- -1610 -880 -1475 150 -- -- 35 -1.26 TA = +85C Min. -1025 -1810 -1035 -- -1165 -1810 -- 0.5 -300 -- -1.38 Max. -880 -1620 -- -1610 -880 -1475 150 -- -- 38 -1.26 Unit mV mV mV mV mV mV A A mA V Input HIGH Voltage Input LOW Voltage Input High Current Input LOW Current(4) NOTES: 1. This table replaces the three traditionally seen in ECL 100K data books. Outputs are terminated through a 50 resistor to -2.0V. 2. VIN = VIH(Max) or VIL(Min). 3. VIN = VIH(Min) or VIL(Max). 4. VIN = VIL(Max). 2 Micrel ClockWorksTM SY100EL15L AC ELECTRICAL CHARACTERISTICS VEE = 3.3V 10%; VCC = GND(1) TA = -40C Symbol tPLH tPHL Parameter Propagation Delay CLK to Q (Diff) CLK to Q (SE) SCLK to Q Part-to-Part Skew(1) Within-Device Skew Setup Time EN Hold Time EN Minimum Input Swing CLK Common Mode VPP < 500mV VPP 500mV Output Rise/Fall TimesQ (20% - 80%) Range(2) -2.0 -1.8 375 -0.4 -0.4 625 -2.1 -1.9 325 -0.4 -0.4 575 -2.1 -1.9 325 -- -- -- -0.4 -0.4 575 -2.1 -1.9 325 -0.4 -0.4 575 ps Min. 460 410 410 -- -- 150 400 250 Max. 660 710 710 200 50 -- -- -- TA = 0C Min. 470 420 420 -- -- 150 400 250 Max. 670 720 720 200 50 -- -- -- Min. 470 420 420 -- -- 150 400 250 TA = +25C Typ. -- -- -- -- -- -- -- -- Max. 670 720 720 200 50 -- -- -- TA = +85C Min. 500 450 470 -- -- 150 400 250 Max. 700 750 750 200 50 -- -- -- ps ps ps mV mV Unit ps tskew tS tH VPP VCMR tr tf NOTES: 1. Skews are specified for identical LOW-to-HIGH or HIGH-to-LOW transitions. 2. VCMR is referenced to the most positive side of the differential input signal. Normal operation is obtained when the input signals are within the VCMR range and the input swing is greater than VPP(Min.) and <1V. The lower end of the VCMR range varies 1:1 with VEE. The numbers in the spec table assume a nominal VEE = -3.3V. Note for PECL operation, the VCMR(Min) will be fixed at 3.3V - |VCMR(Min)|. PRODUCT ORDERING CODE Ordering Code SY100EL15LZC SY100EL15LZCTR Package Type Z16-2 Z16-2 Operating Range Commercial Commercial 3 Micrel ClockWorksTM SY100EL15L 16 LEAD PLASTIC SOIC .150" WIDE (Z16-2) MICREL-SYNERGY TEL 3250 SCOTT BOULEVARD SANTA CLARA CA 95054 USA + 1 (408) 914-7878 WEB + 1 (408) 980-9191 FAX http://www.synergysemi.com http://www.micrel.com This information is believed to be accurate and reliable, however no responsibility is assumed by Micrel for its use nor for any infringement of patents or other rights of third parties resulting from its use. No license is granted by implication or otherwise under any patent or patent right of Micrel Inc. (c) 1999 Micrel Incorporated 4 |
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