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Micrel, Inc.
3.3V 1:9 HIGH-PERFORMANCE, LOW-VOLTAGE BUS CLOCK DRIVER
Precision Edge(R) SY89809L Precision Edge(R)
SY89809L
FEATURES
s 3.3V core supply, 1.8V output supply for reduced s s s s s s s
power LVPECL and HSTL inputs 9 differential HSTL (low-voltage swing) output pairs HSTL outputs drive 50 to ground with no offset voltage 500MHz maximum clock frequency Low part-to-part skew (200ps max.) Low pin-to-pin skew (50ps max.) Available in 32-pin TQFP package
Precision Edge(R)
DESCRIPTION
The SY89809L is a High-Performance Bus Clock Driver with 9 differential HSTL (High-Speed Transceiver Logic) output pairs. The part is designed for use in low-voltage (3.3V/1.8V) applications which require a large number of outputs to drive precisely aligned, ultralow skew signals to their destination. The input is multiplexed from either HSTL or LVPECL (Low-Voltage Positive-Emitter-Coupled Logic) by the CLK_SEL pin. The Output Enable (OE) is synchronous so that the outputs will only be enabled/ disabled when they are already in the LOW state. This avoids any chance of generating a runt clock pulse when the device is enabled/disabled as can happen with an asynchronous control. The SY89809L features low pin-to-pin skew (50ps max.) and low part-to-part skew (200ps max.)--performance previously unachievable in a standard product having such a high number of outputs. The SY89809L is available in a single space saving package, enabling a lower overall cost solution.
LOGIC SYMBOL
CLK_SEL HSTL_CLK /HSTL_CLK 0 9 9 LVPECL_CLK 1 /LVPECL_CLK
LEN Q
Q0 - Q8 /Q0 - /Q8
OE
D
APPLICATIONS
s High-performance PCs s Workstations s Parallel processor-based systems s Other high-performance computing s Communications
TRUTH TABLE
OE(1) 0 0 1 1 CLK_SEL 0 1 0 1 Q0 - Q8 LOW LOW HSTL_CLK LVPECL_CLK /Q0 - /Q8 HIGH HIGH /HSTL_CLK /LVPECL_CLK
SIGNAL GROUPS
Level HSTL HSTL LVPECL LVCMOS/LVTTL Direction Input Output Input Input Signal HSTL_CLK, /HSTL_CLK Q0 - Q8, /Q0 - /Q8 LVPECL_CLK, /LVPECL_CLK CLK_SEL, OE
Note: 1. The OE (output enable) signal is synchronized with the low level of the HSTL_CLK and LVPECL_CLK signal.
Precision Edge is a registered trademark of Micrel, Inc. M9999-092005 hbwhelp@micrel.com or (408) 955-1690
Rev.: E Amendment: /0
1
Issue Date: September 2005
Micrel, Inc.
Precision Edge(R) SY89809L
PACKAGE/ORDERING INFORMATION
VCCO Q0 Q1 VCCO /Q0 /Q1 /Q2 Q2
Ordering Information(1)
Part Number
VCCO Q3 /Q3 Q4 /Q4 Q5 /Q5 VCCO
VCCI HSTL_CLK /HSTL_CLK CLK_SEL LVPECL_CLK /LVPECL_CLK GND OE
32 31 30 29 28 27 26 25 24 1 2 3 4 5 6 7 8 23 22
Package Type T32-1 T32-1 T32-1 T32-1
Operating Range Industrial Industrial Industrial Industrial
Package Marking SY89809LTC SY89809LTC
Lead Finish Sn-Pb Sn-Pb
SY89809LTC SY89809LTCTR(2) SY89809LTH(3) SY89809LTHTR(2, 3)
Top View TQFP T32-1
21 20 19 18
SY89809LTH with NiPdAu Pb-Free bar line indicator Pb-Free SY89809LTH with NiPdAu Pb-Free bar line indicator Pb-Free
17 9 10 11 12 13 14 15 16
VCCO VCCO /Q8 /Q7 /Q6 Q8 Q7 Q6
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel. 3. Pb-Free package is recommended for new designs.
32-Pin TQFP (T32-1)
PIN DESCRIPTION
Pin Number 2, 3 Pin Name HSTL_CLK, /HSTL_CLK LVPECL_CLK, /LVPECL_CLK CLK_SEL OE Type HSTL Input LVPECL Input LVTTL Input LVTTL Input Pin Function Differential clock input selected by CLK_SEL. Can be left floating if not selected. Floating input, if selected produces an indeterminate output. HSTL input signal requires external termination 50 to GND. Differential clock input selected by CLK_SEL. Can be left floating. Floating input, if selected produces a LOW at the output (internal 75 pull-downs). Requires external termination. 75k pull-up. Selects HSTL_CLK input when LOW and LVPECL_CLK output when HIGH. 11k pull-up. Enable input synchronized internally to prevent glitching of the Q0-Q8 and /Q0-/Q8 outputs. Must be a minimum of three clock periods wide if synchronous with the CLK inputs and must meet the tS and tH requirements (refer to AC Electrical Characteristics). If asynchronous, must be a minimum of four clock periods wide. 11k pull-up. Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated with 50 to GND. Q0-Q8 outputs are static LOW when OE = LOW. Unused output pairs may be left floating. Differential clock outputs from HSTL_CLK when CLK_SEL = LOW and LVPECL outputs when CLK_SEL = HIGH. HSTL outputs must be terminated with 50 to GND. /Q0-/Q8 outputs are static HIGH when OE = LOW. Unused output pairs may be left floating. Core VCC connected to 3.3V supply. Bypass with 0.1F in parallel with 0.01F low ESR capacitors as close to VCCI pin as possible. Output Buffer VCC connected to 1.8V supply. Bypass with 0.1F in parallel with 0.01F low ESR capacitors as close to VCCO pins as possible. All VCCO pins should be connected together on the PCB. Ground.
5, 6
4 8
31, 29, 27, 23, 21, 19, 15, 13, 11 30, 28, 26, 22, 20, 18, 14, 12, 10 1 9, 16, 17, 24, 25, 32 7
Q0-Q8
HSTL Output
/Q0-/Q8
HSTL Output
VCCI VCCO
VCC Core Power VCC Output Power Ground
GND
M9999-092005 hbwhelp@micrel.com or (408) 955-1690
2
Micrel, Inc.
Precision Edge(R) SY89809L
Absolute Maximum Ratings(1)
Supply Voltage (VIN) ..................................... -0.5V to VCCI VCC Pin Potential to Ground Pin (VCCI, VCCO) ............................................ -0.5V to +4.0V DC Output Current, Output HIGH (IOUT) .................. -50mA Lead Temperature (soldering, 20 sec.) ..................... 260C Storage Temperature (TS) ....................... -65C to +150C
Operating Ratings(2)
Supply Voltage (VCCI) ............................................... +3.15V to +3.45V (VCCO) ................................................. +1.6V to +2.0V Ambient Temperature (TA) ......................... -40C to +85C Package Thermal Resistance TQFP (JA) -Still-Air ........................................................... 50C/W -500lfpm .......................................................... 42C/W TQFP (JC) .......................................................... 20C/W
DC ELECTRICAL CHARACTERISTICS
Power Supply
TA = 0C Symbol VCCI VCCO ICCI Parameter VCC Core VCC Output ICC Core Min. 3.0 1.6 -- Typ. 3.3 1.8 115 Max. 3.6 2.0 140 Min. 3.0 1.6 -- TA = +25C Typ. 3.3 1.8 115 Max. 3.6 2.0 140 Min. 3.0 1.6 -- TA = +85C Typ. 3.3 1.8 115 Max. 3.6 2.0 140 Unit V V mA
HSTL
TA = 0C Symbol VOH VOL VIH VIL VX IIH IIL Parameter Output HIGH Voltage(3) Output LOW Voltage(3) Min. 1.0 0.2 VX +0.1 -0.3 0.68 +20 -- Typ. -- -- -- -- -- -- -- Max. 1.2 0.4 1.6 VX -0.1 0.9 -350 -500 Min. 1.0 0.2 VX +0.1 -0.3 0.68 +20 -- TA = +25C Typ. -- -- -- -- -- -- -- Max. 1.2 0.4 1.6 VX -0.1 0.9 -350 -500 Min. 1.0 0.2 VX +0.1 -0.3 0.68 +20 -- TA = +85C Typ. -- -- -- -- -- -- -- Max. 1.2 0.4 1.6 VX -0.1 0.9 -350 -500 Unit V V V V V A A
Input HIGH Voltage Input LOW Voltage Input Crossover Voltage Input HIGH Current Input LOW Current
Notes: 1. Permanent device damage may occur if "Absolute Maximum Ratings" are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratlng conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Outputs loaded with 50 to ground.
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Micrel, Inc.
Precision Edge(R) SY89809L
DC ELECTRICAL CHARACTERISTICS (continued)
LVPECL
TA = 0C Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Min. Max. TA = +25C Min. Max. TA = +85C Min. Max. Unit V V A A
VCCI - 1.165 VCCI - 0.880 VCCI - 1.165 VCCI - 0.880 VCCI - 1.165 VCCI - 0.880 VCCI - 1.810 VCCI - 1.475 VCCI - 1.810 VCCI - 1.475 VCCI - 1.810 VCCI - 1.475 -- 0.5 +150 -- -- 0.5 +150 -- -- 0.5 +150 --
LVCMOS/LVTTL
TA = 0C Symbol VIH VIL IIH IIL Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current Min. 2.0 -- +20 -- Typ. -- -- -- -- Max. -- 0.8 -250 -600 Min. 2.0 -- +20 -- TA = +25C Typ. -- -- -- -- Max. -- 0.8 -250 -600 Min. 2.0 -- +20 -- TA = +85C Typ. -- -- -- -- Max. -- 0.8 -250 -600 Unit V V A A
M9999-092005 hbwhelp@micrel.com or (408) 955-1690
4
Micrel, Inc.
Precision Edge(R) SY89809L
AC ELECTRICAL CHARACTERISTICS(4)
TA = 0C Symbol tPHL tPLH fMAX tSKEW tSKPP VPP VCMR tS tH tr tf Parameter Propagation Delay(5) Min. -- 500 -- -- 600 -1.5 1.0 0.5 300 Typ. 1.0 -- -- -- -- -- -- -- -- Max. -- -- 50 200 -- -0.4 -- -- 650 Min. -- 500 -- -- 600 -1.5 1.0 0.5 300 TA = +25C Typ. 1.0 -- -- -- -- -- -- -- -- Max. -- -- 50 200 -- -0.4 -- -- 650 -- 500 -- -- 600 -1.5 1.0 0.5 300 TA = +85C Min. Typ. 1.0 -- -- -- -- -- -- -- -- Max. -- -- 50 200 -- -0.4 -- -- 650 Unit ns MHz ps ps mV V ns ns ps
Maximum Operating Freq.(6) Within-Device Skew(7) Part-to-Part Skew(8) Swing(9) Minimum Input LVPECL_CLK
Common Mode Range(10) LVPECL_CLK OE Set-Up Time(11) OE Hold Time Output Rise/Fall Time (20% - 80%)
Notes: 4. Outputs loaded with 50 to ground. Airflow 300lfpm. 5. Differential propagation delay is defined as the delay from the crossing point of the differential input signals to the crossing point of the differential output signals. 6. Output swing greater than 450mV. 7. The within-device skew is defined as the worst case difference between any two similar delay paths within a single device operating at the same voltage and temperature. 8. The part-to-part skew is defined as the absolute worst case difference between any two delay paths on any two devices operating at the same voltage and temperature. 9. The VPP(min.) is defined as the minimum input differential voltage which will cause no increase in the propagation delay. 10. VCMR is defined as the range within which the VIH level may vary, with the device still meeting the propagation delay specification. The numbers in the table are referenced to VCCI. The VIL level must be such that the peak-to-peak voltage is less than 1.0V and greater than or equal to VPP(min.). The lower end of the CMR range varies 1:1 with VCCI. The VCMR(min) will be fixed at 3.3V - |VCMR(min)|. 11. OE set-up time is defined with respect to the rising edge of the clock. OE HIGH-to-LOW transition ensures outputs remain disabled during the next clock cycle. OE LOW-to-HIGH transition enables normal operation of the next input clock.
M9999-092005 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89809L
OUTPUT WAVEFORMS
/Q (180mV/div)
Q (100mV/div)
TA = 25C
VCCI = 3.0V VCCO = 1.6V
TIME (2ns/div)
Figure 1. 100MHz Output Waveform
/Q (180mV/div)
Q (100mV/div)
TA = 25C
VCCI = 3.0V VCCO = 1.6V
TIME (2ns/div)
Figure 2. 300MHz Output Waveform
M9999-092005 hbwhelp@micrel.com or (408) 955-1690
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Micrel, Inc.
Precision Edge(R) SY89809L
32 LEAD TQFP (T32-1)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131
TEL
USA
+ 1 (408) 944-0800
FAX
+ 1 (408) 474-1000
WEB
http://www.micrel.com
The information furnished by Micrel in this datasheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is at Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2005 Micrel, Incorporated. M9999-092005 hbwhelp@micrel.com or (408) 955-1690
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