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INTEGRATED CIRCUITS
DATA SHEET
TDA8786; TDA8786A 10-bit analog-to-digital interface for CCD cameras
Product specification Supersedes data of 1997 May 20 File under Integrated Circuits, IC02 1997 Nov 17
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
FEATURES * Correlated Double Sampling (CDS), AGC, soft clipper, pre-blanking, 10-bit ADC and reference regulator included * Fully programmable via a 3-wire serial interface * Sampling frequency up to 18 MHz * AGC gain from 3.5 to 33.5 dB (in 0.1 dB steps) * Programmable soft clipper for white compression (starting at 40% of the input signal) * Standby mode available for each block for power saving applications (19 mW) * 6 dB fixed gain analog output for analog iris control * 8-bit and 10-bit DAC included for analog settings * Low power consumption of only 475 mW (typ.) * 5 V operation and 2.5 to 5 V operation for the digital outputs * CDS control pulse: TDA8786 = HIGH; TDA8786A = LOW * TTL compatible inputs, TTL and CMOS compatible outputs. QUICK REFERENCE DATA SYMBOL VCCA VCCD VCCO ICCA ICCD ICCO ADCres Vi(CDS)(p-p) GCDS fCLK(max) AGCdyn Ntot(rms) Ptot PARAMETER analog supply voltage digital supply voltage digital outputs supply voltage analog supply current digital supply current digital outputs supply current ADC resolution CDS input voltage (peak-to-peak value) CDS output amplifier gain maximum clock frequency AGC dynamic range total noise from CDS input to ADC output (RMS value) total power consumption CONDITIONS APPLICATIONS
TDA8786; TDA8786A
GENERAL DESCRIPTION The TDA8786; TDA8786A is a 10-bit analog-to-digital interface for CCD cameras. The device includes a correlated double sampling circuit, AGC, a soft clipper circuit and a low power 10-bit Analog-to-Digital Converter (ADC) together with its reference voltage regulator. The AGC and soft clipper circuits are controlled by on-chip DACs via a serial interface. A 10-bit DAC controls the ADC input clamp level. A pre-blanking function is also included. An additional DAC is provided for additional system controls; its output voltage range is 1.4 V (p-p) which is available at pin OFDOUT.
* CCD camera systems.
MIN. 4.5 4.5 2.5 - - - - - - 18 - - -
TYP. 4.75 4.75 2.6 83 16 1 10 400 6 - 30 0.5 475
MAX. 5.5 5.5 5.5 - - - - 1200 - - - - -
UNIT V V V mA mA mA bits mV dB MHz dB LSB mW
fCLK = 18 MHz; CL = 20 pF; ramp input
gain = 3.5 dB
ORDERING INFORMATION TYPE NUMBER TDA8786G TDA8786AG 1997 Nov 17 PACKAGE NAME LQFP48 DESCRIPTION plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm 2 VERSION SOT313-2
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
BLOCK DIAGRAM
TDA8786; TDA8786A
handbook, full pagewidth
VCCA3 IN2 47 IN1 46 AGND3 48 45 CDSP2 44 CDSP1 43 CLPCDS 42 CLK 41
DGND2
VCCD2 39
VCCO OE 38 37
40
36 TRACKAND-HOLD TRACKAND-HOLD TRACKAND-HOLD CLOCK GENERATOR 35
OGND
TRACKAND-HOLD 19 5 CLAMP
TRACKAND-HOLD
D9
34 CLAMP ref2 33
STGE AGND1
D8
D7
TDA8786 TDA8786A
AMPOUT PBK 4 2 10-BIT ADC AGCOUT CLPOPB 7 1 ref1 PBIN VCCA1 PBOUT ADCIN 8 6 4-BIT DAC 9 10 1 OPTICAL BLACK CLAMP 9-BIT DAC 1 SOFT CLIPPER AGC OUTPUTS BUFFER +6 dB
32
D6
31
D5
30
D4
29
D3
28
D2
27
D1
26 25 10-BIT DAC 8-BIT DAC REGULATOR SERIAL INTERFACE 3
D0 DGND1 OFDOUT
CLPADC
11
CLAMP 12 13 14 15
16
17 VRT
18
23
22
21
20
24 VCCD1
MGE361
Vref
VCCA2 DACOUT AGND2
STDBY SEN DEC1
VRB
SDATA SCLK
Fig.1 Block diagram.
1997 Nov 17
3
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
PINNING SYMBOL CLPOPB PBK OFDOUT AMPOUT AGND1 VCCA1 AGCOUT PBIN PBOUT ADCIN CLPADC Vref DACOUT AGND2 VCCA2 VRB VRT DEC1 STGE SDATA PIN 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 DESCRIPTION
TDA8786; TDA8786A
optical black clamp control pulse input (active HIGH for TDA8786, active LOW for TDA8786A) pre-blanking control pulse input; if PBK is HIGH (LOW) the signal is replaced by the optical black level for TDA8786 (TDA8786A) analog output of the additional 8-bit control DAC (controlled via the serial interface) CDS amplifier output (fixed gain = +6 dB) analog ground 1 analog supply voltage 1 AGC and soft clipper amplifier signal output optical black clamp and pre-blanking block signal input (from AGCOUT via a capacitor) optical black clamp and pre-blanking block signal output ADC analog signal input (from PBOUT or AGCOUT via a capacitor) clamp control input for ADC analog input signal clamp (active HIGH for TDA8786 and active LOW for TDA8786A) ADC input clamp reference voltage (normally connected to pin VRB or DACOUT) DAC output for ADC clamp level analog ground 2 analog supply voltage 2 ADC reference voltage (BOTTOM) code 0 ADC reference voltage (TOP) code 1023 decoupling 1 (decoupled to ground via a capacitor) CDS offset storage serial data input for the 4 control DACs (9-bit DAC for AGC gain, 4-bit DAC for soft clipper; additional 8-bit DAC for OFD output voltage; 10-bit DAC for ADC clamp level and the stand-by mode per block; see Table 1) serial clock input for the control DACs and their serial interface; see Table 1 enable input for the serial interface shift register (active when SEN = logic 0); see Table 1 stand-by control pin (active HIGH); all the output bits are logic 0 when stand-by is enabled digital supply voltage 1 digital ground 1 ADC digital output 0 (LSB) ADC digital output 1 ADC digital output 2 ADC digital output 3 ADC digital output 4 ADC digital output 5 ADC digital output 6 ADC digital output 7 ADC digital output 8 ADC digital output 9 (MSB) digital output ground
SCLK SEN STDBY VCCD1 DGND1 D0 D1 D2 D3 D4 D5 D6 D7 D8 D9 OGND
21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36
1997 Nov 17
4
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
SYMBOL VCCO OE VCCD2 DGND2 CLK CLPCDS CDSP1 CDSP2 VCCA3 IN1 IN2 AGND3 PIN 37 38 39 40 41 42 43 44 45 46 47 48 digital output supply voltage DESCRIPTION
TDA8786; TDA8786A
output enable (LOW: digital outputs active; HIGH: digital outputs high impedance) digital supply voltage 2 digital ground 2 ADC clock input CDS clamp control input (active HIGH for TDA8786; active LOW for TDA8786A) CDS control pulse input 1 (active HIGH for TDA8786; active LOW for TDA8786A) CDS control pulse input 2 (active HIGH for TDA8786; active LOW for TDA8786A) analog supply voltage 3 input signal 1 from CCD (usually black channel) input signal 2 from CCD (usually video channel) analog ground 3
42 CLPCDS
40 DGND2
48 AGND3
39 VCCD2
45 VCCA3
44 CDSP2
43 CDSP1
37 VCCO
41 CLK
46 IN1
38 OE
47 IN2
CLPOPB PBK OFDOUT AMPOUT AGND1 VCCA1 AGCOUT PBIN PBOUT
1 2 3 4 5 6 7 8 9
36 OGND 35 D9 34 D8 33 D7 32 D6
TDA8786 TDA8786A
31 D5 30 D4 29 D3 28 D2 27 D1 26 D0 25 DGND1
ADCIN 10 CLPADC 11 Vref 12
DACOUT 13
AGND2 14
VCCD1 24
SCLK 21
VCCA2 15
DEC1 18
STGE 19
SDATA 20
SEN 22
VRB 16
VRT 17
STDBY 23
MGE360
Fig.2 Pin configuration.
1997 Nov 17
5
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
LIMITING VALUES In accordance with the Absolute Maximum Rating System (IEC 134). SYMBOL VCCA VCCD VCCO VCC PARAMETER analog supply voltage digital supply voltage output stages supply voltage supply voltage difference between VCCA and VCCD between VCCA and VCCO between VCCD and VCCO Vi VCLK(p-p) Io Tstg Tamb Tj Note input voltage AC input voltage for switching (peak-to peak-value) output current storage temperature operating ambient temperature junction temperature referenced to VSSA referenced to VSSD CONDITIONS note 1 note 1 note 1
TDA8786; TDA8786A
MIN. -0.3 -0.3 -0.3 -1.0 -1.0 -1.0 -0.3 - - -55 -20 -
MAX. +7.0 +7.0 +7.0 +1.0 +4.0 +4.0 +7.0 VCCD 10 +150 +75 150 V V V V V V V V
UNIT
mA C C C
1. The supply voltages VCCA, VCCD and VCCO may have any value between -0.3 and +7.0 V provided that the supply voltage difference VCC remains as indicated. HANDLING Inputs and outputs are protected against electrostatic discharges in normal handling. However, to be totally safe, it is desirable to take normal precautions appropriate to handling integrated circuits. THERMAL CHARACTERISTICS SYMBOL Rth(j-a) PARAMETER thermal resistance from junction to ambient CONDITIONS in free air VALUE 76 UNIT K/W
1997 Nov 17
6
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
TDA8786; TDA8786A
CHARACTERISTICS VCCA = VCCD = 4.75 V; VCCO = 2.6 V; fCLK = 18 MHz; Tamb = 25 C; unless otherwise specified. SYMBOL Supplies VCCA VCCD VCCO ICCA ICCD ICCO Digital inputs CLOCK INPUT: CLK (REFERENCED TO DGND) VIL VIH IIL IIH Zi Ci VIL VIH IIL IIH VIL VIH Ii tsu1 tsu2 LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current input impedance input capacitance VCLK = 0.8 V VCLK = 2.0 V fCLK = 18 MHz fCLK = 18 MHz 0 2.0 -1 - - - 0 2.2 VIL = 0.6 V VIH = 2.2 V - - 0 2.2 -2 - - - - - - 2 2 - - -100 0 - - - 4 4 0.8 VCCD +1 20 - - 0.6 VCCD - - 0.6 VCCD +2 - - V V A A k pF analog supply voltage digital supply voltage digital outputs supply voltage analog supply current digital supply current digital outputs supply current CL = 20 pF on all data outputs; ramp input 4.5 4.5 2.5 - - - 4.75 4.75 2.6 83 16 1 5.5 5.5 5.5 - - - V V V mA mA mA PARAMETER CONDITIONS MIN. TYP. MAX. UNIT
INPUTS: CDSP1 AND CDSP2 LOW-level input voltage HIGH-level input voltage LOW-level input current HIGH-level input current V V A A V V A ns ns
INPUTS: SEN, STDBY, CLPCDS, CLPOPB, PBK AND CLPADC LOW-level input voltage HIGH-level input voltage input current
INPUTS: SEN, SDATA AND SCLK (see Fig.14) SEN set-up time compared to SCLK rising edge SDATA set-up time compared to SCLK rising edge SEN set-up time compared to SCLK falling edge SEN hold time compared to SCLK rising edge SDATA hold time compared to SCLK rising edge
tsu3 thd3 thd4
- - -
4 4 4
- - -
ns ns ns
1997 Nov 17
7
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
SYMBOL PARAMETER CONDITIONS - -2 fi(CDS1,2) = fCLK(pix) Vi(CDS)(p-p) = 1200 mV black-to-white transition in one pixel (1 LSB typ.) see Fig.15 see Fig.15 12 MIN.
TDA8786; TDA8786A
TYP.
MAX.
UNIT
Correlated Double Sampling; CDS Vi(CDS)(p-p) ISTGE,IN1,IN2 tCDS(min) CDS input amplitude (peak-to-peak value) input current pins 19, 46 and 47 CDS control pulses minimum active time (HIGH for TDA8786, LOW for TDA8786A) hold time IN1 compared to control pulse CDSP1 hold time of IN2 compared to control pulse CDSP2 400 - - 1200 +2 - mV A ns
thd1 thd2
- -
1 -0.5
- -
ns ns
Amplifier outputs GAMPOUT ZAMPOUT VAMPOUT(p-p) output amplifier gain output amplifier impedance output amplifier dynamic voltage level (peak-to-peak value) output amplifier black level voltage AGC output amplifier dynamic voltage level (peak-to-peak value) AGC output amplifier black level voltage AGC output amplifier output impedance AGC output static drive current optical black clamp and blanking block output dynamic voltage (peak-to-peak value) optical black clamp and blanking block output black level voltage optical black clamp and blanking block output impedance OPB output current drive input current pin 8 minimum gain of AGC circuit AGC DAC input code = 00 (9-bit control) 8 at 10 kHz at 10 kHz static - - - 6 300 2.4 - - - dB V
VAMPOUT(bl) VAGCOUT(p-p)
- -
1.1 1800
- -
V mV
VAGCOUT ZAGCOUT IAGCOUT VOPB(p-p)
- - - -
1.1 5 - 1.8
- - 1 -
V mA V
VOPB
-
1.4
-
V
ZOPB
-
-
5
IOPB IPBIN GAGC(min)
static
- -2 -
- - 3.5
1 +2 -
mA A dB
1997 Nov 17
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
SYMBOL GAGC(max) VAGCOUT Vinflex(p-p) PARAMETER maximum gain of AGC circuit AGC output amplifier black level voltage voltage at soft clipper inflexion point (peak-to-peak value) soft clipper compression ratio soft clipper 4-bit control DAC input code = 00 soft clipper 4-bit control DAC input code = 15 Vi(sc) < Vinflex Vi(sc) > Vinflex at clamp level at clamp level at clamp level CONDITIONS AGC DAC input - code = 319 (9-bit control) - - - - - - - - - MIN.
TDA8786; TDA8786A
TYP. 33.5 1.1
MAX. - -
UNIT dB V V V
40% - VAGCOUT(p-p) 100% - VAGCOUT(p-p) 1.0 0.66 - - - - - -
CRsc CLAMPS gmADC gmPBK gmCDS VPBIN(clamp)
ADC clamps transconductance PBK clamp transconductance CDS clamps transconductance clamp voltage at PBIN input
60 60 5.5 1.4
mS mS mS V
Analog-to-Digital Converter; ADC fCLK(max) tCPH tCPL SRCLK Vi(ADC)(p-p) VRB VRT IADCIN ILE DLE td(s) maximum clock frequency clock pulse width HIGH clock pulse width LOW clock input slew rate (rising and falling edge) ADC input voltage level (peak-to-peak value) ADC reference voltage output code 0 ADC reference voltage output code 1023 input current pin 10 integral linearity error differential linearity error sampling delay time fCLK = 18 MHz; ramp input fCLK = 18 MHz; ramp input 10 to 90% 18 15 15 0.5 - - - -2 - - - - - - - 1.8 1.4 3.2 - 1.0 0.4 - - - - - - - - +2 2.0 0.75 5 MHz ns ns V/ns V V V A LSB LSB ns
1997 Nov 17
9
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
SYMBOL PARAMETER CONDITIONS - MIN.
TDA8786; TDA8786A
TYP.
MAX. -
UNIT
Total chain timing (CDS + ADC + SOFT CLIPPER + PRE BLANKING + ADC) td time delay between CDSP1 and CLK 50% at rising edges of CLK and CDSP1: transition full-scale code 0 to code 1023; Vi(CDS)(p-p) = 1200 mV gain = 3.5 dB 40 ns
N(rms) VOFDOUT(p-p)
noise (RMS value)
- -
0.5
- -
LSB
Digital-to-Analog Converters (OFDOUT DAC) additional 8-bit control DAC (OFD) output voltage (peak-to-peak value) DC output voltage for code 0 DC output voltage for code 255 additional 8-bit control DAC (OFD) output impedance OFD output current drive static 1.4 V
VOFDOUT(0) VOFDOUT(255) ZOFDOUT
- - -
2.0 3.4 2000
- - -
V V
IOFDOUT VDACOUT(p-p)
- -
-
50 -
A
ADC clamp control DAC (see Fig.5) ADC clamp 10-bit control DAC output voltage (peak-to-peak value) DC output voltage ADC clamp control DAC output impedance DAC output current drive maximum offset error of DAC + ADC clamp loop static code 0 code 1023 code 0 code 1023 ZDACOUT IDACOUT OFELOOP 0.9 V
VDACOUT
- - - - - -
1.4 2.3 - - 5 5
- - 250 50 - -
V V A LSB LSB
1997 Nov 17
10
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
SYMBOL PARAMETER CONDITIONS MIN.
TDA8786; TDA8786A
TYP.
MAX.
UNIT
Digital outputs (fCLK = 18 MHz; CL = 20 pF) VOH VOL IOZ to(h) to(d) HIGH-level output voltage LOW-level output voltage output current in 3-state mode output hold time output delay Ci = 20 pF; VCCO = 4.75 V Ci = 20 pF; VCCO = 3.15 V Ci = 20 pF; VCCO = 2.7 V Serial interface fSCLK(max) maximum frequency of serial interface 5 - - MHz IOH = -1 mA IOL = 1 mA 0.5 V < Vo < VCCO VCCO - 0.5 0 -20 5 - - - - - - - 12 17 21 VCCO 0.5 +20 - 15 20 24 V V A ns ns ns ns
handbook, halfpage
MGE365
33.5 GAGC (dB)
3.5
0
319 AGC control DAC input code
511
Fig.3 AGC gain as a function of DAC input code.
1997 Nov 17
11
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
TDA8786; TDA8786A
handbook, full pagewidth
MGE364
AGCOUT control DAC input code = 15 100% control DAC input code = 00 (1) (2) 40%
0 Vo (1) ----- = 1 Vi Vo (2) ----- = 0.66 Vi
0
40%
100%
130% soft clipper input
Fig.4 Soft clipper output voltage as a function of soft clipper input voltage.
handbook, halfpage
MGE366
handbook, halfpage
MGD599
2.3 ADC CLAMP DAC voltage output (V)
3.4 OFD DAC voltage output (V)
1.4 0
2.0 1023 ADC CLAMP control DAC input code 0 255 OFD control DAC input code
Fig.5 DAC voltage output as a function of DAC input code.
1997 Nov 17
12
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
TDA8786; TDA8786A
handbook, full pagewidth
8 x fSC = 2fCLK >12 ns CDSP1
>12 ns CDSP2
MGE370
Fig.6 CCD high band control signal timing (TDA8786).
handbook, full pagewidth
8 x fSC = 3fCLK >12 ns CDSP1
>12 ns CDSP2
MGE369
Fig.7 CCD normal band control signal timing (TDA8786).
1997 Nov 17
13
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
TDA8786; TDA8786A
handbook, full pagewidth
8 x fSC = 2fCLK
CDSP1 >12 ns
CDSP2
MGE371
>12 ns
Fig.8 CCD high band control signal timing (TDA8786A).
handbook, full pagewidth
8 x fSC = 3fCLK
CDSP1 >12 ns
CDSP2
MGE372
>12 ns
Fig.9 CCD normal band control signal timing (TDA8786A).
1997 Nov 17
14
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
TDA8786; TDA8786A
IPBIN handbook, halfpage (A) 450
I handbook, halfpage (A) 350
0 1.4 -450 30 mV
MBK058
0 VPBIN (V) -350 200 mV
MBK057
2.85
V (V)
Fig.10 Typical PBK clamp current.
Fig.11 Typical clamp currents for pins IN1, IN2 and STGE.
ADC clamping When pin CLPADC is HIGH (TDA8786) (LOW for TDA8786A), the ADC input is clamped to voltage level Vref. Vref should normally be connected to VRB (ADC reference voltage code 0) or to DACOUT (10-bit DAC output). The DAC is controlled via the serial interface, its output covers the lower half of the ADC input range.
IADCIN handbook, halfpage (A) 450 Vref 0 VADCIN (V) -450 30 mV 500 mV
MBK059
slope = 1 k
Fig.12 Typical ADC clamp current.
1997 Nov 17
15
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
TDA8786; TDA8786A
handbook, full pagewidth
SDATA D0 SCLK LSB D1 D2 D3
SHIFT REGISTER D4 D5 D6 D7 D8 D9 MSB 10 LATCH SELECTION A0 A1 A2
SEN
8 (D7 to D0) OFD LATCHES
9 (D8 to D0) AGC GAIN LATCHES
4 (D3 to D0) SOFT CLIP LATCHES
4 (D3 to D0) PARTIAL STANDBY
10 (D9 to D0) CLAMP REFERENCE LATCHES
8-bit DAC
AGC control
soft clip control
standby control
10-bit DAC
MGD526
Fig.13 Serial interface block diagram.
handbook, full pagewidth
tsu2 MSB thd4 D9 D8 D7 D6 D5 D4 LSB D3 D2 D1 D0
SDATA
A2
A1
A0
SCLK
SEN
MGE373
tsu1
thd3 tsu3
tsu = 4 ns (min.); thd3 = thd4 = 4 ns (min.).
Fig.14 Loading sequence of control DACs input data via the serial interface.
1997 Nov 17
16
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
Table 1 Serial interface programming (see note 1)
TDA8786; TDA8786A
ADDRESS BITS DATA BITS D9 to D0 A2 0 0 0 0 A1 0 0 1 1 A0 0 1 0 1 OFDOUT output control (D7 to D0). Soft clipper control. Only the 4 LSBs (D3 to D0) are used. Bits D9 to D4 should be set to logic 0. AGC gain control (D8 to D0). Partial standby controls for power consumption optimization. Only the 4 LSBs (D3 to D0) are used. Bits D9 to D4 should be set to logic 0: D0 = 1: CDS + AGC + soft clipper block in standby; ICCA + ICCD = 48 mA D1 = 1: optical black clamp + blanking block in standby; ICCA + ICCD = 92 mA D2 = 1: OFD DAC in standby; ICCA + ICCD = 98 mA D3 = 1: 6 dB amplifier (output on AMPOUT pin) in standby; ICCA + ICCD = 98.5 mA. 1 Note 1. At the end of each programming sequence (usually during the video vertical blanking), the soft clipper register must be reloaded (for example if the soft clipper is not used, code 15 must be entered in the soft clipper register at the end of each TDA8786(A) programming sequence). Table 2 Standby selection STDBY 1 0 D9 to D0 LOW active ICCA + ICCD 4 mA (typ.) 99 mA (typ.) 0 0 Clamp reference DAC (D9 to D0).
1997 Nov 17
17
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
TDA8786; TDA8786A
handbook, full pagewidth
IN1 and IN2
PIXEL N
CDSP1 (active HIGH) sample N CDSP2 (active HIGH)
,,,,,,, ,,,,, ,, ,,,
PIXEL N+1 PIXEL N+2 PIXEL N+3 PIXEL N+4 thd2 td th PIXEL N - 3 PIXEL N - 2 PIXEL N - 1 td (OUT) PIXEL N
MGE367
thd1
CLK
DATA OUTPUT D0 to D7
PIXEL N - 4
The hatched areas represent active video.
Fig.15 Pixel frequency timing diagram.
handbook, full pagewidth
AGCOUT
VIDEO
OPTICAL BLACK
HORIZONTAL FLYBACK
DUMMY
VIDEO
CLPCDS (active HIGH) CLPOPB (active HIGH) PBK (active HIGH)
PREBLANKING OUTPUT CLPADC (active HIGH)
VIDEO
BLACK LEVEL
VIDEO
MGE368
Fig.16 Line frequency timing diagram.
1997 Nov 17
18
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
APPLICATION INFORMATION
TDA8786; TDA8786A
TDA8786 and SAA8110 can be used with Sharp CCDs. TDA8786A and SAA8110 can be used with Sony CCDs. Table 3 gives as an example some references of ICs which may be used with Philips TDA8786(A)/SAA8110. This overview is not restrictive, both devices are compatible with other CCD/V-driver/PPG combinations including the more recent ones. Table 3 Possible components for the application of Figs 17 and 18 NTSC CCD TYPE Sony CCDs COMPONENT TYPE CCD V-driver timing generator Sharp CCDs CCD V-driver timing generator Notes to the application diagram 1. In the configuration of Figs 17 and 18, the microcontroller reads and writes data from/to the DSP using the SNERT-bus (UART mode 0). Optional external control is available via the I2C-bus. 2. Free I/O pins of the microcontroller can be used to control PGG, or for other purposes. 3. 83Cxxx processing is synchronized by VD interruption. Depending on VD polarity, it can be necessary to invert VD. 4. A customized 83Cxxx is available for this application. Please contact your nearest Philips sales office. CXD1257AR LZ95G55 ICX056AK MEDIUM RESOLUTION LZ2313H5 HIGH RESOLUTION LZ2353A LZ95G71 ICX068AK CXD1265R MEDIUM RESOLUTION LZ2323H5 LZ95G55 ICX057AK CXD1257AR PAL HIGH RESOLUTION LZ2363 LZ95G71 ICXo69AK CXD1265R
LR36683N
CXD1250MN, CXD1267N
1997 Nov 17
19
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
TDA8786; TDA8786A
handbook, full pagewidth
P0 P1 CDACOUT CLK1 CLK2 CDSPULSE1 CDSPULSE2 digital ground analog ground
P0 (optional, PPG setting) P1 (optional, PPG settings) CDACOUT (optional, can be used for frequency tuning) CLK1 (to ADC and DSP) CLK2 (to DSP, CLK2 = 2 x CLK1) CDSPULSE1 CDSPULSE2 CLAMPCDS (CLAMP CDS, OPB, ADC can be the same) CLAMPOPB CLAMPADC PreBlank (optional) HD (to DSP and C) VD (to DSP and C) FI (to DSP and C) CLK1 CLAMPCDS CDSPULSE1 CDSPULSE2 100 nF VDDA1 100 nF 1 F OEN (optional) (from microcontroller) VDDD CLPCDS 100 nF VCCO OE
VERTICAL DRIVER (PPG)
CLAMPCDS CLAMPOPB CLAMPADC PreBlank Horizontal Drive Vertical Drive Field Id
V4
V3
V2
V1
H1
H2
Electrical Reset Shutter Pulse
VERTICAL DRIVER BUFFER Reset CCDout OFD level (optional) CLAMPOPB PreBlank
VDDA1
V4 V3 V2 V1
H1
H2
Shutter
CCD
CLPOPB -xxV +xxV 100 nF SMP_CLK (from DSP) VDDA1 PBK OFDOUT AMPOUT 100 nF AMPOUT AGND1 VCCA1 AGCOUT PBIN 220 nF PBOUT ADCIN CLPADC Vref 220 nF 10 k BC848C VD (from PPG) 10 F VDDD P1.0 P1.1 P1.2 OEN (optional) (to ADC) P1.3 P1.4 P1.5 VDDD 4.7 F JB JB JB JB VDDD P1.6/SCL P1.7/SDA RST P3.0/RxD P3.1/TxD P3.2/INT0 P3.3/INT1 P3.4/T0 P3.5/T1 P3.6/WR P3.7/RD XTAL2 XTAL1 VSS VDD P0.0/AD0 CLAMPADC (from PPG) 1 nF VDDD
48 47 46 45 44 43 42 41 40 39 38 37 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 VRB DEC1 STGE SDATA SCLK STBY DACOUT AGND2 VCCD1 VCCA2 VRT SEN 36 35 34
DGND2 VCCD2
AGND3
VCCA3
CDSP2
CDSP1
CLK
IN2
IN1
OGND D9 D8 D7 D6 D5 D4 D3 D2 D1 D0 DGND1 A B C D E F G H I J K
SWITCH MODE POWER SUPPLIES (optional)
ANALOG-TO-DIGITAL INTERFACE
33 32 31
5V 5V 5V
VDDA1 VDDA2 VDDA3
VDDD
TDA8786G or TDA8786AG
30 29 28 27 26 25
100 nF VDDD
10 k
2 3 4 5 6 7 8 9 10 11 13 14 15 16 17 18 19 20 21 22
44 43
VDDA1 VSS 4 EPROM A2 6 PCF8598 3 NC VDDD PTC 7 PCF8594 2 4.7 VDD WP k 8 PCF8582 1 SDA SCL 5 100 nF 100 nF
P0.1/AD1 MICRO42 CONTROLLER P0.2/AD2 41 40 39 38 37 36 P0.3/AD3 P0.4/AD4 P0.5/AD5 P0.6/AD6 P0.7/AD7 4.7 k
L 1 nF 1 nF 2.2 nF 200 nF M
VDDD VDDD
+5 V
GND
SCL
SDA
83C54/ 35 EA VDDD 83C654 ALE (OM-XXX) 33 PSEN
32 31 30 29 28 27 26 25 24 P2.7/A15 P2.6/A14 P2.5/A13 P2.4/A12 P2.3/A11 P2.2/A10 P2.1/A9 P2.0/A8
MGK393
4
3
2
1 A0/SNDA SCL/SNCL HD (opt.) FIIN A1/SNRES 18 pF 12 MHz
RESET_DSP (to DSP)
18 pF
Fig.17 SAA8110G system configuration for camera application (continued in Fig.18).
1997 Nov 17
20
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
TDA8786; TDA8786A
handbook, full pagewidth
26
25
22 A1/SNRES A0/SNDA SDA SCL/SNCL VDDD 100 nF VDDD optional 100 nF
A1/SNRES VDDD(C3) VSSD(P2) SCL/SNCL VSSD(C3) Y7 VDDD(P2) XOUT XIN VSSD(C4) SDA A0/SNDA
DIGITAL OUTPUT CONNECTOR
24
23 21 19 17 15 13 11 9 7 5 3 1 VDDD
20 18 16 14 12 10 8 6 4 VDDD 2
Y4
Y0
Y2
Y5
Y1
100 nF V DDD(C1) CLK1 VD HD FI CLK1 VSYNCIN HSYNCIN
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 1 2 3 4 60 59 58 57 56
Y3
Y6
VDDD
UV0
UV1 UV2 UV3 UV4 UV5 UV6 UV7 VSSD(P1) LLC CREF/PXQ HREF VSYNCOUT FIOUT CLK2 VDDD(P1) VDDA(BG) RBIAS CLK2 (from PPG) VDDD 47 k VDDA3 100 nF
A B C D E F G H I J K
FIIN 5 VSSD(C1) 6 CCD9 7 CCD8 8 CCD7 9 CCD6 10 CCD5 11 CCD4 12 CCD3 13 CCD2 14 CCD1 15 CCD0 16 VSSD(C2) 17 SCLK 18 VSSA(CD) 19 CDACOUT 20 10 nF
DIGITAL SIGNAL PROCESSOR
55 54 53 52 51
SAA8110G
50 49 48 47 46 45 44 43
CDACOUT
VDDA(CD)
VDDD(C2)
SDATA
STROBE
SMP
SIS
T0 VSSA(OB)
OUT2 VDDA(O2)
CDACRBIAS
OUT1 VDDA(O1)
P0
P1
RESET
T2
T1
OUT3 VDDA(O3)
100 nF DECOUPL VSSA(BG) 100 nF 42 VDDA(DC) VDDA3 41 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 100 nF SVHS
3
16 5 27
4
L(1) L(1)
68 L(1)
Y
150 k 100 nF VDDA2 L M SMP_CLK (to power supply) P0 P1 VDDD digital ground analog ground 100 nF VDDD RESET_DSP (from C) VDDA3 100 nF VDDA3 100 nF
Green
6 1 7 2 12 8 3 9 4 10 5 15 14 13 11
L(1) L(1)
68 L(1)
C
U, Blue
L(1) L(1)
68 L(1)
V, Red
CVBS
CVBS-RCA
MGK394
(1) Values depend on DSP output configuration.
Fig.18 SAA8110G system configuration for camera application (continued from Fig.17).
1997 Nov 17
21
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
PACKAGE OUTLINE LQFP48: plastic low profile quad flat package; 48 leads; body 7 x 7 x 1.4 mm
TDA8786; TDA8786A
SOT313-2
c
y X
36 37
25 24 ZE
A
e
E HE
A A2
A1
(A 3) Lp L detail X
wM pin 1 index 48 1 12 ZD bp D HD wM B vM B vM A 13 bp
e
0
2.5 scale
5 mm
DIMENSIONS (mm are the original dimensions) UNIT mm A max. 1.60 A1 0.20 0.05 A2 1.45 1.35 A3 0.25 bp 0.27 0.17 c 0.18 0.12 D (1) 7.1 6.9 E (1) 7.1 6.9 e 0.5 HD 9.15 8.85 HE 9.15 8.85 L 1.0 Lp 0.75 0.45 v 0.2 w 0.12 y 0.1 Z D (1) Z E (1) 0.95 0.55 0.95 0.55 7 0o
o
Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION SOT313-2 REFERENCES IEC JEDEC EIAJ EUROPEAN PROJECTION
ISSUE DATE 94-12-19 97-08-01
1997 Nov 17
22
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
SOLDERING Introduction There is no soldering method that is ideal for all IC packages. Wave soldering is often preferred when through-hole and surface mounted components are mixed on one printed-circuit board. However, wave soldering is not always suitable for surface mounted ICs, or for printed-circuits with high population densities. In these situations reflow soldering is often used. This text gives a very brief insight to a complex technology. A more in-depth account of soldering ICs can be found in our "IC Package Databook" (order code 9398 652 90011). Reflow soldering Reflow soldering techniques are suitable for all LQFP packages. Reflow soldering requires solder paste (a suspension of fine solder particles, flux and binding agent) to be applied to the printed-circuit board by screen printing, stencilling or pressure-syringe dispensing before package placement. Several methods exist for reflowing; for example, infrared/convection heating in a conveyor type oven. Throughput times (preheating, soldering and cooling) vary between 50 and 300 seconds depending on heating method. Typical reflow peak temperatures range from 215 to 250 C. Wave soldering Wave soldering is not recommended for LQFP packages. This is because of the likelihood of solder bridging due to closely-spaced leads and the possibility of incomplete solder penetration in multi-lead devices. CAUTION Wave soldering is NOT applicable for all LQFP packages with a pitch (e) equal or less than 0.5 mm.
TDA8786; TDA8786A
If wave soldering cannot be avoided, for LQFP packages with a pitch (e) larger than 0.5 mm, the following conditions must be observed: * A double-wave (a turbulent wave with high upward pressure followed by a smooth laminar wave) soldering technique should be used. * The footprint must be at an angle of 45 to the board direction and must incorporate solder thieves downstream and at the side corners. During placement and before soldering, the package must be fixed with a droplet of adhesive. The adhesive can be applied by screen printing, pin transfer or syringe dispensing. The package can be soldered after the adhesive is cured. Maximum permissible solder temperature is 260 C, and maximum duration of package immersion in solder is 10 seconds, if cooled to less than 150 C within 6 seconds. Typical dwell time is 4 seconds at 250 C. A mildly-activated flux will eliminate the need for removal of corrosive residues in most applications. Repairing soldered joints Fix the component by first soldering two diagonallyopposite end leads. Use only a low voltage soldering iron (less than 24 V) applied to the flat part of the lead. Contact time must be limited to 10 seconds at up to 300 C. When using a dedicated tool, all other leads can be soldered in one operation within 2 to 5 seconds between 270 and 320 C.
1997 Nov 17
23
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
DEFINITIONS Data sheet status Objective specification Preliminary specification Product specification Limiting values
TDA8786; TDA8786A
This data sheet contains target or goal specifications for product development. This data sheet contains preliminary data; supplementary data may be published later. This data sheet contains final product specifications.
Limiting values given are in accordance with the Absolute Maximum Rating System (IEC 134). Stress above one or more of the limiting values may cause permanent damage to the device. These are stress ratings only and operation of the device at these or at any other conditions above those given in the Characteristics sections of the specification is not implied. Exposure to limiting values for extended periods may affect device reliability. Application information Where application information is given, it is advisory and does not form part of the specification. LIFE SUPPORT APPLICATIONS These products are not designed for use in life support appliances, devices, or systems where malfunction of these products can reasonably be expected to result in personal injury. Philips customers using or selling these products for use in such applications do so at their own risk and agree to fully indemnify Philips for any damages resulting from such improper use or sale.
1997 Nov 17
24
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
NOTES
TDA8786; TDA8786A
1997 Nov 17
25
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
NOTES
TDA8786; TDA8786A
1997 Nov 17
26
Philips Semiconductors
Product specification
10-bit analog-to-digital interface for CCD cameras
NOTES
TDA8786; TDA8786A
1997 Nov 17
27
Philips Semiconductors - a worldwide company
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For all other countries apply to: Philips Semiconductors, International Marketing & Sales Communications, Building BE-p, P.O. Box 218, 5600 MD EINDHOVEN, The Netherlands, Fax. +31 40 27 24825 (c) Philips Electronics N.V. 1997
Internet: http://www.semiconductors.philips.com
SCA56
All rights are reserved. Reproduction in whole or in part is prohibited without the prior written consent of the copyright owner. The information presented in this document does not form part of any quotation or contract, is believed to be accurate and reliable and may be changed without notice. No liability will be accepted by the publisher for any consequence of its use. Publication thereof does not convey nor imply any license under patent- or other industrial or intellectual property rights.
Printed in The Netherlands
547047/1200/03/pp28
Date of release: 1997 Nov 17
Document order number:
9397 750 02926

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