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Dynamic Differential Hall Effect Sensor IC
TLE 4923
Bipolar IC Features * * * * * * * * * * * * * Advanced performance Higher sensitivity Symmetrical thresholds High piezo resistivity Reduced power consumption South and north pole pre-induction possible AC coupled Digital output signal Two-wire interface Large temperature range Large airgap Low cut-off frequency Protection against reversed polarity
P-SSO-3-6
Type w TLE 4923 w New type
Ordering Code Q62705-K408
Package P-SSO-3-6
The differential Hall effect sensor TLE 4923 is compatible to the TLE 4921-3U, except for having a 2-wire interface. The TLE 4923 provides high sensitivity, a superior stability over temperature and symmetrical thresholds in order to achieve a stable duty cycle. TLE 4923 is particularly suitable for rotational speed detection and timing applications of ferromagnetic toothed wheels such as in anti-lock braking systems, transmissions, crankshafts, etc. The integrated circuit (based on Hall effect) provides a digital signal output with frequency proportional to the speed of rotation. Unlike other rotational sensors differential Hall ICs are not influenced by radial vibration within the effective airgap of the sensor and require no external signal processing.
Semiconductor Group
1
1998-04-29
TLE 4923
Pin Configuration (top view)
2.67
Center of sensitive area 0.15
1.53
1
2.5 2
3
VS
GND
C
AEP02039
Figure 1
Pin Definitions and Functions Pin No. 1 2 3 Symbol Function Supply voltage Ground Capacitor
VS
GND
C
Semiconductor Group
2
1998-04-29
TLE 4923
VS
1
Protection Device
Internal Reference and Supply
Vreg (3V)
Hall-Probes HighpassFilter SchmittTrigger
Amplifier
2 GND
3
CF
AEB01896
Figure 2
Block Diagram
Semiconductor Group
3
1998-04-29
TLE 4923
Functional Description The Differential Hall sensor IC detects the motion and position of ferromagnetic and permanent magnet structures by measuring the differential flux density of the magnetic field. To detect ferromagnetic objects the magnetic field must be provided by a back biasing permanent magnet (south or north pole of the magnet attached to the rear unmarked side of the IC package). Using an external capacitor the generated Hall voltage signal is slowly adjusted via an active high pass filter with low frequency cut-off. This causes the output to switch into a biased mode after a time constant is elapsed. The time constant is determined by the external capacitor. Filtering avoids aging and temperature influence from Schmitt-trigger input and eliminates device and magnetic offset. The TLE 4923 can be exploited to detect toothed wheel rotation in a rough environment. Jolts against the toothed wheel and ripple have no influence on the output signal. The on and off state of the IC are indicated by high and low current consumption. Circuit Description (see Figure 2) The TLE 4923 is comprised of a supply voltage reference, a pair of Hall probes spaced at 2.5 mm, differential amplifier, filter for offset compensation, Schmitt-trigger, and a switched current source. The TLE 4923 was designed to have a wide range of application parameter variations. Differential fields up to 40 mT can be detected without influence to the switching performance. The pre-induction field can either come from a magnetic south or north pole, whereby the field strength up to 500 mT or more will not influence the switching points1). The improved temperature compensation enables a superior sensitivity and accuracy over the temperature range. Finally, the optimized piezo compensation and the integrated dynamic offset compensation enable easy manufacturing and elimination of magnet offsets. Protection is provided at the input/supply (pin 1) for reverse polarity.
1)
Differential bias fields exceeding 20 mT, e. g. caused by a misaligned magnet, should be avoided.
Semiconductor Group
4
1998-04-29
TLE 4923
Absolute Maximum Ratings Parameter Supply voltage Capacitor voltage Junction temperature Junction temperature Junction temperature Junction temperature Storage temperature Thermal resistance
1) 2)
Symbol
Limit Values min. max. 24 3 150 160 170 190 - 40 150 190 - 18
1)
Unit V V C C C C C K/W
Remarks
VS VC Tj Tj Tj Tj TS Rth JA
- 0.3
5000 h 2500 h 500 h 4h
2)
Reverse current drawn by the device < 10 mA Can be reduced significantly by further packaging process, e. g. overmolding. The device is ESD protected up to 2 kV (HL test procedure)
Note: Stresses above those listed here may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
Operating Range Parameter Supply voltage Junction temperature Pre-induction Symbol Limit Values min. max. 18 190 500 V C mT At Hall probe; independent of magnet orientation 4.5 - 40 - 500 Unit Remarks
VS Tj B0
Differential induction
B
- 40
40
mT
Note: Unless otherwise noted, all temperatures refer to junction temperature. In the operating range the functions given in the circuit description are fulfilled.
Semiconductor Group
5
1998-04-29
TLE 4923
AC/DC Characteristics The device characteristics listed below are guaranteed in the full operating range. Parameter Supply current Supply current difference Supply current ratio Center of switching points: (BOP + BRP) / 2 Center of switching points: (BOP + BRP) / 2 Hysteresis Current rise time Symbol Limit Values min. typ. max. 3.1 8.1 4.1 5.3 10.5 13.6 6.4 2.4 8.3 3 0.5 mT B = 2.0 mT, f = 200 Hz, - 40 C < Tj 150 C 1) 2) B = 2.0 mT, f = 200 Hz, 150 C < Tj < 190 C 1) 2) B = 2.0 mT, Unit mA mA mA Test Condition Test Circuit 1 1 1 1 2
IS
Ison - Isoff 5.0 ISON / ISOFF
Bm 2
- 0.5 0
Bm
- 0.7 0
0.7
mT
2
Bhy
1
1.5
2.2 0.5 0.5 25 10 15
mT s s s s s k mV/ mT
2 2 2
f = 200 Hz 3)
tr tf Current fall time 4) tdop Delay time tdrp tdop - tdrp 35 Filter input resistance RC Filter sensitivity to B SC
Filter bias voltage Frequency Resistivity against mechanical stress (piezo)6)
B = 5 mT
f = 10 kHz,
2
43 8.5 2.0
52
25 C 2 C 25 C 2 C B = 0 B = 5 mT F=2N
1 1 1 2 2
VC f
Bm BHy
1.6
5)
2.4 0.1 0.1
V mT mT
10000 Hz
- 0.1 - 0.1
Semiconductor Group
6
1998-04-29
TLE 4923
AC/DC Characteristics (cont'd) The device characteristics listed below are guaranteed in the full operating range. Parameter Power Supply Rejection Ratio (PSRR) Symbol Limit Values min. typ. max. 10 Unit V Test Condition Test Circuit
VPSRR
B = 0, only 1 transition may occur
1) 2)
VS modulated with VPSRR, fPSRR = 10 kHz, tr,fPSRR = 1 s,
27)
For B values larger than 10 mT this value may exceed the limits as follows: | Bm | < | 0.05 x B | Leakage currents at pin 3 should be avoided. The bias shift of Bm caused by a leakage current IL can be calculated by: B m =
IL x RC ( T )
-------------------SC ( T )
. See also the typical curves on page 17.
3) 4) 5)
Differential pre-induction (e.g. by magnetic misalignment) has to be smaller than 20 mT. For definition see Figure 6. 1 Depends on filter capacitor CF. The cut-off frequency is given as f = --------------------------------------- . The switching points 2 x x RC x CF are guaranteed over the whole frequency range, but amplitude modification and phase shift have to be taken into account due to the 1st order highpass filter. For definition see Figure 7. For definition see Figure 5.
6) 7)
Note: The listed characteristics are ensured over the operating range of the integrated circuit. Typical characteristics specify mean values expected over the production spread. If not otherwise specified, typical characteristics apply at Tj = 25 C and the given supply voltage.
Semiconductor Group
7
1998-04-29
TLE 4923
RP
180
V SZ
1
S
VS
VLD
4.7 nF
VS
C
1)
3
C
VC
C
GND 2
AES01897
1)
RC =
VC C
Figure 3
Test Circuit 1
1
VS
VS
3C
CF 1 F
GND 2
AES01898
RS 180
Figure 4
Test Circuit 2
Semiconductor Group
8
1998-04-29
TLE 4923
18 V
V PSRR
8V
tr
tf
AED02488
Figure 5
B RP B OP
B
t drp : Delay Time between B = B RP and S LOW to HIGH transient
t drp
t dop
t dop : Delay Time between B = B OP and S HIGH to LOW transient
S
AED02509
Figure 6
Definition of Delay Times (switching points related to initial measurement @B = 2 mT; f = 200 Hz)
F = 2N r = 0.5 0.05 mm IC
4 x d = 1.5
AEA02508
Figure 7
Setup for Piezo Measurements
9 1998-04-29
Semiconductor Group
TLE 4923
Application Notes Two possible applications are shown in Figure 10 and Figure 11 (Toothed and Magnet Wheel). Two-wire application is shown in Figure 12. Gear Tooth Sensing In the case of ferromagnetic toothed wheel applications the IC has to be biased by the south or north pole of a permanent magnet (e.g. SmCo5 (Vacuumschmelze VX170) with the dimensions 8 mm x 5 mm x 3 mm) which should cover both Hall probes. The maximum air gap depends on: - the magnetic field strength (magnet used; pre-induction) and - the tooth wheel that is used (dimensions, material, etc.; resulting differential field). a centered distance of Hall probes b Hall probes to IC surface L IC surface to tooth wheel a = 2.5 mm b = 0.3 mm Figure 8 Sensor Spacing
T
N S b L a
AEA01259
Conversion DIN - ASA
m = 25.4 mm/p T = 25.4 mm CP
AEA01260
d
DIN
d z m T
ASA diameter (mm) number of teeth module m = d/z (mm) pitch T = x m (mm) Tooth Wheel Dimensions
p
diameter pitch p circular pitch
= z/d (inch)
PD CP
pitch diameter PD = z/p (inch) CP = 1 inch x /p
Figure 9
Semiconductor Group
10
1998-04-29
TLE 4923
Gear Wheel
Hall Sensor 1
Hall Sensor 2
Signal Processing Circuitry
S (N) N (S)
Permanent Magnet
AEA01261
Figure 10 TLE 4923, with Ferromagnetic Toothed Wheel
Magnet Wheel
S N
Hall Sensor 1
S
Hall Sensor 2
Signal Processing Circuitry
AEA01262
Figure 11 TLE 4923, with Magnet Wheel
Semiconductor Group 11 1998-04-29
TLE 4923
Two-wire-application Line 1 VS C GND 2 1
VS
3
CS 4.7 nF
CF 1 F
VSIGNAL RS
Sensor typical : R S = 180
Mainframe
AES01899
Figure 12 Application Circuit
Semiconductor Group
12
1998-04-29
TLE 4923
N(S) S(N) 1 B1 Wheel Profile B2 Missing Tooth 3
Magnetic Field Difference B = B2-B1
Small Airgap Large Airgap B RP = 0.75 mT B HY
B OP = -0.75 mT
Output Signal S
Operate point : B2-B1< B OP switches the output ON high current Release point : B2-B1> BRP switches the output OFF low B RP = BOP + B HY
(
(
AED01900
The magnetic field is defined as positive if the south pole of the magnet shows towards the rear side of the IC housing.
Figure 13 System Operation
Semiconductor Group
13
1998-04-29
TLE 4923
If not otherwise specified, all curves reflect typical values at Tj = 25 C and VS = 12 V. Supply Current and Supply Current Minimum Switching Field versus Difference versus Supply Voltage Frequency
12
AED02473
S
mA 10
SON
1.2 mT
AED02475
B min
T j = 190 C
1.0
8
0.8
T j = 150 C T j = 25 C
6
SON SOFF SOFF
0.6
T j = -40 C
4
0.4
2
0.2
0
0
5
10
15
20 V 25 VS
0
1
10
100
1000 Hz 10000 f
Supply Current and Supply Current Difference versus Temperature
12 mA 10
AED02474
Mean Value of Switching Induction
1.2 mT 1.0
AED02476
S
SON
B m
8
0.8
6
SON SOFF SOFF
0.6
4
0.4
2
0.2
B OP B RP 2 f = 200 Hz B m =
typ
0 -40
0
40
80
120
C Tj
200
0 -40
0
40
80
120
C Tj
200
Semiconductor Group
14
1998-04-29
TLE 4923
Hysteresis versus Temperature
1.6 mT
AED02477
Delay Time1) versus Temperature
8 s td 7 6 5 4 3 2
AED02479
B HY 1.4
t dop t drp
typ 1.2
B HY = B RP B OP
f = 200 Hz
1.0
0.8
0.6
1 0 -50
0.4 -40
0
40
80
120
C Tj
200
0
50
100
150 C 200 Tj
Delay Time1) versus Differential Field
6.0 s 5.9 td 5.8 5.7 5.6 5.5 5.4 5.3 5.2 5.1 5.0 0 2 4 6 8
AED02478
Rise and Fall Time versus Temperature
140 ns
AED02480
f = 10 kHz
t
120 100
tf tr
80
t dop
60 40
t drp
20 0 -50
mT B
12
0
50
100
150 C 200 Tj
1)
Switching points related to initial measurement @B = 2 mT, f = 200 Hz
Semiconductor Group
15
1998-04-29
TLE 4923
Capacitor Voltage versus Temperature
2.5
AED02481
Filter Input Resistance versus Temperature
60 k 50
AED02483
VC V
2.0 typ
RC
typ 40
1.5
30
1.0
20
0.5
10
0 -50
0
50
100
150 C 200 Tj
0 -50
0
50
100
150 C 200 Tj
Filter Sensitivity versus Temperature
0 mV/mT S C -2 -4
AED02482
Delay Time tpon for Power ON versus Temperature
0.8 ms/nF t pon = k C F (nF) k 0.7 0.6
AED02484
max.1)
-6 typ -8
0.5
VS = 12 V
-10 -12 -14
0.2 0.4 0.3 min.1)
-16 -18 -20 -50 0 50 100 150 C 200 Tj
1)
0.1 0 -50
0
50
100
150 C 200 Tj
Calculated values for minimum and maximum filter resistance, C F at room temperature.
Semiconductor Group
16
1998-04-29
TLE 4923
Threshold Shift versus Filter Leakage
8 mT B m 7 6 5 4 3 2 1 0 +190C +100C +25C -40C
AED02485
0
20
40
60
80 M 100 RC
Semiconductor Group
17
1998-04-29
TLE 4923
Package Outline P-SSO-3-6 (Plastic Single Small Outline Package)
12.7 1 1 x 45
0.15 max.
5.16 0.08 5.38 0.05
0.2 1.9 max.
1 -0.1 0.25 0.05
1 max.
1.2 0.1
3.71 0.08
3.38 0.06
0.65 0.1 (0.25)
0.87 0.05 1.9 max. 1.67 0.05 123
0.2 +0.1
0.6 max. 0.4 0.05
23.8 0.5 38 max.
9 -0.5
3.81
+0.75
18 0.5
6 0.5
Adhesive Tape 0.25 -0.15 Tape 0.5 0.1
GPO05960
6.35 0.4 12.7 0.3
4 0.3
d
Branded Side
Hall-Probe d : Distance chip to upper side of IC P-SSO-3-6 : 0.3 0.08 mm
AEA02510
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Semiconductor Group 18
Dimensions in mm 1998-04-29
1 -1

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