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Fiber Optics
Parallel Optical Link Transmitter: PAROLI(R) 2 Tx AC, 1.25 Gbit/s Parallel Optical Link Receiver: PAROLI(R) 2 Rx AC, 1.25 Gbit/s
V23832-T2531-M101 V23832-R511-M101
Design Benefits * * * * * Relieve system bandwidth bottle necks Simplifies system design Enables system upgrades in field Low power consumption at increased board density Flat package for height critical application
Features * * * * * * * * * * * * * * * * * * * * * Infineon's highly reliable 850 nm VCSEL technology Power supply 3.3 V Transmitter with multistandard electrical interface Receiver with Infineon's adjustable CML output 12 electrical data channels Asynchronous, AC-coupled optical link 12 optical data channels Internal power monitoring for constant power budget Transmission data rate of up to 1250 Mbit/s per channel, total link data rate up to 15 Gbit/s PIN diode array technology Optimized for 62.5 m multimode graded index fiber MT based optical port (MPO connector) Plug-in module with ultra low profile IEC Class 1M laser eye safety compliant OIF1) compliant GBE mask compliant modules available EMI-shielding for front panel access Standard link length compliant Unused transmitter channels can be switched off DC or AC coupling of input data Telcordia compliant
File: 3104
1)
OIF-VSR4-01.0 Implementation Agreement (VSR OC-192/STM-64).
PAROLI (R) is a registered trademark of Infineon Technologies AG
Data Sheet
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Applications Optical Port * * * * Designed for the industry standard 12 fiber MT Connector (MPO) Alignment pins fixed in module port Integrated mechanical keying Module is provided with a dust cover
Features of MT Connector (MPO) (as part of optional PAROLI fiber optic cables) * * * * Uses standardized MT ferrule MT compatible fiber spacing (250 m) and alignment pin spacing (4600 m) Push-pull mechanism Ferrule bearing spring loaded
Features of the PAROLI 2 Electrical Connector * * * * * * * * Pluggable version using BGA socket 100 pin positions (10x10) 4 mm stack height in mated conditions Plug and receptacle are provided with protective cap Standard BGA process for socket assembly Contact area plating made out of gold over nickel Module side: FCI-MEG-Array(R) -Plug (part no. 84512-202) PCB side: FCI-MEG-Array(R) -Receptacle (part no. 84513-201)
Applications * * * * * Switches, routers, transport equipment Mass storage devices Access network Rack-to-rack/board-to-board interconnect Optical backplane interconnect
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Pin Configuration Pin Configuration
Pin A1
Pin A10
Bottom view
File: 3331
Figure 1
Pin Information Transmitter
Numbering Conventions Transmitter (bottom view) J 1 2 3 4 5 6 7 8 9
VEE
DI04P DI04N DI01P DI01N DI02P DI02N DI03P DI03N
I
DI05N
H
DI05P
G
DI06N
F
DI06P
E
DI07N
D
DI07P
C
DI08N
B
DI08P
A
VEE
DI09N DI09P DI12N DI12P DI11N DI11P DI10N DI10P
VEE VEE VEE VEE VEE VEE VEE VEE VEE
VEE
VEE
VEE
VEE
t.b.l.o. t.b.l.o. t.b.l.o. -LE LE
VEE
VEE
VEE
Reserved Reserved t.b.l.o. Reserved Reserved t.b.l.o.
Reserved Reserved VEE Reserved Reserved VEE
VEE VEE VEE VEE VEE VEE
VEE VEE VEE VEE VEE VEE
t.b.l.o. t.b.l.o. LCU
VEE VEE VEE
VEE VEE VEE VEE VEE VEE
VEE VEE VEE VEE VEE VEE
VIN VCC VCC
-RESET VEE
VCC VCC
VEE VEE
10 VEE
VEE
This edge towards MPO connector
Data Sheet
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Pin Configuration Pin Description Transmitter Symbol Level/Logic Description Power supply voltage of laser driver CML: VIN = Reference supply (e.g. VCC) LVDS, LVPECL: VIN = VEE Ground LVCMOS Out Signal In Signal In Laser Controller Up. High = normal operation. Low = laser fault or RESETlow. Data Input #xx, inverted Data Input #xx, non-inverted
VCC VIN VEE
LCU
DIxxN DIxxP -RESET
LVCMOS In High = laser diode array is active. Low = switches laser diode array off. This input has an internal pull-down to ensure laser eye safety switch off in case of unconnected RESETinput. LVCMOS In Laser ENABLE. High active. High = laser array is on if LE is also active. Low = laser array is off. This input has an internal pull-up, therefore can be left open. LVCMOS In Laser ENABLE. Low active. Low = laser array is on if LE is also active. This input has an internal pull-down, therefore can be left open. to be left open Reserved for future use
LE
-LE
t.b.l.o. Reserved
Data Sheet
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Pin Configuration
Pin A1
Pin A10
Bottom view
File: 3332
Figure 2
Pin Information Receiver
Numbering Conventions Receiver (bottom view) J 1 2 3 4 5 6 7 8 9
VEE
DO04N DO04P DO01N DO01P DO02N DO02P DO03N DO03P
I
DO05P
H
DO05N
G
DO06P
F
DO06N
E
DO07P
D
DO07N
C
DO08P
B
DO08N
A
VEE
DO09P DO09N DO12P DO12N DO11P DO11N DO10P DO10N
VEE VEE VEE VEE VEE VEE VEE VEE VEE
VEE
VEE
VEE
VEE
t.b.l.o. ENSD -SD12
VEE
VEE
VEE
Reserved Reserved t.b.l.o. Reserved Reserved OEN
Reserved Reserved VEE Reserved Reserved VEE
VEE VEE VEE VEE VEE VEE
VEE VEE VEE VEE VEE VEE
SD01
VEE VEE VEE VEE VEE VEE
VEE VEE VEE VEE VEE VEE
VEE VEE VEE VEE VEE VEE
Reserved REFR
VCCO VCCO VCC VCC
VCCO VCCO VCC VCC
10 VEE
VEE
This edge towards MPO connector
Data Sheet
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Pin Configuration Pin Description Receiver Symbol Level/Logic Description Power supply voltage of pre amplifier and analog circuitry Power supply voltage of output stages Adjustment of output current by connecting external resistor to VEE Ground LVCMOS In Output Enable High = normal operation. Low = sets all Data Outputs to low. This input has an internal pull-up which pulls to high level when this input is left open. LVCMOS In High = SD1 and -SD12 function enabled. Low = SD1 and -SD12 are set to permanent active. This input has an internal pull-up which pulls to high level when this input is left open. LVCMOS Out LVCMOS Out low active CML Out CML Out Signal Detect on fiber #1. High = signal of sufficient AC power is present on fiber #1. Low = signal on fiber #1 is insufficient. Signal Detect on fiber #12. Low = signal of sufficient AC power is present on fiber #12. High = signal on fiber #12 is insufficient. Data Output #xx, non-inverted Data Output #xx, inverted to be left open Reserved for future use
VCC VCCO
REFR
VEE
OEN
ENSD
SD1
-SD12
DOxxP DOxxN t.b.l.o. Reserved
Data Sheet
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Description Description PAROLI is a parallel optical link for high-speed data transmission. A complete PAROLI link consists of a transmitter module, a 12-channel fiber optic cable, and a receiver module. The transmitter supports LVDS, CML and LVPECL differential signals. Two different receiver modules are available. Module V23832-R521-M101 is for LVDS electrical output only. This specification (V23832-R511-M101) describes a receiver for Infineon's adjustable CML output.
Transmitter
DC-balanced data stream
Receiver
VCSEL Array
Laser Driver
Converter
Converter
PIN-Array
12
12 parallel channels
12
PAROLI Link
Figure 3
Example of a PAROLI Link
Data Sheet
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Data Out
File: 3509
Amplifier
Data In
V23832-T2531-M101 V23832-R511-M101
Description Transmitter V23832-T2531-M101 The transmitter module converts parallel electrical input signals via a laser driver and a Vertical Cavity Surface Emitting Laser (VCSEL) diode array into parallel optical output signals. All input data signals are Multistandard Differential Signals (LVDS compatible; LVPECL and CML is also supported because of the wide common input range). The electrical interface (LVDS, LVPECL or CML) is selected by the supply inputs VIN. The data rate is up to 1250 Mbit/s for each channel. The transmitter module's min. data rate of 500 Mbit/s is specified for the CID1) worst case pattern (disparity 72) or any pattern with a lower disparity. The transmitter features active feedback of optical output power and extinction ratio, which guarantees a constant power budget. Unused channels can be forced to a quiescent state by applying e.g. a constant high level to the input stage of these channels. The integrated alerter circuit (see "Laser Eye Safety Design Considerations" on Page 12) will switch off the corresponding transmitter output, which results also in a reduced power consumption. Unused transmitter input channels can also be left open. The integrated swing detection circuit will assure a quiescent output state for these channels. A logic low level at -RESET switches all laser outputs off. During power-up -RESET must be used as a power-on reset which disables the laser driver and laser control until the power supply has reached a 3.135 V level. The Laser Controller Up (LCU) output is low if a laser fault is detected or -RESET is forced to low. All non data signals have LVCMOS levels. Transmission delay of the PAROLI system is 1 ns for the transmitter, 1 ns for the receiver and approximately 5 ns per meter for the fiber optic cable.
Electrical Input 12 Input Stage 12 LE -LE Laser Enable Optical Output 12 Data
Data In
Laser Driver
12
Laser Diode Array
Laser Control
VIN
-RESET
Laser Controller Up (LCU)
File: 3317
Figure 4
Transmitter Block Diagram
1)
Consecutive Identical Digit (CID) immunity test pattern for STM-N signals, ITU-T recommendation G.957 sec. II.
Data Sheet
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Description Receiver V23832-R511-M101 The PAROLI receiver module converts parallel optical input signals into parallel electrical output signals. The optical signals received are converted into voltage signals by PIN diodes, trans impedance amplifiers, and gain amplifiers. The differential data outputs are Infineon's adjustable CML signals. A separate module (V23832-R521-M101) with LVDS output is also available. The output differential voltage (swing) is adjusted by an external resistor connected to the REFR module input, the output average is adjustable by external pull-up resistors. The data rate is up to 1250 Mbit/s for each channel. The receiver module's min. data rate of 500 Mbit/s is specified for the CID1) worst case pattern (disparity 72) or any pattern with a lower disparity. Additional Signal Detect outputs (SD1 active high / -SD12 active low) show whether an optical AC input signal is present at data input 1 and/or 12. The signal detect circuit can be disabled with a logic low at ENSD. The disabled signal detect circuit will permanently generate an active level at Signal Detect outputs, even if there is insufficient signal input. This could be used for test purposes. A logic low at Output Enable sets all data outputs to logic low. SD outputs will not be effected. All non data signals have LVCMOS levels. Transmission delay of the PAROLI system is 1 ns for the transmitter, 1 ns for the receiver and approximately 5 ns per meter for the fiber optic cable.
Optical Input 12 Data Pin Diode Array 12 Amplifier Gain Amplifier Signal Detect Circuit 12
REFR 12
Electrical Output Data Out
CML Output Stage
SD1 -SD12
ENSD
Output Enable (OEN)
File: 3323
Figure 5
Receiver Block Diagram
1)
Consecutive Identical Digit (CID) immunity test pattern for STM-N signals, ITU-T recommendation G.957 sec. II.
Data Sheet
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Description Regulatory Compliance The following table shows industry standard test methods and results obtained from the indicated test methods. (The overall system design will affect the electromagnetic interference (EMI), electrostatic discharge (ESD) and immunity). Feature ESD: Electrostatic Discharge to the Electrical Pins (HBM) Standard JEDEC Human Body Model (HBM) Test Method EIA/JESD22-A114-B (MIL-STD 883D method 3015.7) Comments Class 1C
Immunity: EN 61000-4-2 Against Electrostatic IEC 61000-4-2 Discharge (ESD) to the Module Receptacle Immunity: Against Radio Frequency Electromagnetic Field Emission: Electromagnetic Interference (EMI) EN 61000-4-3 IEC 61000-4-3
Discharges ranging from 2 kV to 15 kV on the front end/face-plate/ receptacle cause no damage to module (under recommended mounting conditions). With a field strength of 3 V/m, noise frequency ranges from 10 MHz to 2 GHz1). No effect on module performance between the specification limits. Noise frequency range: 30 MHz to 18 GHz; Radiated Emission does not exceed specified limits when measured inside a shielding enclosure with recommended cutout dimensions. Typically pass with > 11 dB margin to the limit (under recommended mounting conditions).
FCC 47 CFR Part 15, Class B EN 55022 Class B CISPR 22
1)
This test covers high frequency bands of mobile phones.
EMI Recommendations EMI behavior of each PAROLI module revision is evaluated and measured - in order to ensure a good and sufficient EMI performance of all PAROLI modules. As the total EMI performance will also depend on system design and to avoid electromagnetic radiation exceeding the required limits set by the standards, please take note of the following recommendations.
Data Sheet
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Description When Gigabit switching components are found on a PCB (e.g. multiplexer, serializerdeserializer, clock data recovery, etc.), any opening of the chassis may leak radiation; this may also occur at chassis slots other than that of the device itself. Thus every mechanical opening or aperture should be as small as feasible and its length carefully considered. On the board itself, every data connection should be an impedance matched line (e.g. micro strip, strip line or coplanar strip line). Data (D) and Data-not (Dn) should be routed symmetrically. Vias should be avoided. Where internal termination inside an IC or a PAROLI module is not present, a line terminating resistor must be provided. The decision of how best to establish a ground depends on many boundary conditions. This decision may turn out to be critical for achieving lowest EMI performance. At RF frequencies the ground plane will always carry some amount of RF noise. Thus the ground and VCC planes are often major radiators inside an enclosure. As a general rule, for small systems such as PCI cards placed inside poorly shielded enclosures, the common ground scheme has often proven to be most effective in reducing RF emissions. In a common ground scheme, the PCI card becomes more equipotential with the chassis ground. As a result, the overall radiation will decrease. In a common ground scheme, it is strongly recommended to provide a proper contact between signal ground and chassis ground at every location where possible. This concept is designed to avoid hotspots which are places of highest radiation, caused when only a few connections between chassis and signal grounds exist. Compensation currents would concentrate at these connections, causing radiation. However, as signal ground may be the main cause for parasitic radiation, connecting chassis ground and signal ground at the wrong place may result in enhanced RF emissions. For example, connecting chassis ground and signal ground at a front panel/ bezel/chassis by means of a fiber optic module may result in a large amount of radiation especially where combined with an inadequate number of grounding points between signal ground and chassis ground. Thus the fiber optic module becomes a single contact point increasing radiation emissions. Even a capacitive coupling between signal ground and chassis ground may be harmful if it is too close to an opening or an aperture. For a number of systems, enforcing a strict separation of signal ground from chassis ground may be advantageous, providing the housing does not present any slots or other discontinuities. This separate ground concept seems to be more suitable in huge systems. The return path of RF current must also be considered. Thus a split ground plane between Tx and Rx paths may result in severe EMI problems. The bezel opening for a transceiver should be sized so that all contact springs of the transceiver cage make good electrical contact with the face plate. Please consider that the PCB may behave like a dielectric waveguide. With a dielectric constant of 4, the wavelength of the harmonics inside the PCB will be half of that in free space. Thus even the smallest PCBs may have unexpected resonances.
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V23832-T2531-M101 V23832-R511-M101
Laser Eye Safety Laser Eye Safety The transmitter of the AC coupled Parallel Optical Link (PAROLI) is an IEC 60825-1 Amend. 2 Class 1M laser product. It complies with FDA performance standards (21 CFR 1040.10 and 1040.11) for laser products except for deviations pursuant to Laser Notice No. 50, dated July 26, 2001. To avoid possible exposure to hazardous levels of invisible laser radiation, do not exceed maximum ratings. The PAROLI module must be operated under the specified operating conditions (supply voltage can be adjusted between 3.0 V and 3.6 V) under any circumstances to ensure laser eye safety. Class 1M Laser Product Attention: Invisible laser radiation. Do not view directly with optical instruments. Note: Any modification of the module will be considered an act of "manufacturing", and will require, under law, recertification of the product under FDA (21 CFR 1040.10 (i)).
Laser aperture and beam
File: 3506
Figure 6
Laser Emission
Laser Eye Safety Design Considerations To ensure laser eye safety for all input data patterns each channel is controlled internally and will be switched off if the laser eye safety limits are exceeded. A channel alerter switches the respective data channel output off if the input duty cycle permanently exceeds 57% (switching range 57 % min. - 65 % max.). The alerter will not disable the channel below an input duty cycle of 57% under all circumstances. The minimum alerter response time is 1 s with a constant high input, i.e. in the input pattern the time interval of excessive high input (e.g. '1's in excess of a 57% duty cycle, consecutive or non-consecutive) must not exceed 1 s, otherwise the respective channel will be switched off. The alerter switches the respective channel from off to on without the need of resetting the module if the input duty cycle is no longer violated. All of the channel alerters operate independently, i.e. an alert within a channel does not affect the other channels. To decrease the power consumption of the module unused channel inputs can be tied to high input level. In this way a portion of the supply current in this channel is triggered to shut down by the corresponding alerter.
Data Sheet
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Laser Eye Safety Laser Eye Safety Measurement Conditions Laser Data Symbol min. Center wavelength C Array size Divergence angle/ Numerical Aperture IEC class 1M Accessible Emission Limit Applying penalties (safety margin) Test limit /NA 44/0.22 830 Values typ. 850 12 max. 860 nm channels /rad full / NA half angle 7 mm aperture @ 100 mm distance Tcase 0...80C Unit Condition
AEL
6.36
dBm
Popt
4.2 2.16
dB dBm
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Technical Data Technical Data Absolute Maximum Ratings Stress beyond the values stated below may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods of time may affect device reliability. Performance between absolute maximum ratings and recommended operating conditions is not guaranteed. Parameter Supply Voltage Data/Control Input Levels
1)
Symbol
Limit Values min. max. 4.5 -0.3 -0.5 0 -40 5
Unit V V V C C % kV
VCC-VEE VIN
|VID|
VCC+0.5
2.0 90 100 95 1
Data Input Differential Voltage 2) Operating Case Temperature 3) Storage Ambient Temperature Relative Humidity (non condensing) ESD Resistance (all pins to VEE, human body model) 4) (see table "Regulatory Compliance" on Page 10)
1) 2) 3) 4)
Tcase Tstg
At Data and LVCMOS inputs. |VID| = |(input voltage of non-inverted input minus input voltage of inverted input)|. Measured at case temperature reference point (see Figure 18 on Page 31). To avoid electrostatic damage, handling cautions similar to those used for MOS devices must be observed.
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Technical Data Recommended Operating Conditions1) Parameter Transmitter Operating Case Temperature Power Supply Voltage Noise on Power Supply 2) Data Input Voltage Range (DC-coupled) 3), 4) Data Input Differential Voltage (DC- or AC-coupled) 4), 5) Data Input Skew 6) Data Input Rise/Fall Time
7)
Symbol min.
Values typ. 45 3.3 max. 80 3.6 200 500 80
Unit
Tcase VCC NPS VDATAI
|VID|
0 3.135
C V mV mV mV
VCC
1000
tSPN tR-DI, tF-DI 50 VLVCMOSIH 2.0 VLVCMOSIL VEE tR-LVCMOSI, tF-LVCMOSI VCC, VCCO 3.0 3.3 NPS Iout 3 Vout VCCO-1.8
|VOD| 80
0.5 x tR-DI, ps
tF-DI
360 ps V V ns LVCMOS Input High Voltage LVCMOS Input Low Voltage LVCMOS Input Rise/Fall Time 8) Receiver Power Supply Voltages Noise on Power Supply 2) Output Current 9) Output Voltage (DC-coupled) 10) Output Differential Voltage (DC- or AC-coupled)10), 11) LVCMOS Input High Voltage LVCMOS Input Low Voltage LVCMOS Input Rise/Fall Time 8) Optical Input Rise/Fall Time12) Input Extinction Ratio Input Center Wavelength
Voltages refer to VEE = 0 V.
VCC
0.8 20
3.6 200 9 800 150
V mV mA mV ps V V ns ps dB nm
VCCO+0.5 V
Output Load RC Time Constant tRC
VLVCMOSIH 2.0 VLVCMOSIL VEE tR-LVCMOSI, tF-LVCMOSI tR-OI, tF-OI
ER C 6.0 830
VCC
0.8 20 400 860
Data Sheet
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V23832-T2531-M101 V23832-R511-M101
Technical Data
1) 2)
3) 4) 5) 6) 7) 8) 9) 10) 11)
12)
Recommended range of input parameters for specified module functional performance. Noise frequency is 1 kHz to fmax, where fmax is equal to the maximum data rate in units of MHz. E.g. for a maximum data rate of 2700 Mbit/s, fmax = 2700 MHz. Power supply noise is defined with the recommended filter in place at the supply side of the filtering circuit (see Figure 9 on Page 17). The input stage can also be AC-coupled. Input level diagram: see Figure 7 on Page 16. |VID| = |(input voltage of non-inverted input minus input voltage of inverted input)|. Skew between positive and negative inputs measured at 50% level. 20% - 80% level. Measured between 0.8 V and 2.0 V. Iout 10*1.15 V/Rexternal. Resistor Rexternal to be connected externally between REFR and VEE. Output level diagram: see Figure 8 on Page 16. |VOD| = Iout*(300 || RLOAD). The output current range of 3 mA to 9 mA corresponds to |VOD| = 130 mV to 385 mV for RLOAD = 50 . |VOD| = |(output voltage of non-inverted output minus output voltage of inverted output)|. 20% - 80% level. Non filtered values.
mV VCC |VID| 500
Time
File: 3318
Figure 7
Input Level Diagram, DC-coupling
mV VCCO+0.5 |VOD| VCCO-1.8
Time
File: 3319
Figure 8
Output Level Diagram, DC-coupling
Data Sheet
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Technical Data Recommended Power Supply Filtering A power supply filtering is recommended for the transmitter and the receiver module. A possible filtering scheme is shown in Figure 9. The module signal and chassis ground refer to a common ground plane, which can be contacted to the PCB ground by the mounting screws (see Figure 17 "PCB Layout" on Page 28).
VCC
L1 1 H
VCC to PAROLI Tx or Rx Module
C1 22 F
C3 100 nF
C2 100 nF
Board Ground Plane
File: 3330
Figure 9
Filtering Scheme
Transmitter Module VCC Data In P Rin/2 Rin/2 Data In N VIN > 6 k 1.95 V
File: 3320
internal P
internal N
Figure 10
Transmitter - Input Stage
Data Sheet
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Technical Data
Receiver Module 600 internal logic signal
Out P Out N
Iout: 3 mA...9 mA Iout (adjust- max. high level = VCCO+0.5 V able) min. low level = VCCO-1.8 V BGR ~1.15 V VCCO: Paroli module supply for output stage Iout /10 REFR module pin Rexternal (one setting applies to all outputs)
File: 3324
Figure 11
Receiver - CML Output Stage
Data Sheet
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Technical Data The electro-optical characteristics described in the following tables are valid only for use under the recommended operating conditions. Transmitter Electrical Characteristics Parameter Supply Current1) Power Consumption1) Data Rate per Channel LVCMOS Output Voltage Low LVCMOS Output Voltage High LVCMOS Input Current High/Low LVCMOS Output Current Low 4) Data Differential Input Impedance 5)
1)
Symbol min.
Values typ. 400 1.3 500 2) max. 450 1.6 1250 0.4 100 0.5 4.0 100 120
Unit mA W Mbit/s V V A mA mA
ICC P
DR
VLVCMOSOL VLVCMOSOH 2.5 ILVCMOSI -100
LVCMOS Output Current High 3) ILVCMOSOH
ILVCMOSOL RIN 80
2)
3) 4) 5)
Measured at the recommended case temperature of Tcase = 45C. For Tcase = 0C a decrease of approximately 10% and for Tcase = 80C an increase of approximately 15% can be expected. Specified for CID worst case pattern (disparity 72) or any pattern with a smaller disparity. The minimum data rate depends on the disparity of the used data pattern. For example, a regular clock signal (1-0 sequence) can be transmitted down to a data rate as low as 1 Mbit/s. Source current. Sink current. Data input stage.
Data Sheet
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Technical Data Transmitter Electro-Optical Characteristics Parameter Optical Rise Time 1) Optical Fall Time 1) Total Jitter 2), 3) Deterministic Jitter3), 4) Channel-to-channel skew
5) 6)
Symbol min.
Values typ. max. 200 200 0.284 0.1 100 -8.0 830 -5.0 850 0.35 6.0 0.19 12) 0.46 13) GBE -3.0 -30.0 860 0.65 -117
Unit ps ps UI UI ps dBm dBm nm nm dB/Hz dB mW
tR tF
TJ DJ
Launched Average Power Center Wavelength
7)
Launched Power Shutdown Spectral Width (rms)8) Relative Intensity Noise9) Extinction Ratio (dynamic) Optical Modulation Amplitude 10), 11) Eye mask compliance
tCSK PAVG PSD
C RIN ER OMA
Electro-optical parameters valid for each channel and measured at the highest specified data rate. All optical parameters are measured with a 62.5 m multimode fiber.
1) 2)
3) 4)
5)
6)
7) 8) 9) 10) 11)
12) 13)
20% - 80% level, non filtered values. The Total Jitter (TJ) is composed of Random Jitter (RJ) and Deterministic Jitter (DJ) according to: TJ = RJ (14 Sigma value) + DJ. The TJ is specified at a BER of 10-12 from TP1 to TP2 according to IEEE 802.3, sec. 38.5. The RJ is measured at the 50% level of the optical signal as the mean of the rising and falling edge measurement value. UI (Unit Interval) is equal to the length of one bit. For example, 2.72 Gbit/s corresponds to 368 ps. The DJ consists of Duty Cycle Distortion and Data Dependent Jitter and is measured according to IEEE 802.3 using a K28.5 pattern. With input channel-to-channel skew 0 ps and a maximum data channel-to-channel average deviation and swing deviation of 5%. The specified output power is compliant with IEC 60825-1, Amendment 2, Class 1M Accessible Emission Limits (AEL). Wavelength is measured according to IEEE 802.3, sec. 38.6.1. Spectral width is measured according to IEEE 802.3, sec. 38.6.1. RIN is measured according to IEEE 802.3, sec. 38.6.4. Peak to peak values. OMA is defined as the difference of the optical high state ('1') and the optical low state ('0'): OMA = Popt('1') - Popt('0'). Corresponds to a minimum extinction ratio of 6 dB. Corresponds to a typical extinction ratio of 8 dB.
Data Sheet
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Technical Data
VCC
3.6 V 3.135 V
-RESET
2.0 V 0.8 V t3
Data
data invalid t1
data valid t2
File: 3321
Figure 12 Parameter
Timing Diagram Symbol min. Values typ. 15 100 10 max. 50 500 ms ns s Unit
-RESET on delay time -RESET off delay time -RESET low duration 1)
1)
t1 t2 t3
Only when not used as power on reset. At any failure recovery, -RESET must be brought to low level for at least t3.
Data Sheet
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Technical Data Receiver Electrical Characteristics Parameter Supply Current
1)
Symbol min.
Values typ. 170 +15 Iout 0.7 max. 200 +15 Iout 0.9 250 400 100 0.5 4.0 0.33 0.08 100
Unit mA W ps mV mV A mA mA UI UI ps
ICC P tR-DO, tF-DO VLVCMOSOL VLVCMOSOH 2500 ILVCMOSI -100 ILVCMOSOH ILVCMOSOL
TJ DJ
Power Consumption1), 2) Data Output Rise/Fall Time 3) LVCMOS Output Voltage Low LVCMOS Output Voltage High LVCMOS Input Current High/Low LVCMOS Output Current High 4) LVCMOS Output Current Low 5) Total Jitter 6), 7), 8), 9), 10) Deterministic Jitter 6), 9), 11) Channel-to-channel skew 12)
1) 2) 3)
tCSK
4) 5) 6) 7) 8) 9) 10)
11)
12)
Typical value is measured at Tcase = 45C and 3.3 V, maximum value is measured at Tcase = 80C and 3.6 V. Calculated for Iout = 3 mA. Measured between 20% and 80% level. Maximum value is related to a maximum RC load time constant of tRC = 150 ps. Source current. Sink current. With no optical input jitter. Measured with an optical input power of 3 dB above minimum receiver sensitivity. Unused channels shall be terminated by 50 . UI (Unit Interval) is equal to the length of one bit. For example, 2.72 Gbit/s corresponds to 368 ps. The Total Jitter (TJ) is the sum from Random Jitter (RJ) and Deterministic Jitter (DJ) according to: TJ = RJ (14 Sigma value) + DJ. The TJ is specified at a BER of 10-12 from TP3 to TP4 according to IEEE 802.3, sec. 38.5. The RJ is measured at the 50% level of the optical signal as the mean of the rising and falling edge RJ measurement value. The DJ consists of Duty Cycle Distortion and Data Dependent Jitter and is measured according to IEEE 802.3 using a K28.5 pattern. With input channel-to-channel skew 0 ps.
Data Sheet
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V23832-T2531-M101 V23832-R511-M101
Technical Data Receiver Electro-Optical Characteristics Parameter Data Rate Per Channel Sensitivity (Average Power)
2)
Symbol min. DR 500
1)
Values max. 1250 -16.0 0.030 4) -2.0 -17.0 -27.0 1.0 12 4.0
Unit Mbit/s dBm mW dBm dBm dBm dB dB
PIN
OMA
Optical Modulation Amplitude 3) Saturation (Average Power)5) Signal Detect Assert Level 6) Signal Detect Deassert Level 6) Signal Detect Hysteresis 6) Return Loss of Receiver 7)
PSAT PSDA PSDD PSDA
-PSDD ORL
Electro-optical parameters valid for each channel and measured at the highest specified data rate. All optical parameters are measured with a 62.5 m multimode fiber.
1)
2)
3) 4) 5) 6)
7)
Specified for CID worst case pattern (disparity 72) or any pattern with a smaller disparity. The minimum data rate depends on the disparity of the used data pattern. For example, a regular clock signal (1-0 sequence) can be received down to a data rate as low as 6 Mbit/s. Sensitivity is measured for BER = 10-12 with a Pseudo Random Bit sequence of length 223-1 (PRBS23) and a test pattern source with RIN of -117 dB/Hz or better. Sensitivity is specified for the worst case extinction ratio and maximum cross talk possibility. The maximum crosstalk possibility is defined as the "victim" receiver channel operating at its sensitivity limit and the neighboring channels operating at 6 dB higher incident optical power. Peak to peak value. Corresponds to a maximum sensitivity (average power) of -16 dBm at an extinction ratio of 6 dB. Saturation is specified with a Pseudo Random Bit sequence of length 223-1 (PRBS23) and ER 6 dB. PSDA: Average optical power when SD switches from inactive to active. PSDD: Average optical power when SD switches from active to inactive. Return loss is specified as the ration of the received optical power to the reflected optical power back into the link fiber.
Data Sheet
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V23832-T2531-M101 V23832-R511-M101
Technical Data
Data Out 1, 12 t1 Signal Detect 1 t2
Signal Detect 12
File: 3325
Output Enable OEN
2.0 V 0.8 V
Data Out
data valid t3
data Low t4
data valid
File: 3326
Figure 13 Parameter
Timing Diagrams Symbol min. Values typ. 3 2 14 18 max. 10 10 20 20 s s s s Unit
Signal Detect Deassert Time Signal Detect Assert Time Output Enable off Delay Time Output Enable on Delay Time
t1 t2 t3 t4
Data Sheet
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Technical Data
VCC 2 x 50 Receiver Module 600 internal logic signal Out P Out N In P In N
Iout (adjustable)
BGR
Iout /10 REFR module pin Rexternal (one setting applies to all outputs)
File: 3327
Figure 14
Interfacing to CML
Data Sheet
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V23832-T2531-M101 V23832-R511-M101
Technical Data
VCC 2 x 300 Receiver Module 600 Out N internal logic signal Out P In P 100 In N
Iout (adjustable)
BGR
Iout /10 REFR module pin Rexternal (one setting applies to all outputs)
File: 3328
VCC 2 x 75 Receiver Module 600 internal logic signal Out P Out N In P In N 2 x 150
Iout (adjustable)
BGR
Iout /10 REFR module pin Rexternal (one setting applies to all outputs)
File: 3329
Figure 15
Interfacing to LVPECL
Data Sheet
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V23832-T2531-M101 V23832-R511-M101
Technical Data Host Face-Plate Layout for Panel Accessed Modules
F1 F2
F6
F3
F4
F9 F10
F11 F7 F12 F8 F5 File: 3507
Figure 16 Key min. F1 F2 F3 F4 F5 F6 F7 F8 F9 F10 F11 F12 15.3 7.6 1.7 mm 16.8 4.25 38 18.42 16.7 9.1 4.42 44.5 Values typ. 20 16.8 9.2 4.52 16.9 9.3 4.62 46 1 max. mm mm mm mm mm mm mm mm mm mm Cutout center spacing Cutout width Cutout height Center of cutout and center of receptacle to top of PCB Face-plate placement Radius Opt. reference plane to top of PCB Limitation for PCB length Length of receptacle Including shield, without spring contacts Including shield, without spring contacts See Package Outlines Figure 18 on Page 31
27 2003-11-19
Unit
Comments
Data Sheet
V23832-T2531-M101 V23832-R511-M101
Technical Data
Dimensions in mm
File: 3508
Figure 17
PCB Layout
1. Figure 17 describes the recommended customer board layout for the PAROLI 2 modules. 2. The holes for the screwing leads and ground plates must be tied to signal ground. 3. Modules must be screwed on the 4 indicated positions (tightening torque should be typically 10 cNm). 4. Screw size for PCB or heat sink mounting = M1.6. 5. Screw length (PCB mounting) = PCB thickness + 5.2-0.5 mm. 6. Screw length (heat sink mounting) = heat sink thickness + 3.1-0.5 mm. 7. Modules can be mounted directly side by side. 8. The dashed lines in Figure 17 indicate the typical keep out area for straight MPO connectors as well as for the module MPO receptacle in case of central board placement of the module.
Data Sheet
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Technical Data Thermal Characteristics The thermal behaviour of PAROLI modules (transmitter and receiver) depends on the operating conditions for different applications. The following table gives a guideline for system designers. T case - T ambient The thermal resistance Rth ( R th = ------------------------------------------ ; Pel = electrical power consumption)
P el
can be used for calculating the module case temperature under different operating conditions and is displayed for two different module options: a) Baseplate module without heat sink. b) Baseplate module with customer designed heat sink (e.g. height = 9 mm, length = 41 mm, width = 18 mm, no. of cooling fins = 9). Air Velocity1) Rth - Option a) Rth - Option b)
1)
0 m/s 23.3 20.0
1.5 m/s 10.3 5.2
3 m/s 8.6 4.2
4 m/s 7.5 4.0
Unit K/W K/W
The air velocity is applied along the shortest side of the module in parallel to the direction of the heat sinks.
Link Length The link length calculations are based on the most conservative assumption of PAROLI modules working on their worst case specification limits. Multimode fibers of different types (modal bandwidth at 850 nm) are shown. The stated link length is valid under all specified operating conditions and includes 2 dB of additional connector loss.
Fiber Type Diameter Core/Cladding [m] 62.5 / 125 62.5 / 125
Modal Bandwidth [MHz*km] 200 400
Link Distance at 0.5 Gbit/s [m] 850 1300
Link Distance at 1.25 Gbit/s [m] 360 640
Data Sheet
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Technical Data Channel Description Transmitter Module (front view as looking into the MPO connector receptacle of the module)
Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1
Host PCB below
Receiver Module (front view as looking into the MPO connector receptacle of the module)
Ch 12 Ch 11 Ch 10 Ch 9 Ch 8 Ch 7 Ch 6 Ch 5 Ch 4 Ch 3 Ch 2 Ch 1
Host PCB below
The MPO connector provides a keying functionality, which requires a 180 degree twist of fiber cable, if used as a direct connection between transmitter and receiver module. (For example the transmitter channel 1 is directly connected to the receiver cannel 1).
Handling Instructions Washing Process The PAROLI mating BGA connector can be handled according to standard industry wave solder, hand solder and washing processes. The PAROLI modules shall not be washed, due to possible influence on module performance. Dust Cover The optical connector is provided with a dust cover, which protects the optical interface from potential damage and contamination from dust during handling. The dust cover should always remain in the module, when no connector is used.
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Package Outlines Package Outlines
PAROLI 2 Tx
Temperature Reference Point on top of the module
PAROLI 2 Rx
Temperature Reference Point on top of the module
Typical module mass approximately 10.4 grams The front collar EMI shield is electrically separated from module signal ground Dimensions in mm
File: 3203
Figure 18
Data Sheet 31 2003-11-19
V23832-T2531-M101 V23832-R511-M101
Ordering Information Ordering Information Part Number V23832-T2531-M101 V23832-T2131-M101 V23832-T2431-M101 V23832-T2331-M101 V23832-R521-M101 V23832-R121-M101 V23832-R421-M101 V23832-R321-M101 V23832-R511-M101 V23832-R111-M101 V23832-R411-M101 V23832-R311-M101 Description PAROLI Transmitter, 12 x 1.25 Gbit/s, multistandard electrical interface PAROLI Transmitter, 12 x 1.6 Gbit/s, multistandard electrical interface PAROLI Transmitter, 12 x 2.7 Gbit/s, multistandard electrical interface PAROLI Transmitter, 12 x 3.125 Gbit/s, multistandard electrical interface PAROLI Receiver, 12 x 1.25 Gbit/s, LVDS electrical interface PAROLI Receiver, 12 x 1.6 Gbit/s, LVDS electrical interface PAROLI Receiver, 12 x 2.7 Gbit/s, LVDS electrical interface PAROLI Receiver, 12 x 3.125 Gbit/s, LVDS electrical interface PAROLI Receiver, 12 x 1.25 Gbit/s, CML electrical interface PAROLI Receiver, 12 x 1.6 Gbit/s, CML electrical interface PAROLI Receiver, 12 x 2.7 Gbit/s, CML electrical interface PAROLI Receiver, 12 x 3.125 Gbit/s, CML electrical interface
Data Sheet
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V23832-T2531-M101 V23832-R511-M101 Revision History: Previous Version: Page 2003-11-19 2003-05-21 DS2
Subjects (major changes since last revision) Document completely revised
Edition 2003-11-19 Published by Infineon Technologies AG, St.-Martin-Strasse 53, 81669 Munchen, Germany
(c) Infineon Technologies AG 2003.
All Rights Reserved. Attention please! The information herein is given to describe certain components and shall not be considered as a guarantee of characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office (www.infineon.com). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.

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