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W28V400B/T 4M(512K x 8/256K x 16) SMARTVOLTAGE FLASH MEMORY
Table of Contents1. GENERAL DESCRIPTION.................................................................................................................. 3 2. FEATURES ......................................................................................................................................... 3 3. PRODUCT OVERVIEW ...................................................................................................................... 4 4. BLOCK DIAGRAM .............................................................................................................................. 5 5. PIN CONFIGURATION ....................................................................................................................... 6 6. PIN DESCRIPTION ............................................................................................................................. 7 7. PRINCIPLES OF OPERATION........................................................................................................... 8 Data Protection ................................................................................................................................ 8 8. BUS OPERATION ............................................................................................................................. 10 Read............................................................................................................................................... 10 Output Disable ............................................................................................................................... 10 Standby .......................................................................................................................................... 10 Deep Power-down.......................................................................................................................... 10 Read Identifier Codes Operation ................................................................................................... 11 Write ............................................................................................................................................... 11 9. COMMAND DEFINITIONS................................................................................................................ 11 Read Array Command ................................................................................................................... 13 Read Identifier Codes Command................................................................................................... 13 Read Status Register Command ................................................................................................... 14 Clear Status Register Command ................................................................................................... 14 Block Erase Command .................................................................................................................. 14 Word/Byte Write Command ........................................................................................................... 15 Block Erase Suspend Command ................................................................................................... 15 Word/Byte Write Suspend Command ............................................................................................ 16 Considerations of Suspend ............................................................................................................ 16 Block Locking ................................................................................................................................. 16 10. DESIGN CONSIDERATIONS ......................................................................................................... 22 Three-line Output Control............................................................................................................... 22 RY/#BY, Block Erase and Word/Byte Write Polling....................................................................... 22 Power Supply Decoupling .............................................................................................................. 22
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Publication Release Date: April 11, 2003 Revision A4
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VPP Trace on Printed Circuit Boards .............................................................................................. 22 VDD, VPP, #RESET Transitions ...................................................................................................... 22 Power-up/Down Protection ............................................................................................................ 23 Power Dissipation .......................................................................................................................... 23 11. ELECTRICAL SPECIFICATIONS ................................................................................................... 24 Absolute Maximum Ratings* .......................................................................................................... 24 Operating Conditions ..................................................................................................................... 24 Capacitance(1)............................................................................................................................... 24 AC Input/Output Test Conditions ................................................................................................... 25 DC Characteristics ......................................................................................................................... 27 AC Characteristics - Read-only Operations(1) .............................................................................. 29 AC Characteristics - Write Operations(1) ...................................................................................... 33 Alternative #CE-Controlled Writes(1)............................................................................................. 37 Reset Operations ........................................................................................................................... 41 Block Erase And Word/Byte Write Performance(3) ....................................................................... 42 12. FLASH MEMORY W28V400 FAMILY DATA PROTECTION ......................................................... 44 Recommended Operating Conditions............................................................................................ 45 13. ORDERING INFORMATION........................................................................................................... 47 14. PACKAGE DIMENSION.................................................................................................................. 47 48-Lead Standard Thin Small Outline Package (measured in millimeters)................................... 47 15. VERSION HISTORY ....................................................................................................................... 48
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W28V400B/T
1. GENERAL DESCRIPTION
The W28V400B/T Flash memory with SmartVoltage technology is a high-density, cost-effective, nonvolatile, read/write storage solution for a wide range of applications. It operates off of VDD = 2.7V and VPP = 2.7V. This low voltage operation capability realize battery life and suits for cellular phone application. Its Boot, Parameter and Main-blocked architecture, as well as low voltage and extended cycling. These features provide a highly flexible device suitable for portable terminals and personal computers. Additionally, the enhanced suspend capabilities provide an ideal solution for both code and data storage applications. For secure code storage applications, such as networking where code is either directly executed out of flash or downloaded to DRAM, the device offers four levels of protection. These are: absolute protection, enabled when VPP VPPLK; selective hardware blocking; flexible software blocking; or write protection. These alternatives give designers comprehensive control over their code security needs. The device is manufactured on 0.35 m process technology. It comes in industry-standard package: the 48-lead TSOP, ideal for board constrained applications.
2. FEATURES
* SmartVoltage Technology
- VDD = 2.7V, 3.3V or 5V - VPP = 2.7V, 3.3V, 5V or 12V
* User-Configurable x 8 or x 16 Operation * High-Performance Access Time
- Automatic Power Savings Mode Decreases ICCR in Static Mode
* Enhanced Automated Suspend Options
- Word/Byte Write Suspend to Read - Block Erase Suspend to Word/Byte Write - Block Erase Suspend to Read
* Enhanced Data Protection Features
- 85 nS (5V 0.25V), 90 nS (5V 0.5V), 100 nS (3.3V 0.3V), 120 nS (2.7V to 3.6V)
* Operating Temperature
- Absolute Protection with VPP VPPLK - Block Erase, Full Chip Erase, Word/Byte Write and Lock-Bit Configuration Lockout during Power Transitions - Block Blocks Protection with #WP = VIL
* Automated Word/Byte Write and Block Erase
- 0 C to +70 C
* Optimized Array Blocking Architecture
- Two 4k-word (8k-byte) Boot Blocks - Six 4k-word (8k-byte) Parameter Blocks - Seven 32k-word (64k-byte) Main Blocks - Top Boot Location (W28V400TT) - Bottom Boot Location (W28V400BT)
* Extended Cycling Capability
- Command User Interface (CUI) - Status Register (SR)
* SRAM-Compatible Write Interface * Industry-Standard Packaging
- Minimum 100,000 Block Erase Cycles
* Low Power Management
- 48-Lead TSOP
- Deep Power-down Mode
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3. PRODUCT OVERVIEW
The W28V400B/T is a high-performance 4M-bit SmartVoltage Flash memory organized as 512k-byte of 8 bits or 256k-word of 16 bits. The 512k-byte/256k-word of data is arranged in two 8k-byte/4k-word boot blocks, six 8k-byte/4k-word parameter blocks and seven 64kbyte/32k-word main blocks which are individually erasable in-system. The memory map is shown in Figure 3. SmartVoltage technology provides a choice of VDD and VPP combinations, as shown in Table 1, to meet system performance and power expectations. 2.7V VDD consumes approximately one-fifth the power of 5V VDD. But, 5V VDD provides the highest read performance. VPP at 2.7, 3.3V and 5V eliminates the need for a separate 12V converter, while VPP = 12V maximizes block erase and word/byte write performance. In addition to flexible erase and program voltages, the dedicated VPP pin gives complete data protection when VPP VPPLK. Table 1. VDD and VPP Voltage Combinations Offered by SmartVoltage Technology
VDD VOLTAGE VPP VOLTAGE
2.7V 3.3V 5V
2.7V, 3.3V, 5V, 12V 3.3V, 5V, 12V 5V, 12V
Internal VDD and VPP detection Circuitry automatically configures the device for optimized read and write operations. A Command User Interface (CUI) serves as the interface between the system processor and internal operation of the device. A valid command sequence written to the CUI initiates device automation. An internal Write State Machine (WSM) automatically executes the algorithms and timings necessary for block erase and word/byte write operations. A block erase operation erases one of the device's 32k-word blocks typically within 0.39s (5V VDD, 12V VPP), 4k-word blocks typically within 0.25s (5V VDD, 12V VPP) independent of other blocks. Each block can be independently erased 100,000 times. Block erase suspend mode allows system software to suspend block erase to read or write data from any other block. Writing memory data is performed in word/byte increments of the device's 32k-word blocks typically within 8.4 S (5V VDD, 12V VPP), 4k-word blocks typically within 17 S (5V VDD, 12V VPP). Word/byte write suspend mode enables the system to read data or execute code from any other flash memory array location. The boot blocks can be locked for the #WP pin. Block erase or word/byte write for boot block must not be carried out by #WP to Low and #RESET to VIH. The status register indicates when the WSM's block erase or word/byte write operation is finished. The RY/#BY output gives an additional indicator of WSM activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). Status polling using RY/#BY minimizes both CPU overhead and system power consumption. When low, RY/#BY indicates that the WSM is performing a block erase or word/byte write. RY/#BY-high indicates that the WSM is ready for a new command, block erase is suspended (and word/byte write is inactive), word/byte write is suspended, or the device is in deep power-down mode.
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The access time is 85ns (tAVQV) over the commercial temperature range (0 C to +70 C) and VDD supply voltage range of 4.75V to 5.25V. At lower VDD voltages, the access times are 90ns (4.5V to 5.5V), 100 nS (3.0V to 3.6V) and 120 nS (2.7V to 3.6V). The Automatic Power Savings (APS) feature substantially reduces active current when the device is in static mode (addresses not switching). In APS mode, the typical ICCR current is 1mA at VDD = 5V. When #CE and #RESET pins are at VDD, the ICC CMOS standby mode is enabled. When the #RESET pin is at VSS, deep power-down mode is enabled which minimizes power consumption and provides write protection during reset. A reset time (tPHQV) is required from #RESET switching high until outputs are valid. Likewise, the device has a wake time (tPHEL) from #RESET-high until writes to the CUI are recognized. With #RESET at VSS, the WSM is reset and the status register is cleared. The device is available in 48-lead TSOP (Thin Small Outline Package, 1.2 mm thick). Pinout is shown in Figure 2.
4. BLOCK DIAGRAM
DQ0 -DQ15
Output Buffer
Input Buffer
I/O Logic Identifier Register Output Multiplexer Status Register Data Register Command User Interface
A-1 VDD #BYTE #CE #WE #OE #RESET #WP
Data Comparator
Parameter Block 0
Parameter Block 1
Parameter Block 2
Parameter Block 3
Parameter Block 4
Parameter Block 5
A0-A17
Boot Block 0
Boot Block 1
Input Buffer
Y Decoder
Y-Gating
Main Block 0 Main Block 1
Write State Machine
Main Block 5 Main Block 6
RY/#BY Program/Erase Voltage Switch VPP
Address Latch
X Decoder
32K-Word (64K-Byte) Main Blocks x7
VDD VSS
Address Counter
Figure 1. Block Diagram
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5. PIN CONFIGURATION
A15 A14 A13 A12 A11 A10 A9 A8 NC NC #WE #RESET VPP #WP RY/#BY NC A17 A7 A6 A5 A4 A3 A2 A1
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24
48-pin TSOP Standard Pinout 12mm X 20mm Top View
48 47 7 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25
A16 #BYTE Vss DQ15/A-1 DQ7 DQ14 DQ6 DQ13 DQ5 DQ12
DQ4
VDD DQ11 DQ3 DQ10 DQ2 DQ9 DQ1 DQ8 DQ0 #OE Vss #CE A0
Figure 2. TSOP 48-Lead Pinout
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W28V400B/T
6. PIN DESCRIPTION
SYM.
A-1 A0 - A17
TYPE
NAME AND FUNCTION
ADDRESS INPUTS: Addresses are internally latched during a write cycle. A - 1: Byte Select Address. Not used in x 16 mode. A0 - A10: Row Address. Selects 1 of 2048 word lines. A11 - A14: Column Address. Selects 1 of 16 bit lines. A15 - A17: Main Block Address. (Boot and Parameter block Addresses are A12 - A17.) DATA INPUT/OUTPUTS: DQ0 - DQ7:Inputs data and commands during CUI write cycles; outputs data during memory array, status register and identifier code read cycles. Data pins float to high-impedance when the chip is deselected or outputs are disabled. Data is internally latched during a write cycle. DQ8 - DQ15:Inputs data during CUI write cycles in x 16 mode; outputs data during memory array read cycles in x 16 mode; not used for status register and identifier code read mode. Data pins float to high-impedance when the chip is deselected, outputs are disabled, or in x 8 mode (#Byte = VIL). Data is internally latched during a write cycle. CHIP ENABLE: Activates the device's control logic, input buffers, decoders and sense amplifiers. #CE-high deselects the device and reduces power consumption to standby levels. RESET/DEEP POWER-DOWN: Puts the device in deep power-down mode and resets internal automation. #RESET-high enables normal operation. When driven low, #RESET inhibits write operations which provides data protection during power transitions. Exit from deep power-down sets the device to read array mode. With #RESET = VHH, block erase or word/byte write can operate to all blocks without #WP state. Block erase or word/byte write with VIH < #RESET < VHH produce spurious results and should not be attempted. OUTPUT ENABLE: Gates the device's outputs during a read cycle. WRITE ENABLE: Controls writes to the CUI and array blocks. Addresses and data are latched on the rising edge of the #WE pulse. WRITE PROTECT: Master control for boot blocks locking. When VIL, locked boot blocks cannot be erased and programmed. BYTE ENABLE: #BYTE VIL places the device in byte mode (x 8), All data is then input or output on DQ0 - 7, and DQ8 - 15 float. #BYTE VIH places the device in word mode (x 16), and turns off the A-1 input buffer. READY/#BUSY: Indicates the status of the internal WSM. When low, the WSM is performing an internal operation (block erase or word/byte write). RY/#BY-high indicates that the WSM is ready for new commands, block erase is suspended, and word/byte write is inactive, word/byte write is suspended, or the device is in deep power-down mode. RY/#BY is always active and does not float when the chip is deselected or data outputs are disabled. BLOCK ERASE AND WORD/BYTE WRITE POWER SUPPLY: For erasing array blocks or writing words/bytes. With VPP VPPLK, memory contents cannot be altered. Block erase and word/byte write with an invalid VPP (see DC Characteristics) produce spurious results and should not be attempted. DEVICE POWER SUPPLY: Internal detection configures the device for 2.7V, 3.3V or 5V operation. To switch from one voltage to another, ramp VDD down to VSS and then ramp VDD to the new voltage. Do not float any power pins. With VDD VLKO, all write attempts to the flash memory are inhibited. Device operations at invalid VDD voltage (see DC Characteristics) produce spurious results and should not be attempted. GROUND: Do not float any ground pins. NO CONNECT: Lead is not internal connected; it may be driven or floated. Table 1.
INPUT
DQ0 - DQ15
INPUT/ OUTPUT
#CE
INPUT
#RESET
INPUT
#OE #WE #WP
INPUT INPUT INPUT
#BYTE
INPUT
RY/#BY
OUTPUT
VPP
SUPPLY
VDD
SUPPLY
VSS NC
SUPPLY
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7. PRINCIPLES OF OPERATION
The W28V400B/T SmartVoltage Flash memory includes an on-chip WSM to manage block erase and word/byte write functions. It allows for 100 percent TTL-level control inputs, fixed power supplies during block erase, full chip erase, word/byte write and lock-bit configuration, and minimal processor overhead with RAM-like interface timings. After initial device power-up or return from reset mode (see Bus Operations section), the device defaults to read array mode. Manipulation of external memory control pins allow array read, standby and output disable operations. Status register and identifier codes can be accessed through the CUI independent of the VPP voltage. High voltage on VPP enables successful block erase, word/byte writing. All functions associated with altering memory contents (block erase, word/byte write, status and identifier codes) are accessed via the CUI and verified through the status register. Commands are written using standard microprocessor write timings. The CUI contents serve as input to the WSM, which controls the block erase and word/byte write. The internal algorithms are regulated by the WSM, including pulse repetition, internal verification and margining of data. Addresses and data are internally latched during write cycles. Writing the appropriate command outputs array data, accesses the identifier codes, or outputs status register data. Interface software that initiates and polls progress of block erase and word/byte write can be stored in any block. This code is copied to and executed from system RAM during flash memory updates. After successful completion, reads are again possible via the Read Array command. Block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspend. Word/byte write suspend allows system software to suspend a word/byte write to read data from any other flash memory array location.
Data Protection
Depending on the application, the system designer may choose to make the VPP power supply switchable (available only when memory block erases or word/byte writes are required) or hardwired to VPPH1/2/3. The device accommodates either design practice and encourages optimization of the processor-memory interface. When VPP VPPLK, memory contents cannot be altered. The CUI, with two-step block erase or word/byte write command sequences, provides protection from unwanted operations even when high voltage is applied to VPP. All write functions are disabled when VDD is below the write lockout voltage VLKO or when #RESET is at VIL. The device's boot blocks locking capability for #WP provides additional protection from inadvertent code or data alteration by block erase and word/byte write operations. Refer to Table 6 for write protection alternatives.
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W28V400B/T
Top Boot
3FFFF 3F000 3EFFF 3E000 3DFFF 3D000 3CFFF 3C000 3BFFF 3B000 3AFFF 3A000 39FFF 39000 38FFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 00000
Bottom Boot
3FFFF 38000 37FFF 30000 2FFFF 28000 27FFF 20000 1FFFF 18000 17FFF 10000 0FFFF 08000 07FFF 07000 06FFF 06000 05FFF 05000 04FFF 04000 03FFF 03000 02FFF 02000 01FFF 01000 00FFF 00000
4K-word Boot Block 0 4K-word Boot Block 1 4K-word Parameter Block 0 4K-word Parameter Block 1 4K-word Parameter Block 2 4K-word Parameter Block 3 4K-word Parameter Block 4 4K-word Parameter Block 5 32K-word Main Block 0 32K-word Main Block 1 32K-word Main Block 2 32K-word Main Block 3 32K-word Main Block 4 32K-word Main Block 5 32K-word Main Block 6
32K-word Main Block 6 32K-word Main Block 5 32K-word Main Block 4 32K-word Main Block 3 32K-word Main Block 2 32K-word Main Block 1 32K-word Main Block 0 4K-word Parameter Block 5 4K-word Parameter Block 4 4K-word Parameter Block 3 4K-word Parameter Block 2 4K-word Parameter Block 1 4K-word Parameter Block 0 4K-word Boot Block 1 4K-word Boot Block 0
Figure 3. Memory Map
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8. BUS OPERATION
The local CPU reads and writes flash memory in-system. All bus cycles to or from the flash memory conform to standard microprocessor bus cycles.
Read
Information can be read from any block, identifier codes or status register independent of the VPP voltage. #RESET can be at either VIH or VHH. The first task is to write the appropriate read mode command (Read Array, Read Identifier Codes or Read Status Register) to the CUI. Upon initial device power-up or after exit from deep power-down mode, the device automatically resets to read array mode. Six control pins dictate the data flow in and out of the component: #CE, #OE, #WE, #RESET, #WP and #BYTE. #CE and #OE must be driven active to obtain data at the outputs. #CE is the device selection control, and when active enables the selected memory device. #OE is the data output (DQ0 - DQ15) control and when active drives the selected memory data onto the I/O bus. #WE must be at VIH and #RESET must be at VIH or VHH. Figure 13, 14 illustrates read cycle.
Output Disable
With #OE at a logic-high level (VIH), the device outputs are disabled. Output pins (DQ0 - DQ15) are placed in a high-impedance state.
Standby
Setting #CE to a logic-high level (VIH) deselects the device and places it in standby mode, which substantially reduces device power consumption. DQ0 - DQ15 outputs are placed in a high impedance state independent of #OE. If deselected during block erase or word/byte write, the device continues functioning, and it continues to consume active power until the operation is completed.
Deep Power-down
Setting #RESET to VIL initiates the deep power-down mode. In read modes, setting #RESET at VIL deselects the memory, places output drivers in a highimpedance state and turns off all internal circuits. #RESET must be held low for a minimum of 100 nS. A delay (tPHQV) is required after return from reset until initial memory access outputs are valid. After this wake-up interval, normal operation is restored. The CUI is reset to read array mode status register is set to 80H. During block erase or word/byte write modes, #RESET at VIL will abort the operation. RY/#BY remains low until the reset operation is complete. Memory contents at the aborted location are no longer valid since the data may be partially erased or written. A delay (tPHWL) is required after #RESET goes to logic-high (VIH) before another command can be written. As with any automated device, it is important to assert #RESET during system reset. When the system comes out of reset, it expects to read from the flash memory. Automated flash memories provide status information when accessed during block erase or word/byte write modes. If a CPU reset occurs with no flash memory reset, proper CPU initialization may not occur because the flash memory may be providing status information instead of array data. Winbond's flash memories allow proper CPU initialization following a system reset through the use of the #RESET input. In this application, #RESET is controlled by the same #RESET signal that resets the system CPU.
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W28V400B/T
Read Identifier Codes Operation
The read identifier codes operation outputs the manufacturer code and device code (refer to Figure 4). Using the manufacturer and device codes, the system CPU can automatically match the device with its proper algorithms.
[A17-A0] 3FFFF
Reserved for Future Implementation
00002 00001 00000
Device Code Manufacture Code
Figure 4. Device Identifier Code Memory Map
Write
Writing commands to the CUI enable reading of device data and identifier codes. They also control inspection and clearing of the status register. When VDD = VDD1/2/3/4 and used. VPP = VPPH1/2/3, the CUI additionally controls block erasure and word/byte write. The Block Erase command requires appropriate command data and an address within the block to be erased. The Word/Byte Write command requires the command and address of the location to be written. The CUI does not occupy an addressable memory location. A write occurs when #WE and #CE are active (low). The address and data needed to execute a command are latched on the rising edge of #WE or #CE, whichever occurs first. Standard microprocessor write timings are used. Figures 15 and 16 illustrate #WE and #CE controlled write operations.
9. COMMAND DEFINITIONS
When VPP VPPLK, read operations from the status register, identifier codes, or blocks are enabled. Setting VPPH1/2/3 = VPP enables successful block erase and word/byte write operations. Device operations are selected by writing specific commands into the CUI. Table 4 defines these commands.
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Table 3.1. Bus Operations (#BYTE = VIH) (Note 1, 2)
MODE Read (Note 8) Output Disable Standby (Note 10) Deep Power-down (Note 4, 10) Read Identifier Codes (Note 8) Write (Note 6, 7, 8) #RESET VIH or VHH VIH or VHH VIH or VHH VIL VIH or VHH VIH or VHH #CE VIL VIL VIH X VIL VIL #OE VIL VIH X X VIL VIH #WE VIH VIH X X VIH VIL ADDRESS X X X X See Figure 4 X
VPP
X X X X X X
DQ0 - 15 RY/#BY(3) DOUT High Z High Z High Z Note 5 DIN X X X VOH VOH X
Table 3.2. Bus Operations (#BYTE = VIL) (Note 1, 2)
MODE Read (Note 8) Output Disable Standby (Note 10) Deep Power-down (Note 4, 10) Read Identifier Codes (Note 8, 9) Write (Note 6, 7, 8)
Notes: 1. Refer to DC Characteristics. When VPP VPPLK, memory contents can be read, but not altered. 2. X can be VIL or VIH for control pins and addresses, and VPPLK or VPPH1/2/3 for VPP. See DC Characteristics for VPPLK and VPPH1/2/3 voltages. 3. RY/#BY is VOL when the WSM is executing internal block erase or word/byte write algorithms. It is VOH during when the WSM is not busy, in block erase suspend mode (with word/byte write inactive), word/byte write suspend mode or deep power-down mode. 4. #RESET at VSS 0.2V ensures the lowest deep power-down current. 5. See Read Identifier Codes Command section for details. 6. Command writes involving block erase or word/byte write are reliably executed when VPP = VPPH1/2/3 and VDD = VDD1/2/3/4. Block erase or word/byte write with VIH < #RESET < VHH produce spurious results and should not be attempted. 7. Refer to Table 4 for valid DIN during a write operation. 8. Never hold #OE low and #WE low at the same timing. 9. A-1 set to VIL or VIH in byte mode (#BYTE = VIL). 10. #WP set to VIL or VIH.
#RESET VIH or VHH VIH or VHH VIH or VHH VIL VIH or VHH VIH or VHH
#CE VIL VIL VIH X VIL VIL
#OE VIL VIH X X VIL VIH
#WE ADDRESS VIH VIH X X VIH VIL X X X X See Figure 4 X
VPP
X X X X X X
DQ0 - 7 DQ8 - 15 RY/#BY(3) DOUT High Z High Z High Z Note 5 DIN High Z High Z High Z High Z High Z X X X X VOH VOH X
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W28V400B/T
Table 4. Command Definitions(10)
COMMAND Read Array/Reset Read Identifier Codes Read Status Register Clear Status Register Block Erase Word/Byte Write Block Erase and Word/Byte Write Suspend Block Erase and Word/Byte Write Resume
Notes: 1. BUS operations are defined in Table 3.1 and Table 3.2. 2. X = Any valid address within the device. IA = Identifier Code Address: see Figure 4. A-1 set to VIL or VIH in Byte Mode (#BYTE = VIL). BA = Address within the block being erased. The each block can select by the address pin A17 through A12 combination. WA = Address of memory location to be written. 3. SRD = Data read from status register. See Table 7 for a description of the status register bits. WD = Data to be written at location WA. Data is latched on the rising edge of #WE or #CE (whichever goes high first). ID = Data read from identifier codes. 4. Following the Read Identifier Codes command, read operations access manufacturer and device codes. See Read Identifier Codes Command section for details. 5. If the block is boot block, #WP must be at VIH or #RESET must be at VHH to enable block erase or word/byte write operations. Attempts to issue a block erase or word/byte write to a boot block while #WP is VIH or #RESET is VIH. 6. Either 40H or 10H are recognized by the WSM as the word/byte write setup. 7. Commands other than those shown above are reserved by Winbond for future device implementations and should not be used.
BUS CYCLES REQ'D. 1 2 (Note 4) 2 1 2 (Note 5) 2 (Note 5, 6) 1 (Note 5) 1 (Note 5)
FIRST BUS CYCLE Oper(1) Write Write Write Write Write Write Write Write Addr(2) X X X X BA WA X X Data(3) FFH 90H 70H 50H 20H 40H or 10H B0H D0H
SECOND BUS CYCLE Oper(1) Read Read Write Write Addr(2) IA X BA WA Data(3) ID SRD D0H WD
Read Array Command
Upon initial device power-up and after exit from deep power-down mode, the device defaults to read array mode. This operation is also initiated by writing the Read Array command. The device remains enabled for reads until another command is written. Once the internal WSM has started a block erase or word/byte write, the device will not recognize the Read Array command until the WSM completes its operation unless the WSM is suspended via an Erase Suspend or Word/Byte Write Suspend command. The Read Array command functions independently of the VPP voltage and #RESET can be VIH or VHH.
Read Identifier Codes Command
The identifier code operation is initiated by writing the Read Identifier Codes command. Following the command write, read cycles from addresses shown in Figure 4 retrieve the manufacturer and device codes (see Table 5 for identifier code values). To terminate the operation, write another valid command. Like the Read Array command, the Read Identifier Codes command functions independently of the VPP voltage and #RESET can be VIH or VHH. Following the Read Identifier Codes command, the following information can be read:
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Table 4. Identifier Codes
CODE Manufacture Code Device Code Top Boot Bottom Boot ADDRESS [A17 - A0] 00000H 00001H DATA [DQ7 - DQ0] B0H 58H 5AH
Read Status Register Command
The status register may be read to determine when a block erase or word/byte write is complete and whether the operation completed successfully. It may be read at any time by writing the Read Status Register command. After writing this command, all subsequent read operations output data from the status register until another valid command is written. The status register contents are latched on the falling edge of #OE or #CE, whichever occurs. #OE or #CE must toggle to VIH before further reads to update the status register latch. The Read Status Register command functions independently of the VPP voltage. #RESET can be VIH or VHH.
Clear Status Register Command
Status register bits SR.5, SR.4, SR.3 or SR.1 are set to "1"s by the WSM and can only be reset by the Clear Status Register command. These bits indicate various failure conditions (see Table 7). By allowing system software to reset these bits, several operations (such as cumulatively erasing multiple blocks or writing several words/bytes in sequence) may be performed. The status register may be polled to determine if an error occurred during the sequence. To clear the status register, the Clear Status Register command (50H) is written. It functions independently of the applied VPP voltage. #RESET can be VIH or VHH. This command is not functional during block erase or word/byte write suspend modes.
Block Erase Command
Erase is executed one block at a time and initiated by a two-cycle command. A block erase setup is first written, followed by an block erase confirm. This command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to FFFFH). Block preconditioning, erase, and verify are handled internally by the WSM (invisible to the system). After the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see Figure 5). The CPU can detect block erase completion by analyzing the output data of the RY/#BY pin or status register bit SR.7. When the block erase is complete, status register bit SR.5 should be checked. If a block erase error is detected, the status register should be cleared before system software attempts corrective actions. The CUI remains in read status register mode until a new command is issued. This two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. An invalid Block Erase command sequence will result in both status register bits SR.4 and SR.5 being set to "1". Also, reliable block erasure can only occur when VDD = VDD1/2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, block contents are protected against erasure. If block erase is attempted while VPP VPPLK, SR.3 and SR.5 will be set to "1". Successful block erase for boot blocks requires that the corresponding if set, that #WP = VIH or #RESET = VHH. If block erase is attempted to boot block when the corresponding #WP = VIL or #RESET = VIH, SR.1 and SR.5 will be set to "1". Block erase operations with VIH < #RESET < VHH produce spurious results and should not be attempted. - 14 -
W28V400B/T
Word/Byte Write Command
Word/byte write is executed by a two-cycle command sequence. Word/byte write setup (standard 40H or alternate 10H) is written, followed by a second write that specifies the address and data (latched on the rising edge of #WE). The WSM then takes over, controlling the word/byte write and write verify algorithms internally. After the word/byte write sequence is written, the device automatically outputs status register data when can be read (see Figure 6). The CPU can detect the completion of the word/byte write event by analyzing the RY/#BY pin or status register bit SR.7. When word/byte write is complete, status register bit SR.4 should be checked. If word/byte write error is detected, the status register should be cleared. The internal WSM verify only detects errors for "1"s that do not successfully write to "0"s. The CUI remains in read status register mode until it receives another command. Reliable word/byte writes can only occur when VDD = VDD1/2/3/4 and VPP = VPPH1/2/3. In the absence of this high voltage, memory contents are protected against word/byte writes. If word/byte write is attempted while VPP VPPLK, status register bits SR.3 and SR.4 will be set to "1". Successful word/byte write for boot blocks requires that the corresponding if set, that #WP = VIH or #RESET = VHH. If word/byte write is attempted to boot block when the corresponding #WP= VIL or #RESET= VIH, SR.1 and SR.4 will be set to "1". Word/byte write operations with VIH < #RESET < VHH produce spurious results and should not be attempted.
Block Erase Suspend Command
The Block Erase Suspend command allows block-erase interruption to read or word/byte write data in another block of memory. Once the block-erase process starts, writing the Block Erase Suspend command requests that the WSM suspend the block erase sequence at a predetermined point in the algorithm. The device outputs status register data when read after the Block Erase Suspend command is written. Polling status register bits SR.7 and SR.6 can determine when the block erase operation has been suspended (both will be set to "1"). RY/#BY will also transition to VOH. Specification tWHRH2 defines the block erase suspend latency. At this point, a Read Array command can be written to read data from blocks other than that which is suspended. A Word/Byte Write command sequence can also be issued during erase suspend to program data in other blocks. Using the Word/Byte Write Suspend command (see Word/Byte Write Suspend Command section), a word/byte write operation can also be suspended. During a word/byte write operation with block erase suspended, status register bit SR.7 will return to "0" and the RY/#BY output will transition to VOL. However, SR.6 will remain "1" to indicate block erase suspend status. The only other valid commands while block erase is suspended are Read Status Register and Block Erase Resume. After a Block Erase Resume command is written to the flash memory, the WSM will continue the block erase process. Status register bits SR.6 and SR.7 will automatically clear and RY/#BY will return to VOL. After the Erase Resume command is written, the device automatically outputs status register data when read (see Figure 7). VPP must remain at VPPH1/2/3 (the same VPP level used for block erase) while block erase is suspended. #RESET must also remain at VIH or VHH (the same #RESET level used for block erase). #WP must also remain at VIL or VIH (the same #WP level used for block erase). Block erase cannot resume until word/byte write operations initiated during block erase suspend have completed.
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W28V400B/T
Word/Byte Write Suspend Command
The Word/Byte Write Suspend command allows word/byte write interruption to read data in other flash memory locations. Once the word/byte write process starts, sending the Word/Byte Write Suspend command causes the WSM to suspend the word/byte write sequence at a predetermined point in the algorithm. The device continues to output status register data when read after the Word/Byte Write Suspend command is written. Polling status register bits SR.7 and SR.2 can determine when the word/byte write operation has been suspended (both will be set to "1"). RY/#BY will also transition to VOH. Specification tWHRH1 defines the word/byte write suspend latency. At this point, a Read Array command can be written to read data from locations other than that which is suspended. The only other valid commands while word/byte write is suspended are Read Status Register and Word/Byte Write Resume. After Word/Byte Write Resume command is written to the flash memory, the WSM will continue the word/byte write process. Status register bits SR.2 and SR.7 will automatically clear and RY/#BY will return to VOL. After the Word/Byte Write Resume command is written, the device automatically outputs status register data when read (see Figure 8). VPP must remain at VPPH1/2/3 (the same VPP level used for word/byte write) while in word/byte write suspend mode. #RESET must also remain at VIH or VHH (the same #RESET level used for word/byte write). #WP must also remain at VIL or VIH (the same #WP level used for word/byte write).
Considerations of Suspend
After the suspend command write to the CUI, read status register command has to write to CUI, then status register bit SR.6 or SR.2 should be checked for places the device in suspend mode.
Block Locking
This Boot Block Flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary.
VPP = VIL for Complete Protection
The VPP programming voltage can be held low for complete write protection of all blocks in the flash device.
#WP = VIL for Block Locking
The lockable blocks are locked when #WP = VIL; any program or erase operation to a locked block will result in an error, which will be reflected in the status register. For top configuration, the top two boot blocks are lockable. For the bottom configuration, the bottom two boot blocks are lockable. Unlocked blocks can be programmed or erased normally (Unless VPP is below VPPLK).
#WP = VIH for Block Unlocking
#WP = VIH unlocks all lockable blocks. These blocks can now be programmed or erased. #WP controls 2 boot blocks locking and VPP provides protection against spurious writes. Table 6 defines the write protection methods.
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W28V400B/T
Table 6. Write Protection Alternatives
OPERATION VPP #RESET X #WP X X X All Blocks Locked. All Blocks Locked. All Blocks Unlocked. 2 Boot Blocks Locked. All Blocks Unlocked. EFFECT
VIL
Block Erase or Word/Byte Write > VPPLK
VIL VHH VHH
VIL VIH
Table 7. Status Register Definition
WSMS 7 ESS 6 ES 5 WBWS 4 VPPS 3 WBWSS 2 DPS 1 R 0
Notes: SR.7 = WRITE STATE MACHINE STATUS (WSMS) 1 = Ready 0 = Busy SR.6 = ERASE SUSPEND STATUS (ESS) 1 = Block Erase Suspended 0 = Block Erase in Progress/Completed SR.5 = ERASE STATUS (ES) 1 = Error in Block Erase 0 = Successful Block Erase SR.4 = WORD/BYTE WRITE STATUS (WBWSLBS) 1 = Error in Word/Byte Write 0 = Successful Word/Byte Write SR.3 = VPP STATUS (VPPS) 1 = VPP Low Detect, Operation Abort 0 = VPP OK SR.2 = WORD/BYTE WRITE SUSPEND STATUS (WBWSS) 1 = Word/Byte Write Suspended 0 = Word/Byte Write in Progress/Completed SR.1 = DEVICE PROTECT STATUS (DPS) 1 = WP# or RP# Lock Detected, Operation Abort 0 = Unlock SR.0 = RESERVED FOR FUTURE ENHANCEMENTS (R) SR.3 does not provide a continuous indication of VPP level. The WSM interrogates and indicates the VPP level only after Block Erase or Word/Byte Write command sequences. SR.3 is not guaranteed to reports accurate feedback only when VPP VPPH1/2/3. The WSM interrogates the #WP and #RESET only after Block Erase or Word/Byte Write command sequences. It informs the system, depending on the attempted operation, if the #WP is not VIH, #RESET is not VHH. SR.0 is reserved for future use and should be masked out when polling the status register. If both SR.5 and SR.4 are "1"s after a block erase attempt, an improper command sequence was entered. Check RY/#BY or SR.7 to determine block erase or word/byte write completion. SR.6-0 are invalid while SR.7 = "0".
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W28V400B/T
Bus Operation
Start
Command Erase Setup
Write
Write 20H Block Address
Write
Write D0H, Block Address Read Status Register No SR.7= 1 Full Status Check if Desired Block Erase Complete 0 Suspend Block Erase
Erase Confirm
Read Standby
Comments Data = 20H Addr = Within Block to be Erased Data = D0H Addr = Within Block to be Erased Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Suspend Block Erase Loop Yes
Repeat for subsequent block erasures. Full status check can be done after each block erase or after a sequence of block erasures. Write FFH after the last operation to place device in read array mode.
Full STATUS CHECK PROCEDURE
Read Status Register Data(See Above) 1
Bus Operation Command Standby
Vpp Range Error
SR.3= 0 SR.1= 0 SR.4,5= 0 SR.5= 0 Block Erase Sucessfully
Standby
Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect Check SR.4, 5 Both 1 = Command Sequence Error Check SR.5 1 = Block Erase Error
1
Device Protect Error
Standby
1
Command Sequence Error
Standby
1
Block Erase Error
SR.5, SR.4, SR.3 and SR.1 are only cleared by the Clear Status. Register Command in cases where multiple blocks are erased before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery.
Figure 5. Automated Block Erase Flowchart
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W28V400B/T
Start
Bus Operation Write
Write 40H or 10H, Address Write Word/Byte Data and Adddress Read Status Register No SR.7= 1 Full Status Check if Desired Word/Byte Write Complete 0
Suspend Word/Byte Write
Write Read
Suspend Word/Byte Write Loop Yes
Command Comments Setup Data = 40H or 10H Word/Byte Addr = Location to Be Write Written Data = Data to Be Word/Byte Written Write Addr = Location to Be Written Status Register Data Check SR.7 1 = WSM Ready 0 = WSM Busy
Standby
Repeat for subsequent byte writes. SR full status check can be done after each Word/Byte write, or after a sequence of Word/Byte writes. Write FFH after the last Word/Byte write operation to place device in read array mode.
Full STATUS CHECK PROCEDURE
Read Status Register Data(See Above) 1
Bus Operation Standby
Vpp Range Error
Command
Comments Check SR.3 1 = VPP Error Detect Check SR.1 1 = Device Protect Detect Check SR.4 1 = Data Write Error
SR.3= 0 SR.1= 0 SR.4= 0 Word/Byte Write Successfully
Standby Standby
1
Device Protect Error
1
SR.4, SR.3 and SR.1 are only cleared by the Clear Status Register command in cases where multiple locations are written before full status is checked. If error is detected, clear the Status Register before attempting retry or other error recovery.
Word/Byte Write Error
Figure 6. Automated Word/Byte Write Flowchart
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W28V400B/T
Start
Bus Operation Write
Command Erase Suspend
Write B0H
Read
Read Status Register
Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.6 1 = Block Erase Suspended 0 = Block Erase Completed Data = D0H Addr = X
Standby
SR.7= 1 SR.6= 1 Read Read Array Data
Read or Word/Byte Write?
0
0
Block Erase Complete
Standby
Word/Byte write Wore/Byte Write Loop
Write
Erase Resume
No Done? Yes Write D0H
Write FFH
Block Erase Resumed
Read Array Data
Figure 7. Block Erase Suspend/Resume Flowchart
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W28V400B/T
Start
Bus Operation Write Read
Write B0H
Command Word/Byte Write Suspend
Comments Data = B0H Addr = X Status Register Data Addr = X Check SR.7 1 = WSM Ready 0 = WSM Busy Check SR.2 1 = Word/Byte Write Suspended 0 = Word/Byte Write Completed Data = FFH Addr = X Read Array locations other than that being written. Data = D0H Addr = X
Read Status Register
Standby
SR.7= 1 SR.2= 1 Write FFH 0 Word/Byte Write Completed 0
Standby
Write Read
Read Array
Read Array Data
Write
Done Reading Yes Write D0H Write FFH No
Word/Byte Write Resume
Word/Byte Write Resumed
Read Array Data
Figure 8. Word/Byte Write Suspend/Resume Flowchart
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W28V400B/T
10. DESIGN CONSIDERATIONS
Three-line Output Control
This device will often be used in large memory arrays. Winbond provides three control inputs to accommodate multiple memory connections. Three-line control provides for: a. Lowest possible memory power dissipation. b. Complete assurance that data bus contention will not occur. To use these control inputs efficiently, an address decoder should enable #CE while #OE should be connected to all memory devices and the system's #READ control line. This assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. #RESET should be connected to the system POWERGOOD signal to prevent unintended writes during system power transitions. POWERGOOD should also toggle during system reset.
RY/#BY, Block Erase and Word/Byte Write Polling
RY/#BY is a full CMOS output that provides a hardware method of detecting block erase and word/byte write completion. It transitions low after block erase or word/byte write commands and returns to VOH when the WSM has finished executing the internal algorithm. RY/#BY can be connected to an interrupt input of the system CPU or controller. It is active at all times. RY/#BY is also VOH when the device is in block erase suspend (with word/byte write inactive), word/byte write suspend or deep power-down modes.
Power Supply Decoupling
Flash memory power switching characteristics require careful device decoupling. System designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of #CE and #OE. Transient current magnitudes depend on the device outputs' capacitive and inductive loading. Two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. Each device should have a 0.1 F ceramic capacitor connected between VDD and VSS and between VPP and VSS. These high frequency, low inductance capacitors should be placed as close as possible to package leads. Additionally, for every eight devices, a 4.7 F electrolytic capacitor should be placed at the array's power supply connection between VDD and VSS. The bulk capacitor will overcome voltage drops caused by PC board trace inductance.
VPP Trace on Printed Circuit Boards
Updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the VPP power supply trace. The VPP pin supplies the memory cell current for word/byte writing and block erasing. Use similar trace widths and layout considerations given to the VDD power bus. Adequate VPP supply traces and decoupling will decrease VPP voltage spikes and overshoots.
VDD, VPP, #RESET Transitions
Block erase and word/byte write are not guaranteed if VPP falls outside of a valid VPPH1/2/3 range, VDD falls outside of a valid VDD1/2/3/4 range, or #RESET VIH or VHH. If VPP error is detected, status register bit SR.3 is set to "1" along with SR.4 or SR.5, depending on the attempted operation. If #RESET - 22 -
W28V400B/T
transitions to VIL during block erase or word/byte write, RY/#BY will remain low until the reset operation is complete. Then, the operation will abort and the device will enter deep power-down. The aborted operation may leave data partially altered. Therefore, the command sequence must be repeated after normal operation is restored. Device power-off or #RESET transitions to VIL clear the status register. The CUI latches commands issued by system software and is not altered by VPP or #CE transitions or WSM actions. Its state is read array mode upon power-up, after exit from deep power-down or after VDD transitions below VLKO. After block erase or word/byte write, even after VPP transitions down to VPPLK, the CUI must be placed in read array mode via the Read Array command if subsequent access to the memory array is desired.
Power-up/Down Protection
The device is designed to offer protection against accidental block erasure or word/byte writing during power transitions. Upon power-up, the device is indifferent as to which power supply (VPP or VDD) powers-up first. Internal circuitry resets the CUI to read array mode at power-up. A system designer must guard against spurious writes for VDD voltages above VLKO when VPP is active. Since both #WE and #CE must be low for a command write, driving either to VIH will inhibit writes. The CUI's two-step command sequence architecture provides added level of protection against data alteration. #WP provide additional protection from inadvertent code or data alteration. The device is disabled while #RESET = VIL regardless of its control inputs state.
Power Dissipation
When designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. Flash memory's nonvolatility increases usable battery life because data is retained when system power is removed. In addition, deep power-down mode ensures extremely low power consumption even when system power is applied. For example, portable computing products and other power sensitive applications that use an array of devices for solid-state storage can consume negligible power by lowering #RESET to VIL standby or sleep modes. If access is again needed, the devices can be read following the tPHQV and tPHWL wake-up cycles required after #RESET is first raised to VIH. See AC Characteristics - Read Only and Write Operations and Figures 13, 14, 15 and 16 for more information.
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11. ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings*
Operating Temperature During Read, Block Erase, and Word/Byte Write ................................................ .......... 0 C to +70 C (1) Temperature under Bias .................................................................. ............................... -10 C to +80 C Storage Temperature ........................................................................................................ -65 C to +125 C Voltage On Any Pin (except VDD, VPP and #RESET) ........................................................................ ........... -0.5V to +7.0V (2)
VDD Supply Voltage................................ ............................................................................ -0.2V to +7.0V (2) VPP Update Voltage during Block
Erase and Word/Byte Write ........................................................... ......................... -0.2V to +14.0V (2, 3)
#RESET Voltage .......................................................................................................... -0.5V to +14.0V (2, 3) Output Short Circuit Current .......................................................................... ................................100 mA (4) *WARNING: Stressing the device beyond the "Absolute Maximum Ratings" may cause permanent damage. These are stress ratings only. Operation beyond the "Operating Conditions" is not recommended and extended exposure beyond the "Operating Conditions" may affect device reliability.
Notes: 1. Operating temperature is for commercial temperature product defined by this specification. 2. All specified voltages are with respect to VSS. Minimum DC voltage is -0.5V on input/output pins and -0.2V on VDD and VPP pins. During transitions, this level may undershoot to -2.0V for periods <20 nS. Maximum DC voltage on input/output pins and VDD is VDD +0.5V which, during transitions, may overshoot to VDD +2.0V for periods <20 nS. 3. Maximum DC voltage on VPP and #RESET may overshoot to +14.0V for periods <20 nS. 4. Output shorted for no more than one second. No more than one output shorted at a time.
Operating Conditions
Temperature and VDD Operating Conditions
PARAMETER Operating Temperature SYMBOL TA MIN. 0 2.7 3.0 4.75 4.50 MAX. +70 3.6 3.6 5.25 5.50 UNIT C V V V V TEST CONDITION Ambient Temperature
VDD Supply Voltage (2.7V to 3.6V) VDD Supply Voltage (3.3V 0.3V) VDD Supply Voltage (5.0V 0.25V) VDD Supply Voltage (5.0V 0.5V)
VDD1 VDD2 VDD3 VDD4
Capacitance(1)
TA = +25 C, f = 1 MHz
PARAMETER Input Capacitance Output Capacitance
Note: Sampled, not 100% tested.
SYMBOL CIN COUT
TYP. 7 9
MAX. 10 12
UNIT pF pF
CONDITION VIN = 0.0V VOUT = 0.0V
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W28V400B/T
AC Input/Output Test Conditions
2.7 INPUT 0.0 1.35 TEST POINTS 1.35 OUTPUT
AC test inputs are driven at 2.7V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.35V. Input rise and fall times (10% to 90%) <10 nS.
Figure 9. Transient Input/Output Reference Waveform for VDD = 2.7V to 3.6V
3.0 INPUT 0.0 1.5 TEST POINTS 1.5 OUTPUT
AC test inputs are driven at 3.0V for a Logic "1" and 0.0V for a Logic "0". Input timing begins, and output timing ends, at 1.5V. Input rise and fall times (10% to 90%) <10 nS. Figure 10. Transient Input/Output Reference Waveform for VDD = 3.3V 0.3V and VDD = 5V 0.25V (High Speed Testing Configuration)
2.4 INPUT 0.45
2.0 TEST POINTS 0.8
2.0 OUTPUT 0.8
AC test inputs are driven at VOH (2.4 VTTL) for a Logic "1" and VOL (0.45 VTTL) for a Logic "0." Input timing begins at VIH (2.0 VTTL) and VIL (0.8 VTTL). Output timing ends at VIH and VIL. Input rise and fall times (10% to 90%) <10 nS.
Figure 11. Transient Input/Output Reference Waveform for VDD = 5V 0.5V (Standard Testing Configuration)
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W28V400B/T
1.3V
(IN914)
R L =3.3K ohm
DEVICE UNDER TEST
C L Includes Jig Capacitance CL
OUT
Figure 12. Transient Equivalent Testing Load Circuit
Test Configuration Capacitance Loading Value
TEST CONFIGURATION CL(PF)
VDD = 3.3V 0.3V, 2.7V to 3.6V VDD = 5V 0.25V VDD = 5V 0.5V
30 30 100
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W28V400B/T
DC Characteristics
PARAMETER SYM. TEST CONDITIONS VDD = 2.7V- 3.6V VDD = 5V 0.5 Typ. Max. 0.5 0.5 Typ. Max. 1 10 UNIT A A A
Input Load Current (Note1) Output Leakage Current (Note1)
ILI ILO
VDD = VDD Max. VIN = VDD or VSS VDD = VDD Max. VOUT = VDD or VSS CMOS Level Inputs VDD = VDD Max. #CE = #RESET = VDD 0.2V 25 0.2 4
50 2 10
30 0.4
100 2 10
VDD Standby Current (Note 1, 3, 6, 10)
ICCS
TTL Level Inputs VDD = VDD Max. #CE = #RESET = VIH #RESET = VSS 0.2V IOUT(RY/#BY) = 0 mA CMOS Inputs VDD = VDD Max., #CE = VSS, f = 5 MHz (3.3V 0.3), f = 5 MHz (2.7V - 3.6V) f = 8 MHz (5V+ 0.5V) IOUT = 0 mA TTL Inputs VDD = VDD Max., #CE = VSS, f = 5 MHz (3.3V 0.3), f = 5 MHz (2.7V - 3.6V) f = 8 MHz (5V 0.5V), IOUT = 0 mA
mA
A
VDD Reset Power-down Current (Note 1, 10)
ICCD
15
25
50
mA
VDD Read Current (Note 1, 5, 6)
ICCR
30
65
mA
VDD Word/Byte Write Current (Note 1, 7)
ICCW
VPP = 2.7V - 3.6V VPP = 4.5V - 5.5V VPP = 11.4V - 12.6V VPP = 2.7V - 3.6V
5 5 5 4 4 4 1
2
17 17 12 17 17 12 6
15
-
35 30
mA mA mA mA mA mA mA
A A A
-
30 25
VDD Block Erase Current (Note 1, 7) VDD Word/Byte Write or Block Erase Suspend Current (Note1, 2) VPP Standby or Read Current (Note1) VPP Deep Power-Down Current (Note1) VPP Word/Byte Write Current (Note 1, 7)
ICCE
VPP = 4.5V - 5.5V VPP = 11.4V - 12.6V
ICCWS ICCES IPPS ICPPR IPPD
#CE = VIH VPP VDD VPP > VDD #RESET = VSS 0.2V VPP = 2.7V - 3.6V
1
2
10
15
10 0.1 12
200 5 40 40 30
10 0.1 -
200 5 40 30
mA mA mA mA mA mA
A
IPPW
VPP = 4.5V - 5.5V VPP = 11.4V - 12.6V VPP = 2.7V - 3.6V 8
25 25 20
-
25 20
VPP Block Erase Current (Note 1, 7)
IPPE
VPP = 4.5V - 5.5V VPP = 11.4V - 12.6V
VPP Word/Byte Write or Block Erase Suspend Current (Note 1)
IPPWS IPPES
VPP = VPPH1/2/3
10
200
10
200
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W28V400B/T
DC Characteristics (Continued) PARAMETER Input Low Voltage (Note 7) Input High Voltage (Note 7)
SYM. TEST CONDITIONS VDD = 2.7V - 3.6V Min. Max. VDD = 5V 0.5V Min. Max. UNIT
VIL VIH VDD = VDD Min. IOL = 5.8 mA (5V 0.5V) IOL = 2.0 mA (3.3V 0.3V) IOL = 2.0 mA (2.7V - 3.6V) VDD = VDD Min.
-0.5 2.0
0.8 VDD +0.5
-0.5 2.0
0.8 VDD +0.5
V V
Output Low Voltage (Note 3, 7)
VOL
0.4
0.45
V
Output High Voltage (TTL) (Note 3, 7)
VOH1
IOH = -2.5 mA (5V 0.5V) IOH = -2.0 mA (3.3V 0.3V) IOH = -1.5 mA (2.7V - 3.6V)
2.4
2.4
V
Output High Voltage (CMOS) (Note 3, 7)
VOH2
VDD = VDD Min. IOH = -2.0 mA VDD = VDD Min. IOH = -100 A
0.85 VDD VDD -0.4 1.5 2.7 4.5 11.4 2.0 3.6 5.5 12.6
0.85 VDD VDD -0.4 1.5 4.5 11.4 2.0 12.6 11.4 12.6 5.5 12.6
V V V V V V V V
VPP Lockout during Normal Operations VPPLK (Note 4, 7) VPP during Block Erase or Word/Byte Write Operations VPP during Block Erase or Word/Byte Write Operations VPP during Block Erase or Word/Byte Write Operations VDD Lockout Voltage #RESET Unlock Voltage (Note 8, 9)
Notes:
VPPH1 VPPH2 VPPH3 VLKO VHH Unavailable #WP
11.4
1. All currents are in RMS unless otherwise noted. Typical values at nominal VDD voltage and TA = +25 C. 2. ICCWS and ICCES are specified with the device de-selected. If read or word/byte written while in erase suspend mode, the device's current draw is the sum of ICCWS or ICCES and ICCR or ICCW , respectively. 3. Includes RY/#BY. 4. Block erases and word/byte writes are inhibited when VPP VPPLK, and not guaranteed in the range between VPPLK (max.) and VPPH1 (min.), between VPPH1 (max.) and VPPH2 (min.), between VPPH2 (max.) and VPPH3 (min.), and above VPPH3 (max.). 5. Automatic Power Savings (APS) reduces typical ICCR to 1mA at 5V VDD and 3 mA at 2.7V and 3.3V VDD in static operation. 6. CMOS inputs are either VDD 0.2V or VSS 0.2V. TTL inputs are either VIL or VIH. 7. Sampled, not 100% tested. 8. Boot block erases and word/byte writes are inhibited when the corresponding #RESET = VIH and #WP = VIL. Block erase and word/byte write operations are not guaranteed with VIH < #RESET < VHH and should not be attempted. 9. #RESET connection to a VHH supply is allowed for a maximum cumulative period of 80 hours. 10. #BYTE input level is VDD 0.2V in word mode or VSS 0.2V in byte mode. #WP input level is VDD 0.2V or VSS 0.2V.
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W28V400B/T
AC Characteristics - Read-only Operations(1)
VDD = 2.7V to 3.6V, TA = 0 C to +70 C
PARAMETER Read Cycle Time Address to Output Delay #CE to Output Delay (Note 2) #RESET High to Output Delay #OE to Output Delay (Note 2) #CE to Output in Low Z (Note 3) #CE High to Output in High Z (Note 3) #OE to Output in Low Z (Note 3) #OE High to Output in High Z (Note 3) Output Hold from Address -, #CE or #OE Change, Whichever Occurs First (Note 3) #BYTE to Output Delay (Note 3) #BYTE Low to Output in High Z (Note 3) #CE to #BYTE High or Low (Note 3, 6)
Notes: See 5.0V VDD Read-only Operations for notes 1 through 6.
SYM. tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH tFVQV tFLQZ tELFV
MIN. 120
MAX. 120 120 600 50
UNIT nS nS nS nS nS nS nS nS nS nS
0 55 0 20 0 120 30 5
nS nS nS
VDD = 3.3V 0.3V, TA = 0 C to +70 C
PARAMETER Read Cycle Time Address to Output Delay #CE to Output Delay (Note 2) #RESET High to Output Delay #OE to Output Delay (Note 2) #CE to Output in Low Z (Note 3) #CE High to Output in High Z (Note 3) #OE to Output in Low Z (Note 3) #OE High to Output in High Z (Note 3) Output Hold from Address, #CE or #OE Change, Whichever Occurs First (Note 3) #BYTE to Output Delay (Note 3) #BYTE Low to Output in High Z (Note 3) #CE to #BYTE High or Low (Note 3, 6)
Note: See 5.0V VDD Read-only Operations for notes 1 through 6.
SYM. tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH tFVQV tFLQZ tELFV
MIN. 100
MAX. 100 100 600 50
UNIT nS nS nS nS nS nS nS nS nS nS
0 55 0 20 0 100 30 5
nS nS nS
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Publication Release Date: April 11, 2003 Revision A4
W28V400B/T
VDD = 5V 0.5V, 5V 0.25V, TA = 0 C to +70 C
PARAMETER Read Cycle Time Address to Output Delay #CE to Output Delay (Note 2) #RESET High to Output Delay #OE to Output Delay (Note 2) #CE to Output in Low Z (Note 3) #CE High to Output in High Z (Note 3) #OE to Output in Low Z (Note 3) #OE High to Output in High Z (Note 3) Output Hold from Address, #CE or #OE Change, Whichever Occurs First (Note 3) #BYTE to Output Delay (note3) #BYTE Low to Output in High Z (Note 3) #CE to #BYTE High or Low (Note 3, 6)
Notes:
SYM. tAVAV tAVQV tELQV tPHQV tGLQV tELQX tEHQZ tGLQX tGHQZ tOH tFVQV tFLQZ tELFV
VDD = 5V 0.25V(4) MIN. 85 85 85 400 40 0 55 0 10 0 85 25 5 MAX.
5V 0.5V(5) MIN. 90 90 90 400 45 0 55 0 10 MAX.
UNIT nS nS nS nS nS nS nS nS nS nS
90 30 5
nS nS nS
1. See AC Input/Output Reference Waveform for maximum allowable input slew rate. 2. #OE may be delayed up to tELQV to tGLQV after the falling edge of #CE without impact on tELQV. 3. Sampled, not 100% tested. 4. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Speed Configuration) for testing characteristics. 5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics. 6. If #BYTE transfer during reading cycle, exist the regulations separately.
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W28V400B/T
Address(A) #CE(E)
VIH VIL VIH VIL VIH VIL VIH VIL
Standby
Device Address Selection Address Stable
Data Valid
t AVAV t EHQZ
#OE(G)
tGHQZ
#WE(W)
t GLQV t ELQV tELQX tGLQX
tOH
DATA(D/Q) V OH (DQ0-DQ15) VOL V DD V IH V IL
HIGH Z
t AVQV
Valid Output
HIGH Z
t PHQV
#RESET(P)
Figure 13. AC Waveform for Read Operations
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Publication Release Date: April 11, 2003 Revision A4
W28V400B/T
Address(A) #CE(E)
VIH VIL VIH VIL
Standby
Device Address Selection Address Stable
Data Valid
t AVAV t EHQZ
VIH #OE(G) V IL #BYTE(F) VIH VIL HIGH Z
tGHQZ t ELFV t GLQV t FVQV
DATA(D/Q) VOH (DQ0-DQ7) V OL DATA(D/Q) V OH (DQ0-DQ7) V OL
t ELQV tGLQX tELQX tAVQV
tOH
HIGH Z Data Output
t FLQZ
Valid Output
HIGH Z
Data Output
HIGH Z
Figure 14. #BYTE Timing Waveform
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W28V400B/T
AC Characteristics - Write Operations(1)
VDD = 2.7V to 3.6V, TA = 0 C to +70 C
PARAMETER Write Cycle Time #RESET High Recovery to #WE Going Low (Note 2) #CE Setup to #WE Going Low #WE Pulse Width #RESET VHH Setup to #WE Going High (Note 2) #WP VIH Setup to #WE Going High (Note 2) VPP Setup to #WE Going High (Note 2) Address Setup to #WE Going High (Note 3) Data Setup to #WE Going High (Note 3) Data Hold from #WE High Address Hold from #WE High #CE Hold from #WE High #WE Pulse Width High #WE High to RY/#BY Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/#BY High (Note 2, 4) #RESET VHH Hold from Valid (Note 2, 4) #WP VIH Hold from Valid SRD, RY/#BY High (Note 2, 4) #BYTE Setup to #WE Going High (Note 7) #BYTE Hold from #WE High (Note 7)
Note: See 5.0V VDD AC Characteristics - Write Operations for notes 1 through 7.
SYM. tAVAV tPHWL tELWL tWLWH TPHHWH tSHWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL TQVPH tQVSL tFVWH tWHFV
MIN. 120 1 10 50 100 100 100 50 50 0 5 10 30
MAX.
UNIT nS S nS nS nS nS nS nS nS nS nS nS nS
100 0 0 0 0 50 120
nS nS nS nS nS nS nS
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Publication Release Date: April 11, 2003 Revision A4
W28V400B/T
VDD = 3.3V 0.3V, TA = 0 C to +70 C
PARAMETER Write Cycle Time #RESET High Recovery to #WE Going Low (Note 2) #CE Setup to #WE Going Low #WE Pulse Width #RESET VHH Setup to #WE Going High (Note 2) #WP VIH Setup to #WE Going High (Note 2) VPP Setup to #WE Going High (Note 2) Address Setup to #WE Going High (Note 3) Data Setup to #WE Going High (Note 3) Data Hold from #WE High Address Hold from #WE High #CE Hold from #WE High #WE Pulse Width High #WE High to RY/#BY Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/#BY High (Note 2, 4) #RESET VHH Hold from Valid (Note 2, 4) #WP VIH Hold from Valid SRD, RY/#BY High (Note 2, 4) #BYTE Setup to #WE Going High (Note 7) #BYTE Hold from #WE High (Note 7)
SYM. tAVAV tPHWL tELWL tWLWH TPHHWH tSHWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL TQVPH tQVSL tFVWH tWHFV
MIN. 100 1 10 50 100 100 100 50 50 0 5 10 30
MAX.
UNIT nS S nS nS nS nS nS nS nS nS nS nS nS
100 0 0 0 0 50 100
nS nS nS nS nS nS nS
Note: See 5.0V VDD AC Characteristics - Write Operations for notes 1 through 7.
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W28V400B/T
VDD = 5V 0.5V, 5V 0.25V, TA = 0 C to +70 C
PARAMETER Write Cycle Time #RESET High Recovery to #WE Going Low (Note 2) #CE Setup to #WE Going Low #WE Pulse Width #RESET VHH Setup to #WE Going High (Note 2) #WP VIH Setup to #WE Going High (Note 2) VPP Setup to #WE Going High (Note 2) Address Setup to #WE Going High (Note 3) Data Setup to #WE Going High (Note 3) Data Hold from #WE High Address Hold from #WE High #CE Hold from #WE High #WE Pulse Width High #WE High to RY/#BY Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/#BY High (Note 2, 4) #RESET VHH Hold from Valid SRD, RY/BY# High (Note 2, 4) #WP VIH Hold from Valid SRD, RY/#BY High (Note 2, 4) #BYTE Setup to #WE Going High (Note 7) #BYTE Hold from #WE High (Note 7)
Notes:
SYM. tAVAV tPHWL tELWL tWLWH TPHHWH tSHWH tVPWH tAVWH tDVWH tWHDX tWHAX tWHEH tWHWL tWHRL tWHGL tQVVL TQVPH tQVSL tFVWH tWHFV
5V 0.25V(5) MIN. 85 1 10 40 100 100 100 40 40 0 5 10 30 90 0 0 0 0 40 85 MAX.
5V 0.5V(6) MIN 90 1 10 40 100 100 100 40 40 0 5 10 30 90 0 0 0 0 40 90 MAX.
UNIT nS S nS nS nS nS nS nS nS nS nS nS nS nS nS nS
nS nS nS
1. Read timing characteristics during block erase and word/byte write operations are the same as during read-only operations. Refer to AC Characteristics for read-only operations. 2. Sampled, not 100% tested. 3. Refer to Table 4 for valid AIN and DIN for block erase or word/byte write. 4. VPP should be held at VPPH1/2/3 (and if necessary #RESET should be held at VHH) until determination of block erase or word/byte write success (SR.1/3/4/5 = 0). 5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration) for testing characteristics. 6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics. 7. If #BYTE switch during reading cycle, exist the regulations separately.
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Publication Release Date: April 11, 2003 Revision A4
W28V400B/T
1 Address(A) #CE(E) VIH V IL VIH V IL V IH VIL V IH V IL VIH VIL V IH V IL VOH RY/#BY(R) VOL VIH V IL V HH #RESET(P) VIH V IL VPPH3,2,1 VPP (V) V PPLK V IL HIGH Z
t PHWL t ELWL
2
A IN t AVAV
3
A IN t AVWH
4
5
6
t WHAX
t WHEH
t WHGL
#OE(G)
t WHWL
t WHQV1,2
#WE(W)
t WLWH t DVWH t WHDX D IN t FVWH D IN t WHFV
DATA(D/Q)
Valid
SRD
D IN
#BYTE(F)
t WHRL t
t SHWH
t QVSL
#WP(S)
t PHHWH
t QVPH
t VPWH
t QVVL
Figure 15. AC Waveform for #WE-Controlled Write Operations
Notes:
1. VDD power-up and standby. 2. Write block erase or word/byte write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command.
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W28V400B/T
Alternative #CE-Controlled Writes(1)
VDD = 2.7V to 3.6V, TA = 0 C to +70 C
PARAMETER Write Cycle Time #RESET High Recovery to #CE Going Low (Note 2) #WE Setup to #CE Going Low #CE Pulse Width #RESET VHH Setup to #CE Going High (Note 2) #WP VIH Setup to #CE Going High (Note 2) VPP Setup to #CE Going High (Note 2) Address Setup to #CE Going High (Note 3) Data Setup to #CE Going High (Note 3) Data Hold from #CE High Address Hold from #CE High #WE Hold from #CE High #CE Pulse Width High #CE High to RY/#BY Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/#BY High (Note 2, 4) #RESET VHH Hold from Valid SRD, RY/#BY High (Note 2, 4) #WP VIH Hold from Valid SRD, RY/#BY High (Note 2, 4) #BYTE Setup to #CE Going High (Note 7) #BYTE Hold from #CE High (Note 7)
Note: See 5.0V VDD Alternative #CE-Controlled Writes for notes 1 through 7.
SYM. tAVAV tPHEL tWLEL tELEH tPHHEH tSHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHGL tQVVL TQVPH tQVSL tFVEH tEHFV
MIN. 120 1 0 70 100 100 100 50 50 0 5 0 25
MAX.
UNIT nS S nS nS nS nS nS nS nS nS nS nS nS
100 0 0 0 0 50 120
nS nS nS nS nS nS nS
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Publication Release Date: April 11, 2003 Revision A4
W28V400B/T
VDD = 3.3V 0.3V, TA = 0 C to +70 C
PARAMETER Write Cycle Time #RESET High Recovery to #CE Going Low (Note 2) #WE Setup to #CE Going Low #CE Pulse Width #RESET VHH Setup to #CE Going High (Note 2) #WP VIH Setup to #CE Going High (Note 2) VPP Setup to #CE Going High (Note2) Address Setup to #CE Going High (Note 3) Data Setup to #CE Going High (Note 3) Data Hold from #CE High Address Hold from #CE High #WE Hold from #CE High #CE Pulse Width High #CE High to RY/#BY Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/#BY High (Note 2, 4) #RESET VHH Hold from Valid SRD, RY/#BY High (Note 2, 4) #WP VIH Hold from Valid SRD, RY/#BY High (Note 2, 4) #BYTE Setup to #CE Going High (Note 7) #BYTE Hold from #CE High (Note 7)
Note: See 5.0V VDD Alternative #CE-Controlled Writes for notes 1 through 7.
SYM. tAVAV tPHEL tWLEL tELEH tPHHEH tSHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHGL tQVVL TQVPH tQVSL tFVEH tEHFV
MIN. 100 1 0 70 100 100 100 50 50 0 5 0 25
MAX.
UNIT nS S nS nS nS nS nS nS nS nS nS nS nS
100 0 0 0 0 50 100
nS nS nS nS nS nS nS
- 38 -
W28V400B/T
VDD = 5V 0.5V, 5V 0.25V, TA = 0 C to +70 C
PARAMETER Write Cycle Time #RESET High Recovery to #CE Going Low (Note 2) #WE Setup to #CE Going Low #CE Pulse Width #RESET VHH Setup to #CE Going High (Note 2) #WP VIH Setup to #CE Going High (Note 2) VPP Setup to #CE Going High (Note 2) Address Setup to #CE Going High (Note 3) Data Setup to #CE Going High (Note 3) Data Hold from #CE High Address Hold from #CE High #WE Hold from #CE High #CE Pulse Width High #CE High to RY/#BY Going Low Write Recovery before Read VPP Hold from Valid SRD, RY/#BY High (Note 2, 4) #RESET VHH Hold from Valid SRD, RY/#BY High (Note 2, 4) #WP VIH Hold from Valid SRD, RY/#BY High (Note 2, 4) #BYTE Setup to #CE Going High (Note 7) #BYTE Hold from #CE High (Note 7)
Notes:
SYM. tAVAV tPHEL tWLEL tELEH tPHHEH tSHEH tVPEH tAVEH tDVEH tEHDX tEHAX tEHWH tEHEL tEHRL tEHGL tQVVL TQVPH tQVSL tFVEH tEHFV
VDD = 5V 0.25V(5) Min. 85 1 0 50 100 100 100 40 40 0 5 0 25 90 0 0 0 0 40 85 Max.
5V 0.5V(6) Min. 90 1 0 50 100 100 100 40 40 0 5 0 25 90 0 0 0 0 40 90 Max.
UNIT nS S nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS nS
1. In systems where #CE defines the write pulse width (within a longer #WE timing waveform), all setup, hold, and inactive #WE times should be measured relative to the #CE waveform. 2. Sampled, not 100% tested. 3. Refer to Table 4 for valid AIN and DIN for block erase or word/byte write. 4. VPP should be held at VPPH1/2/3 (and if necessary #RESET should be held at VHH) until determination of block erase or word/byte write success (SR.1/3/4/5 = 0). 5. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (High Seed Configuration) for testing characteristics. 6. See Transient Input/Output Reference Waveform and Transient Equivalent Testing Load Circuit (Standard Configuration) for testing characteristics. 7. If #BYTE switch during reading cycle, exist the regulations separately.
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Publication Release Date: April 11, 2003 Revision A4
W28V400B/T
1 Address(A) #CE(E) VIH V IL V IH V IL V IH V IL V IH V IL VIH V IL V IH V IL VOH VOL VIH V IL
t WLEL
2
A IN t AVAV tEHEL t ELEH t DVEH
3
A IN t AVEH
4
5
6
t EHAX
t EHGL
#OE(G)
#WE(W)
t EHWH t EHDX D IN t FVEH D IN
t EHQV1,2 Valid
SRD
DATA(D/Q)
HIGH Z
t PHEL
D IN
t EHFV
#BYTE(F)
t EHRL t
RY/#BY(R)
t SHEH
t QVSL
#WP(S)
t PHHEH
t QVPH
V HH #RESET(P) VIH V IL
t VPEH t QVVL
VPPH3,2,1 VPP (V) V PPLK V IL
Figure 16. AC Waveform for #CE-Controlled Write Operations
Notes:
1. VDD power-up and standby. 2. Write block erase or word/byte write setup. 3. Write block erase confirm or valid address and data. 4. Automated erase or program delay. 5. Read status register data. 6. Write Read Array command.
- 40 -
W28V400B/T
Reset Operations
V OH RY/#BY(R) V OL V IH V IL
t PLPH
#RESET(P)
(A)Reset During Read Array Mode V OH RY/#BY(R) V OL V IH V IL
t PLPH t PLRH
#RESET(P)
(B)Reset During Block Erase, Full Chip Erase, Word/Byte Write or Lock-Bit Configuration 2.7V/3.3V/5V VDD V IL V IH V IL (C)#RESET Rising Timing
t 235VPH
#RESET(P)
Figure 17. AC Waveform for Reset Operation
Reset AC Specifications
SYM. PARAMETER #RESET Pulse Low Time (If RP# is tied to VDD, this specification is not applicable) #RESET Low to Reset during Block Erase or Word/Byte Write (Note 1, 2)
VDD 2.7V to #RESET High VDD 3.0V to #RESET High VDD 4.5V to #RESET High (Note 3)
VDD = 2.7V - 3.6V VDD = 3.0V - 3.6V VDD = 4.5V - 5.5V
Min. 100
Max.
Min. 100
Max.
Min. 100
Max.
UNIT
tPLPH tPLRH t235VPH
Notes:
nS 12 S nS
22 100 100
20 100
1. If #RESET is asserted while a block erase or word/byte write operation is not executing, the reset will complete within 100nS. 2. A reset time, tPHQV, is required from the later of RY/#BY or #RESET going high until outputs are valid. 3. When the device power-up, holding #RESET low minimum 100 nS is required after VDD has been in predefined range and also has been in stable there.
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Publication Release Date: April 11, 2003 Revision A4
W28V400B/T
Block Erase And Word/Byte Write Performance(3)
VDD = 2.7V to 3.6V, TA = 0 C to +70 C
SYM.
PARAMETER Word/Byte Write Time Block Write Time 32K word Block 4K word Block 32K word Block 4K word Block
NOTE 2 2 2, 4 2, 4 2 2
VPP = 2.7V - 3.6V VPP = 4.5V - 5.5V VPP = 11.4V - 12.6V
TYP.(1) MAX. TYP.(1) MAX. TYP.(1) MAX.
UNIT S S S S S S
44.6 45.9 1.46 0.19 1.14 0.38 7 18 8 22
17.7 26.1 0.58 0.11 0.61 0.32 6 11 8 14
12.6 24.5 0.42 0.11 0.51 0.31 6 11 7 14
tWHQV1 tEHQV1
32K word Block tWHQV2 Block Erase Time tEHQV2 4K word Block
tWHRH1 Word/Byte Write Suspend Latency tEHRH1 Time to Read tWHRH2 Erase Suspend Latency Time to tEHRH2 Read
S S
Note: See 5V VDD Block Erase and Word/Byte Write Performance for Notes 1 through 4.
VDD = 3.3V 0.3V, TA = 0 C to +70 C
SYM.
PARAMETER Word/Byte Write Time Block Write Time 32K word Block 4K word Block 32K word Block 4K word Block
NOTE 2 2 2, 4 2, 4 2 2
VPP = 2.7V - 3.6V VPP = 4.5V - 5.5V VPP = 11.4V - 12.6V
Typ.(1) 44 45 1.44 0.19 1.11 0.37 6 16.2 7 20 Max. Typ.(1) Max. 17.3 25.6 0.57 0.11 0.59 0.31 5 9.6 7 12 Typ.(1) 12.3 24 0.41 0.1 0.5 0.3 5 9.6 6 12 Max.
UNIT S S S S S S S S
tWHQV1 tEHQV1
32K word Block tWHQV2 Block Erase Time tEHQV2 4K word Block
tWHRH1 Word/Byte Write Suspend Latency tEHRH1 Time to Read tWHRH2 Erase Suspend Latency Time to tEHRH2 Read
Note: See 5V VDD Block Erase and Word/Byte Write Performance for Notes 1 through 4.
- 42 -
W28V400B/T
VDD = 5V 0.5V, 5V 0.25V, TA = 0 C to +70 C
SYM.
PARAMETER 32K word Block 4K word Block 32K word Block 4K word Block 32K word Block 4K word Block
NOTE 2 2 2, 4 2, 4 2 2
VPP = 4.5V - 5.5V
Typ.(1) 12.2 18.3 0.4 0.08 0.46 0.26 5 9.6 6 12 Max.
VPP = 11.4V - 12.6V
Typ.(1) 8.4 17 0.28 0.07 0.39 0.25 4 9.6 5 12 Max.
UNIT S S S S S S S S
tWHQV1 tEHQV1 tWHQV2 tEHQV2 tWHRH1 tEHRH1 tWHRH2 tEHRH2
Notes:
Word/Byte Write Time Block Write Time Block Erase Time
Word/Byte Write Suspend Latency Time to Read Erase Suspend Latency Time to Read
1. Typical values measured at TA = +25 C and nominal voltages. Subject to change based on device characterization. 2. Excludes system-level overhead. 3. Sampled but not 100% tested. 4. All values are in word mode (#BYTE = VIH). At byte mode (#BYTE = VIL), those values are double.
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Publication Release Date: April 11, 2003 Revision A4
W28V400B/T
12. FLASH MEMORY W28V400 FAMILY DATA PROTECTION
Noises having a level exceeding the limit specified in this document may be generated under specific operating conditions on some systems. Such noises, when induced onto #WE signal or power supply, may be interpreted as false commands, and which will cause undesired memory updating. To protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1. Protecting data in specific block By setting a #WP to low, only the boot block can be protected against overwriting. Parameter and main blocks cannot be locked. System program, etc., can be locked by storing them in the boot block. When a high voltage is applied to #RESET, overwrite operation is enabled for all blocks. 2. Data protection through VPP When the level of VPP is lower than VPPLK (lockout voltage), write operation on the flash memory is disabled. All blocks are locked and the data in the blocks are completely write protected. 3. Data protection through #RESET When the #RESET is kept low during power up and power down sequence such as voltage transition, write operation on the flash memory is disabled, write protecting all blocks. 4. Noise rejection of #WE Consider noise rejection of #WE in order to prevent false write command input.
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W28V400B/T
Recommended Operating Conditions
At Device Power-up
AC timing illustrated in Figure 18 is recommended for the supply voltages and the control signals at device power-up. If the timing in the figure is ignored, the device may not operate correctly.
VDD (p) #RESET Vpp
*2
V (min) DD Vss VIH VIL
tVR
*1 t2VPH
tR
tPHQV
(V) VPPH1/2 Vss VIH VIL V IH V IL V IH V IL
tR or tF
tAVQV
tR or tF
(A) ADDRESS
Valid Address
tF tELQV tR
#CE (E)
#WE (W)
tF
t GLQV
tR
#OE (G)
V IH V IL V IH V IL V OH V OL HIGH Z Valid Output
#WP (S)
DATA (D/Q)
*1 t5VPH for the device in 5V operations. *2 To prevent the unwanted writes, system designers should consider the VPP switch, which connects VPP to VSS during read operations and VPPH1/2/3 during write or erase operations. Figure 18. AC Timing at Device Power-up For the AC specifications tVR, tR, tF in the figure, refer to the next page. See the "ELECTRICAL SPECIFICATIONS" described in specifications for the supply voltage range, the operating temperature and the AC specifications not shown in the next page.
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Publication Release Date: April 11, 2003 Revision A4
W28V400B/T
Rise and Fall Time
PARAMETER SYMBOL MIN. MAX. UNIT
VDD Rise Time (Note 1) Input Signal Rise Time (Note 1, 2) Input Signal Fall Time (Note 1, 2)
Notes:
tVR tR tF
0.5
30000 1 1
S/ V S/ V S/ V
1. Sampled, not 100% tested. 2. This specification is applied for not only the device power-up but also the normal operations. tR (Max.) and tF (Max.) for #RESET are 100 S/V
Glitch Noises
Do not input the glitch noises which are below VIH (Min.) or above VIL (Max.) on address, data, reset, and control signals, as shown in Figure 19 (b). The acceptable glitch noises are illustrated in Figure 19 (a).
Input Singal VIH(Min.)
Input Singal VIH(Min.)
VIL (Max.) Input Singal
VIL (Max.) Input Singal
(a) Acceptable Glitch Noises
(b) NOT Acceptable Glitch Noises
Figure 19. Waveform for Glitch Noises
See the "DC CHARACTERISTICS" described in specifications for VIH (Min.) and VIL (Max.).
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W28V400B/T
13. ORDERING INFORMATION
PART NO. W28V400BT85C W28V400TT85C
Notes:
ACCESS TIME (nS) 85 85
OPERATING TEMPERATURE (C) 0 - 70 0 - 70
BOOT BLOCK Bottom Boot Top Boot
PACKAGE 48L TSOP 48L TSOP
1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure.
14. PACKAGE DIMENSION
48-Lead Standard Thin Small Outline Package (measured in millimeters)
1
48
e
MILLIMETER INCH Sym. MIN. NOM. MAX. MIN. NOM. MAX. A A1 A2 0.90 18.2 19.7 11.8 0.12 0.10
0.50
1.20 1.00 18.4 20.0 12.0 0.20 1.10 18.6 20.3 12.2
0.047 0.035 0.039 0.043 0.718 0.724 0.730 0.775 0.787 0.799 0.466 0.472 0.478 0.004
0.020
0.075 0.125 0.175 0.003 0.005 0.007
E b
D HD E
D HD A2
L
L1
c
b c e
L L1
0.28 0.005 0.011 0.017
0.21
0.50
0.80 0.10
0.008
0.35
0.65
0.020 0.026 0.032
0.031 0.004
A A1 Y
Y
0
8
0
8
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Publication Release Date: April 11, 2003 Revision A4
W28V400B/T
15. VERSION HISTORY
VERSION A1 A2 A3 A4 DATE May 22, 2002 Aug. 5, 2002 Nov. 18, 2002 Apr. 11, 2003 PAGE All 45 All Initial Issued Update descriptions and correct typo Correct the typo in Figure 18 Update descriptions and correct typo DESCRIPTION
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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