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W536020K/030K/060K/090K/120K VOICE/MELODY/LCD CONTROLLER (ViewTalk TM Series)
Table of Contents1. 2. 3. 4. 5. GENERAL DESCRIPTION ......................................................................................................... 2 FEATURES ................................................................................................................................. 3 BLOCK DIAGRAM ...................................................................................................................... 5 PAD DESCRIPTION ................................................................................................................... 6 ELECTRICAL CHARACTERISTICS........................................................................................... 9 5.1 5.2 5.3 6. Absolute Maximum Ratings............................................................................................... 9 DC Characteristics............................................................................................................. 9 AC Characteristics ........................................................................................................... 11
TYPICAL APPLICATION CIRCUITS ........................................................................................ 14 6.1 6.2 Sub Clock with RC Mode................................................................................................. 14 Sub Clock with Crystal Mode........................................................................................... 15
7.
REVISION HISTORY ................................................................................................................ 16
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Publication Release Date: May 21, 2003 Revision A3
W536020K/030K/060K/090K/120K
1. GENERAL DESCRIPTION
The W536XXXK, a member of ViewTalkTM family, is a high-performance 4-bit micro-controller (uC) with built-in speech unit, melody unit and 40seg * 8 com LCD driver unit which includes internal regulator, pump circuit and dedicated one page LCD RAM. The 4-bit uC core contains dual clock source, 4-bit ALU, two 8-bit timers, one 14 bits divider, maximum 24 pads for input or output, 8 interrupt sources and 8-level nesting for subroutine/interrupt applications. Speech unit, integrated as a single chip with maximum 128 seconds (based on 6.4K sample rate with 5 bits MDPCM), is capable of expanding to 512 seconds speech addressed by external memory W55XXX with serial bus interface. It can be implemented with Winbond Power Speech using MDPCM algorithm. Melody unit provides dual tone output and can store up to 1k notes. Power reduction mode is also built in to minimize power dissipation. It is ideal for games, educational toys, remote controllers, watches, clocks and other application products which incorporate both LCD display and speech.
Body
W536020K
W536030K
W536060K
W536090K
W536120K
Voice I/O pad WDT disable/Enable (Mask Option) Sub-clock RC/XTAL mode (Mask Option) RD port shared as serial bus (Mask Option) Tri-state serial bus (Mask Option) (3) Cascaded Voice ROM through serial bus (2)
Notes:
20 sec 4I/O,8I
(RA/RC/RD)
30 sec 4I/O, 8I
(RA/RC/RD)
60 sec 8io, 8i
(RA/RB/RC/RD)
90 sec 8I/O, 8I, 8O
(RA/RB/RC/RD/RE/ RF)
120 sec 8I/O, 8I, 8O
(RA/RB/RC/RD/ RE/RF)
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y
Y(1)
Y(1)
N
N
N (2)
Y N
Y Y(1)
N N
Y N
Y Y
1. Share 3 pads of RD port (RD1/CLK, RD2/DATA and RD3/ADDR) 2. Dedicate serial bus 3 pads (CLK, DATA and ADDR) to interface with W55XXX. Cascaded Voice ROM can help to expand voice up to 512 sec by W55XXX chip. 3. Tri-state serial bus mask option can float serial bus while voice playing is no active. Let this mask option is disabled to get minimum power consumption in general.
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W536020K/030K/060K/090K/120K
2. FEATURES
* Operating voltage: 2.4 volt ~ 5.5 volt * Watch dog disabled/enabled by mask option * Dual clock operating system - Main clock with Ring/Crystal (400 KHz to 4 MHz) - Sub-clock with 32.768 KHz RC/Crystal by mask option * Memory - Program ROM (P-ROM): 16K x 20 (ROM Bank0) - Data RAM (W-RAM): 1K x 4 bit (RAM Bank 0 is 512 nibbles from 0: 000~0: 1FF and 0: 380~0:3FF are mapped to specia register. RAM Bank F is 512 nibbles from F: 200~F: 3FF either data RAM or dedicated to script kernel) - LCD RAM (L-RAM): 80x 4 bit (RAM Bank1 from 200~24F) * Maximum 24 input/output pads - Ports for input only: 8 pads (RC, RD port; RD1~3 can share as serial bus for external memory W55XXX interface @W5360020/30K) - Ports for output only: 8 pads (RE & RF port; W536090K/120K available only) - Ports for Input/output: 8 pads (RA and RB port; RB port is available for W536060/090K/ 120K only) * Power-down mode - Hold mode (except for 32KHz oscillator) - Stop mode (including 32KHz oscillator and release by RD or RC port) * Eight types of interrupts - Five internal interrupts (Divider, Timer 0, Timer 1, Speech, Melody) - Three external interrupts (Port RC, RD, RA) * One built-in 14-bit clock frequency divider circuit * Two built-in 8-bit programmable countdown timers - Timer 0: one of two clock sources (FOSC/4 or FOSC/1024) can be selected - Timer 1: built-in auto-reload function includes internal timer, external event counter from RC.0 * Built-in 18/14-bit watchdog timer for system reset. * Powerful instruction sets * 8-level subroutine (including interrupt) nesting * LCD driver unit capability - VLCD higher than (VDD -0.5V) - Built-in voltage regulator to V2 pad - 40 seg x 8 com
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Publication Release Date: May 21, 2003 Revision A3
W536020K/030K/060K/090K/120K
- 1/8 or 1/4 duty, 1/4 or 1/3 bias, internal pump circuit option by special register - COM 4~ 7 and SEG16~39 can be shared as general input/output by special register - Either uC ROM or voice ROM used as LCD picture * Speech function - Provided 640K / 1M/ 2M/ 3M/ 4M bits Voice ROM for W536020K/030K/060K/090K/120K based on 5 bits MDPCM algorithm - Voice ROM (V-ROM) available for uC data or LCD picture data. - Maximum 8*256 Label/Interrupt vector (voice section number) available - Provide two types of speech busy flag to either each GO or each trigger - Maximum up to 16M bits speech address capability interface with external memory W55XXX through serial bus. * Melody function - Provide 1K notes (22bits/note) dedicated melody ROM - Provide two types of melody busy flag to uC either each note or each song - Provide 6 kinds of beat, 16 kinds of tempo, and pitch range from G3# to C7 - Tremolo, triple frequency and 3 kinds of percussion available - Maximum 31 songs available * Can mix speech with melody * Multi-engine controller * Direct driving speaker/buzzer or DAC output * Chip On Board available
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W536020K/030K/060K/090K/120K
3. BLOCK DIAGRAM
V3,V5,V6
VHI
SEG0~39
COM0~7
V2
DH1,DH2
LCDRAM 80*4 bit Data RAM 1K*4 bit
LCD DRIVER
VLCD PUMP & REGULATOR
VDD TEST
PORT RA
RA0~3
ROM 16K*20Bit
ACC
TONE
PORT RB
RB0~3
ALU
PORT RC
PORT RD
RC0~3
RD0~3
RE0~3 RF0~3
ADDR CLK DATA
PC
Special Register
IEF HEF
SPC
PORT RE
EVF
PEF
STACK (8 Levels)
HCF
MLD FLAG0
PORT RF
FLAG1 PM0
LPX0 LPX1
LPX4 LPX5
MR0
LPX2
LPY0
PSR0 LPX3
LPY1
Parallel to Serial
SPC_bus y SPC_pla y
ROSC
MDPCM Speech
PWM1/DAC
Timer 0
Timer 1
Interrupt ,Hold & Stop Control
MLD_busy
MLD_play
Voice ROM (640K/1M/3M/ 4M)
Dual Tone Melody
Watch Dog
Divide
Timing Generator
PWM/ DAC MIX Block
PWM2
VSS
VDDP
VSSP
RES
XIN
XOUT X32I X32O
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Publication Release Date: May 21, 2003 Revision A3
W536020K/030K/060K/090K/120K
4. PAD DESCRIPTION
SYMBOL I/O FUNCTION
XIN/RXIN
I
Input pad for main clock oscillator. It can be connected to crystal when crystal mode is selected (SCR0.2 = 1), otherwise connect a resistor to VDD to generate main system clock while Ring mode is selected (SCR0.2 = 0 and default). Oscillator can be enabled or stopped by set SCR0.1 to 1 or clear to 0 separately. External capacitor connects to start oscillation and get more accurate clock when crystal mode Output pad for oscillator which is connected to another crystal pad when in crystal mode. External capacitor connects to start oscillation when in crystal mode. 32.768 KHz crystal input pad or external resistor node 1 by mask option. External 15~20pF capacitor connects to start oscillation and get more accurate clock when in crystal mode. 32.768 KHz crystal output pad or external resistor node 2 by mask option. External 15~20pF capacitor connects to start oscillation when in crystal mode. General Input/Output port specified by PM1 register. If output mode is selected, PM0 register bit 0 can be used to specify CMOS/NMOS driving capability option. Initial state is input mode. RA3 may be uses as TONE if bit 0 of MR0 special register is set to logic 1. An interrupt source. General Input/Output port specified by PM2 register. If output mode is selected, PM0 register bit 1 can be used to specify CMOS/NMOS driving capability option. Initial state is input mode (W536060K/090K/120K only.) 4-bit schmitter input with internal pull high option specified by PM3 register bit 2. Each pad has an independent interrupt capability specified by PEFL special register. Interrupt and STOP mode wake up source. RC0 is also the external event counter source of Timer1. 4-bit schmitter input port with internal pull high option specified by PM3 register bit 3. Each pad has an independent interrupt capability specified by PEFH special register. Interrupt and STOP mode wake up source. RD1~3 will be shared as the external memory W55XXX interface pads while RD port shared as serial bus mask option is enabled @W536020K/030K. For W536020K/030K only, "Tri-state serial bus" mask option can use to float ADDR/CLK/DATD while "RD port shared as serial bus" mask option is enabled.
XOUT
O
X32I/RSUB1
I
X32O/RSUB2
O
RA0 ~ RA3/TONE (9) RB0 ~ RB3 (9) RC0 ~ RC3
I/O
I/O
I
RD0 RD1/CLK RD2/DATA RD3/ADDR (4) RE0~RE3 (9) RF0~RF3 (9) I
O O
Output port only. PM3 register bit 0 can be used to specify CMOS/NMOS driving capability option. (W536090K/120K only) Output port only. PM3 register bit 1 can be used to specify CMOS/NMOS driving capability option. (W536090K/120K only)
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W536020K/030K/060K/090K/120K
PAD Description, continued
SYMBOL
RES
I/O
FUNCTION
I I I O O O O I/O O O/O
System reset pad, active low with internal pull-high resistor. Test pad. Active high with internal pull low resistor. Connect resistor to VDD pad to generate speech or melody playing clock source. While speech or melody is active, PWM1/DAC is speaker direct driving output or DAC output controlled by voice output file. While speech or melody is active, PWM2 is another speaker direct driving output. External serial memory address write clock for voice extension (W536120K only). External serial memory address read clock for voice extension. (W536120K only). External serial memory data in/out for voice extension (W536120K only). Dedicated LCD segment output pads. LCD segment output pads, and can be shared as general output by register LCDM3 bit 1. Default function is segment pad. LCD segment output pads, and can be shared as general input by register LCDM3 bit 0. Default function is segment pad and PM5.1=0 to inhibit LCD waveform abnormal. LCD segment output pads, and can be shared as general output by register LCDM2 bit 3. Default function is segment pad. LCD segment output pads, and can be shared as general input by register LCDM2 bit 2. Default function is segment pad and PM5.0=0 to inhibit LCD waveform abnormal. LCD segment output pads, and can be shared as general input/output by register LCDM2 bit 1. PM4 register is used to select input or output while shared I/O function is active. Default function is segment pad and PM4.3 = 0 to inhibit LCD waveform abnormal. LCD segment output pads, and can be shared as general input/output by register LCDM2 bit 0. PM4 register is used to select input or output while shared I/O function is active. Default function is segment pad and PM4.2 = 0 to inhibit LCD waveform abnormal.
TEST ROSC PWM1/DAC PWM2 ADDR (5) CLK (5) DATA (5) SEG0-SEG15 SEG16/PORTN.0 SEG19/PORTN.3 SEG20/PORTM.0 SEG23/PORTM.3 SEG24/PORTL.0 SEG27/PORTL.3 SEG28/PORTK.0 SEG31/PORTK.3 SEG32/PORTJ.0 SEG35/PORTJ.3 SEG36/PORTI.0 SEG39/PORTI.3
O/I
O/O
O/I
O/IO
O/IO
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Publication Release Date: May 21, 2003 Revision A3
W536020K/030K/060K/090K/120K
PAD Description, continued
SYMBOL
I/O
FUNCTION
COM0-COM3 COM4/PORTO.0 COM7/PORTO.3 DH1, DH2 (6) VHI V3 V5 V6 (6)
O
LCD common signal output pads either 1/8 duty or 1/4duty. The LCD frame rate is controlled by LCDM1 register, and default value LCDM1 = 0111b with 64Hz frame rate. LCD common signal output pads, or shared as general input by register LCDM3.2 when in 1/4 duty mode. Default function is common function and PM5.2 = 0 to inhibit LCD waveform abnormal. Connection terminal for voltage double capacitor with 0.1uF. The DH2 connects to capacitor positive node and DH1 negative node if polar capacitor is used. Connect to V6 (LCD's VLCD) or VDD which has higher voltage, to make sure there is no any abnormal leakage current appearance. LCD COM/SEG output driving voltage. Need an external 0.1uF capacitor when 1/4 bias. (LCDM0.1 = 1) LCD COM/SEG output driving voltage. Need an external 0.1uF capacitor to every pad terminal. Voltage regulator output pad. An external capacitor is a must. Output level can be controlled from 0~Fh by LCDM4 register. If internal pump is enabled (LCDM3.3 = 0 and default value), LCD operating voltage (VLCD) will be 3*V2 or 4*V2 depending on 1/3 bias or 1/4 bias. A limitation should be noted that VLCD must be higher than (VDD -0.5v) to avoid chip leakage current. While external reference voltage is selected (LCDM3.3 = 1), V2 pad input voltage can not be over 1.5 Volt to inhibit chip damage. Power ground for PWM or DAC playing output. Power ground Power source for PWM or DAC playing output. Power Source
O/I
O I O O
V2 (6)
I/O
VSSP (7) VSS (7) VDDP (7) VDD (7)
Notes: (4) (5) (6) (7) (8) (9)
I I I I
RD1~3 are shared as CLK/DATA/ADDR to interface with W55XXX @W536020K/030K. @W536120K only 0.1uF is default value, and capacitor value should be larger than 0.1uF if LCD dot size over 0.5mm * 0.5mm. External application circuit should connect together, please refer to APPLICATION CIRCUIT. To sure chip operation properly, please bond all VDD, VDDP, VSS and VSSP pads and connect VSS and VSSP from chip outside PCB circuit. VHI pad is bonded to V6 or VDD. When working at NMOS open drain mode, external pull high voltage can't bigger than VDD to avoid leakage current.
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W536020K/030K/060K/090K/120K
5. ELECTRICAL CHARACTERISTICS
5.1 Absolute Maximum Ratings
PARAMETER RATING UNIT
Supply Voltage to Ground Potential Applied Input/Output Voltage Power Dissipation Ambient Operating Temperature Storage Temperature
-0.3 to +7.0 -0.3 to +7.0 120 0 to +70 -55 to +150
V V mW C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
5.2 DC Characteristics
(VDD-VSS = 3.0V, no load, FM = 4 MHz with Ring mode, Fs = 32.768 KHz, with Xtal mode, TA = 25 C, STN LCD panel on with dot size 0.5mm*0.5mm; unless otherwise specified)
PARAMETER
SYM.
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Op. Voltage Op. Current (No Load, no Voice, no) Melody) Hold Mode Current (No Load, LCD OFF) Hold Mode Current (No load, LCD ON) Stop Mode Current CLK/ADDR Output High Current CLK/ADDR Output low Current Input Low Voltage Input High Voltage Port RA, RB, RE, RF Output Low Voltage Port RA, RB, RE, RF Output High Voltage
VDD IOP1 Dual clock with crystal Dual clock with Ring type Sub-clock only, LCD off Sub-clock only, LCD on IOP2 IOP3 IOP4 IoH1 IoL1 VIL VIH VABL VABH Sub-clock active only Sub-clock active only LCD auto off Vout = 2.7V Vout = 0.4V IOL = 2.0 mA IOH = -2.0 mA
2.4 600 600 40 70 3
5.5 700 700 50 90 5 35 1 -0.8 0.8
V A
A uA A mA mA VDD VDD V V
VSS 0.7 2.4
-
0.3 1 0.4 -
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Publication Release Date: May 21, 2003 Revision A3
W536020K/030K/060K/090K/120K
DC Characteristics, continued
PARAMETER
SYM.
CONDITIONS
MIN.
TYP.
MAX.
UNIT
Pull-up Resistor Share Output RI, RJ, RL, RN, RP Sink Current RES Pull-up Resistor PWM1/2 Source Current (8) (RLOAD =8 between PWM1 And PWM2) PWM1/2 Sink Current (8) (RLOAD = 8 between PWM1 And PWM2) DAC output Current LCD Supply Current COM/SEG On Resistor V2 Pad Output Voltage V2 Pad Output Deviation (9) V2 Pad Voltage Step V6 Pad Output Voltage (LCD's VLCD depended on LCDM4 register) (9) V2 input voltage
Notes: (8) (9)
RCD IOL3 RRES ISPH
Port RC, RD VOL= 0.4V Volume Option = 00 Volume Option = 01 Volume Option = 10 Volume Option = 11
200 -300 50
300
400
K uA
100 -20 -70 -110 -135 20 70 110 135
200
K mA
ISPL
Volume Option = 00 Volume Option = 01 Volume Option = 10 Volume Option = 11
mA
IDAC ILCD RON VRR VD1 VR2 VLCD
VDD = 3V, RL = 100ohm No Load, All Seg. ON IOH = 50 A Depended on LCDM4 No Load LCDM4 increased 1 1/3 Bias & no load 1/4 Bias & no load
-4 -
-5 50 5K
-6 10K 1.45 5
mA A V % mV
0.7
50 2.85 * V2 3.8 * V2 2.9 * V2 3.85 * V2 2.95 * V2 3.9 * V2 1.5
V
VEXT
LCDM3.3 = 1
V
PWM current deviation will be 20%. Deviation is governed by LCD dot size. More larger LCD dot will get larger deviation..
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W536020K/030K/060K/090K/120K
5.3 AC Characteristics
(VDD-VSS = 3.0V, no load, FM = 4 MHz with Ring mode, Fs = 32.768 KHz, with Xtal mode, TA = 25 C, STN LCD on with dot size 0.5mm*0.5mm; unless otherwise specified)
PARAMETER Sub-clock Frequency Main-clock Frequency Chip Operation Frequency Instruction Cycle Time Reset Active Width Interrupt Active Width Main clock Ring frequency (10)
SYM. FSUB FM FOSC TCYC TRAW TIAW FRXIN
CONDITIONS Crystal type and X32IN and X32O with 17pF external cap. Ring type/Crystal type SCR0.0 = 1, FSYS = FSUB SCR0.0 = 0; FSYS = FMAIN One machine cycle FOSC = 32.768 KHz FOSC = 32.768 KHz RXIN = 680K RXIN = 330K RXIN = 200K RXIN = 130K
MIN.
TYP. 32768
MAX.
UNIT Hz
400K 400K 1 1
32768 4/FOSC 1M 2M 3M 4M 32
4M 4M -
Hz Hz S S S Hz
Sub-Clock RC Oscillator Sub-Clock Oscillation Stable Time @ Cold Start Frequency Deviation of main-clock FRXIN 2MHz Frequency Deviation of main-clock FRXIN = 3 MHz Frequency Deviation of main-clock FRXIN = 4 MHz ROSC Frequency Frequency Deviation of FROSC = 3MHz Frame frequency
Notes: (10)
FRSUB FSTOP f f f f f f FROSC f f FLCD
RSUB = 680K RSUB = 680K
f(3V) - f(2.4V) f(3V) f(3V) - f(2.4V) f(3V) f(3V) - f(2.4V) f(3V)
KHz 1 10 15 20 S % % % MHz 7.5 % Hz
0.8
ROSC=680K
f(3V) - f(2.4V) f(3V)
3
LCDM1 = 0111 b(default)
64
The deviation will be +20% while VDD drops from 5.5V to 2.4V based on same resistor
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Publication Release Date: May 21, 2003 Revision A3
W536020K/030K/060K/090K/120K
Iop Vs. Main clock RC mode
1000 800 600 Iop (uA) 400 200 0
3V 4.5V
1
2
3
4
Freq (MhZ)
Oscillation Freq Vs. Sub-Clock
44 40 36
Fsub (KhZ) 32
3V 4.5V
28 24 20 560 620 680 750 820 1K Rsub (Kohm)
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W536020K/030K/060K/090K/120K
Main Freq Vs. Rxin
6 5 4
Fmain 3 (MhZ)
2 1 0 130 150 160 200 330 680 2K 3K
2.4V 3v 4.5V 5.5V
RXIN (Kohm)
Voice Operating Freq. Vs. ROSC
Freq (MhZ)
4.5 4 3.5 3 2.5 2 470 560 680 910
ROSC (Kohm)
3V 4.5V
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Publication Release Date: May 21, 2003 Revision A3
W536020K/030K/060K/090K/120K
6. TYPICAL APPLICATION CIRCUITS 6.1 Sub Clock with RC Mode
1/4 bias, VLCD = 4.5V, VDD = 2.4~3.6V
40SEG*8COM LCD Panel
SEG0~39 COM 0~7
VDDP
SPEAKER Q1 8050
470
VDDP
(*3)
(*2)
SWITCH
C4
R5
___ RES VDDP
PWM1/DAC PWM2
(*4) C6
CLK/RD1 DATA/RD2 ADDR/RD3 DH1 DH2 C13 V6 C12 V5 C11 V3 C10 V2 C9
V6
VDDP
SPEAKER
1
C1
R4
C2 C3
VDD W536XXXK Rosc
R1
W55MXX
Battery
2
XIN
R3 C5
(*4)
X32IN
R2
(*1)
X32IO
VHI
VDD
VSSP
VSS
(*5)
COMPONENT Value VDD = 3V
C1
C2~C4
C5~C6 100pF
C7~C8
C9~C13
R1
R2
R3 680K/1MHz 350K/2MHz 215K/3MHz 150K/4MHz 750K/1MHz 350K/2MHz 225K/3MHz 160K/4MHz
R4
4.7uF
0.1uF
-
0.1~1uF
680K
655K
100
Value VDD = 4.5V Notes:
4.7uF
0.1uF
100pF
-
0.1~1uF
680K
675K
100
1. C9~C13 depends on LCD panel dot size. 2. Option R5 equals to 100 if high noise immunity is needed. 3. For DAC option application. 4. To ensure that three batteries function well in W536F20 demo board. C6 should stay close to pad PWM/PWM2 at its best. Under the mask ROM version, C5 and C6 can be skipped. 5. Sure chip operation properly, please bond all VDDP, VDD, VSSP and VSS; and connect VSSP pad to VSS from external PCB circuit.
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W536020K/030K/060K/090K/120K
6.2 Sub Clock with Crystal Mode
1/3 bias, VLCD = 3V, VDD = 3.6~5.4V
40SEG*4COM LCD Panel
COM0~3 SEG0~39
VDDP
VDDP
SPEAKER Q1 8050
SWITCH (*2)
R5
470
(*3)
C4
___ RES VDDP
PWM1/DAC
(*4)
VDDP
C6 PWM2
CLK/RD1
SPEAKER
1
C1
R4
VDD Rosc R1 XIN R3 C5
W536XXXK
DATA/RD2 ADDR/RD3 DH2 DH1 C12 V5 C11 V3 C10 V2 C9
VHI
W55MXX
Battery
C2 C3
2
(*4)
X32IN
C7 32K
(*1)
V6 VDD
X32IO
C8
VSSP VSS
(*5)
Component Value VDD = 3V Value VDD = 4.5V Notes:
C1 4.7uF
C2~C4 0.1uF
C5~C6 100pF
C7~C8 15~30PF
C9~C12 0.1~1uF
R1 680K
R2 -
R3 680K/1MHz 350K/2MHz 215K/3MHz 150K/4MHz 750K/1MHz 350K/2MHz 225K/3MHz 160K/4MHz
R4 100
4.7uF
0.1uF
100pF
15~30PF
0.1~1uF
680K
-
100
1. C9~C12 depends on LCD panel dot size. 2. Option R5 equals to 100 if high noise immunity is needed. 3. For DAC option application. 4. To ensure that three batteries function well in W536F20 demo board. C6 should stay close to 5. pad PWM/PWM2 at its best. Under the mask ROM version, C5 and C6 can be skipped. 5. Sure chip operation properly, please bond all VDDP, VDD, VSSP and VSS; and connect VSSP pad to VSS from external PCB circuit.
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Publication Release Date: May 21, 2003 Revision A3
W536020K/030K/060K/090K/120K
7. REVISION HISTORY
VERSION DATE WRITER DESCRIPTION
A1 A2 A3
SEP. 18, 2000 NOV. 24, 2000 May 21, 2003
Jimmy Chen Jimmy Chen Jimmy Chen Application circuit modify Application circuit modify
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
Information contained in this publication regarding device applications and the like is intended for suggestion only and may be superseded updates. No representation or warranty is given and no liability is assumed by Winbond Electronics Corp. with respect to the accuracy or use of such information, or infringement of patents or other intellectual property.
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