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| (R) XC3100A Logic Cell Array Families Product Specifications Features * Ultra-high-speed FPGA family with six members - 50-85 MHz system clock rates - 190 to 325 MHz guaranteed flip-flop toggle rates - 1.75 to 4.1 ns logic delays * High-end additional family member in the 22 X 22 CLB array-size XC3195A device * 8 mA output sink current and 8 mA source current * Maximum power-down and quiescent current is 5 mA * Both families are 100% architecture and pin-out compatible with other XC3000 families * Beyond this, XC3100A is also software and bitstream compatible with the XC3000, XC3000A, and XC3000L families * 100% PCI complaint (A-2 speed grade in plastic quad flat pack (PQFP) packaging). XC3100A combines the features of the XC3000A and XC3100 families. * Additional interconnect resources for TBUFs and CE inputs * Error checking of the configuration bitstream * Soft startup holds all outputs slew-rate limited during initial power-up * More advanced CMOS process Description The XC3100A is a performance-optimized relative of the XC3000 and XC3000A families. While all families are footprint compatible, XC3100A familiy extends the system performance beyond 80 MHz. The XC3100A familiy follows the XC4000 speed-grade nomenclature, indicating device performance with a number that is based on the internal logic-block delay, in ns. The XC3100A family offers the following enhancements over the popular XC3100 family. The XC3100A family has additional interconnect resources to drive the I-inputs of TBUFs driving horizontal Longlines. The CLB Clock Enable input can be driven from a second vertical Longline. These two additions result in more efficient and faster designs when horizontal Longlines are used for data bussing. During configuration, the XC3100A devices check the bitstream format for stop bits in the appropriate positions. Any error terminates the configuration and pulls INIT Low. When the configuration process is finished and the device starts up in user mode, the first activation of the outputs is automatically slew-rate limited. This feature, called Soft Startup, avoids the potential ground bounce when all outputs are turned on simultaneously. After start-up, the slew rate of the individual outputs is, as in all XC3000 families, determined by the individual configuration option. The XC3100A family is a superset of the XC3000 families. Any bitstream used to configure an XC3000, XC3000A, XC3000L or XC3100 device, will configure the same-size XC3100A device exactly the same way. Device XC3120A XC3130A XC3142A XC3164A XC3190A XC3195A CLBs 64 100 144 224 320 484 Array 8x8 10 x 10 12 x 12 16 x 14 16 x 20 22 x 22 User I/O Max 64 80 96 120 144 176 Flip-Flops 256 360 480 688 928 1,320 Horizontal Longlines 16 20 24 28 40 44 Configuration Data Bits 14,779 22,176 30,784 46,064 64,160 94,944 2-177 XC3100, XC3100A Logic Cell Array Family Xilinx maintains test specifications for each product as controlled documents. To insure the use of the most recently released device performance parameters, please request a copy of the current test-specification revision. Absolute Maximum Ratings Symbol Description VCC VIN VTS TSTG TSOL Supply voltage relative to GND Input voltage with respect to GND Voltage applied to 3-state output Storage temperature (ambient) Maximum soldering temperature (10 s @ 1/16 in.) Junction temperature plastic TJ Junction temperature ceramic +150 -0.5 to +7.0 -0.5 to VCC +0.5 -0.5 to VCC +0.5 -65 to +150 +260 +125 Units V V V C C C C Note: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those listed under Recommended Operating Conditions is not implied. Exposure to Absolute Maximum Ratings conditions for extended periods of time may affect device reliability. Operating Conditions Symbol VCC Description Supply voltage relative to GND Commercial 0C to +85C junction Supply voltage relative to GND Industrial -40C to +100C junction VIHT VILT VIHC VILC TIN High-level input voltage -- TTL configuration Low-level input voltage -- TTL configuration High-level input voltage -- CMOS configuration Low-level input voltage -- CMOS configuration Input signal transition time Min 4.75 4.5 2.0 0 70% 0 Max 5.25 5.5 VCC 0.8 100% 20% 250 Units V V V V VCC VCC ns At junction temperatures above those listed as Operating Conditions, all delay parameters increase by 0.3% per C. 2-178 DC Characteristics Over Operating Conditions Symbol VOH VOL VOH VOL VCCPD ICCO Description High-level output voltage (@ IOH = -8.0 mA, VCC min) Commercial Low-level output voltage (@ IOL = 8.0 mA, VCC min) High-level output voltage (@ IOH = -8.0 mA, VCC min) Industrial Low-level output voltage (@ IOL = 8.0 mA, VCC min) Power-down supply voltage (PWRDWN must be Low) Quiescent LCA supply current Chip thresholds programmed as CMOS levels1 Chip thresholds programmed as TTL levels IIL CIN Input Leakage Current Input capacitance, all packages except PGA175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 Input capacitance, PGA 175 (sample tested) All Pins except XTL1 and XTL2 XTL1 and XTL2 IRIN IRLL Pad pull-up (when selected) @ VIN = 0V (sample tested) Horizontal long line pull-up (when selected) @ logic Low 0.02 0.20 -10 2.30 0.40 V V 3.76 0.40 V V Min 3.86 Max Units V 8 14 +10 mA mA A 10 15 pF pF 15 20 0.17 2.80 pF pF mA mA Note: 1. With no output current loads, no active input or long line pull-up resistors, all package pins at VCC or GND, and the LCA configured with a MakeBits tie option. 2. Total continuous output sink current may not exceed 100 mA per ground pin. The number of ground pins varies from two for the XC3120A in the PC84 package, to eight for the XC3195A in the PQ208 or PG223 package. 2-179 XC3100, XC3100A Logic Cell Array Family CLB Switching Characteristic Guidelines CLB Output (X, Y) (Combinatorial) 1 CLB Input (A,B,C,D,E) 2 CLB Clock 12 TCL 4 CLB Input (Direct In) 6 CLB Input (Enable Clock) 8 CLB Output (Flip-Flop) TCKO T ECCK 7 TCKEC TDICK 11 T CH 5 TCKDI T ICK 3 T CKI T ILO CLB Input (Reset Direct) 13 TRPW 9 T RIO CLB Output (Flip-Flop) X5424 T Buffer (Internal) Switching Characteristic Guidelines Speed Grade Description Global and Alternate Clock Distribution* Either: Normal IOB input pad through clock buffer to any CLB or IOB clock input Or: Fast (CMOS only) input pad through clock buffer to any CLB or IOB clock input TBUF driving a Horizontal Long line (L.L.)* I to L.L. while T is Low (buffer active) (XC3100) (XC3100A) T to L.L. active and valid with single pull-up resistor T to L.L. active and valid with pair of pull-up resistors T to L.L. High with single pull-up resistor T to L.L. High with pair of pull-up resistors BIDI Bidirectional buffer delay Symbol -5 Max -4 Max -3 Max -2 Max -1 ADVANCE INFORMATION Max Units TPID TPIDC 6.8 5.4 6.5 5.1 5.6 4.3 5.2 4.0 4.8 3.8 ns ns TIO TIO TON TON TPUS TPUF 4.1 3.6 5.6 7.1 15.6 12.0 3.7 3.6 5.0 6.5 13.5 10.5 3.1 3.1 4.2 5.7 11.4 8.8 3.1 4.2 5.7 11.4 8.1 2.9 4.0 5.5 10.4 7.1 ns ns ns ns ns ns TBIDI 1.4 1.2 1.0 0.9 0.85 ns * Timing is based on the XC3142A, for other devices see XACT timing calculator. 2-180 CLB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Description Combinatorial Delay Logic Variables A, B, C, D, E, to outputs X or Y Sequential delay Clock K to outputs X or Y Clock K to outputs X or Y when Q is returned through function generators F or G to drive X or Y Set-up time before clock K Logic Variables Data In Enable Clock Reset Direct inactive Hold Time after clock k Logic Variables Data In Enable Clock Clock Clock High time Clock Low time Max. flip-flop toggle rate Reset Direct (RD) RD width delay from RD to outputs X or Y Global Reset, from RESET Pad, RESET width (Low) (XC3142A) delay from RESET pad to outputs X or Y Notes: -5 Min Max Min -4 Max -3 Min Max -2 -1 Units Symbol Min Max Min Max ADVANCE INFORMATION 1 TILO 4.1 3.3 2.7 2.2 1.75 1.4 ns 8 TCKO 3.1 2.5 2.1 1.7 ns TQLO 6.3 5.2 4.3 3.5 3.2 ns A, B, C, D, E DI EC RD 2 TICK 3.1 4 TDICK 2.0 6 TECCK 3.8 1.0 2.5 1.6 3.2 1.0 2.1 1.4 2.7 1.0 1.8 1.3 2.5 1.0 1.7 1.2 2.3 1.0 ns ns ns ns A, B, C, D, E DI EC 3 TCKI 0 5 TCKDI 1.0 7 TCKEC 1.0 0 1.0 0.8 0 0.9 0.7 0 0.9 0.7 0 0.8 0.6 ns ns ns 11 TCH 12 TCL FCLK 2.4 2.4 190 2.0 2.0 230 1.6 1.6 270 1.3 1.3 325 1.3 1.3 325 ns ns MHz 13 TRPW 9 TRIO 3.8 4.4 3.2 3.7 2.7 3.1 2.3 2.7 2.3 2.4 ns ns TMRW 14.0 TMRQ 17.0 14.0 14.0 12.0 12.0 12.0 12.0 12.0 12.0 ns ns The CLB K to Q output delay (TCKO, #8) of any CLB, plus the shortest possible interconnect delay, is always longer than the Data In hold time requirement (TCKDI, #5) of any CLB on the same die. TILO, TQLO and TICK are specified for 4-input functions. For 5-input functions or base FGM functions, each of these specifications for the XC3100A family increses by 0.50 ns (-5), 0.42 ns (-4) and 0.35 ns (-3). 2-181 XC3100, XC3100A Logic Cell Array Family IOB Switching Characteristic Guidelines I/O Block (I) 3 I/O Pad Input 1 I/O Clock (IK/OK) 12 TIOL I/O Block (RI) 4 RESET 5 I/O Block (O) 10 TOP I/O Pad Output (Direct) 7 I/O Pad Output (Registered) TOKPO TOOK 6 TOKO 15 TRPO TIKRI 13 TRRI 11 TIOH T PICK T PID I/O Pad TS 8 I/O Pad Output X5425 TTSON 9 T TSHZ Vcc PROGRAM-CONTROLLED MEMORY CELLS OUT INVERT 3-STATE INVERT OUTPUT SELECT SLEW RATE PASSIVE PULL UP 3- STATE (OUTPUT ENABLE) T OUT O D Q FLIP FLOP OUTPUT BUFFER I/O PAD R DIRECT IN REGISTERED IN I Q QD FLIP FLOP or LATCH R OK IK (GLOBAL RESET) TTL or CMOS INPUT THRESHOLD CK1 CK2 PROGRAM CONTROLLED MULTIPLEXER = PROGRAMMABLE INTERCONNECTION POINT or PIP X3029 2-182 IOB Switching Characteristic Guidelines (continued) Testing of the switching parameters is modeled after testing methods specified by MIL-M-38510/605. All devices are 100% functionally tested. Since many internal timing parameters cannot be measured directly, they are derived from benchmark timing patterns. The following guidelines reflect worst-case values over the recommended operating conditions. For more detailed, more precise, and more up-to-date timing information, use the values provided by the XACT timing calculator and used in the simulator. Speed Grade Description Propagation Delays (Input) Pad to Direct In (I) Pad to Registered In (q) with latch transparent (XC3100A) (XC3100) Clock (IK) to Registered In (Q) Set-up Time (Input) Pad to Clock (IK) set-up time XC3100 Family XC3120A,XC3130A XC3142A XC3164A XC3190A XC3195A Propagation Delays (Output) Clock (OK) to Pad (fast) same (slew-rate limited) Output (O) to Pad (fast) same (slew-rate limited) (XC3100A) (XC3100) 3-state to Pad begin hi-Z (fast) same (slew-rate limited) 3-state to Pad active and valid (fast) (XC3100A) same (slew-rate limited) 3-state to Pad active and valid (fast) (XC3100) same (slew-rate limited) Set-up and Hold Times (Output) Output (O) to clock (OK) set-up time,(XC3100A) (XC3100) Output (O) to clock (OK) hold time Clock Clock High time Clock Low time Max. flip-flop toggle rate Global Reset Delays RESET Pad to Registered In (Q), (XC3120/XC3120A) (XC3195/XC3195A) RESET Pad to output pad (fast) (slew-rate limited) Symbol 3 TPID TPTG TPTG 4 TIKRI Min -5 Max 2.8 14.0 16.0 2.8 -4 Min Max 2.5 12.0 15.0 2.5 -3 Min Max 2.2 11.0 13.0 2.2 -2 Min Max 2.0 11.0 1.9 -1 Min-Max 1.8 Units ns ns ns ns 1 TPICK 15.0 10.9 11.0 11.2 11.5 12.0 5.5 14.0 4.1 12.1 13.0 6.9 6.9 10.0 18.0 12.0 20.0 5.0 6.2 0 2.4 2.4 190.0 14.0 10.6 10.7 11.0 11.2 11.6 5.0 12.0 3.7 11.0 11.0 6.2 6.2 10.0 17.0 10.0 17.0 4.5 5.6 0 2.0 2.0 230.0 12.0 9.4 9.5 9.7 9.9 10.3 4.4 10.0 3.3 9.0 9.0 5.5 5.5 9.0 15.0 9.0 15.0 4.0 5.0 0 1.6 1.6 270.0 ADVANCE INFORMATION 1.8 3.6 8.9 2.7 8.0 11.0 8.9 9.0 9.2 9.4 9.8 4.0 9.7 3.0 8.7 5.0 5.0 8.5 14.2 8.5 8.6 8.8 9.0 9.4 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns MHz 7 7 10 10 10 9 9 8 8 8 8 TOKPO TOKPO TOPF TOPS TOPF TTSHZ TTSHZ TTSON TTSON TTSON TTSON 4.5 4.5 6.5 11.8 5 TOOK 5 TOOK 6 TOKO 11 TIOH 12 TIOL FCLK 3.6 0 1.3 1.3 325.0 3.2 0 1.3 1.3 325.0 13 TRRI 15 TRPO 15 TRPO 18.0 29.5 24.0 32.0 15.0 25.0 20.0 27.0 13.0 21.0 17.0 23.0 13.0 21.0 17.0 23.0 13.0 21.0 17.0 22.0 ns ns ns ns Notes: 1. Timing is measured at pin threshold, with 50 pF external capacitive loads (incl. test fixture). For larger capacitive loads, see XAPP 024. Typical slew rate limited output rise/fall times are approximately four times longer. 2. Voltage levels of unused (bonded and unbonded) pads must be valid logic levels. Each can be configured with the internal pull-up resistor or alternatively configured as a driven output or driven from an external source. 3. Input pad set-up time is specified with respect to the internal clock (IK). In order to calculate system set-up time, subtract clock delay (pad to ik) from the input pad set-up time value. Input pad holdtime with respect to the internal clock (IK) is negative. This means that pad level changes immediately before the internal clock edge (IK) will not be recognized. 4. TPID, TPTG, and TPICK are 3 ns higher for XTAL2 when the pin is configured as a user input. 2-183 XC3100, XC3100A Logic Cell Array Family For a detailed description of the device architecture, see pages 2-105 through 2-123. For a detailed description of the configuration modes and their timing, see pages 2-124 through 2-132. For detailed lists of package pin-outs, see pages 2-140 through 2-150. For package physical dimensions and thermal data, see Section 4. Example: XC3130A-70PC44C Temperature Range Ordering Information Device Type Toggle Rate Number of Pins Package Type Component Availability PINS TYPE 44 PLAST. PLCC 64 PLAST. VQFP 68 PLAST. PLCC 84 PLAST. PLCC CERAM PLAST. PGA PQFP 100 PLAST. TQFP 132 144 160 164 175 176 208 223 TOPPLAST. BRAZED PLAST. CERAM. PLAST. VQFP CQFP PGA PGA TQFP TOPPLAST. BRAZED PLAST. CERAM. PLAST. PQFP CQFP PGA PGA TQFP PLAST. CERAM. PQFP PGA CODE PC44 -5 -4 -3 -2 -1 -5 -4 -3 -2 -1 -5 -4 -3 -2 -1 -5 -4 -3 -2 -1 -5 -4 -3 -2 -1 -5 -4 -3 -2 -1 VQ64 PC68 CI CI CI C C PC84 CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C PG84 PQ100 TQ100 VQ100 CB100 PP132 PG132 TQ144 PQ160 CB164 PP175 PG175 TQ176 PQ208 PG223 CI CI CI C C CI CI CI C C CIMB CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C C C C C C C C C C C MB C C C C C CI CI CI C C CIMB CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C MB MB CI CI CI C C CI CI CI C C CIMB CI CI C C CIMB CI CI C C CI CI CI C C CI CI CI C C CI CI CI C C CIMB CI CI C C XC3120A CI CI CI C C CI CI CI C C XC3130A XC3142A XC3164A XC3190A XC3195A C = Commercial = 0 to +85 C I = Industrial = -40 to +100 C Parentheses indicate future product plans M = Mil Temp = -55 to +125 C B = MIL-STD-883C Class B 2-184 |
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