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Preliminary
XRD64L44
Dual 10-Bit 50MSPS CMOS ADC
March 2000-1
FEATURES
APPLICATIONS
* 10-Bit Resolution * * * * * * * * * *
Two Monolithic Complete 10-Bit ADCs 50 MSPS Conversion Rate On-Chip Track-and-Hold On-Chip Voltage Reference Low 5 pF Input Capacitance TTL/CMOS Outputs Tri-State Output Buffers Single +3V or +5V Power Supply Operation Low Power Dissipation: 250mW-typ @ 3.0V -40C to +85C Operation Temperature Range
* Medical Ultrasound Imaging * I & Q Modems
BENEFITS
* * * *
Reduction of Components Reduction of System Cost High Performance @ Low Power Dissipation Long Term Time and Temperature Stability
GENERAL DESCRIPTION The XRD64L44 is two 10-bit, monolithic, 50 MSPS ADCs. Manufactured using a standard CMOS process, the XRD64L44 offers low power, low cost and excellent performance. The on-chip track-and-hold amplifier(T/H) and voltage reference (VREF) eliminate the need for external active components, requiring only an external ADC conversion clock for the application. The XRD64L44 analog input can be driven with ease due to the high input impedance of RIN = 25KOhms and CIN = 5pF. The design architecture uses 17 time- interleaved 10bit SAR ADCs in each converter to achieve high conversion rate of 50 MSPS minimum. In order to insure and maintain accurate 10-bit operation with respect to time and temperature, XRD64L44 incorporates an auto-calibration circuit which continuously adjusts and matches the offset and linearity of each ADC. This auto-calibration circuit is transparent to the user after the initial 3.4ms calibration (168,000 initial clock cycles). The power dissipation is only 250mW at 50 MSPS and 225mW at 40 MSPS with +3.0V power supply. The digital output data is straight binary format, and the tri-state disable function is provided for common bus interface. The XRD64L44 internal reference provides cost savings and simplifies the design/development. The output voltage of the internal reference is set by two external resistors. The internal reference can be disabled if an external reference is used for a power savings of 50mW.
ORDERING INFORMATION
Part Number XRD64L44AIV Package Type 64-Lead TQFP Temperature Range -40C to +85C
Rev. P1.00
EXAR Corporation, 48720 Kato Road, Fremont, CA 94538 * (510) 668-7000 * FAX (510) 668-7017
XRD64L44
Preliminary
VCLMPA VINA+ VINA-
Bandgap
10 Bit A/D's
ADC A
A/D 1a
VBG
VFBK VRHF
+
A/D 17a
11
DA9 - DA0, OTRA TRI_A DIFF SYNCO PD CKIN CLAMP
K
CONTROL LOGIC
10 Bit A/D's
ADC B
A/D 1b
VRLF
11
VCMO
+
DB9 - DB0, OTRB TRI_B
A/D 17b
VCLMPB VINB+ VINB-
Figure 1. XRD64L44 Simplified Block Diagram
Rev. P1.00
2
Preliminary
XRD64L44
DOGND
DOVDD
DGND
DVDD
OTRA
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
OTRB
33
DA9
DA8
DA7
DA6
DA5
DA4
DA3
DA2
DA1
DA0
VCMO DGND AGND AVDD AGND AGND VINBVINB+ AGND VINA+ VINAAGND AVDD AVDD AGND AGND
DB9 DB8 DB7 DB6 DB5 DB4 DB3 DGND DOVDD DOGND DB2 DB1 DB0 SYNCO CKIN TRI_A
49
50
51
52
53
54
55
56
XRD64L44 64QFP
57
58
59
60
61
62
63
64
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
VCLMPA
VCLMPB
VRHF
VRHF
VFBK
VRLF
VRLF
VBG
Rev. P1.00
3
CLAMP
AGND
DGND
DGND
TRI_B
DVDD
DIFF
PD
17
18
19
20
21
22
23
24
25
26
27
28
29
30
31
32
XRD64L44
PIN DESCRIPTION
Pin # 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 Symbol VBG VFBK VRHF VRHF VRLF VRLF VCLMPA VCLMPB AGND DGND DGND PD DVDD TRI_B DIFF CLAMP TRI_A CKIN SYNCO DB0 DB1 DB2 DOGND DOVDD DGND DB3 DB4 DB5 DB6 DB7 DB8 DB9 OTRB DA0 DA1 DA2 DA3 DA4 DOVDD DOGND DVDD
Preliminary
Description Bandgap Voltage Output Analog Reference Feedback Top Voltage Reference Force Top Voltage Reference Force Bottom Voltage Reference Force Bottom Voltage Reference Force Analog Input Clamp A Analog Input Clamp B Analog Ground Digital Ground Digital Ground Power Down Digital Supply Voltage Tri-state for the B Channel Outputs Differential / Single-Ended Input Mode Digital Clamp Control Tri-state for the A Channel Outputs Clock Input Data Valid Output Digital Output Bit 0 (LSB) ADC B Digital Output Bit 1 ADC B Digital Output Bit 2 ADC B Digital Output Ground Digital Output Supply Voltage Digital Ground Digital Output Bit 3 ADC B Digital Output Bit 4 ADC B Digital Output Bit 5 ADC B Digital Output Bit 6 ADC B Digital Output Bit 7 ADC B Digital Output Bit 8 ADC B Digital Output Bit 9 (MSB) ADC B Over Range Digital Output Bit ADC B Digital Output Bit 0 (LSB) ADC A Digital Output Bit 1 ADC A Digital Output Bit 2 ADC A Digital Output Bit 3 ADC A Digital Output Bit 4 ADC A Digital Output Supply Voltage Digital Output Ground Digital Supply Voltage
Rev. P1.00
4
Preliminary
PIN DESCRIPTION (CONT'D)
Pin # 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 Symbol DGND DA5 DA6 DA7 DA8 DA9 OTRA VCMO DGND AGND AVDD AGND AGND VINBVINB+ AGND VINA+ VINAAGND AVDD AVDD AGND AGND Description Digital Ground Digital Output Bit 5 ADC A Digital Output Bit 6 ADC A Digital Output Bit 7 ADC A Digital Output Bit 8 ADC A Digital Output Bit 9 ADC A Over Range Digital Output Bit ADC A Differential Common Mode Voltage Output Digital Ground Analog Ground Analog Supply Voltage Analog Ground Analog Ground Analog Input B(-) Analog Input B(+) Analog Ground Analog Input A(+) Analog Input A(-) Analog Ground Analog Supply Voltage Analog Supply Voltage Analog Ground Analog Ground
XRD64L44
Rev. P1.00
5
XRD64L44
Preliminary
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25C AVDD = DVDD = +3.3V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 50 MSPS, 50% Duty Cycle, Differential Input Mode
Symbol Parameter Min. Typ. Max. Unit Conditions/Comments DC ACCURACY DNL INL MON FSE ZSE Differential Non-Linearity Integral Non-Linearity Monotonicity Full Scale Error Zero Scale Error -1.0 +/-0.4 +/-1.1 No Missing Codes +10 5 mV mV 1.0 LSB LSB Guaranteed by Test F.S. = (VRHF - VRLF)x0.97 Single Ended Mode
ANALOG INPUT INVR INRES INCAP INBW Input Voltage Range Input Resistance Input Capacitance Input Bandwidth
0 VRHFx0.97 V
VRLF Grounded
20 5 400
KOhms pF MHz -1dB Small Signal
REFERENCE INPUT, INTERNAL BANDGAP REFERENCE AND REFERENCE BUFFER RLAD RLADTCO VBG VBGTC VRLF VRHF VRHF External Reference VRHF PSRR Internal Reference Buffer Ladder Resistance Ladder Resistance Tempco Bandgap Output Voltage Range Bandgap Reference Tempco 0.0
VRLF+1.0 VRLF+1.0
100
125 +0.8 1.25 30
150
Ohms Ohms/C V ppm/C
2.0
AVdd-0.6
V V Internal Reference Buffer V External mV/V
AVdd 6
CONVERSION and TIMING CHARACTERISTICS (CL = 10pF) MAXCON MINCON PDEL tad APJT tr tf tpd tden tdis CLKDC Maximum Conversion Rate Minimum Conversion Rate Pipeline Delay(Latency) Aperture Delay Time Aperture Jitter Time Digital Output Rise Time Digital Output Fall Time Output Data Propagation Delay Output Data Enable Delay Output Data Disable Delay Clock Duty Cycle 40 4 12 3 3 6 6 5 50 60 14 14 50 60 100 17 MSPS KSPS CLK ns ps ns ns ns ns ns % Guaranteed by Design Guaranteed by Design Guaranteed by Design Peak-to Peak Clock Cycles Digital Data Delay
Rev. P1.00
6
Preliminary
XRD64L44
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25C AVDD = DVDD = +3.3V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V, 50% Duty Cycle, Differential Input Mode
SymbolParameter DYNAMIC PERFORMANCE Fs = 40MHz SNR Signal-to-Noise Ratio Fin = 1.0 MHz fin = 4.0 MHz SINAD Signal-to Noise and Distortion fin = 1.0 MHz fin = 4.0 MHz fin = 12.5 MHz ENOB Effective Number of Bits fin = 1.0 MHz fin = 4.0 MHz fin = 12.5 MHz SFDR Spurious Free Dynamic Range SFDR Crosstalk fin = 4.0 MHz fin = 4.0 MHz 70 75 dB dB 9.5 9.5 9.3 Bit Bit Bit 58 58 57 dB dB dB 60 60 dB dB Not Including Harmonics Min. Typ. Max. Unit Conditions/Comments
Rev. P1.00
7
XRD64L44
Preliminary
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25C AVDD = DVDD = +3.3V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V, 50% Duty Cycle, Differential Input Mode
SymbolParameter DYNAMIC PERFORMANCE Fs = 50MHz SNR Signal-to-Noise Ratio Fin = 1.0 MHz fin = 4.0 MHz SINAD Signal-to Noise and Distortion fin = 1.0 MHz fin = 4.0 MHz fin = 12.5 MHz ENOB Effective Number of Bits fin = 1.0 MHz fin = 4.0 MHz fin = 12.5 MHz SFDR Spurious Free Dynamic Range SFDR Crosstalk fin = 4.0 MHz fin = 4.0 MHz 70 75 dB dB 9.0 9.0 8.8 9.3 9.3 9.1 Bit Bit Bit 55 54 54 57 57 56 dB dB dB 56 56 58 58 dB dB Not Including Harmonics Min. Typ. Max. Unit Conditions/Comments
Rev. P1.00
8
Preliminary
XRD64L44
ELECTRICAL CHARACTERISTICS TABLE (CONT'D) Test Conditions (Unless Otherwise Specified) TA = 25C AVDD = DVDD = +3.3V, VIN = GND to +2.5V, VRLF = GND, VRHF = +2.5V and Fs = 50 MSPS, 50% Duty Cycle, Differential Input Mode
SymbolParameter DIGITAL INPUTS DVINH DVINL DIINH Digital Input High Voltage Digital Input Low Voltage 2.5 0.5 V V Min. Typ. Max. Unit Conditions/Comments
Digital Input High Current (The DIFF input has an internal pull-up resistor, TRI_A and TRI_B have internal pull-down resistors
CKIN DIFF
Clock Input Differential/Single-Ended Input
-5.0 -1.0
0.05 -0.25
5.0 1.0 -50.0
nA uA uA
TRI_A/TRI_B A/B Channel Tri-State DIINL
-125.0 -90.0
Digital Input Low Current (The DIFF input has an internal pull-up resistor, TRI_A and TRI_B have internal pull-down resistors
CKIN DIFF
Clock Input Differential/Single-Ended Input
-5.0 50.0 -1.0
0.05 90.0 0.25 5
5.0 125.0 1.0 8
nA uA uA pF
TRI_A/TRI_B A/B Channel Tri-State DINC Digital Input Capacitance
DIGITAL OUTPUTS (CL = 10 pF) DOHV DOLV IOZ Digital Output High Voltage Digital Output Low Voltage High-Z Leakage -20
DVdd -0.4VDVdd-0.3V
V V nA
IOH = 1.5 mA IOL = 1.5 mA
0.3 0.2
0.4 20
POWER SUPPLIES AVDD DVDD AIDD DIDD DOIDD VRHF PDISS AIDD DIDD DOIDD VRHF PDISS Analog Power Supply Voltage Digital Power Supply Range Analog Supply Current Digital Supply Current Output Driver Current Top Voltage Ref Force Current Power Dissipation Analog Supply Current Digital Supply Current Output Driver Current Top Voltage Ref Force Current Power Dissipation 3.0 3.3 AVDD 37 15 15 8 225 38 19 18 8 250 3.6 V V mA mA mA mA mW mA mA mA mA mW VRHF/125, VRHF = 1.0V VRHF/125, VRHF = 1.0V DVDD = AVDD
Fs = 40 MHz, AVdd = DVdd = 3.0V, CL = 10pF, Fin = 10MHz
Fs = 50 MHz, AVdd = DVdd = 3.0V, CL = 10pF, Fin = 10MHz
Rev. P1.00
9
XRD64L44
Preliminary
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2, 3 VDD to GND
Notes: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100ms. 3 VDD refers to AVDD and DVDD. GND refers to AGND and DGND
Rev. P1.00
10

ESD
2000V min

VRT & VRB VIN All Inputs All Outputs Storage Temperature

VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V VDD +0.5 to GND -0.5V -65C to 150C
+7.0V
Lead Temperature (Soldering 10 seconds) 300C Maximum Junction Temperature 150C Package Power Dissipation Ratings (TA= +70C) SSOP JA = 89.4C/W

Preliminary
XRD64L44
65
60.00
55.00 SINAD in db
SINAD in db
60
50.00
55
45.00
40.00
3.0V 3.2V 3.4V 3.6V
50
2.8V
3.0V 2.90MHz
3.2V 6.90MHz
3.4V 9.90MHz
3.6V
Fclk = 50.0MHz Fclk = 56.7MHz
Fclk = 53.3MHz Fclk = 60.0MHz
Figure 2 - SINAD vs. Fin and Vdd @Fc = 40.0MHz, DIFFERENTIAL INPUT MODE
0.00 -20.00
Figure 3 - SINAD vs. Fclock and Vdd DIFFERENTIAL INPUT MODE
0.00
Relative Power in db
Relative Power in db
-40.00 -60.00 -80.00 -100.00 -120.00 DC 4.0
Single Tone 8192 Point FFT SFDR -72.66 SINAD -57.97
-20.00
-40.00
Single Tone 8192 Point FFT SFDR -69.77 SINAD -57.11
-60.00
-80.00
-100.00
-120.00 DC 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0 18.0
8.1
12.1
16.1
Frequency in MHz
Frequency in MHz
Figure 4 - FFT Spectrum @Fclock = 40.0MHz, Fin = 4.0MHz, DIFFERENTIAL INPUT MODE
60
Figure 5 - FFT Spectrum @Fclock = 40.0MHz, Fin = 10.0MHz, DIFFERENTIAL INPUT MODE
0.00
Relative Power in db
55 SINAD in db
-20.00 -40.00 -60.00 -80.00 -100.00 -120.00
Single Tone 8192 Point FFT SFDR -62.57 SINAD -55.25
50
45
40 2.8V 3.0V 2.90MHz 3.2V 6.90MHz 3.4V 9.90MHz 3.6V
DC
4.0
8.1
12.1
16.1
Frequency in MHz
Figure 6 - SINAD vs. Fin and Vdd @Fc = 40.0MHz, SINGLE-ENDED INPUT MODE
Figure 7 - FFT Spectrum @Fclock = 40.0MHz, Fin = 4.0MHz, Single-ended INPUT MODE
Rev. P1.00
11
XRD64L44
0.00 -20.00 -40.00 -60.00 -80.00 -100.00 -120.00 DC 2.0 4.0 6.0 8.0 10.0 12.0 14.0 16.0
Preliminary
60.00 Single Tone 8192 Point FFT SFDR -60.95 SINAD -54.48 SINAD in db
18.0
Relative Power in db
55.00
50.00
45.00 2.80V 3.00V 2.90MHz 3.20V 6.90MHz 3.40V 9.90MHz 3.60V
Frequency in MHz
Figure 8 - FFT Spectrum @Fclock = 40.0MHz, Fin = 10.0MHz, Single-ended INPUT MODE
0.00 -20.00 Relative Power in db -40.00 -60.00 -80.00 -100.00 Single Tone 8192 Point FFT SFDR -66.93 SINAD -56.70
Figure 9 - SINAD vs. Fin and Vdd @Fc = 50.0MHz, DIFFERENTIAL INPUT MODE
0.00 -20.00
Relative Power in db
-40.00 -60.00 -80.00 -100.00 -120.00
Single Tone 8192 Point FFT SFDR -66.93 SINAD -56.70
-120.00 DC 4.0 8.0 12.0 16.0 20.0 24.1 Frequency in MHz
DC
2.5
5.0
7.5
10.0 12.5 15.0 17.5 20.0 22.5 Frequency in MHz
Figure 10 - FFT Spectrum @Fclock = 50.0MHz, Fin = 4.0MHz, DIFFERENTIAL INPUT MODE
0.00 -20.00
Figure 11 - SINAD @Fclock = 50.0MHz, Fin = 12.5MHz, DIFFERENTIAL INPUT MODE
Relative Power in db
-40.00 -60.00 -80.00 -100.00 -120.00 DC
Single Tone 8192 Point FFT SFDR -64.15 SINAD -50.91 SINAD in db
10.5 12.1 13.6 15.1 16.6 18.1 19.6 21.1 22.6 24.1 1.5 3.0 4.5 6.0 7.5 9.0
60.00
55.00
50.00
45.00
40.00 2.80V 3.00V 2.90MHz 3.20V 6.90MHz 3.40V 9.90MHz 3.60V
Frequency in MHz
Figure 12 - FFT Spectrum @Fclock = 50.0MHz, Fin = 24.1MHz, DIFFERENTIAL INPUT MODE
Figure 13 - SINAD vs. Fin and Vdd @Fc = 50.0MHz, SINGLE-ENDED INPUT MODE
Rev. P1.00
12
Preliminary
XRD64L44
0.00 -20.00 Single Tone 8192 Point FFT SFDR -64.09 SINAD -54.21
0.00 -20.00
Relative Power in db
Relative Power in db
-40.00 -60.00 -80.00
-40.00
Single Tone 8192 Point FFT SFDR -54.01 SINAD -51.75
-60.00 -80.00 -100.00 -120.00
-100.00 -120.00 DC 4.0 8.0 12.0 16.0 20.0 24.0
DC
2.5
5.0
7.5
10.0
12.5
15.0
17.5
20.0
22.5
Fre quency in M Hz
Frequency in MHz
Figure 14 - SINAD @Fclock = 50.0MHz, Fin = 4.0MHz, SINGLE-ENDED INPUT MODE
0.00 -20.00 Relative Power in db -40.00 -60.00 -80.00 -100.00 -120.00
DC 3.0 6.0 9.0 12.1 15.1 18.1 21.1 24.1
Figure 15 - FFT SPECTRUM @Fclock = 50.0MHz, Fin = 12.5MHz, SINGLE-ENDED INPUT MODE
Single Tone 8192 Point FFT SFDR -53.43 SINAD -47.36
Frequency in MHz
Figure 16 - SINAD @Fclock = 50.0MHz, Fin = 24.1MHz, SINGLE-ENDED INPUT MODE
Rev. P1.00
13
XRD64L44
Preliminary Notes
Rev. P1.00
14
Preliminary
XRD64L44
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contained here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for in accuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances.
Copyright 1999 EXAR Corporation
Datasheet February 1999 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. P1.00
15

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