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IMP51 1 1/51 1 2
DATA COMMUNICATIONS
9-Line SCSI Terminator
Key Features
x x x x x x x x x x x x x x Ultra-Fast response for Fast-20 SCSI applications 35MHz channel bandwidth 3.3V operation Less than 3pF output capacitance Sleep-mode current less than 275A Thermally self limiting No external compensation capacitors Implements 8-bit or 16-bit (wide) applications Compatible with active negation drivers (60mA/channel) Compatible with passive and active terminations Approved for use with SCSI 1, 2, 3 and UltraSCSI Hot swap compatible Pin-for-pin compatible with LX5211 and UC5606 (IMP5111) Pin-for-pin compatible with LX5212 and UC5603/5613/5614 (IMP5112)
- 35MHz Channel Bandwidth
The 9-channel IMP5111/5112 SCSI terminator is part of IMP's family of high-performance SCSI terminators that deliver true UltraSCSI performance. The BiCMOS design offers superior performance over first generation linear regulator/resistor based terminators. IMP's new architecture employs high-speed adaptive elements for each channel, thereby providing the fastest response possible - typically 35MHz, which is 100 times faster than the older linear regulator terminator approach. The bandwidth of terminators based on the older regulator/resistor terminator architecture is limited to 500kHz since a large output stabilization capacitor is required. The IMP architecture eliminates the external output compensation capacitor and the need for transient output capacitors while maintaining pin compatibility with first generation designs. Reduced component count is inherent with the IMP5111/5112. The IMP5111/5112 architecture tolerates marginal system designs. A key improvement offered by the IMP5111/5112 lies in its ability to insure reliable, error-free communications even in systems which do not adhere to recommended SCSI hardware design guidelines, such as improper cable lengths and impedance. Frequently, this situation is not controlled by the peripheral or host designer. For portable and configurable peripherals, the IMP5111/5112 can be placed in a sleep mode with a disconnect signal. Quiescent current is less than 275A when disabled. When disabled, the outputs are in a high impedance state with output capacitance less than 3pF.
Block Diagrams
Term Power
Thermal Limiting Circuit
Current Biasing Circuit
24mA Current Limiting Circuit
DATA OUTPUT PIN DB (0)
2.85V
DISCONNECT (IMP5111) DISCONNECT (IMP5112)
-
1 of 9 Channels
+
1.4V
5111/5112_01.eps
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IMP51 1 1/51 1 2
Pin Configuration
SO-16
T7 T8 T9 HEAT SINK/GND GND DISCONNECT* T1 T2 1 2 3 4 5 6 7 8 DW Package IMP5111 IMP5112 16 T6 15 T5 14 NC 13 HEAT SINK/GND 12 HEAT SINK/GND 11 VTERM 10 T4 9 T3 T7 T8 T9 NC GND HEAT SINK/GND HEAT SINK/GND HEAT SINK/GND HEAT SINK/GND
5111/5112__02.eps
TSSOP-24
1 2 3 4 5 6 7 8 9 IMP5111 IMP5112 24 T6 23 T5 22 NC 21 NC 20 HEAT SINK/GND 19 HEAT SINK/GND 18 HEAT SINK/GND 17 HEAT SINK/GND 16 NC 15 VTERM 14 T4 13 T3 PW Package
5111/5112_02a.eps
* DISCONNECT (IMP5111) DISCONNECT (IMP5112)
DISCONNECT* 10 T1 11 T2 12
* DISCONNECT (IMP5111) DISCONNECT (IMP5112)
Ordering Information
Part Number
IMP5111CDP IMP5111CDPT IMP5111CPWP IMP5111CPWPT IMP5112CDP IMP5112CDPT IMP5112CPWP IMP5112CPWPT
Temperature Range
0C to 125C 0C to 125C 0C to 125C 0C to 125C 0C to 125C 0C to 125C 0C to 125C 0C to 125C
Package
16-pin Plastic SO Tape and Reel, 16-pin Plastic SO 24-pin Plastic TSSOP Tape and Reel, 24-pin Plastic TSSOP 16-pin Plastic SO Tape and Reel, 16-pin Plastic SO 24-pin Plastic TSSOP Tape and Reel, 24-pin Plastic TSSOP
5111/5112_t01.at3
Absolute Maximum Ratings1
TermPwr Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . +7V Signal Line Voltage . . . . . . . . . . . . . . . . . . . . . . . . 0V to +7V Regulator Output Current . . . . . . . . . . . . . . . . . . 0.4A Operating Junction Temperature Plastic (DP, PWP Packages) . . . . . . . . . . . . . . . 150C Storage Temperature Range . . . . . . . . . . . . . . . . . -65C to 150C Lead Temperature (Soldering, 10 seconds) . . . . . 300C Note: 1. Exceeding these ratings could cause damage to the device. All voltages are with respect to Ground. Currents are positive into, negative out of the specified terminal.
Thermal Data
DP Package: Thermal Resistance Junction-to-Leads, JL . . . . . . . . 20C/W Thermal Resistance Junction-to-Ambient, JA . . . . . . 50C/W PW Package: Thermal Resistance Junction-to-Leads, JL . . . . . . . . 27C/W Thermal Resistance Junction-to-Ambient, JA . . . . . . 100C/W 2 Junction Temperature Calculation: TJ = TA + (PD x JA). The JA numbers are guidelines for the thermal performance of the device/pc-board system. All of the ambient airflow is assumed.
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IMP51 1 1/51 1 2
Recommended Operating Conditions2
Parameter
TermPwr Voltage High Level Enable Input Voltage IMP5111 IMP5112 Low Level Disable Input Voltage IMP5111 IMP5112 Operating Junction Temperature Range VIL
Symbol
VTERM VIH
Min
3.3 2 0 0 2 0
Typ
Max
5.5 VTERM 0.8 0.8 VTERM 125
Units
V V
V
C
5111/5112_t02.eps
Note:
2. Recommended operating conditions indicate the range over which the device is functional.
Electrical Characteristics
Unless otherwise specified, these specifications apply at an ambient operating temperature of TA = 25C. TermPwr = 4.75V. Low duty cycle pulse testing techniques are used which maintain junction and case temperatures equal to the ambient temperature.
Parameter
Output High Voltage TermPwr Supply Current
Symbol Conditions
VOUT ICC All data lines = Open All data lines = 0.5V IMP5111 IMP5112 DISCONNECT Pin < 0.8V DISCONNECT Pin > 2.0V IOUT IMP5111 IIN VOUT = 0.5V DISCONNECT Pin = 4.75V DISCONNECT Pin = 0V
Min
2.65
Typ
2.85 6 215 275 275
Max
9 225
Units
V mA A
Output Current DISCONNECT Input Current
-21
-23 10 -90 -90 10 10 10 3 35
-24
mA nA A A nA nA
DISCONNECT Input Current
IMP5112
IIN
DISCONNECT Pin = 0V DISCONNECT Pin = 4.75V
Output Leakage Current
IMP5111 IMP5112
IOL
DISCONNECT Pin < 0.8V, VO = 0.5V DISCONNECT Pin > 2.0V, VO = 0.5V
Capacitance in DISCONNECT Mode Channel Bandwidth Termination Sink Current, per Channel
COUT BW ISINK
VOUT = 0V, Frequency = 1MHz
pF MHz mA
5111/5112_t03.eps
VOUT = 4V
60
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Data Communications
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IMP51 1 1/51 1 2
Application Information
Figure 1. Receiving Waveform - 20MHz
Receiver 1 Meter, AWG 28
Figure 2. Driving Waveform - 20MHz
Driver
IMP5111 IMP5112
IMP5111 IMP5112
5111/5112_03.eps
Figure 3.
IMP5111/IMP5112 Maximizes Line Current
Cable transmission theory suggests to optimize signal speed and quality, the termination should act both as an ideal voltage reference when the line is released (deasserted) and as an ideal current source when the line is active (asserted). Common active terminators which consist of linear regulators in series with resistors (typically 110) are a compromise. With coventional linear terminators as the line voltage increases the amount of current decreases linearly by the equation;
Disable /Sleep Mode
The IMP5111 has an active LOW disconnect pin, and the IMP5112 has an active HIGH disconnect pin. The disable mode is entered if the disconnect pin on either device is left open. When disabled the termination lines are in a high impedance state, and the power supply current drops to 275A typically. The disable mode can be used to save power or completely eliminate the terminator from the SCSI bus. Disabled terminators appear as distributed capacitance on the bus. The IMP5111/5112 have been optimized to have only 3pF of capacitance per output when in the disabled mode. The IMP5111/5112 are compatible with active negation drivers. The devices will handle up to 60mA of sink current for drivers which exceed the 2.85V output high level.
(VREF - VLINE) = I.
R The IMP5111/5112, with their unique architecture, applies the maximum amount of current regardless of line voltage until the termination high threshold (2.85V) is reached.
Table 1. Power Up/ Power Down Function Table
IMP5111 DISCONNECT
H L Open
IMP5112 DISCONNECT
L H Open
Outputs
Enabled Disabled/High Impedance Disabled/High Impedance
Quiescent Current
6mA 275A 275A
5111/5112_t04a.eps
4
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IMP51 1 1/51 1 2
Package Dimensions
SO (16-Pin)
Inches Min
A A1 B C D E
M A C e B A1 L
16-Pin (SO).eps
Millimeters Max SO (16-Pin)*
0.069 0.010 0.018 0.010 0.394 0.158 0.244 0.050 8 0.041 0.012 0.0071 0.311 0.176
Min
1.35 0.10 0.35 0.19 9.78 3.81 5.79 0.40 0 0.80 0.19 0.09 7.70 4.30 0.05 -- 0.50 0 6.25
Max
1.75 0.25 0.46 0.25 10.01 4.01 1.27 BSC 6.20 1.27 8 1.05 0.30 0.180 7.90 4.48 0.65 BSC 0.15 1.10 0.70 8 6.50
5111/5112_t06.at3
E
H
0.053 0.004 0.014 0.007 0.385 0.150 0.228 0.016 0 0.032 0.007 0.0035 0.303 0.169
D
e H L M A B C D E F
0.050 BSC
TSSOP (24-Pin)
TSSOP (24-Pin)
0.025 BSC
E
P
123
D F AH SEATING PLANE B G L
E
G 0.002 0.005 0.0433 -- H L 0.020 0.028 M 0 8 P 0.246 0.256 * JEDEC Drawing MS-012AC
M C
24-Pin (TSSOP).eps
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Data Communications
5
IMP51 1 1/51 1 2
Daily Silver IMP Microelectronics Co.,Ltd 7 Keda Road , Hi-Tech Park, NingBo,Zhejiang, P.R.C. Post Code : 315040 Tel:(086)-574-87906358 Fax:(086)-574-87908866 e-mail:sales@ds-imp.com.cn http://www.ds-imp.com.cn
The IMP logo is a registered trademark of Daily Silver IMP. All other company and product names are trademarks of their respective owners.
2005 Daily Silver IMP Revision : A Issue Date: 08 / 08 / 05 Type: Product

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