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| FDMS9620S Dual N-Channel PowerTrench(R) MOSFET July 2007 FDMS9620S Dual N-Channel PowerTrench(R) MOSFET Q1: 30V, 16A, 21.5m Q2: 30V, 18A, 13m Features Q1: N-Channel Max rDS(on) = 21.5m at VGS = 10V, ID = 7.5A Max rDS(on) = 29.5m at VGS = 4.5V, ID = 6.5A Q2: N-Channel Max rDS(on) = 13m at VGS = 10V, ID = 10A Max rDS(on) = 17m at VGS = 4.5V, ID = 8.5A Low Qg high side MOSFET Low rDS(on) low side MOSFET Thermally efficient dual Power 56 package Pinout optimized for simple PCB design RoHS Compliant tm General Description This device includes two specialized MOSFETs in a unique dual Power 56 package. utilization. It is designed to provide an optimal Synchronous Buck power stage in terms of efficiency and PCB The low switching loss "High Side" MOSFET is complemented by a Low Conduction Loss "Low Side" SyncFET. Applications Synchronous Buck Converter for: Notebook System Power General Purpose Point of Load G1 D1 S1/D2 G2 S2 S2 S2 D1 D1 D1 S2 S2 S2 G2 5 6 7 8 4 3 2 1 D1 D1 D1 G1 Power 56 MOSFET Maximum Ratings TA = 25C unless otherwise noted Symbol VDS VGS Parameter Drain to Source Voltage Gate to Source Voltage Drain Current ID -Continuous (Package limited) TC = 25C -Continuous (Silicon limited) -Continuous -Pulsed PD TJ, TSTG Power Dissipation for Single Operation TA = 25C TA = 25C Operating and Storage Junction Temperature Range (Note 1a) (Note 1b) TC = 25C TA = 25C (Note 1a) Q1 30 20 16 21 7.5 60 2.5 1 -55 to +150 Q2 30 20 18 44 10 60 W C A Units V V Thermal Characteristics RJC RJA RJA Thermal Resistance, Junction to Case Thermal Resistance, Junction to Ambient Thermal Resistance, Junction to Ambient (Note 1a) (Note 1b) 8.2 50 120 3.1 C/W Package Marking and Ordering Information Device Marking FDMS9620S Device FDMS9620S Package Power 56 Reel Size 13" Tape Width 12mm Quantity 3000 units (c)2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 1 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench(R) MOSFET Electrical Characteristics TJ = 25C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Off Characteristics BVDSS BVDSS TJ IDSS IGSS Drain to Source Breakdown Voltage Breakdown Voltage Temperature Coefficient Zero Gate Voltage Drain Current Gate to Source Leakage Current ID = 250A, VGS = 0V ID = 1mA, VGS = 0V ID = 250A, referenced to 25C ID = 1mA, referenced to 25C VDS = 24V, VGS = 0V VGS = 20V, VDS= 0V Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 30 30 23 23 1 500 100 100 V mV/C A nA On Characteristics VGS(th) VGS(th) TJ Gate to Source Threshold Voltage Gate to Source Threshold Voltage Temperature Coefficient VGS = VDS, ID = 250A VGS = VDS, ID = 1mA ID = 250A, referenced to 25C ID = 1mA, referenced to 25C VGS = 10V, ID = 7.5A VGS = 4.5V, ID = 6.5A VGS = 10V, ID = 7.5A , TJ = 125C VGS = 10V, ID = 10A VGS = 4.5V, ID = 8.5A VGS = 10V, ID = 10A , TJ = 125C VDD = 10V, ID = 7.5A VDD = 10V, ID = 10A Q1 Q2 Q1 Q2 Q1 1 1 1.6 1.6 -4 -4 18 23 25 9 13 14 25 27 21.5 29.5 32 13 17 22 3 3 V mV/C rDS(on) Drain to Source On Resistance m Q2 Q1 Q2 gFS Forward Transconductance S Dynamic Characteristics Ciss Coss Crss Rg Input Capacitance Output Capacitance Reverse Transfer Capacitance Gate Resistance f = 1MHz VDS = 15V, VGS = 0V, f = 1MHZ Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 500 700 100 500 65 100 0.9 1.8 665 935 135 665 100 150 pF pF pF Switching Characteristics td(on) tr td(off) tf Qg Qgs Qgd Turn-On Delay Time Rise Time Turn-Off Delay Time Fall Time Total Gate Charge Gate to Source Gate Charge Gate to Drain "Miller" Charge Q1 VDD = 15V, VGS = 10V ,ID = 7.5A Q2 VDD = 15V, VGS = 10V ,ID = 10A VDD = 15V, ID = 1A, VGS = 10V, RGEN = 6 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 11 15 7 13 23 27 2.3 7 10 18 1.7 2.8 2.0 3.6 20 27 14 24 37 44 10 14 14 25 ns ns ns ns nC nC nC (c)2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 2 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench(R) MOSFET Electrical Characteristics TJ = 25C unless otherwise noted Symbol Parameter Test Conditions Type Min Typ Max Units Drain-Source Diode Characteristics IS VSD trr Qrr Maximum Continuous Drain-Source Diode Forward Current Source to Drain Diode Forward Voltage Reverse Recovery Time Reverse Recovery Charge VGS = 0V, IS = 2.1A VGS = 0V, IS = 3.5A Q1 IF = 7.5A, di/dt = 100A/s Q2 IF = 10A, di/dt = 300A/s (Note 2) (Note 2) Q1 Q2 Q1 Q2 Q1 Q2 Q1 Q2 0.7 0.5 13 14 4 9 2.1 3.5 1.2 1.0 A V ns nC Notes: 1: RJA is determined with the device mounted on a 1in2 pad 2 oz copper pad on a 1.5 x 1.5 in. board of FR-4 material. RJC is guaranteed by design while RCA is determined by the user's board design. b. 120C/W when mounted on a minimum pad of 2 oz copper a.50C/W when mounted on a 1 in2 pad of 2 oz copper 2: Pulse Test: Pulse Width < 300s, Duty cycle < 2.0%. (c)2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 3 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench(R) MOSFET Typical Characteristics (Q1 N-Channel)TJ = 25C unless otherwise noted 60 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE VGS = 10V 2.8 VGS = 6V VGS = 4.5V VGS = 4V 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0 10 20 VGS =3.5V VGS = 4V 50 ID, DRAIN CURRENT (A) PULSE DURATION = 300s DUTY CYCLE = 2.0%MAX 40 30 20 10 0 0 VGS = 4.5V VGS = 6V VGS = 3.5V PULSE DURATION = 300s DUTY CYCLE = 2.0%MAX VGS = 10V 1 2 3 4 30 40 50 60 VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT(A) Figure 1. On Region Characteristics Figure 2. Normalized On-Resistance vs Drain Current and Gate Voltage 70 SOURCE ON-RESISTANCE (m) 1.6 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.5 1.4 ID = 7.5A VGS =10V 60 50 40 ID = 3.8A PULSE DURATION = 300s DUTY CYCLE = 2.0%MAX 1.2 1.1 1.0 0.9 0.8 0.7 -50 -25 0 25 50 75 100 125 150 rDS(on), DRAIN TO 1.3 TJ = 125oC 30 20 TJ = 25oC 10 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC) Figure 3. Normalized On Resistance vs Junction Temperature 40 IS, REVERSE DRAIN CURRENT (A) PULSE DURATION = 300s DUTY CYCLE = 2.0%MAX Figure 4. On-Resistance vs Gate to Source Voltage 60 VGS = 0V ID, DRAIN CURRENT (A) 10 TJ = 125oC 30 VDD = 5V 1 20 TJ =125oC 0.1 TJ = 25oC 10 TJ = 25oC TJ = -55oC 0.01 TJ = -55oC 0 1 2 3 4 VGS, GATE TO SOURCE VOLTAGE (V) 5 1E-3 0.2 0.4 0.6 0.8 1.0 1.2 1.4 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 5. Transfer Characteristics Figure 6. Source to Drain Diode Forward Voltage vs Source Current (c)2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 4 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench(R) MOSFET Typical Characteristics (Q1 N-Channel)TJ = 25C unless otherwise noted 10 VGS, GATE TO SOURCE VOLTAGE(V) ID = 7.5A VDD =10V CAPACITANCE (pF) 1000 8 Ciss 6 4 2 0 0 2 4 6 8 VDD = 15V Coss VDD = 20V 100 f = 1MHz VGS = 0V Crss 10 12 30 0.1 1 10 30 Qg, GATE CHARGE(nC) VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 7. Gate Charge Characteristics Figure 8. Capacitance vs Drain to Source Voltage 100 P(PK), PEAK TRANSIENT POWER (W) 100 VGS = 10V ID, DRAIN CURRENT (A) 10 1 SINGLE PULSE TJ = MAX RATE RJA = 120oC TA = 25oC 1ms 10ms 100ms 1s 10s DC 10 SINGLE PULSE RJA = 120 C/W o 0.1 THIS AREA IS LIMITED BY rDS(ON) 1 0.5 -3 10 TA= 25 C o 0.01 0.1 1 10 100 10 -2 10 -1 10 0 10 1 10 2 10 3 VDS, DRAIN to SOURCE VOLTAGE (V) t, PULSE WIDTH (s) Figure 9. Forward Bias Safe Operating Area 2 Figure 10. Single Pulse Maximum Power Dissipation 1 NORMALIZED THERMAL IMPEDANCE, ZJA DUTY CYCLE-DESCENDING ORDER 0.1 D = 0.5 0.2 0.1 0.05 0.02 0.01 PDM t1 t2 SINGLE PULSE RJA = 120 C/W o NOTES: DUTY FACTOR: D = t1/t2 PEAK TJ = PDM x ZJA x RJA + TA 0.01 -3 10 10 -2 10 -1 10 0 10 1 10 2 10 3 t, RECTANGULAR PULSE DURATION (s) Figure 11. Transient Thermal Response Curve (c)2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 5 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench(R) MOSFET Typical Characteristics (Q2 SyncFET) 60 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 2.8 VGS = 10V VGS = 4.5V VGS = 4V 2.6 2.4 2.2 2.0 1.8 1.6 1.4 1.2 1.0 0.8 0 50 ID, DRAIN CURRENT (A) VGS =3.5V PULSE DURATION = 300s DUTY CYCLE = 2.0%MAX 40 30 20 10 0 0.0 VGS = 6V VGS = 3.5V VGS = 4V VGS = 4.5V VGS = 6V PULSE DURATION = 300s DUTY CYCLE = 2.0%MAX VGS = 10V 0.5 1.0 1.5 2.0 2.5 10 20 30 40 50 60 VDS, DRAIN TO SOURCE VOLTAGE (V) ID, DRAIN CURRENT(A) Figure 12. On-Region Characteristics Figure 13. Normalized on-Resistance vs Drain Current and Gate Voltage 60 SOURCE ON-RESISTANCE (m) 1.8 NORMALIZED DRAIN TO SOURCE ON-RESISTANCE 1.6 1.4 1.2 1.0 0.8 0.6 -50 ID = 10A VGS =10V rDS(on), DRAIN TO 50 40 30 ID = 5A PULSE DURATION = 300s DUTY CYCLE = 2.0%MAX TJ = 125oC 20 10 TJ = 25oC -25 0 25 50 75 100 125 150 0 2 4 6 8 10 VGS, GATE TO SOURCE VOLTAGE (V) TJ, JUNCTION TEMPERATURE (oC) Figure 14. Normalized On-Resistance vs Junction Temperature Figure 15. On-Resistance vs Gate to Source Voltage 60 50 40 30 20 10 0 1 2 3 4 5 VGS, GATE TO SOURCE VOLTAGE (V) TJ =125oC TJ = 25oC TJ = -55oC IS, REVERSE DRAIN CURRENT (A) 10 PULSE DURATION = 300s DUTY CYCLE = 2.0%MAX VGS = 0V ID, DRAIN CURRENT (A) VDD = 5V 1 TJ = 125oC 0.1 TJ = 25oC 0.01 TJ = -55oC 0.001 0.0 0.2 0.4 0.6 0.8 VSD, BODY DIODE FORWARD VOLTAGE (V) Figure 16. Transfer Characteristics Figure 17. Source to Drain Diode Forward Voltage vs Source Current (c)2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 6 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench(R) MOSFET Typical Characteristics 10 VGS, GATE TO SOURCE VOLTAGE(V) 2000 ID = 10A VDD =10V CAPACITANCE (pF) 8 6 4 2 0 0 4 8 12 16 20 Qg, GATE CHARGE(nC) 1000 Ciss VDD = 15V Coss VDD = 20V 100 50 0.1 f = 1MHz VGS = 0V Crss 1 10 30 VDS, DRAIN TO SOURCE VOLTAGE (V) Figure 18. Gate Charge Characteristics Figure 19. Capacitance vs Drain to Source Voltage (c)2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 7 www.fairchildsemi.com FDMS9620S Dual N-Channel PowerTrench(R) MOSFET Dimensional Outline and Pad Layout (c)2007 Fairchild Semiconductor Corporation FDMS9620S Rev.D2 8 www.fairchildsemi.com TRADEMARKS The following are registered and unregistered trademarks and service marks Fairchild Semiconductor owns or is authorized to use and is not intended to be an exhaustive list of all such trademarks. ACEx(R) Build it NowTM CorePLUSTM CROSSVOLTTM CTLTM Current Transfer LogicTM EcoSPARK(R) Fairchild(R) Fairchild Semiconductor(R) FACT Quiet SeriesTM FACT(R) FAST(R) FastvCoreTM FPSTM FRFET(R) Global Power ResourceSM Green FPSTM Green FPSTM e-SeriesTM GTOTM i-LoTM IntelliMAXTM ISOPLANARTM MegaBuckTM MICROCOUPLERTM MicroFETTM MicroPakTM Motion-SPMTM OPTOLOGIC(R) OPTOPLANAR(R) (R) PDP-SPMTM Power220(R) Power247(R) POWEREDGE(R) Power-SPMTM PowerTrench(R) Programmable Active DroopTM QFET(R) QSTM QT OptoelectronicsTM Quiet SeriesTM RapidConfigureTM SMART STARTTM SPM(R) STEALTHTM SuperFETTM SuperSOTTM-3 SuperSOTTM-6 SuperSOTTM-8 SyncFETTM The Power Franchise(R) TinyBoostTM TinyBuckTM TinyLogic(R) TINYOPTOTM TinyPowerTM TinyPWMTM TinyWireTM SerDesTM UHC(R) UniFETTM VCXTM DISCLAIMER FAIRCHILD SEMICONDUCTOR RESERVES THE RIGHT TO MAKE CHANGES WITHOUT FURTHER NOTICE TO ANY PRODUCTS HEREIN TO IMPROVE RELIABILITY, FUNCTION, OR DESIGN. FAIRCHILD DOES NOT ASSUME ANY LIABILITY ARISING OUT OF THE APPLICATION OR USE OF ANY PRODUCT OR CIRCUIT DESCRIBED HEREIN; NEITHER DOES IT CONVEY ANY LICENSE UNDER ITS PATENT RIGHTS, NOR THE RIGHTS OF OTHERS. THESE SPECIFICATIONS DO NOT EXPAND THE TERMS OF FAIRCHILD'S WORLDWIDE TERMS AND CONDITIONS, SPECIFICALLY THE WARRANTY THEREIN, WHICH COVERS THESE PRODUCTS. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in significant injury to the user. 2. A critical component is any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. PRODUCT STATUS DEFINITIONS Definition of Terms Datasheet Identification Advance Information Product Status Formative or In Design Definition This datasheet contains the design specifications for product development. Specifications may change in any manner without notice. This datasheet contains preliminary data; supplementary data will be published at a later date. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains final specifications. Fairchild Semiconductor reserves the right to make changes at any time without notice to improve design. This datasheet contains specifications on a product that has been discontinued by Fairchild semiconductor. The datasheet is printed for reference information only. Rev. I30 Preliminary First Production No Identification Needed Full Production Obsolete Not In Production |
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