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Dual-Phase Single or Two Output Synchronous Step-Down Controllers
POWER MANAGEMENT Description
The SC2446 is a high-frequency dual synchronous stepdown switching power supply controller. It provides outof-phase high-current output gate drives to all N-channel MOSFET power stages. The SC2446 operates in synchronous continuous-conduction mode. Both phases are capable of maintaining regulation with sourcing or sinking load currents, making the SC2446 suitable for generating both VDDQ and the tracking VTT for DDR applications. The SC2446 employs fixed frequency peak current-mode control for the ease of frequency compensation and fast transient response. The dual-phase step-down controllers of the SC2446 can be configured to provide two individually controlled and regulated outputs or a single output with shared current in each phase. The Step-down controllers operate from an input of at least 4.7V and are capable of regulating outputs as low as 0.5V The step-down controllers in the SC2446 have the provision to sense a synthesized MOSFET RDS(ON) for current-mode control. This sensing scheme (U.S. patent 6,441,597) eliminates the need of the current-sense resistor and is more noise-immune than direct sensing of the high-side or the low-side MOSFET voltage. Precise current-sensing with sense resistor is optional. Individual soft-start and overload shutdown timer is included in each step-down controller. The SC2446 implements hiccup overload protection. In two-phase singleoutput configuration, the master timer controls the softstart and overload shutdown functions of both controllers.
SC2446
Features
2-Phase synchronous continuous conduction mode for high efficiency step-down converters Out of phase operation for low input current ripples Output source and sink currents Fixed frequency peak current-mode control 75mV/-110mV maximum current sense voltage Synthesized MOSFET RDS(ON) current-sensing for low-cost applications Optional resistor current-sensing for precise currentlimit Dual outputs or 2-phase single output operation Excellent current sharing between individual phases Wide input voltage range: 4.7V to 16V Individual soft-start, overload shutdown and enable Duty cycle up to 88% 0.5V feedback voltage for low-voltage outputs External reference input for DDR applications Buffered VDDQ/2 output Programmable frequency up to 1 MHz per phase External synchronization Industrial temperature range 28-lead TSSOP - EDP package
Applications
Telecommunication power supplies DDR memory power supplies Graphic power supplies Servers and base stations
Typical Application Circuit
VIN
C92 D11
PVCC
D12
Q21
VO2
C99 + R79 C96 C95
R73 C93
BST2 GDH2
BST1 GDH1
R74 C94
Q22 L12 Q24 C98 + R76 C97 R80
L11 Q23
VO1
C100
CFILTER R75 RFILTER
R77
GDL2 GDL1 PGND VPN2 CS2+ VPN1 CS1+ CS1IN1COMP1 REF AGND Rosc AVCC REFOUT
R78
CFILTER RFILTER
RCS+ RCS-
RCS+ RCS-
R81 C101 R83 C103
CS2IN2COMP2
R82 C102
REF VIN SYNC
REFIN VIN2 SYNC SS1/EN1 SS2/EN2
C104
C105
R84
R85 VIN
C106
C107
Figure 1
Revision: September 9, 2004
SC2446
Dual Independant Outputs
U1
C108
C109
1
U.S. Patent No. 6,441,597, www.semtech.com
SC2446
POWER MANAGEMENT Absolute Maximum Rating
Exceeding the specifications below may result in permanent damage to the device, or device malfunction. Operation outside of the parameters specified in the Electrical Characteristics section is not implied.
Parameter Supply Voltage For Step-D own C ontrollers Input Voltage For the Second C onverter Hi gh-Si de D ri ver Supply Voltages
Symbol AVC C , PVC C VIN2 VBST1,VBST2
Maximum R atings -0.3 to 20 -0.3 to 20 -0.3 to 32 (steady state) -0.3 to 40 (for <10ns @ freq. < 500kHz) -0.3 to 20 (steady state) -0.3 to 26 (for <10ns @ freq. < 500kHz) -0.3 to AVC C +0.3 -0.3 to 6 -0.3 to AVC C +0.3 -0.3 to AVC C +0.3 -0.3 to AVC C +0.3 -0.3 to AVC C +0.3 -0.3 to 6 3 100 -40 to 85 13 84 -60 to 150 260 150
U nits V V V
VPN V VPN IN1-, IN2- Voltages REF, REFOUT Voltages REFIN Voltage C OMP1, C OMP2 Voltages C S1+, C S1-, C S2+ and C S2- Voltages SYNC Voltage SS1/EN1 AND SS2/EN2 Voltages Peak Gate D ri ve C urrents Peak VPN1 and VPN2 Output C urrents Ambi ent Temperature Range Thermal Resi stance Juncti on to C ase (TSSOP-28) Thermal Resi stance Juncti on to Ambi ent (TSSOP-28) Storage Temperature Range Lead Temperature (Solderi ng) 10 sec Maxi mum Juncti on Temperature VIN1-,VIN2VREF ,VREFOUT VREFIN VCOMP1,VCOMP2 VCS1+,VCS1-,VCS2+,VCS2VSYNC VSS1,VSS2 IGDH1, IGDH2, IGDL1, IGDL2 IVPN1, IVPN2 TA J C J A TSTG TLEAD TJ
V V V V V V V V A mA C C /W C /W C C C
Electrical Characteristics
Unless specified: AVCC = PVCC = VIN2 =12V, VBST1 = VBST2 = 12V, SYNC= 0, ROSC = 51.1k, -40C < TA = TJ < 85C
Parameter Undervoltage Lockout AVCC Start Threshold AVCC Start Hysteresis AVCC Operating Current AVCC Quiescent Current in UVLO Channel 1 Error Amplifier Non-inverting Input Voltage Non-inverting Input Line Regulation Input Offset Voltage Inverting Input Bias Current Amplifier Transconductance Amplifier Open-Loop Gain Amplifier Unity Gain Bandw idth Minimum COMP1 Sw itching Threshold
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Symbol
Conditions
Min
Typ
Max
Units
AVCCTH AVCCHYST ICC
AVCC Increasing
4.5 0.17
4.7
V V
AVCC= 12V AVCC = AVCCTH - 0.2V
12 1.7 0.490 0.500 1
16
mA mA
VIN1+ AVCCTH < AVCC< 15V IIN1G M1 aOL1 VCS1+ = VCS1- = 0 VSS1 Increasing
2
0.510 0.02 3 -250
V %/ V mV nA -1 d z V
-100 260 65 5 2.2
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SC2446
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: AVCC = PVCC = VIN2 =12V, VBST1 = VBST2 = 12V, SYNC= 0, ROSC = 51.1k, -40C < TA = TJ < 85C
Parameter Amplifier Output Sink Current Amplifier Output Source Current Channel 2 Error Amplifier Input Common-mode Voltage Range Inverting Input Voltage Range Input Offset Voltage Non-inverting Input Bias Current Inverting Input Bias Current Inverting Input Voltage for 2-Phase Single Output Operation Amplifier Transconductance Amplifier Open-Loop Gain Amplifier Unity Gain Bandwidth Minimum COMP2 Switching Threshold Amplifier Output Sink Current Amplifier Output Source Current Oscillator Channel Frequency Synchronizing Frequency SY NC Input High Voltage SY NC Input Low Voltage SY NC Input Current Channel Maximum Duty Cycle Channel Minimum Duty Cycle Current-limit Comparators Input Common-Mode Range Cycle-by-cycle Peak Current Limit Valley Current Overload Shutdown Threshold Positive Current-Sense Input Bias Current Negative Current-Sense Input Bias Current Gate Drivers High-side Gate Drive Peak Source Current High-side Gate Drive Peak Sink Current
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Symbol
Conditions VIN1- = 1V, VCOMP1 = 2.5V VIN1- = 0, VCOMP1 = 2.5V (Note 1) (Note 1)
Min
Typ 16 12
Max
Units A A
0 0 1.5 -150 -100 2.5
3 AVCC 3 -380 -250
V V mV nA nA V
IIN2+ IIN2-
G M2 aOL2 VCS2+ = VCS2- = 0 VSS2 Increasing VCOMP2 = 2.5V VCOMP2 = 2.5V fCH1, fCH2 (Note 1) 450 2.1fCH 1.5
260 65 5 2.2 16 12 500 550
-1 d MHz V A A KHz KHz V 0.5 V A % 0 % V mV mV A A 1 100
ISYNC DMAX1, DMAX2 DMIN1, DMIN2
VSYNC = 0.2V VSYNC = 2V 88
0 VILIM1+, VILIM2+ VILIM1-, VILIM2ICS1+, ICS2+ ICS1-, ICS2VCS1- = VCS2- = 0.5V, Sourcing Mode VCS1- = VCS2- = 0.5V, Sinking Mode VCS1+ = VCS1- = 0 VCS2- = VCS2- = 0 VCS1+ = VCS1- = 0 VCS2+ = VCS2- = 0 60 -85 75 -110 -0.7 -0.7
AVCC - 1 90 -130 -2 -2
VBST1 ,VBST2 = 12V VBST1 ,VBST2 = 12V
3
1.5 1
A A
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SC2446
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: AVCC = PVCC = VIN2 =12V, VBST1 = VBST2 = 12V, SYNC= 0, ROSC = 51.1k, -40C < TA = TJ < 85C
Parameter Low-side Gate Drive Peak Source Current Low-side Gate Drive Peak Sink Current Gate Drive Rise Time Gate Drive Fall Time Low-side Gate Drive to High-side Gate Drive Non-overlapping Delay High-side Gate Drive to Low-side Gate Drive Non-overlapping Delay Minimum On-Time Soft-Start, Overload Latchoff and Enable Soft-Start Charging Current Overload Latchoff Enabling Soft-Start Voltage Overload Latchoff IN1- Threshold Overload Latchoff IN2- Threshold Soft-Start Discharge Current Overload Latchoff Recovery Soft-Start Voltage Gate Drive Disable SS/EN Voltage Gate Drive Enable SS/EN Voltage Channel 1 Virtual Phase Node Voltage Output High Voltage Output Low Voltage Output Sourcing Current Output Sinking Current Channel 2 Virtual Phase Node Voltage Output High Voltage Output Low Voltage Output Sourcing Current Output Sinking Current External Reference Buffer External Reference Input Voltage Range Buffered Output Voltage
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Symbol
Conditions AVCC = PVCC =12V AVCC = PVCC =12V CL = 2200pF CL = 2200pF CL = 0 CL = 0 TA = 25C
Min
Typ 1.5 1 20 20 90 90 150
Max
Units A A ns ns ns ns ns
ISS1, ISS2
VSS1 = VSS2 = 1.5V VSS1 and VSS2 Increasing VSS1 = 3.8V, VIN1-Decreasing VSS2 = 3.8V, VIN2-Decreasing
2 3.2 0.75VREF 0.72 X VREFIN 1.4 0.3 0.7 0.5 0.9 1.2 1.5 0.7
A V V V A V V V
ISS1(DIS), ISS2(DIS) VSSRCV1, VSSRCV2
VIN1-= 0.5VREF, VIN2-= 0.5VREFIN , VSS1 = VSS2 = 3.8V VSS1 and VSS2 Decreasing
VVPN1H VVPN1L
IVPN1= -100A, VBST1= 24V IVPN1= 100A, VBST1= 24V VBST1= 24V, VVPN1= VPVCC - 0.2V VBST1= 24V, VVPN1= 0.2V IVPN2= -100A, VBST2= 24V IVPN2= 100A, VBST2= 24V VBST2= 24V, VVPN2= VIN2 - 0.2V VBST2= 24V, VVPN2= 0.2V
VPVCC-0.05 20 7 7
V mV mA mA
VVPN2H VVPN2L
VIN2 - 0.05 20 7 7
V mV mA mA
VREFIN VREFOUT VREFIN=1.25V, IREFOUT= -1mA
4
0 VREFIN -0.01 VREFIN
4 VREFIN +0.01
V V
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SC2446
POWER MANAGEMENT Electrical Characteristics (Cont.)
Unless specified: AVCC = PVCC = VIN2 =12V, VBST1 = VBST2 = 12V, SYNC= 0, ROSC = 51.1k, -40C < TA = TJ < 85C
Parameter Load Regulation Internal 0.5V Reference Buffer Output Voltage Load Regulation
Symbol
Conditions 0 < IREFOUT < -5mA
Min
Typ 0.02
Max
Units %/mA
VREF
IREF= -1mA 0 < IREF < -5mA
490
500 0.05
510
mV %/mA
Notes: (1) Guaranteed by design not tested in production. (2) This device is ESD sensitive. Use of standard ESD handling precautions is required.
Pin Configurations
(TOP VIEW)
CS1+ CS1ROSC IN1COMP1 SYNC AGND REF REFOUT REFIN COMP2 IN2CS2CS2+ SS1/EN1 VPN1 BST1 GDH1 GDL1 PVCC PGND GDL2 GDH2 BST2 VPN2 VIN2 AVCC SS2/EN2
Ordering Information
Device SC2446ITETRT(2) S C 2446E V B Package(1) TSSOP-28-EDP Evaluation Board Temp. Range( TA) -40 to 85C
Notes: (1) Only available in tape and reel packaging. A reel contains 2500 devices for TSSOP package. (2) Lead free product.
(28-Pin TSSOP) Figure 2
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SC2446
POWER MANAGEMENT Pin Descriptions
TSSOP Package
Pin 1 2 3 4 5 Pin Name CS1+ CS1ROSC IN1COMP1 Pin Function The Non-inverting Input of the Current-sense Amplifier/Comparator for the Controller 1. The Inverting Input of the Current-sense Amplifier/Comparator for the Controller 1. Normally tied to the output of the converter. An external resistor connected from this pin to GND sets the oscillator frequency. Inverting Input of the Error Amplifier for the Step-down Controller 1. Tie an external resistive divider between OUTPUT1 and the ground for output voltage sensing. The Error Amplifier Output for Step-down Controller 1. This pin is used for loop compensation. Edge-triggered Synchronization Input. When not synchronized, tie this pin to a voltage above 1.5V or the ground. An external clock (frequency > frequency set with ROSC) at this pin synchronizes the controllers. Analog Signal Ground. Buffered Output of the Internal 0.5V Reference. The non-inverting input of the error amplifier for the step-down converter 1 is internally connected to this pin . Buffered output of the external voltage applied to Pin 10. An external Reference voltage is applied to this pin.The non-inverting input of the error amplifier for the step-down converter 2 is internally connected to this pin. The Error Amplifier Output for Step-down Controller 2. This pin is used for loop compensation. Inverting Input of the Error Amplifier for the Step-down Controller 2. Tie an external resistive divider between output2 and the ground for output voltage sensing. Tie to AVCC for two-phase single output applications The Inverting Input of the Current-sense Amplifier/Comparator for the Controller 2. Normally tied to the output of the converter. The Non-inverting Input of the Current-sense Amplifier/Comparator for the Controller 2 An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off time for step-down converter 2. Pulling this pin below 0.7V shuts off the gate drivers for the second controller. Leave open for two-phase single output applications. Power Supply Voltage for the Analog Portion of the Controllers. This pin is tied to the voltage supplying the drain of the high side power MOSFET of converter 2. This pin is used only in "Combi" current sense. The Second Step-down Converter Virtual Phase Node (Unloaded). Used for "Combi" current sense only. This pin is left open when sensing current with a sense resistor at the converter output. Bootstrapped Supply for the High-side Gate Drive 2. Connect to a bootstrap capacitor and an external diode as described in application information. Gate Drive Output for the High-side N-channel MOSFET of Output 2. Gate drive voltage swings from ground to VBST2.
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6 7 8 9 10 11
SY NC AGND REF REFOUT REFIN COMP2
12
IN2-
13 14 15 16 17
CS2CS2+ SS2/EN2 AVCC VIN2
18
VPN2
19 20
BST2 GDH2
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SC2446
POWER MANAGEMENT Pin Descriptions
Pin 21 22 23 24 25 26 Pin Name GDL2 PGND PVCC GDL1 GDH1 BST1 Pin Function Gate Drive Output for the Low-side N-channel MOSFET of Output 2. Gate drive voltage swings from ground to PVCC. Ground Supply for All the Gate drivers. Power Supply Voltage for Low-side MOSFET Drivers. Gate Drive Output for the Low-side N-channel MOSFET of Output 1. Gate drive voltage swings from ground to PVCC. Gate Drive Output for the High-side N-channel MOSFET of Output 1. Gate drive voltage swings from ground to VBST1. Bootstrapped Supply for the High-side Gate Drive 1. Connect to a bootstrap capacitor and an external diode as described in application information. The First Step-down Converter Virtual Phase Node (Unloaded). Used for "Combi" current sense only. This pin is left open when sensing current with a sense resistor at the converter output. An external capacitor tied to this pin sets (i) the soft-start time (ii) output overload latch off time for buck converter 1. Pulling this pin below 0.7V shuts off the gate drivers for the first controller.
27
VPN1
28
SS1/EN1
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SC2446
POWER MANAGEMENT Block Diagram
SYNC 6 ROSC 3 COMP1 5 IN14 REF/IN1+ 8 OSCILLATOR AVCC 16 UVLO 4.3/4.5V BST1 26 GDH1 25
CLK2 CLK1 REFERENCE
EA1 + + 0.5V
PWM +
R S Q
Non-Overlapping Conduction Control
UVLO
PVCC 23 GDL1 24 VPN1 27 PGND 22 SS1/EN1 28 GDH2 20
CS1+ 1 CS12
+ISEN +ILIM+ 75mV 110mV
++
SLOPE COMP
0.75 VREF
Soft-Start And Overload Hiccup Control
OL DSBL
COMP2 11 IN212 REFIN/IN2+ 10 REFOUT 9 AGND 7
ILIM+ EA2 + + -
OCN
VIN2 17 VPN2 18 GDL2 21
0.72 VREFOUT
Figure 3. SC2446 Block Diagram (Channel 1 PWM Control Only)
OCN
IN0.75(VREF) / 0.72(VREFOUT) SS/EN
+ 2
S Q R 0.5V/3.2V OL
DSBL UVLO 0.9V/1.2V
3 .4
Figure 4. Soft-Start and Overload Hiccup Control Circuit
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SC2446
POWER MANAGEMENT Operation
Overview The SC2446 is a constant frequency 2-phase currentmode step-down PWM switching controller driving all Nchannel MOSFET's. The two channels of the controller operate at 180 degrees out of phase from each other. Since input currents are interleaved in a two-phase converter, input ripple current is lower and smaller input capacitor can be used for filtering. Also, with lower inductor current and smaller inductor ripple current per phase, overall I2R losses are reduced. The SC2446 operates in synchronous continuousconduction mode. It can be configured either as two independent step-down controllers producing two separate outputs or as a dual-phase single-output controller by tying the IN2- pin to VCC. In single output operation, the channel one error amplifier controls both channels and the channel two error amplifier is disabled. Soft-start and overload hiccup of both channels is synchronized to channel one. Frequency Setting and Synchronization The internal oscillator of the SC2446 runs at twice the phase frequency. The free-running frequency of the oscillator can be programmed with an external resistor from the ROSC pin to the ground. The step-down controllers are capable of operating up to 1 MHz. It is necessary to consider the operating duty-ratio before deciding the switching frequency. See Applications Information section for more details. When synchronized externally, the applied clock frequency should be twice the desired phase frequency. The synchronizing clock frequency should also be between 11.33 times the set free-running frequency. Control Loop The SC2446 uses peak current-mode control for fast transient response, ease of compensation and current sharing in single output operation. The low-side MOSFET of each channel is turned off at the falling-edge of the phase timing clock. After a brief non-overlapping time interval of 90ns, the high-side MOSFET is turned on. The phase inductor current ramps up. When the sensed inductor current reaches the threshold determined by the error amplifier output and ramp compensation, the high-side MOSFET is turned off. After a non-overlapping conduction time of 90ns, the low-side MOSFET is turned on. The supply voltages for the high-side gate drivers are obtained from two diode-capacitor bootstrap circuits. If the bootstrap capacitor is charged from VCC, the high-side gate drive voltage swing will be from approximately 2VCC to the ground. The power dissipated in the high-side gate driver is not higher with higher voltage swing because the gatesource voltage of the high-side MOSFET still swing from zero to VCC.The outputs of the low-side gate drivers swing from VC to the ground. The SC2446 has internal ramp-compensation to prevent sub-harmonic oscillation when operating above 50% duty cycle. There is enough ramp internally for a sensed voltage ripple between 1/4 to 1/3 of the full-scale sensed voltage limit of 75mV. The maximum sensed voltage limit is unaffected by the compensation ramp. Current-Sensing There are two ways to sense the inductor current for current-mode control with the SC2446. Since the peak inductor current corresponds to 75mV of sensed voltage (CS+ - CS-), resistor current sensing can be used at the output without resulting in excessive power dissipation. Although accurate and far easier to lay out than highside resistor sensing, a pair of precision sense resistors adds cost to the converter. The SC2446 has provision to reconstruct a differential voltage proportional to the inductor current at the output of the converter (U.S. patent 6,441,597). The voltage to current ratio or the equivalent sense resistance Req is a combination of high-side and lowside MOSFET RDS(ON) 's and the inductor series resistance (hence the name "Combi-Sense"). The SC2446 provides the virtual phase voltages VPN1 and VPN2 (these are
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SC2446
POWER MANAGEMENT Operation (Cont.)
unloaded versions of their respective power phase voltages) for current sensing. This method does not require any precision sense resistor. It is cheaper to implement but is less accurate than resistor current sensing. Since the sensed voltage is developed at the output of the step-down converter, it is less prone to switching transient spikes. This method will be described in more details in the Applications Information section. Error Amplifiers In closed loop operation, the error amplifier output ranges from 1.1V to 3.5V. The upper output operating range of either error amplifier is reserved for positive currentsense voltage (CS+ - CS-) and corresponds to positive (sourcing) output current. If the amplifier swings to its lower operating range, the amplifier will still modulate the high-side gate drive duty-ratio. However the peak current-sense voltage (hence the peak inductor current) will be limited to a negative value. The error amplifier output is about 2.2V when the peak sense-voltage is zero. The built-in offset in the current sense amplifier together with synchronous continuous-conduction mode of operation allows the SC2446 to regulate the output irrespective of the direction of the load current. The non-inverting input of the first feedback amplifier is tied to the internal 0.5V voltage reference. Both the noninverting and the inverting inputs of the second error amplifier are brought out as device pins so that the output of the second converter can be made to track the output of the first channel. For example in DDR applications, Channel 1 can be used to generate VDDQ (2.5V) from the input (5V or 12V) and channel 2 is used to produce a tracking VTT (1.25V) with VDDQ being its input. Current-Limit The maximum current sense voltage of +75mV is the cycle-by-cycle peak current limit when the load is drawing current from the converter. There is no cycle-by-cycle current limiting when the inductor current flows in the negative direction. However once the valley of the current sense voltage exceeds -110mV, the corresponding channel will undergo shutdown and restart (hiccup). Soft-Start and Overload Protection The undervoltage lockout circuit discharges the SS/EN capacitors. After VCC rises above 4.5V, the SS/EN capacitors are slowly charged by internal 2A current source. With internal PNP transistors, the SS/EN voltages clamp the error amplifier outputs. When the error amplifier output rises to 2.2V, the high-side MOSFET starts to switch. As the SS/EN capacitor continues to be charged, the COMP voltage follows. The converter gradually delivers increasing power to the output. The inductor current follows the COMP voltage envelope until the output goes into regulation. The SS/EN clamp on COMP is then released. After the SS/EN capacitor is charged above 3.2V (high enough for the error amplifier to provide full load current), the overload detection circuit is activated. If the output voltage falls below 70% of its set value or the valley current-sense voltage exceeds -110mV, an overload latch will be set and both the top and the bottom MOSFETs will be turned off. The SS/EN capacitor is slowly discharged with an internal 1.4A current sink. The overload latch is reset when the SS/EN capacitor is discharged below 0.5V. The SS/EN capacitor is then recharged with the 2A current source and the converter undergoes soft-start. If overload persists, the SC2446 will undergo repetitive shutdown and restart (Figure 3). If the output is short-circuited, the inductor current will not increase indefinitely between the time the inductor current reaching its current limit and the instant the converter shuts down. This is due to cycle skipping reduces the actual operating frequency. The SS/EN pin can also be used as the enable input for that channel. Both the high-side and the low-side MOSFETs will be turned off if the SS/EN pin is pulled below 0.7V.
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SC2446
POWER MANAGEMENT Application Information
SC2446 consists of two current-mode synchronous buck controllers with many integrated functions. By proper application circuitry configuration, SC2446 can be used to generate 1) two independent outputs from a common input or two different inputs or 2) dual phase output with current sharing, 3) current sourcing/sinking from common or separate inputs as in DDR (I and II) memory application. The application information related to the converter design using SC2446 is described in the following. Step-down Converter Starting from the following step-down converter specifications, Input voltage range: Vin [ Vin,min , Vin,max ] Input voltage ripple (peak-to-peak): Vin Output voltage: Vo Output voltage accuracy: Output voltage ripple (peak-to-peak): Vo Nominal output (load) current: Io Maximum output current limit: Io,max Output (load) current transient slew rate: dIo (A/s) Circuit efficiency: Selection criteria and design procedures for the following are described. 1) output inductor (L) type and value, 2) output capacitor (Co) type and value, 3) input capacitor (Cin) type and value, 4) power MOSFET's, 5) current sensing and limiting circuit, 6) voltage sensing circuit, 7) loop compensation network. Operating Frequency (fs) The switching frequency in the SC2446 is userprogrammable. The advantages of using constant frequency operation are simple passive component selection and ease of feedback compensation. Before setting the operating frequency, the following trade-offs should be considered. 1) 2) 3) 4) 5) Passive component size Circuitry efficiency EMI condition Minimum switch on time and Maximum duty ratio
For a given output power, the sizes of the passive components are inversely proportional to the switching frequency, whereas MOSFET's/Diodes switching losses are proportional to the operating frequency. Other issues such as heat dissipation, packaging and the cost issues are also to be considered. The frequency bands for signal transmission should be avoided because of EM interference. Minimum Switch On Time Consideration In the SC2446 the falling edge of the clock turns on the top MOSFET. The inductor current and the sensed voltage ramp up. After the sensed voltage crosses a threshold determined by the error amplifier output, the top MOSFET is turned off. The propagation delay time from the turnon of the controlling FET to its turn-off is the minimum switch on time. The SC2446 has a minimum on time of about 150ns at room temperature. This is the shortest on interval of the controlling FET. The controller either does not turn on the top MOSFET at all or turns it on for at least 150ns. For a synchronous step-down converter, the operating duty cycle is VO/VIN. So the required on time for the top MOSFET is VO/(VINfs). If the frequency is set such that the required pulse width is less than 150ns, then the converter will start skipping cycles. Due to minimum on time limitation, simultaneously operating at very high switching frequency and very short duty cycle is not practical. If the voltage conversion ratio VO/VIN and hence the required duty cycle is higher, the switching frequency can be increased to reduce the sizes of passive components. There will not be enough modulation headroom if the on time is simply made equal to the minimum on time of the SC2446. For ease of control, we recommend the required pulse width to be at least 1.5 times the minimum on time.
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SC2446
POWER MANAGEMENT Application Information (Cont.)
Setting the Switching Frequency The switching frequency is set with an external resistor connected from Pin 3 to the ground. The set frequency is inversely proportional to the resistor value (Figure 5). The followings are to be considered when choosing inductors. a) Inductor core material: For high efficiency applications above 350KHz, ferrite, Kool-Mu and polypermalloy materials should be used. Low-cost powdered iron cores can be used for cost sensitive-applications below 350KHz but with attendant higher core losses. b) Select inductance value: Sometimes the calculated inductance value is not available off-the-shelf. The designer can choose the adjacent (larger) standard inductance value. The inductance varies with temperature and DC current. It is a good engineering practice to re-evaluate the resultant current ripple at the rated DC output current. c) Current rating: The saturation current of the inductor should be at least 1.5 times of the peak inductor current under all conditions. Output Capacitor (Co) and Vout Ripple The output capacitor provides output current filtering in steady state and serves as a reservoir during load transient. The output capacitor can be modeled as an ideal capacitor in series with its parasitic ESR (Resr) and ESL (Lesl) (Figure 6).
Co
800 700 600 fs (kHz) 500 400 300 200 100 0 0 50 100 150 200 250 Rosc (k Ohm)
Figure 5. Free running frequency vs. ROSC. Inductor (L) and Ripple Current Both step-down controllers in the SC2446 operate in synchronous continuous-conduction mode (CCM) regardless of the output load. The output inductor selection/design is based on the output DC and transient requirements. Both output current and voltage ripples are reduced with larger inductors but it takes longer to change the inductor current during load transients. Conversely smaller inductors results in lower DC copper losses but the AC core losses (flux swing) and the winding AC resistance losses are higher. A compromise is to choose the inductance such that peak-to-peak inductor ripple-current is 20% to 30% of the rated output load current. Assuming that the inductor current ripple (peak-to-peak) value is *Io, the inductance value will then be
V (1 - D) L= o . Io fs
Lesl
Resr
Figure 6. An equivalent circuit of Co. If the current through the branch is ib(t), the voltage across the terminals will then be
v o ( t ) = Vo + di ( t ) 1 ib ( t )dt + L esl b + R esr ib ( t ). Co 0 dt
t
The peak current in the inductor becomes (1+/2)*Io and the RMS current is
IL,rms = Io 1 + 2 . 12
This basic equation illustrates the effect of ESR, ESL and Co on the output voltage. The first term is the DC voltage across Co at time t=0. The second term is the voltage variation caused by the charge balance between the load and the converter output. The
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SC2446
POWER MANAGEMENT Application Information (Cont.)
third term is voltage ripple due to ESL and the fourth term is the voltage ripple due to ESR. The total output voltage ripple is then a vector sum of the last three terms. Since the inductor current is a triangular waveform with peak-to-peak value *Io, the ripple-voltage caused by inductor current ripples is
v C Io , 8C o fs Io , D
should be an order of magnitude smaller than the voltage ripple caused by the ESR. To guarantee this, the capacitance should satisfy
Co > 10 . 2fsR esr
the ripple-voltage due to ESL is
v ESL = L esl fs
In many applications, several low ESR ceramic capacitors are added in parallel with the aluminum capacitors in order to further reduce ESR and improve high frequency decoupling. Because the values of capacitance and ESR are usually different in ceramic and aluminum capacitors, the following remarks are made to clarify some practical issues. Remark 1: High frequency ceramic capacitors may not carry most of the ripple current. It also depends on the capacitor value. Only when the capacitor value is set properly, the effect of ceramic capacitor low ESR starts to be significant. For example, if a 10F, 4m ceramic capacitor is connected in parallel with 2x1500F, 90m electrolytic capacitors, the ripple current in the ceramic capacitor is only about 42% of the current in the electrolytic capacitors at the ripple frequency. If a 100F, 2m ceramic capacitor is used, the ripple current in the ceramic capacitor will be about 4.2 times of that in the electrolytic capacitors. When two 100F, 2m ceramic capacitors are used, the current ratio increases to 8.3. In this case most of the ripple current flows in the ceramic decoupling capacitor. The ESR of the ceramic capacitors will then determine the output ripple-voltage. Remark 2: The total equivalent capacitance of the filter bank is not simply the sum of all the paralleled capacitors. The total equivalent ESR is not simply the parallel combination of all the individual ESR's either. Instead they should be calculated using the following formulae.
C eq () := (R1a + R1b )2 2C1a C1b + (C1a + C1b )2 (R1a C1a + R1b C1b )2 C1a C1b + (C1a + C1b ) R1aR1b (R1a + R1b )2C1a C1b + (R1b C1b + R1a C1a ) (R1a + R1b )2 2 C1a C1b + (C1a + C1b )2
2 2 2 2 2 2 2 2 2 2
and the ESR ripple-voltage is
v ESR = R esr Io .
Aluminum capacitors (e.g. electrolytic, solid OS-CON, POSCAP, tantalum) have high capacitances and low ESL's. The ESR has the dominant effect on the output ripple voltage. It is therefore very important to minimize the ESR. When determining the ESR value, both the steady state ripple-voltage and the dynamic load transient need to be considered. To keep the steady state output ripple-voltage < Vo, the ESR should satisfy
R esr1 < Vo . Io
To limit the dynamic output voltage overshoot/undershoot within (say 3%) of the steady state output voltage) from no load to full load, the ESR value should satisfy
R esr 2 < Vo . Io
Then, the required ESR value of the output capacitors should be Resr = min{Resr1,Resr2 }. The voltage rating of aluminum capacitors should be at least 1.5Vo. The RMS current ripple rating should also be greater than
Io 23 .
R eq () :=
Usually it is necessary to have several capacitors of the same type in parallel to satisfy the ESR requirement. The voltage ripple cause by the capacitor charge/discharge
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where R 1a and C 1a are the ESR and capacitance of electrolytic capacitors, and R1b and C1b are the ESR and capacitance of the ceramic capacitors respectively. (Figure 7)
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SC2446
POWER MANAGEMENT Application Information (Cont.)
C1a
C1b
Ceq
R1a
R1b
Req
Figure 7. Equivalent RC branch. Req and Ceq are both functions of frequency. For rigorous design, the equivalent ESR should be evaluated at the ripple frequency for voltage ripple calculation when both ceramic and electrolytic capacitors are used. If R1a = R1b = R1 and C1a = C1b = C1, then Req and Ceq will be frequencyindependent and Req = 1/2 R1 and Ceq = 2C1. Input Capacitor (Cin) The input supply to the converter usually comes from a pre-regulator. Since the input supply is not ideal, input capacitors are needed to filter the current pulses at the switching frequency. A simple buck converter is shown in Figure 8.
Figure 9. Typical waveforms at converter input. It can be seen that the current in the input capacitor pulses with high di/dt. Capacitors with low ESL should be used. It is also important to place the input capacitor close to the MOSFET's on the PC board to reduce trace inductances around the pulse current loop. The RMS value of the capacitor current is approximately
ICin = Io D[(1 + 2 D D )(1 - )2 + 2 (1 - D) ]. 12
The power dissipated in the input capacitors is then PCin = ICin2Resr. For reliable operation, the maximum power dissipation in the capacitors should not result in more than 10oC of temperature rise. Many manufacturers specify the maximum allowable ripple current (ARMS) rating of the capacitor at a given ripple frequency and ambient temperature. The input capacitance should be high enough to handle the ripple current. For higher power applications, multiple capacitors are placed in parallel to increase the ripple current handling capability.
Figure 8. A simple model for the converter input In Figure 8 the DC input voltage source has an internal impedance Rin and the input capacitor Cin has an ESR of Resr. MOSFET and input capacitor current waveforms, ESR voltage ripple and input voltage ripple are shown in Figure 9.
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SC2446
POWER MANAGEMENT Application Information (Cont.)
Sometimes meeting tight input voltage ripple specifications may require the use of larger input capacitance. At full load, the peak-to-peak input voltage ripple due to the ESR is
v ESR = R esr (1 + )Io . 2 ICin 0.5Io1 + D 2 (Io1 + Io 2 )2 + (D1 - D 2 - 0.5)Io 2 .
2 2
If D1>0.5 and D2 > 0.5, then
ICin (D1 + D 2 - 1)(Io1 + Io 2 )2 + (1 - D 2 )Io1 + (1 - D1 )Io2 .
2 2
The peak-to-peak input voltage ripple due to the capacitor is
v C DIo , Cin fs
Choosing Power MOSFET's Main considerations in selecting the MOSFET's are power dissipation, cost and packaging. Switching losses and conduction losses of the MOSFET's are directly related to the total gate charge (Cg) and channel on-resistance (Rds(on)). In order to judge the performance of MOSFET's, the product of the total gate charge and on-resistance is used as a figure of merit (FOM). Transistors with the same FOM follow the same curve in Figure 10.
From these two expressions, CIN can be found to meet the input voltage ripple specification. In a multi-phase converter, channel interleaving can be used to reduce ripple. The two step-down channels of the SC2446 operate at 180 degrees from each other. If both step-down channels in the SC2446 are connected in parallel, both the input and the output RMS currents will be reduced. Ripple cancellation effect of interleaving allows the use of smaller input capacitors. When converter outputs are connected in parallel and interleaved, smaller inductors and capacitors can be used for each channel. The total output ripple-voltage remains unchanged. Smaller inductors speeds up output load transient. When two channels with a common input are interleaved, the total DC input current is simply the sum of the individual DC input currents. The combined input current waveform depends on duty ratio and the output current waveform. Assuming that the output current ripple is small, the following formula can be used to estimate the RMS value of the ripple current in the input capacitor. Let the duty ratio and output current of Channel 1 and Channel 2 be D1, D2 and Io1, Io2, respectively. If D1<0.5 and D2<0.5, then
ICin D I
2 1 o1
50 Gate Charge (nC) 40 Cg( 100 , Rds) Cg( 200 , Rds) Cg( 500 , Rds) 20
1
0
0 1
5
10
15
20 20
FOM:100*10^{-12} FOM:200*10^{-12} FOM:500*10^{-12}
Rds On-resistance (mOhm)
Figure 10. Figure of Merit curves. The closer the curve is to the origin, the lower is the FOM. This means lower switching loss or lower conduction loss or both. It may be difficult to find MOSFET's with both low Cg and low Rds(on. Usually a trade-off between Rds(on and Cg has to be made. MOSFET selection also depends on applications. In many applications, either switching loss or conduction loss dominates for a particular MOSFET. For synchronous buck converters with high input to output voltage ratios, the top MOSFET is hard switched but conducts with very low duty cycle. The bottom switch conducts at high duty cycle but switches at near zero voltage. For such applications, MOSFET's with low Cg are used for the top switch and
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+ D 2Io2 .
2
If D1>0.5 and (D1-0.5) < D2<0.5, then
ICin 0.5Io1 + (D1 - 0.5)(Io1 + Io 2 )2 + (D 2 - D1 + 0.5)Io 2 .
2 2
If D1>0.5 and D2 < (D1-0.5) < 0.5, then
2004 Semtech Corp.
SC2446
POWER MANAGEMENT Application Information (Cont.)
MOSFET's with low Rds(on) are used for the bottom switch. MOSFET power dissipation consists of a) conduction loss due to the channel resistance Rds(on), b) switching loss due to the switch rise time tr and fall time tf, and c) the gate loss due to the gate resistance RG. Top Switch: The RMS value of the top switch current is calculated as
IQ1,rms = Io D(1 +
2 12
Qgs2 is the additional gate charge required for the switch current to reach its full-scale value Ids and . Qgd is the charge needed to charge gate-to-drain (Miller) capacitance when Vds is falling. Switching losses occur during the time interval [t1, t3]. Defining tr = t3-t1 and tr can be approximated as
tr = (Q gs 2 + Q gd )R gt Vcc - Vgsp .
).
The conduction losses are then Ptc = IQ1,rms2 Rds(on). Rds(on) varies with temperature and gate-source voltage. Curves showing R ds(on) variations can be found in manufacturers' data sheet. From the Si4860 datasheet, Rds(on) is less than 8m when Vgs is greater than 10V. However R ds(on) increases by 50% as the junction temperature increases from 25oC to 110oC. The switching losses can be estimated using the simple formula
1 Pts = 2 ( t r + t f )(1 + 2 )Io Vin f s .
where Rgt is the total resistance from the driver supply rail to the gate of the MOSFET. It includes the gate driver internal impedance R gi, external resistance Rge and the gate resistance Rg within the MOSFET i.e. Rgt = Rgi+Rge+Rg. Vgsp is the Miller plateau voltage shown in Figure 11. Similarly an approximate expression for tf is
tf =
(Q gs 2 + Q gd )R gt Vgsp
.
where tr is the rise time and tf is the fall time of the switching process. Different manufactures have different definitions and test conditions for t and t . To clarify these, we sketch r f the typical MOSFET switching characteristics under clamped inductive mode in Figure 11.
Only a portion of the total losses Pg = QgVccfs is dissipated in the MOSFET package. Here Qg is the total gate charge specified in the datasheet. The power dissipated within the MOSFET package is
Ptg = Rg R gt Q g Vcc fs .
The total power loss of the top switch is then Pt = Ptc+Pts+Ptg. If the input supply of the power converter varies over a wide range, then it will be necessary to weigh the relative importance of conduction and switching losses. This is because conduction losses are inversely proportional to the input voltage. Switching loss however increases with the input voltage. The total power loss of MOSFET should be calculated and compared for high-line and low-line cases. The worst case is then used for thermal design.
Gate charge
Figure 11. MOSFET switching characteristics In Figure 11, Qgs1 is the gate charge needed to bring the gate-to-source voltage Vgs to the threshold voltage Vgs_th,
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Bottom Switch: The RMS current in bottom switch can be shown to be
IQ 2,rms = Io (1 - D)(1 +
2 12
).
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SC2446
POWER MANAGEMENT Application Information (Cont.)
The conduction losses are then Pbc=IQ2,rms2 Rds(on). where Rds(on) is the channel resistance of bottom MOSFET. If the input voltage to output voltage ratio is high (e.g. Vin=12V, Vo=1.5V), the duty ratio D will be small. Since the bottom switch conducts with duty ratio (1-D), the corresponding conduction losses can be quite high. Due to non-overlapping conduction between the top and the bottom MOSFET's, the internal body diode or the external Schottky diode across the drain and source terminals always conducts prior to the turn on of the bottom MOSFET. The bottom MOSFET switches on with only a diode voltage between its drain and source terminals. The switching loss
1 Pbs = 2 ( t r + t f )(1 + 2 )Io Vd fs
Integrated Power MOSFET Drivers In SC2446 there are four internally integrated gate drivers to drive all the MOSFETs in dual channels. With the device bipolar process, emitter-follower based Darlington bipolar transistors are used for the output stage. The key advantage of the Darlington configuration is that the total current gain is greatly improved which leads to larger driving current Igs. This in turn will help reduce the MOSFETs switching losses. In order to estimate the losses associated with the gate driver, we first measured the gate driver waveform (typical waveforms of Vce and Igs) as shown in Figure12.
is negligible due to near zero-voltage switching. The gate losses are estimated as
Pbg = Rg R gt Q g Vcc fs .
The total bottom switch losses are then Pb=Pbc+Pbs+Pbg. Once the power losses Ploss for the top (Pt) and bottom (Pb) MOSFET's are known, thermal and package design at component and system level should be done to verify that the maximum die junction temperature (Tj,max, usually 125oC) is not exceeded under the worst-case condition. The equivalent thermal impedance from junction to ambient (ja) should satisfy
ja Tj,max - Ta,max Ploss .
v ce ( t ) = Vcc 2
Figure 12. Measured gate driver output waveforms with 2.2 current limit resistor. It is clear that the saturation voltage is not a constant. It changes with the driving current in a nonlinear fashion. A simple formula to calculate the losses with a reasonable accuracy is not available. But, we use a curve fitting technique to estimate the power losses in gate driver. First, the saturation voltage vce(t) is approximated as
- 1 t ( )2 2 T1
ja depends on the die to substrate bonding, packaging material, the thermal contact surface, thermal compound property, the available effective heat sink area and the air flow condition (free or forced convection). Actual temperature measurement of the prototype should be carried out to verify the thermal design.
.
Where, Vcc is the gate driver collector voltage, T1 is a time constant related to the fall time of vce. For the example in Fig. 12, Vcc=12V, T1=0.5Tf with Tf being measured as ~50 ns. With these parameters, the approximated vce(t) is plotted as in Figure 13 a).
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SC2446
POWER MANAGEMENT Application Information (Cont.)
Pgd =
12 vce (V) 20
1 Ts
Ts
v
0
ce
( t )i gs ( t )dt.
v ce( t )
10
0
0 0 0
5 .10
8
t
time (s)
1 10
-7
For SC2446, there are 4 gate drivers, the total gate driver losses is then 4Pgd. For the example in Figure 12, the power losses for each gate driver is estimated as 122 mW when the operating frequency is about 300kHz. The total losses for the 4 gate drivers is then about 488 mW. Remark 3: It is beneficial to select low gate charge MOSFET's for lower switching losses in the MOSFET package and lower power dissipation in the gate-driving IC. Once the MOSFET is chosen with a specified input gate charge, one can adjust the gate driving resistor to balance the driver IC losses and the power MOSFET switching losses. To the first order of approximation, smaller gate resistance leads to higher gate driving current and faster MOSFET switching. But, the driver incurs more power losses. On the other hand, larger gate drive resistance limits the gate drive current, which leads to low Vce and less power losses. But, the MOSFET suffers more switching losses. Using low gate charge MOSFET's reduces switching loss. To prevent shoot-through between the top and the bottom MOSFET's during commutation, one MOSFET should be completely turned off before the other is turned on. In the SC2446 the top and the bottom gate drive pulses are made non-overlapping. When not driving any load, the nonoverlapping commutation intervals from the top to the bottom and from the bottom to the top gate drives are set at 90ns. If MOSFET's are driven from the SC2446, the non-overlapping commutation times will decrease due to finite gate-source voltage rise and fall times. The gatesource voltage waveforms of the MOSFET's should not overlap above their respective thresholds when driven from the SC2446. Use of low gate charge MOSFET's reduces transition times and the tendency of shoot-through. The combined rise and fall times during both commutations should be less than the preset non-overlapping intervals. Current Sensing (Combi-Sense) Inductor current sensing is required for the current-mode control. Although the inductor current can be sensed with a precision resistor in series with the inductor, a novel lossless Combi-sense technique is used in the SC2446. This SEMTECH proprietary technique has the advantages of
Figure 13 a). Approximated gate driver vce(t) waveform. Similarly, the gate drive current is approximated as
) -( t i gs ( t ) = Igsp ( )2 e T2 . T2 t2
Where, Igsp is a scaling parameter proportional to the gate drive peak current, T2 is a time constant proportional to the fall time of v ce . For the example in Figure 13, Igsp=3.15A, T2=0.77Tf with Tf being measured as ~50 ns.
1.158 igs (A) 1.5 1 i gs( t ) 0.5 0 0 0 0
5 .10
8
t
time (s)
1 10
-7
Figure 13 b). Approximated gate drive current igs(t) waveform. With these parameters, the approximated igs(t) is plotted as in Figure 13 b). Based on the approximation formulae of vce(t) and igs(t), one can calculate the power losses for each gate driver pair as
2004 Semtech Corp.
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SC2446
POWER MANAGEMENT Application Information (Cont.)
1) lossless current sensing, 2) higher signal-to-noise ratio, and 3) preventing thermal run-away. The basic arrangement of the Combi-sense is shown in Figure 14. Where, RL is the equivalent series resistance of the output inductor. The added Rs and Cs form a RC branch for inductor current sensing. This branch is driven from a small totem pole driver (Q3 and Q4) integrated within SC2446. The base driving signals Vbe3 and Vbe4
Vin
Rds1 iL(t) PN Cin VPN vC(t) Rs Cs L RL
Vo
Cout Rload
Figure 15 a). Equivalent sub-circuit.
Vin
Q1 Vgs1 i L (t ) PN C in Rs Q2 Vgs2 v C (t ) Cs L RL
Vo
C ou t R l o ad
Vin
PN
C in
iL(t)
L Rs
RL Cs
Vbe 3 VP N Vbe 4
Q3
Rds2
VP N vC (t)
Vo
C ou t
Rload
Q4
Figure 14. The basic structure of Combi-Sense. are designed to follow the gate drive signals Vgs1 and Vgs2, respectively, with minimal delay drive. Ideally, the leading and falling edges of the Virtual Phase Node (VPN) follow that of the Phase Node (PN) when Q1~Q4 switch accordingly. Specifically, when Q1/Q3 are ON and Q2/Q4 are OFF, the equivalent circuit of Figure 14 reduces to Figure 15 a). Where, Rds1 is the on-resistance of the top MOSFET. The two branches, consisting of {(Rds1+RL), L} and {Rs, CS}, are in parallel. The DC voltage drop (Rds1+RL)Io equals VCs. In this way, the output current is sensed from VCs when (Rds1+RL) is known. When Q1/Q3 are OFF and Q2/Q4 are ON, the equivalent circuit of Figure 14 becomes the sub-circuit as shown in Figure 15 b). Where, Rds2 is the channel resistance of the bottom MOSFET. In this case, the branch {Rs,Cs} is in parallel with {(Rds2+RL), L} and V Cs=(Rds2+RL)I o. In average,
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Figure 15 b). Equivalent sub-circuit.
VCs=[D(Rds1+RL)+(1-D)(Rds2+RL)]Io, or equivalently VCs=[D Rds1+(1-D)Rds2+RL]Io=ReqIo. It is noted that the DC value of VCs is independent of the value of L, Rs and Cs. This means that, if only the average load current information is needed (such as in average current mode control), this current sensing method is effective without time constant matching requirement. In the current mode control as implemented in SC2446, the voltage ripple on Cs is critical for PWM operation. In fact, the AC voltage ripple peak-to-peak value of VCs (denoted as VCs) directly effects the signal-to-noise ratio of the PWM operation. In general, smaller VCs leads to lower signal-to-noise ratio and more noise sensitive operation. Larger VCs leads to more circuit (power stage)
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SC2446
POWER MANAGEMENT Application Information (Cont.)
parameter sensitive operation. A good engineering compromise is to make V Cs~R eqIo. The prerequisite for such relation is the so called time constant matching condition
L R sC s . R eq
Cin
In the following design steps, the capacitor CS in the current sensing part is commonly selected in the range of 22nF ~ 68nF.
Vin
Q1 V gs1 iL(t) PN Rs Q2 V gs2 vC(t) Rs 1 L RL
When Rds1=Rds2, the above relations become equations. For an example of application circuit, L=1.3H, RL=1.56m and Rds1=Rds2=8m , the time constant RsCs should be set as 136s. If one selects Cs=33 nF, then Rs=4.12 k. Scaling the Current Limit Over-current is handled differently in the SC2446 depending on the direction of the inductor current. If the differential sense voltage between CS+ and CS- exceeds +75mV, the top MOSFET will be turned off and the bottom MOSFET will be turned on to limit the inductor current. This +75mV is the cycle-by-cycle peak current limit when the load is drawing current from the converter. There is no cycle-by-cycle current limit when the inductor current flows in the reverse direction. If the voltage between CS1+ and CS- falls below -113mV, the controller will undergo overload shutdown and time-out with both the top and the bottom MOSFETs shut off. (See the section Overload Protection and Hiccup). In the circuit of Figure 14, the equivalent inductor current limits are set according to
ILMcp = 75mV , R eq
Vo
Cs C out Rload
V be3 VP N V be4
Q3
Q4
+1 IS N E -2
Rs 2 R s3
Figure 16. Scaling the equivalent current limit. a) When the required current limit value ILM is greater than ILMcp, one just needs to remove Rs3, and solve the following equations
(R s // R s1 ) Cs = L , R eq
ILMR eq
R s1 = 75mV, R s + R s1
and for
R s2 = R s // R s1 . R s ,R s1 and R s 2 .
when the load is sourcing current from the converter and
ILMcn = - 110mV , R eq
when the load is forcing current back to the input power source. If Req = 9.56mW, then ILM = 7.8/-11.8A. The circuit in Figure 16 allows the user to scale the equivalent current limit with the same Req.
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Note that RS2 is selected as RS//RS1 in order to reduce the bias current effect of the current amplifier in SC2446. If the current limit is to be set to ILM = 15A with the existing power circuit parameter and Cs = 33nF, it is calculated that Rs2 = 4.12 k, Rs = 7.87 k and Rs1 = 8.66 k. b) When the required current limit ILM is less than ILMcp, one just needs to remove Rs1 and solve
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SC2446
POWER MANAGEMENT Application Information (Cont.)
R sC s = L , R eq
ILMR eq +
Rs VO = 75mV, R s3
off until it is no longer overloaded. This hiccup mode of overload protection is a form of foldback current limiting. The following calculations estimate the average inductor current when the converter output is shorted to the ground. a) The time taken to discharge the capacitor from 3.2V to 0.5V
t ssf = C32 (3.2 - 0.5)V . 1.4A
for Rs and RS3. Rs2 is then obtained from
R s2 = R s 3R s . R s3 - R s
If C32 = 0.1F, tssf is calculated as 193ms. b) The soft start time from 0.5V to 3.2V
t ssr = C32 (3.2 - 0.5)V . 2A
If the current limit is to be set to ILM = 5A with the existing power circuit parameter and Cs, it is calculated that Rs=4.12 k, Rs3=190 k and Rs2=4.22 k. Similar steps and equations apply to the current limit setting and scaling for current sinking mode. Remark 4: When the current limit ILM is lower than ILMcp, the designer has the freedom of selecting higher Rds(ON) MOSFETs to reduce cost. As a result, Reg is increased and I LMcp is reduced. Although the use of low-cost MOSFET's is always preferred, the current-limit setting technique described above allows quick adjustment on a well-tested prototype without the need to replace the power MOSFETs. Overload Protection and Hiccup During start-up, the capacitor from the SS/EN pin to ground functions as a soft-start capacitor. After the converter starts and enters regulation, the same capacitor operates as an overload shutoff timing capacitor. As the load current increases, the cycle-bycycle current-limit comparator will first limit the inductor current. Further increase in loading will cause the output voltage (hence the feedback voltage) to fall. If the feedback voltage falls to less than (75% for Ch1, 72% for Ch2) of the reference voltage, the controller will shut off both the top and the bottom MOSFET's. Meanwhile an internal 1.4A current source discharges the soft-start capacitor C32(C33) connected to the SS/EN pin. When the capacitor is discharged to 0.5V, a 2A current source recharges the SS/EN capacitor and converter restarts. If overload persists, the controller will shut down the converter when the soft start capacitor voltage exceeds 3.2V. The converter will repeatedly start and shut
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When C32 = 0.1F, tssr is calculated as 135ms. Note that during soft start, the converter only starts switching when the voltage at SS/EN exceeds 1.2V. c) The effective start-up time is
t sso = C32 (3.2 - 1.2)V . 2A
The average inductor current is then
ILeff = ILMcp t sso . t ssf + t ssr
ILeff 0.30 ILMcp and is independent of the soft start capacitor value. The converter will not overheat in hiccup. Setting the Output Voltage The non-inverting input of the channel-one error amplifier is internally tied the 0.5V voltage reference output (Pin 8). The non-inverting input of the channel-two error amplifier is brought out as a device pin (Pin 10) to which the user can connect Pin 8 or an external voltage reference. A simple voltage divider (Ro1 at top and Ro2 at bottom) sets the converter output voltage. The voltage feedback gain h=0.5/Vo is related to the divider resistors value as
Ro2 = h R o1. 1- h
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SC2446
POWER MANAGEMENT Application Information (Cont.)
Once either R o1 or R o2 is chosen, the other can be calculated for the desired output voltage Vo. Since the number of standard resistance values is limited, the calculated resistance may not be available as a standard value resistor. As a result, there will be a set error in the converter output voltage. This non-random error is caused by the feedback voltage divider ratio. It cannot be corrected by the feedback loop. The following table lists a few standard resistor combinations for realizing some commonly used output voltages.
complex high-Q poles of the output LC networks is split into a dominant pole determined by the output capacitor and the load resistance and a high frequency pole. This pole-splitting property of current-mode control greatly simplifies loop compensation. The inner current-loop is unstable (sub-harmonic oscillation) unless the inductor current up-slope is steeper than the inductor current down-slope. For stable operation above 50% duty-cycle, a compensation ramp is added to the sensed-current. In the SC2446 the compensation ramp is made duty-ratio dependent. The compensation ramp is approximately
Iramp = De1.76D * 30A.
Vo (V) (1- h)/h
0.6 0.2
0.9 0.8 806 1K
1.2 1.4 1.4K 1K
1.5 2 2K 1K
1.8 2.6
2.5 4
3.3 5.6
The slope of the compensation ramp is then
S e = (1 + 1.76D)e1.76D fs * 30A.
Ro1 (Ohm) 200 Ro2 (Ohm) 1K
2.61K 4.02K 5.62K 1K 1K 1K
Only the voltages in boldface can be precisely set with standard 1% resistors. From this table, one may also observe that when the value
1 - h Vo - 0.5 = h 0.5
The slope of the internal compensation ramp is well above the minimal slope requirement for current loop stability and is sufficient for all the applications. With the inner current loop stable, the output voltage is then regulated with the outer voltage feedback loop. A simplified equivalent circuit model of the synchronous Buck converter with current mode control is shown in Figure 17.
and its multiples fall into the standard resistor value chart (1%, 5% or so), it is possible to use standard value resistors to exactly set up the required output voltage value. The input bias current of the error amplifier also causes an error in setting the output voltage. The maximum inverting input bias currents of error amplifiers 1 and 2 is -250nA. Since the non-inverting input is biased to 0.5V, the percentage error in the second output voltage will be -100% * (0.25A) * R R /[0.5 * (R +R ) ]. To keep o1 o2 o1 o2 this error below 0.2%, R < 4k. o2 Loop Compensation SC2446 uses current-mode control for both step-down channels. Current-mode control is a dual-loop control system in which the inductor peak current is loosely controlled by the inner current-loop. The higher gain outer loop regulates the output voltage. Since the current loop makes the inductor appear as a current source, the
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k
Figure 17. A simple model of synchronous buck converter with current mode control.
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SC2446
POWER MANAGEMENT Application Information (Cont.)
The transconductance error amplifier (in the SC2446) has a gain gm of 260A/V. The target of the compensation design is to select the compensation network consisting of C2, C3 and R2, along with the feedback resistors Ro1, Ro2 and the current sensing gain, such that the converter output voltage is regulated with satisfactory dynamic performance. With the output voltage Vo known, the feedback gain h and the feedback resistor values are determined using the equations given in the "Output Voltage Setting" section with
0.5 h= . Vo s z2 = 1 , R 2C 2
and
sp2 = 1 . C 2C 3 R2 C 2 + C3
The loop transfer function is then T(s)=Gvc(s)C(s). To simplify design, we assume that C3<C2 = gmhkR o , 2fc R oCo , C2
For the rated output current Io, the current sensing gain k is first estimated as
k= Io . 2.1
From Figure 17, the transfer function from the voltage error amplifier output vc to the converter output vo is
s Vo (s) s z1 . := G vc (s) = kR o s Vc (s) 1+ s p1 1+
R2 =
and
C3 = R oesr C o K, R2
where, the single dominant pole is
s p1 = 1 , (R o + R oesr )C o
and the zero due to the output capacitor ESR is
s z1 = 1 R oesr C o .
with a constant K. For example, if Vo=2.5V, Io=15A, fs=300kHz, Co=1.68mF, Roesr=4.67m, one can calculate that
Ro = Vo = 167m, Io 0.5 = 0.2, Vo
The dominant pole moves as output load varies. The controller transfer function (from the converter output vo to the voltage error amplifier output vc) is
s gm h s z2 C(s) = , s s(C 2 + C 3 ) 1+ sp2 1+
h=
and
k= Io = 7.14. 2.1
where
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SC2446
POWER MANAGEMENT Application Information (Cont.)
If the converter crossover frequency is set around 1/10 of the switching frequency, fc = 30kHz, the controller parameters then can be calculated as
C2 = gmhkR o 0.328nF. 2fc
arg G vc( f) C( f) f - 88.78 88 89 90 91 92 - 92.702 93 10 10 100
where, gm is the error amplifier transconductance gain (260 -1). If we use C2 = 0.33 nF,
R2 = R oCo 848 .5k, C2
(
)
180
1 .10
3
f
1 .10
4
1 .10
5
1 .10 3x10
5
6
use R2 = 770k. With K = 1, it is further calculated that
C3 = R oesr C o K 10.2pF, R2
Figure 18. The loop transfer function Bode plot of the example. It is clear that the resulted crossover frequency is about 27.1 kHz with phase margin 91o. It is noted that the current sensing gain k was first estimated using the DC value in order to quickly get the compensation parameter value. When the circuit is operational and stable, one can further improve the compensation parameter value using AC current sensing gain. One simple and practical method is to effectively measure the output current at two points, e.g. Io1 and Io2 and the corresponding error amplifier output voltage Vc1 and Vc2. Then, the first order AC gain is
use C3 = 10pF. The Bode plot of the loop transfer function (magnitude and phase) is shown in Figure 18
69.241
100
50 20 log G vc( f ) C( f )
(
)
0
k=
Io I -I = o1 o 2 Vc Vc1 - Vc 2
- 20.73 50 10 10 100
1 .10
3
f
1 .10
4
1 .10
5
1 .10 3x10
5
6
With this k value, one can further calculate the improved compensator parameter value using the previous equations. For example, if one measured that Io1=1A, Io2=15A and Vc1=2.139V, Vc2=2.457V. k is then calculated as 44. Substituting this parameter to the equations before, one can derive that C2 2.024nF. Select C2 = 2.2nF. R2 127.3k. Select R2 = 127k. C3 61.78pF. Select C3 = 47pF
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SC2446
POWER MANAGEMENT Application Information (Cont.)
In some initial prototypes, if the circuit noise makes the control loop jittering, it is suggested to use a bigger C3 value than the calculated one here. Effectively, the converter bandwidth is reduced in order to reject some high frequency noises. In the final working circuit, the loop transfer function should be measured using network analyzer and compared with the design to ensure circuit stability under different line and load conditions. The load transient response behavior is further tested and measured to meet the specification. PC Board Layout Issues Circuit board layout is very important for the proper operation of high frequency switching power converters. A power ground plane is required to reduce ground bounces. The followings are suggested for proper layout. Power Stage 1) Separate the power ground from the signal ground. In SC2446, the power ground PGND should be tied to the source terminal of lower MOSFETs. The signal ground AGND should be tied to the negative terminal of the output capacitor. 2) Minimize the size of high pulse current loop. Keep the top MOSFET, bottom MOSFET and the input capacitors within a small area with short and wide traces. In addition to the aluminum energy storage capacitors, add multilayer ceramic (MLC) capacitors from the input to the power ground to improve high frequency bypass. 3) Reduce high frequency voltage ringing. Widen and shorten the drain and source traces of the MOSFET's to reduce stray inductances. Add a small RC snubber if necessary to reduce the high frequency ringing at the phase node. Sometimes slowing down the gate drive signal also helps in reducing the high frequency ringing at the phase node. 4) Shorten the gate driver path. Integrity of the gate drive (voltage level, leading and falling edges) is important for circuit operation and efficiency. Short and wide gate drive traces reduce trace inductances. Bond wire inductance is about 2~3nH. If the length of the PCB trace from the gate driver to the MOSFET gate is 1 inch, the trace inductance will be about 25nH. If the gate drive current is 2A with 10ns rise and falling times, the voltage drops across the bond wire and the PCB trace will be 0.6V and 5V respectively. This may slow down the switching transient of the MOSFET's. These inductances may also ring with the gate capacitance. 5) Put the decoupling capacitor for the gate drive power supplies (BST and PVCC) close to the IC and power ground. Control Section 6) The frequency-setting resistor Rosc should be placed close to Pin 3. Trace length from this resistor to the analog ground should be minimized. 7) Solder the bias decoupling capacitor right across the AVCC and analog ground AGND. 8) Place the Combi-sense components away from the power circuit and close to the corresponding CS+ and CSpins. Use X7R type ceramic capacitor for the Combi-sense capacitor because of their temperature stability. 9) Use an isolated local ground plane for the controller and tie it to the negative side of output capacitor bank.
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SC2446
POWER MANAGEMENT Application Information
VIN
C92 D11
PVCC
D12
Q21
VO2
C99 + R79 C96 C95
R73 C93
BST2 GDH2
BST1 GDH1
R74 C94
Q22 L12 Q24 C98 + R76 C97 R80
L11 Q23
VO1
C100
CFILTER R75 RFILTER
R77
GDL2 GDL1 PGND VPN2 CS2+ VPN1 CS1+ CS1IN1COMP1 REF AGND Rosc AVCC REFOUT
R78
CFILTER RFILTER
RCS+ RCS-
RCS+ RCS-
R81 C101 R83 C103
CS2IN2COMP2
R82 C102
REF VIN SYNC
REFIN VIN2 SYNC SS1/EN1 SS2/EN2
C104
C105
R84
R85 VIN
C106
C107
SC2446
Dual Independant Outputs
U1
C108
C109
Figure 19
VIN
C38 D5
PVCC
D6
Q9
VO1
C45 + C42 C41
R32 C39
BST2 GDH2
BST1 GDH1
R33 C40
Q10 L6 Q12 C44 + R35 C43 R38
L5 Q11
VO1
C46
CFILTER R34 RFILTER
R36
GDL2 GDL1 PGND VPN2 CS2+ VPN1 CS1+ CS1IN1COMP1 REF AGND Rosc AVCC REFOUT
R37
CFILTER RFILTER
RCS+ RCS-
RCS+ RCS-
CS2IN2COMP2
R39 C48
AVCC
C47 R40 C49 REF VIN SYNC
REFIN VIN2 SYNC SS1/EN1 SS2/EN2
C50
C51
R41
R42 VIN
C52
C53
SC2446
Single Output, Current Share Mode
U1
C54
C55
Figure 20
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SC2446
POWER MANAGEMENT Application Information (Cont.)
VIN
C56 D7
PVCC
D8
Q13
VTT
C63 + R49 C60 C59
R43 C57
BST2 GDH2
BST1 GDH1
R44 C58
Q14 L8 Q16 C62 + R46 C61 R50
L7 Q15
VDDQ
C64
CFILTER R45 RFILTER
R47
GDL2 GDL1 PGND VPN2 CS2+ VPN1 CS1+ CS1IN1COMP1 REF AGND Rosc AVCC REFOUT
R48
CFILTER RFILTER
RCS+ RCS-
RCS+ RCS-
R51 C65 R53 C67
CS2IN2-
R52 C66
VDDQ
R54 R56
COMP2 REFIN
C68
C69
R55
VIN
SYNC
VIN2 SYNC SS1/EN1 SS2/EN2
R57 VIN
C70
C71
SC2446
U1
C72
C73
Figure 21
DDR Memory Applications (Common Input Voltage)
VIN
VDDQ
C74 D9
PVCC
D10
Q17
VTT
C81 + R64 C78 C77
R58 C75
BST2 GDH2
BST1 GDH1
R59 C76
Q18 L10 Q20 C80 + R61 C79 R65
L9 Q19
VDDQ
C82
CFILTER R60 RFILTER
R62
GDL2 GDL1 PGND VPN2 CS2+ VPN1 CS1+ CS1IN1COMP1 REF AGND Rosc AVCC REFOUT
R63
CFILTER RFILTER
RCS+ RCS-
RCS+ RCS-
R66 C83 R68 C85
CS2IN2-
R67 C84
VDDQ
R69 R71
COMP2 REFIN
C86
C87
R70
VDDQ
SYNC
VIN2 SYNC SS1/EN1 SS2/EN2
R72 VIN
C88
C89
SC2446
DDR Memory Applications (Separate Input Voltage)
U1
C90
C91
Figure 22
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SC2446
POWER MANAGEMENT Typical Performance Characteristics
4.6 4.55 AVCC UVLO (V) 4.5
AVCC (Rising) AVCC (Falling)
502.5 502 501.5 501 REF (V) 500.5 500 499.5 499 498.5 498 -50 0 50 Ta (degree) 100
4.45 4.4 4.35 4.3 -50 0 50 Ta (degree) 100
AVCC UVLO vs. Temperature REF Voltage vs. Temperature
1.26 Typ. Frequency (kHz) 1.25 REFout (V) 1.24 1.23 1.22 1.21 1.2 -50 0 Ta (degree) REFin=1.25V 50 100
512 510 508 506 504 502 500 498 -50 0
Rosc=51.1 kOhm
50 Ta (degree)
100
REFout Voltage vs. Temperature
Switching Frequency vs. Temperature
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SC2446
POWER MANAGEMENT Typical Performance Characteristics
75.00 Current Lim it (m V) 74.00 73.00 72.00 71.00 70.00 69.00 -50 0 Ta (degree) 50 100
Ch1
Current Limit (mV)
Ch2
-107.5 -108 -108.5 -109 -109.5 -110 -110.5 -111 -111.5 -112 -112.5 -50
Ch1 Ch2
0 Ta (degree)
50
100
Source Current Limit Threshold vs. Temperature Sink Current Limit Threshold vs. Temperature
112 111 110 109 108 107 106 105 104 103 -60 -40 -20 0 20 Ta (degree) Ch1, Low Side Off to High Side On Ch1, High Side Off to Low Side On 40 60 80 100
Non-overlapping Delay Time (ns)
Non-overlapping Delay Time (ns)
112 110 108 106 104 102 100 -60 -40 -20 0 20 Ta (degree) Ch2, Low Side Off to High Side On Ch2, High Side Off to Low Side On 40 60 80 100
Ch1 Non-overlapping Delay Time
Ch2 Non-overlapping Delay Time
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SC2446
POWER MANAGEMENT Typical Performance Characteristics
Efficiency vs. Load Current (%) Vin=5V 95 Vout Variation (%) Efficiency (%) 90 85 80 75 70 65 0 10 20 30 Load Current (A) Vin=12V 0.1 0 -0.1 0 -0.2 -0.3 -0.4 -0.5 -0.6 Load Current (A) 10 20 30
Channel 1: Vo = 2.5V @ 15A
Load Regulation Vin=12V Vin=5V
Soft-Start
Line Regulation @ Io=15A 0 -0.05 0 Vout Variation (%) -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 Input Voltage (V) 5 10 15
Load Transient
Output Characteristics @ Vin=12V 3 Output Voltage (V) 2.5 2 1.5 1 0.5 0 0 10 20 30 40 Load Current (A)
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SC2446
POWER MANAGEMENT Typical Performance Characteristics
Efficiency vs. Load Current Vin=5V 95 Vout Variation (%) Efficiency (%) 90 85 80 75 70 65 60 0 10 20 30 Load Current (A) Vin=12V 0.1 0 -0.1 0 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 Load Current (A) 10 20 30
Channel 2: Vo = 1.8V @ 15A
Load Regulation Vin=5V Vin=12V
Fig. 18
Soft-Start
Line Regulation at Io=15A 0 -0.05 0 Vout Variation (%) -0.1 -0.15 -0.2 -0.25 -0.3 -0.35 -0.4 Input Voltage (V) 5 10 15
Load Transient
Output Characteristics @ Vin=12V 2 Output Voltage (V) 1.5 1 0.5 0 0 10 20 30 40 Load Current (A)
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VIN VINGND
R32 R31
POWER MANAGEMENT Typical Application Circuit
C16 D11 C1+ C2 D1 C8 + + + C11 C10 + C9
C4+ D2 + + C6+ C38
C3
C7
C5
C13
C12
+ PVCC Q2 R4 25 GDH1 L2 Q6 R8 24 GDL1 PGND VPN1 CS1+ CS1IN1COMP1 REF AGND Rosc AVCC REFOUT C33 U1 C32 R30 SS2/EN2 15 SS1/EN1 28 SY NC 6 R22 VIN2 17 C30 REFIN 10 COMP2 11 C27 R18 IN212 CS213 RCS-1 CS2+ 14 VPN2 18 R10 RCS+1 GDL2 R5 22 R13 27 1 2 4 C28 R19 7 R20 3 16 9 C35 C34 R21 C31 C29 8 5 21 R7 C19 C20 Q5 D7 GDH2 20 BST1 R3 BST2 26 Q3 19 C18 23
C15 +
C14 +
+
C17
VO1
L1 Q7 C23 R6 D10 Q8
VO2
C25 C26 R9
C22
C24
C21
R11
RCS+2
Figure 23
SC2446
R23 R24 R25 R26 R27
32
VO1GND
RCS-2
R15
VO2GND
R16
R17
Notes: 1. Dual Independant Outputs: R15=0, R22 open, R23=0, R24, R25, R26 open, R27=0. 2. Single Output with Current Sharing Mode: R15 open, R22=0, R23=0, R24, R25, R26 open, R27=0. 3. DDR Memory Applications (Common Input Voltage): R15=0, R22 open, R23=0, R24 open, R25=R26=2K, R27 open. 4. DDR Memory Applications (Separate Input Voltage): R15=0, R22, R23 open, R24=0, R25=R26=2K, R27 open.
Title Size B Date:
SC2446 EVB Schematics Document Number Monday , March 15, 2004 Sheet 1 of 1 Rev 2
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SC2446
SC2446
POWER MANAGEMENT Evaluation Board - Bill of Materials
R ef 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 Qty 2 4 2 6 1 2 2 2 4 2 3 1 1 2 2 Reference C1,C4 C2,C3,C6,C38 C8,C12 C9,C10,C11, C13,C14,C15, C 16 C17,C18 C18,C19 C20,C21 C22,C24,C25,C26 C27,C28 C29,C34,C35 C 30 C 31 C32,C33 D1,D2 Part Number/Value 47uF, 16V, 70 mohm, PosCap 10uF, 16V, X5R, Ceramic 1206 680uF, 4V, PosCap 100uF, 6.3V, Ceramic 1210 1uF, 16V, X5R , Ceramic 0805 0.33uF, 50V, X5R, 1206 2.2nF, Ceramic, 0805 22nF, Ceramic, 0805 10uF, 4V, X5R, Ceramic, 1206 68pF, Ceramic, 0805 0.1uF, Ceramic, 0805 1nF, Ceramic, 0805 2.2nF, Ceramic, 0805 100nF, Ceramic, 0805 40V, 1A, Schottky Manufacturer Sanyo P/N: 16TPB47M Taiyo Yuden P/N: EMK316BJ106MM Sanyo P/N: 4TPB680M TDK P/N: C3225XR5R0J107M Taiyo Yuden P/N: EMK316BJ105MM Vishay P/N: VJ1206Y334KXAAT Any Any Taiyo Yuden P/N: AMK325BJ106MM Any Any Any Any Any General Semi. P/N: 1N5819M, MELF or Motorola P/N: MBRS140T3 Diodes Inc. P/N: B340A ZMM5234B Panasonic P/N: ETQP6F1R8BFA, or Sumdia P/N: CEP1251R8MC-SJ Vishay P/N: Si4860DY Any Any Any Any Any Any
16 17 18 19 20 21 22 23 24 25
2 1 2 6 2 2 4 2 1 2
D7,D10 D11 L1,L2 Q2,Q3,Q5,Q6,Q7 RCS+1,RCS+2 RCS-1,RCS-2 R3,R4,R7,R8 R5,R6 R9 R10,R13
40V, 3A, Schottky 6.2V, 500mW, 5%, Zener, SOD123 1.8uH, 14A, 3.3 mohm (1.8uH, 15.5A, 3.4 mohm) 30V, 16A, 8 mohm, 18nC, SO-8 49.9k, 0805 1 0 0 k. 0 8 0 5 1.0 ohm, 5%, 0805 2 0 k, 0 8 0 5 3.40k, 1%, 0805 5.1, 0805
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SC2446
POWER MANAGEMENT Evaluation Board - Bill of Materials
R ef 25 26 27 28 29 30 31 32 33 34 Qty 1 3 1 1 2 1 1 1 1 1 Reference R11 R15,R23,R27 R16 R17 R18,R19 R20 R21 R31 R32 U1 Part Number/Value 4.02k, 1%, 0805 0 ohm, 0805 1k, 1%, 0805 1.3k, 1%, 805 2 0 k, 0 8 0 5 95.3k, 1% 5.1 110, 5%, 1206 300, 5%, 1206 S C 2446 Any Any Any Any Any Any Any Any Any Semtech Corp. Manufacturer
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SC2446
POWER MANAGEMENT Typical Characteristics
Typical waveforms in the evaluation board circuit #2A Steady state
Channel 1: Vo=2.5V @ 15A Over current protection Output short applied
Load transient response Loading: 0A to 15A
Output short removed
Un-loading: 15A to 0A
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SC2446
POWER MANAGEMENT Typical Characteristics (Cont.)
Typical waveforms in the evaluation board circuit #2A Steady state Channel 2: Vo=1.8V @ 15A Load transient response Loading: 0A to 15A
Un-loading: 15A to 0A
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SC2446
POWER MANAGEMENT Typical Characteristics (Cont.)
Over current protection Output short applied
Output short removed
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SC2446
POWER MANAGEMENT Outline Drawing - TSSOP-28-EDP
A e N 2X E/2 E1 PIN 1 INDICATOR ccc C 2X N/2 TIPS 123 E D
DIM
A A1 A2 b c D E1 E e F H L L1 N 01 aaa bbb ccc
DIMENSIONS INCHES MILLIMETERS MIN NOM MAX MIN NOM MAX
.047 .002 .006 .031 .042 .007 .012 .003 .007 .378 .382 .386 .169 .173 .177 .252 BSC .026 BSC .210 .216 .220 .112 .118 .122 .018 .024 .030 (.039) 28 0 8 .004 .004 .008 1.20 0.05 0.15 0.80 1.05 0.19 0.30 0.09 0.20 9.60 9.70 9.80 4.30 4.40 4.50 6.40 BSC 0.65 BSC 5.35 5.50 5.60 2.85 3.00 3.10 0.45 0.60 0.75 (1.0) 28 0 8 0.10 0.10 0.20
e/2 B
aaa C SEATING PLANE
D A2 A
C
bxN bbb
A1 C A-B D
F EXPOSED PAD SIDE VIEW
SEE DETAIL
A
H GAGE PLANE BOTTOM VIEW 0.25
H c L (L1) DETAIL
01
A
NOTES: 1. CONTROLLING DIMENSIONS ARE IN MILLIMETERS (ANGLES IN DEGREES). 2. DATUMS -A- AND -B- TO BE DETERMINED AT DATUM PLANE -H3. DIMENSIONS "E1" AND "D" DO NOT INCLUDE MOLD FLASH, PROTRUSIONS OR GATE BURRS. 4. REFERENCE JEDEC STD MO-153, VARIATION AE.
Land Pattern - TSSOP-28-EDP
F X
DIM
(C) H G Z C F G H P X Y Z
DIMENSIONS INCHES MILLIMETERS
(.222) .224 .161 .126 .026 .016 .061 .283 (5.65) 5.70 4.10 3.20 0.65 0.40 1.55 7.20
Y P
NOTES: 1. THIS LAND PATTERN IS FOR REFERENCE PURPOSES ONLY. CONSULT YOUR MANUFACTURING GROUP TO ENSURE YOUR COMPANY'S MANUFACTURING GUIDELINES ARE MET.
Contact Information
Semtech Corporation Power Management Products Division 200 Flynn Road, Camarillo, CA 93012 Phone: (805)498-2111 FAX (805)498-3804
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