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| Product Specification PFC / Flyback PWM Controller SG6901A very few external components to achieve versatile protections. It is available in a 20-pin SOP package. The patented interleave-switching feature synchronizes the PFC and PWM stages and reduces switching noise. For PFC stage, the proprietary multi-vector control scheme provides a fast transient response in a low-bandwidth PFC loop, in which the overshoot and undershoot of the PFC voltage are clamped. If the feedback loop is broken, the SG6901A shuts off PFC to prevent extra-high voltage on output. Programmable two-level output voltage control reduces the PFC output voltage at low line input to increase the efficiency of the power supply. For the flyback PWM, the synchronized slope compensation ensures the stability of the current loop under continuous-conduction-mode operation. Built-in line-voltage compensation maintains constant output-power limit. Hiccup operation during output overloading is also guaranteed. In addition, SG6901A provides protection functions, such as brownout and RI pin open/short protection. FEATURES OVERVIEW Interleaved PFC/PWM switching Low start-up and operating current Innovative switching charge multiplier-divider Multi-vector control for improved PFC output transient response Average-current-mode control for PFC Programmable two-level PFC output voltage PFC over-voltage and under-voltage protections PFC and PWM feedback open-loop protection Cycle-by-cycle current limiting for PFC/PWM Slope compensation for PWM Constant power limit for PWM Brownout protection Over-temperature protection (OTP) APPLICATIONS Switching Power Supplies with Active PFC and Standby Power High-Power Adaptors DESCRIPTION The highly integrated SG6901A is designed for power supplies with boost PFC and flyback PWM. It requires Typical Application (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) -1- www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A MARKING DIAGRAMS PIN CONFIGURATION SG6901A TP XXXXXXXXYWWV T: S=SOP P : Z=Lead Free Null=regular package XXXXXXXX: Wafer Lot Y: Year; WW: Week V: Assembly Location ORDERING INFORMATION Part Number SG6901ASZ Pb-Free Package 20-pin SOP (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) -2- www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A PIN DESCRIPTIONS Name VRMS Pin No. 1 Type Line-Voltage Detection Function Line voltage detection. The pin is used for PFC multiplier, RANGE control of PFC output voltage, and brownout protection. For brownout protection, the controller is disabled after a delay time when the VRMS voltage drops below a threshold. Reference setting. One resistor connected between RI and ground determines the switching frequency. The switching frequency is equal to [1560 / RI] KHz, where RI is in K. For example, if RI is equal to 24K, the switching frequency is 65KHz. This pin supplies an over-temperature protection signal. A constant current is output from this pin. An external NTC thermistor must be connected from this pin to ground. The impedance of the NTC thermistor decreases whenever the temperature increases. Once the voltage of the OTP pin drops below the OTP threshold, the SG6901A is disabled. This is the output of the PFC current amplifier. The signal from this pin is compared with an internal sawtooth and determines the pulse width for PFC gate drive. The inverting input of the PFC current amplifier. Proper external compensation circuits result in excellent input power factor via average-current-mode control. The non-inverting input of the PFC current amplifier and the output of multiplier. Proper external compensation circuits will result in excellent input power factor via average-current-mode control. The peak-current setting for PFC. The control input for voltage-loop feedback of PWM stage. It is internally pulled high through a 6.5k resistance. Usually an external opto-coupler from secondary feedback circuit is connected to this pin. The current-sense input for the flyback PWM. Via a current sense resistor, this pin provides the control input for peak-current-mode control and cycle-by-cycle current limiting. Signal ground. During startup, the SS pin will charge an external capacitor with a 50A (RI=24K) constant current source. The voltage on FBPWM will be clamped by SS during startup. In the event of a protection condition occurring and/or PWM being disabled, the SS pin will be quickly discharged. The totem-pole output drive for the Flyback PWM MOSFET. This pin is internally clamped under 17V to protect the MOSFET. Power ground. The totem-pole output drive for the PFC MOSFET. This pin is internally clamped under 17V to protect the MOSFET. The power supply pin. Two-level output voltage setting for PFC. The PFC output voltage at low line can be reduced to improve efficiency. The RANGE pin has high impedance whenever the VRMS voltage is lower than a threshold. The PFC stage over voltage input. The comparator disables the PFC output driver if the voltage at this input exceeds a threshold. This pin can be connected to FBPFC or it can be connected to the PFC boost output through a divider network. The feedback input for PFC voltage loop. The inverting input of PFC error amplifier. This pin is connected to the PFC output through a divider network. The error amplifier output for PFC voltage feedback loop. A compensation network (usually a capacitor) is connected between this pin and ground. A large capacitor value results in a narrow bandwidth and improves the power factor. This input is used to provide current reference for the multiplier. RI 2 Oscillator Setting OTP 3 Over Temperature Protection Output for PFC Current Amplifier Inverting Input for PFC Current Amplifier Non-inverting Input for PFC Current Amplifier Peak Current Limit Setting for PFC PWM Feedback Input PWM Current Sense Ground PWM Soft-Start IEA 4 IPFC 5 IMP ISENS E FBPW M 6 7 8 IPWM AGND SS 9 10 11 OPWM GND OPFC VDD RANGE 12 13 14 15 16 PWM Gate Drive Ground PFC Gate Drive Supply PFC Output Voltage Control PFC Over-Voltage Input Voltage Feedback Input for PFC Error Amplifier Output for PFC Voltage Feedback Loop Input AC Current OVP 17 FBPFC 18 VEA 19 IAC 20 (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) -3- www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A BLOCK DIAGRAM (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) -4- www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A ABSOLUTE MAXIMUM RATINGS Symbol VVDD IAC VHigh VLow PD TJ TSTG RJC TL VESD,HBM VESD,MM Parameter DC Supply Voltage* Input AC Current OPWM, OPFC, IAC Others Power Dissipation at TA < 50C Operating Junction Temperature Storage Temperature Range Thermal Resistance (Junction-to-Case) Lead Temperature (Wave Soldering or Infrared, 10 Seconds) Electrostatic Discharge Capability, Human Body Model Electrostatic Discharge Capability, Machine model Value 25 2 -0.3 to +25.0 -0.3 to +7.0 1.15 -40 to +125 -55 to +150 23.64 260 4.5 250 Unit V mA V V W C C C/W C KV V *All voltage values, except differential voltages, are given with respect to GND pin. *Stresses beyond those listed under "absolute maximum ratings" may cause permanent damage to the device. RECOMMENDED OPERATING CONDITIONS Symbol TA Parameter Operating Ambient Temperature* Value -20 to +85 Unit C *For proper operation. ELECTRICAL CHARACTERISTICS VDD=15V, TA=25C unless otherwise noted. VDD Section Symbol VDD-OP IDD-ST IDD-OP VDD-ON VDD-OFF VDD-OVP tD-VDDOVP Parameter Continuously Operating Voltage Start-up Current Operating Current Start Threshold Voltage Minimum Operating Voltage VDD OVP Threshold Debounce Time of VDD OVP Test Conditions 0V < VDD < VDD-ON VDD=15V; OPFC, OPWM open; RI=24K Min. Typ. 10 6 Max. 20 25 10 13 11 25.5 25 Unit V A mA V V V s 11 9 23.5 8 12 10 24.5 Oscillator Section Symbol FOSC RI RIOPEN RISHORT Parameter PWM Frequency RI Pin Resistance Range RI Pin Open Protection If RI > RIopen , SG6901A Turns Off RI Pin Short Protection If RI < RIshort , SG6901A Turns Off Test Conditions RI=24K Min. 62 15.6 Typ. 65 Max. 68 47.0 Unit KHz K K K 200 2 (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) -5- www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A VRMS for UVP and RANGE Symbol VRMS-UVP-1 VRMS-UVP-2 tD-PWM tUVP VRMS-H VRMS-L tRANGE VOL IOH Parameter RMS AC Voltage Under-Voltage Protection Threshold (with tUVP delay) Recovery Level on VRMS When UVP Occurs, Interval from PFC Off to PWM Off Under-Voltage Protection Delay Time* High VRMS Threshold for RANGE Comparator Low VRMS Threshold for RANGE Comparator Range-Enable Delay Time Output Low Voltage of RANGE Pin Output High Leakage Current of RANGE Pin Test Conditions Min. 0.75 VRMS-UVP-1 + 0.16V tUVP-Min+9 150 1.90 1.55 140 Typ. 0.8 VRMS-UVP-1 + 0.18V Max. 0.85 VRMS-UVP-1 + 0.2V tUVP-Min+1 4 Unit V V ms ms V V ms V nA 195 1.95 1.60 170 240 2.00 1.65 200 0.5 50 Io=1mA RANGE=5V * No delay for start-up. PFC Stage Voltage Error Amplifier Symbol VREF Av Zo OVPPFC OVPPFC tOVP-PFC VFBPFC-H GFBPFC-H VFBPFC-L GFBPFC-L IFBPFC-L IFBPFC-H UVPFBPFC tUVP-FBPFC Parameter Reference Voltage Open-Loop Gain Output Impedance PFC Over-Voltage Protection (OVP Pin) PFC Feedback Voltage Protection Hysteresis Debounce Time of PFC OVP Clamp-High Feedback Voltage Clamp-High Gain Clamp-Low Feedback Voltage Clamp-Low Gain Maximum Source Current Maximum Sink Current PFC Feedback Under-Voltage Protection Debounce Time of PFC UVP Test Conditions Min. 2.95 Typ. 3.00 60 110 Max. 3.05 Unit V dB K 3.20 60 40 3.10 2.75 1.5 70 0.35 40 3.25 90 70 3.15 0.5 2.85 6.5 2.0 110 0.40 70 3.30 120 120 3.20 2.90 V mV s V A/mV V mA/mV mA A 0.45 120 V s Current Error Amplifier Symbol VOFFSET AI BW CMRR VOUT-HIGH VOUT-LOW IMR1, IMR2 IL IH Parameter Input Offset Voltage ((-) > (+)) Open-Loop Gain Unit Gain Bandwidth Common Mode Rejection Ratio Output High Voltage Output Low Voltage Reference Current Source Maximum Source Current Maximum Sink Current Test Conditions Min. Typ. 8 60 1.5 Max. Unit mV dB MHz dB V VCM=0 to +1.5V 3.2 70 0.2 V A mA mA RI=24K (IMR=20+IRI*0.8) 50 3 0.25 70 (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) -6- www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A Peak Current Limit Symbol IP VPK tPD-PFC tLEB-PFC Parameter Constant Current Output Peak Current Limit Threshold Voltage Cycle-by-Cycle Limit (VSENSE < VPK) Propagation Delay Leading-Edge Blanking Time Test Conditions RI=24K VRMS=1.05V VRMS=3V Min. 90 0.15 0.35 270 Typ. 100 0.20 0.40 350 Max. 110 0.25 0.45 200 450 Unit A V V ns ns Multiplier Symbol IAC IMO-max IMO-1 IMO-2 VIMP Parameter Input AC Current Maximum Multiplier Current Output Multiplier Current Output (Low-line, High-power) Multiplier Current Output (High-line, High-power) Voltage of IMP Open Test Conditions Multiplier Linear Range RI=24K VRMS=1.05V; IAC=90A; VEA=7.5V; RI=24K VRMS=3V; IAC=264A; VEA=7.5V; RI=24K Min. 0 Typ. 250 Max. 360 Unit A A 200 65 3.4 250 85 3.9 280 A A 4.4 V PFC Output Driver Symbol VZ VOL-PFC tPFC VOH-PFC tR-PFC tF-PFC DCYMAX Parameter Output Voltage Maximum (Clamp) Output Voltage Low Interval OPFC Lags Behind OPWM at Start-up Output Voltage High Rising Time Falling Time Maximum Duty Cycle Test Conditions VDD=20V VDD=15V; IO=100mA Min. Typ. 16 Max. 18 1.5 Unit V V ms V 9.0 VDD=13V; IO=100mA VDD=15V; CL=5nF; O/P=2V to 9V VDD=15V; CL=5nF; O/P=9V to 2V 8 40 40 93 11.5 14.0 70 60 120 110 98 ns ns % PWM Stage FBPWM Symbol Av-PWM ZFB IFB FBOPEN-LOOP tOPEN-PWM tOPEN-PWM-Hiccup Parameter FB to Current Comparator Attenuation Input Impedance Maximum Source Current PWM Open-Loop Protection voltage PWM Open-Loop Protection Delay Time Interval of PWM Open-Loop Protection Reset Test Conditions Min. 2.5 4 0.8 4.2 45 450 Typ. 3.1 5 1.2 4.5 56 600 Max. 3.5 7 1.5 4.8 70 750 Unit V/V K mA V ms ms (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) -7- www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A PWM-Current Sense Symbol tPD-PWM VLIMIT-1 VLIMIT-2 tLEB-PWM VSLOPE Parameter Propagation Delay to Output Peak Current Limit Threshold Voltage1 Peak Current Limit Threshold Voltage2 Leading-Edge Blanking Time Slope Compensation Test Conditions VDD=15V,OPWM<=9V RANGE=Open RANGE=Ground VS=VSLOPE x (Ton/T) VS: Compensation Voltage Added to Current Sense Min. 60 0.65 0.60 270 0.45 Typ. 0.70 0.65 350 0.50 Max. 120 0.75 0.70 450 0.55 Unit ns V V ns V PWM Output Driver Symbol VZ-PWM VOL-PWM VOH-PWM tR-PWM tF-PWM DCYMAXPWM Parameter Output Voltage Maximum (Clamp) Output Voltage Low Output Voltage High Rising Time Falling Time Maximum Duty Cycle Test Conditions VDD=20V VDD=15V; IO=100mA VDD=13V; IO=100mA VDD=15V; CL=5nF; O/P=2V to 9V VDD=15V; CL=5nF; O/P=9V to 2V Min. Typ. 16 Max. 18 1.5 Unit V V V 8 30 30 73 60 50 78 120 110 83 ns ns % OTP Section Symbol IOTP VOTP-ON VOTP-OFF tOTP Parameter OTP Pin Output Current Recovery Level on OTP OTP Threshold Voltage OTP Debounce Time Test Conditions RI=24K Min. 90 1.35 1.15 8 Typ. 100 1.40 1.20 Max. 110 1.45 1.25 25 Unit A V V s Soft-Start Section Symbol ISS RD Parameter Constant Current Output for Soft-Start Discharge RDSON Test Conditions RT=24K Min. 44 Typ. 50 470 Max. 56 Unit A (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) -8- www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A TYPICAL CHARACTERISTICS S tart-Up C urrent (ID D -S T ) vs Temperature 25 20 11.0 10.6 Minimum Operating Voltage (V D D -O F F ) vs Temperature ID D -S T (uA) V D D -O F F (V) -40 -25 -10 5 20 35 50 65 80 95 110 125 15 10 5 0 10.2 9.8 9.4 9.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () Temperature ( ) Operating C urrent (ID D -O P ) vs Temperature 10.0 8.8 68 67 66 64 63 62 PWM Frequency (F OS C ) vs Temperature ID D -O P (mA) 7.6 6.4 5.2 4.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 F OS C (KHz) -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () Temperature ( ) S tart Threshold Voltage (V D D -O N ) vs Temperature 13.0 12.6 V DD Over Voltage Protection (V D D -O VP ) vs 25.5 25.1 Temperature V D D -O N (V ) 12.2 11.8 11.4 11.0 -40 -25 -10 5 20 35 50 65 80 95 110 125 V D D -O VP (V) 24.7 24.3 23.9 23.5 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () Temperature ( ) (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) -9- www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller Hig h VR MS Th resho ld fo r R ANGE C om p arator (V R M S - H ) v s Tem p eratur e SG6901A Reference V oltage (V R E F ) vs Temperature 3.05 3.03 2.00 1.98 VR M S - H (V ) V R E F (V) 1.96 1.94 1.92 1.90 -40 -25 -10 5 20 35 50 65 80 95 110 125 3.01 2.99 2.97 2.95 -40 -25 -10 5 20 35 50 65 80 95 110 125 Tem perature () Temperature () Low V RMS Thres hold for RANG E C omparator 1.65 1.63 Ris ing Time (tR -P F C ) vs Temperature 120 104 (V R M S -L ) vs Temperature tR -P F C (ns ) V R M S -L (V) 1.61 1.59 1.57 1.55 -40 -25 -10 5 88 72 56 40 Temperature ( ) 20 35 50 65 80 95 110 125 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () P F C Over V oltage P rotection (OVP P F C ) vs Temperature 3.30 3.28 96 110 F alling Time (tF -P F C ) vs Temperature OVP PF C (V) tF -P F C (ns) -40 -25 -10 5 20 35 50 65 80 95 110 125 3.26 3.24 3.22 3.20 82 68 54 40 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( ) Temperature () (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) - 10 - www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller Maximum Duty C ycle (DC Y M AX ) vs Temperature 98 97 0.75 0.73 SG6901A P eak Current Limit Threshold V oltage 1 (V L IMIT -1) vs Temperature DC Y M AX (% ) 96 95 94 93 -40 -25 -10 5 20 35 50 65 80 95 110 125 V LIM IT -1 (V ) 0.71 0.69 0.67 0.65 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( ) Temperature () P WM Open Loop P rotection Voltage (F B O P E N -L O O P ) vs Temperature 4.80 0.70 0.68 Peak C urrent Limit Threshold Voltage 2 (V LIM IT -2) vs Temperature F B O P E N -L O OP (V) 4.68 V LIM IT -2 (V) -40 -25 -10 5 20 35 50 65 80 95 110 125 4.56 4.44 4.32 4.20 0.66 0.64 0.62 0.60 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature () Temperature ( ) PW M Open Loop Protection Delay Tim e (t O P E N - P W M ) vs 70 65 Ris ing Time (tR -P WM ) vs Temperature 120 102 Tem perature tOP EN - P W M (m s ) tR -P WM (ns ) 60 55 50 45 -40 -25 -10 5 20 35 50 65 80 95 110 125 84 66 48 30 -40 -25 -10 5 20 35 50 65 80 95 110 125 Tem perature () Temperature () (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) - 11 - www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller F alling Time (tF -P WM ) vs Temperature 110 94 78 62 46 30 -40 -25 -10 5 20 35 50 65 80 95 110 125 SG6901A PWM Maximum Duty C ycle (DC Y M AXPW M ) vs 83 81 79 77 75 73 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature Temperature () DC Y M AXP WM (% ) tF -P W M (ns ) Temperature ( ) PWM Maximum Duty C ycle (DC Y M AXP WM ) vs 83 81 79 77 75 73 -40 -25 -10 5 20 35 50 65 80 95 110 125 OTP Thres hold Voltage (V O T P -O F F ) vs Temperature 1.25 1.23 Temperature DC Y M AXPW M (% ) V OT P-O F F (V) 1.21 1.19 1.17 1.15 -40 -25 -10 5 20 35 50 65 80 95 110 125 Temperature ( ) Temperature ( ) (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) - 12 - www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A OPERATION DESCRIPTION SG6901A is a highly integrated PFC/PWM combination controller. Many functions and protections are built in to provide a compact design. The following sections describe the operation and function. PFC Output Voltage Control (RANGE) For an universal input (90 ~ 264VAC) power supply applying active boost PFC and flyback as a second stage, the output voltage of PFC is usually designed around 250V at low line and 390V at high line. This can improve the efficiency at low-line input. The RANGE pin (open-drain structure) is used for the two-level output voltage setting. Figure 2 shows the RANGE output that programs the PFC output voltage. The RANGE output is shorted to ground when the VRMS voltage exceeds VRMS-H (1.95V) while it is of high impedance (open) whenever the VRMS voltage drops below VRMS-L (1.6V). The output voltages can be designed using equations: Range = Open VO = Range = Ground VO R A + RB x 3V RB Switching Frequency and Current Sources The switching frequency of SG6901A can be programmed by the resistor RI connected between RI pin and GND. The relationship is: FOSC = 1560 (kHz) ----------RI (k ) (1) For example, a 24K resistor RI results in a 65KHz switching frequency. Accordingly, a constant current, IT, flows through RI: IT = 1.2V (mA) ---------------RI (k ) (2) R + (R B // R C ) =A x 3V (R B // R C ) ---- (3) IT is used to generate internal current reference. Line Voltage Detection (VRMS) Figure 1 shows a resistive divider with low-pass filtering for line-voltage detection on the VRMS pin. The VRMS voltage is used for the PFC multiplier, brownout protection, and range control. For brownout protection, the SG6901A is disabled with 195ms delay time if the voltage VRMS drops below 0.8V. For PFC multiplier and range control, refer to section below for more details. FIG.2 Range Control Two-Level Output Voltage FIG.1 Line Voltage Detection Circuit (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) - 13 www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A Through the differential amplification of the signal across RS, better noise immunity is achieved. The output of IEA is compared with an internal sawtooth and the pulse width for PFC is determined. Through the average current-mode control loop, the input current IS is proportional to IMO: Interleave Switching The SG6901A uses interleaved switching to synchronize the PFC and flyback stages, which reduces switching noise and spreads the EMI emissions. Figure 3 shows off-time, TOFF, inserted between the turn-off of the PFC gate drive and the turn-on of the PWM. IMO x R 2 = IS x R S -------------------- (5) According to Equation 5, the minimum value of R2 and maximum of RS can be determined since IMO should not exceed the specified maximum value. There are different concerns in determining the value of the sense resistor RS. The value of RS should be small enough to reduce power consumption, but large enough to maintain the resolution. A current transformer (CT) may be used to improve efficiency of high-power converters. To achieve good power factor, the voltage for VRMS and VEA should be kept as constant as possible, according to Equation 4. Good RC filtering for VRMS and narrow bandwidth (lower than the line frequency) for voltage loop are suggested for better input current shaping. The transconductance error amplifier has output impedance ZO and a capacitor CEA (1F ~ 10F) should be connected to ground. This establishes a dominant pole f1 for the voltage loop: FIG.3 Interleaved Switching Pattern PFC Operation The purpose of a boost active power factor corrector (PFC) is to shape the input current of a power supply. The input current waveform and phase follow that of the input voltage. Average-current-mode control is utilized for continuous-current-mode operation for the PFC booster. With the innovative multi-vector control for voltage loop and switching charge multiplier-divider for current reference, excellent input power factor is achieved with good noise immunity and transient response. Figure 4 shows the total control loop for the average-current-mode control circuit of SG6901A. The current source output from the switching charge multiplier-divider can be expressed as: f1 = 1 2 x Z O x CEA ---------------------- (6) The average total input power can be expressed as: Pin = VIN (rms) x IIN (rms) VRMS x IMO I AC x VEA VRMS 2 IMO = K x IAC x VEA (A) -----------VRMS 2 (4) VRMS x ---------------- (7) As shown in Figure 4, the current output from IMP pin, IMP, is the summation of IMO and IMR1. IMR1 and IMR2 are identical fixed-current sources used to pull high the operating point of the IMP and IPFC pins since the voltage across RS goes negative with respect to ground. Constant current sources IMR1 and IMR2 are typically 60A. VRMS x Vin x VEA R AC VRMS 2 V = 2 x EA R AC From Equation 7, VEA, the output of the voltage error amplifier, controls the total input power and the power delivered to the load. (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) - 14 - www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A FIG.4 Average-Current-Mode Control Loop Multi-Vector Error Amplifier Although the PFC stage has a low bandwidth voltage loop for better input power factor, the innovative multi-vector error amplifier provides a fast transient response to clamp the overshoot and undershoot of the PFC output voltage. Figure 5 shows the block diagram of the multi-vector error amplifier. When the variation of the feedback voltage exceeds 5% of the reference voltage, the transconductance error amplifier adjusts its output impedance to increase the loop response. PFC Over-Voltage Protection Using a voltage divider from the output of PFC to the OVP pin, the PFC output voltage can be safely protected. Once the voltage on the OVP pin is over OVPPFC, the OPFC is disabled. THE OPFC is not enabled again until the OVP voltage falls below OVPPFC. Cycle-by-Cycle Current Limiting SG6901A provides cycle-by-cycle current limiting for both PFC and PWM stages. Figure 6 shows the peak current limit for the PFC stage. The PFC gate drive is terminated once the voltage on the ISENSE pin goes below VPK. The voltage of VRMS determines the voltage of VPK. The relationship between VPK and VRMS is shown in Figure 6. The amplitude of the constant current, IP, is determined by the internal current reference according to the equation: IP = 2 x FIG. 5 Multi-Vector Error Amplifier (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) - 15 - 1.2V --------------------RI (8) www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A Limited Power Control Every time the output of power supply is shorted or overloaded, the FBPWM voltage increases. If the FBPWM voltage is higher than a designed threshold, FBOPEN-LOOP (4.5V) for longer than tOPEN-PWM (56ms), the OPWM is turned off. As long as the voltage on the VDD pin is larger than VDD-OFF (minimum operating voltage), the OPWM is not enabled. This protection is reset every tOPEN-PWM-Hiccup interval. A low-frequency hiccup mode protection prevents the power supply from being overheated under overloading conditions. FIG. 6 VRMS Controlled Current Limiting The peak current of the ISENSE is given by (VRMS<1.05V): ISENSE_peak = (IP x RP ) - 0.2V RS ------------------ (9) Over-Temperature Protection SG6901A provides an OTP pin for over-temperature protection. A constant current is output from this pin. If RI is equal to 24K, the magnitude of the constant current is 100A. An external NTC thermistor must be connected from this pin to ground, as shown as Figure 8. When the OTP voltage drops below VOTP-OFF (1.2V), SG6901A is disabled and does not recover until OTP voltage exceeds VOTP-ON (1.4V). Flyback PWM and Slope Compensation As shown in Figure 7, peak-current-mode control is utilized for flyback PWM. The SG6901A inserts a synchronized 0.5V ramp at the beginning of each switching cycle. This built-in slope compensation ensures stable operation for continuous current-mode operation. FIG. 8 OTP Function FIG. 7 Peak Current Control Loop When the IPWM voltage, across the sense resistor, reaches the threshold voltage (0.9V), the OPWM is turned off after a small propagation delay tPD-PWM. To improve stability or prevent sub-harmonic oscillation, a synchronized positive-going ramp is inserted at every switching cycle. Soft-Start During start-up of PWM stage, the SS pin charges an external capacitor with a constant current source. The voltage on FBPWM is clamped by the SS voltage during start-up. In the event of a protected condition and/or PWM disabled, the SS pin quickly discharges. Gate Drivers SG6901A output stage is a fast totem-pole gate driver. The output driver is clamped by an internal 18V Zener diode to protect the external power MOSFET. (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) - 16 - www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A PACKAGE INFORMATION 20 PINS - PLASTIC SOP (S) E H Detail A 1 b 10 e F c A D y A2 A1 L Detail A Dimensions: Millimeter Min. 2.362 0.101 2.260 Inch Min. 0.093 0.004 0.089 Symbol A A1 A2 b c D E e H L F y Typ. Max. 2.642 0.305 2.337 Typ. Max. 0.104 0.012 0.092 0.406 0.203 12.598 7.391 1.270 10.007 0.406 0.508X45 0 0.101 8 0 10.643 1.270 0.394 0.016 12.903 7.595 0.496 0.291 0.016 0.008 0.508 0.299 0.050 0.419 0.050 0.020X45 0.004 8 (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) - 17 - www.sg.com.tw * www.fairchildsemi.com September 26, 2007 Product Specification PFC / Flyback PWM Controller SG6901A (c) System General Corp. Version 1.0.1 (IAO33.0062.B0) - 18 - www.sg.com.tw * www.fairchildsemi.com September 26, 2007 |
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