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STA517B
60 V 6 A quad power half bridge
Features

Minimum input output pulse width distortion 200 m RdsON complementary DMOS output stage CMOS compatible logic inputs Thermal protection Thermal warning output Under voltage protection Power SO36 slug up
Description
STA517B is a monolithic quad half bridge stage in Multipower BCD Technology. The device can be used as dual bridge or reconfigured, by connecting CONFIG pin to Vdd pin, as single bridge with double current capability, and as half bridge (Binary mode) with half current capability. The device is particularly designed to make the output stage of a stereo all-digital high efficiency (DDXTM) amplifier capable to deliver 175 + 175 W @ THD = 10 % at Vcc 54 V output power on 8 load and 350 W @ THD = 10 % at Vcc 54 V on 4 load in single BTL configuration. The input pins have threshold proportional to VL pin voltage.
Table 1.
Device summary
Part number STA517B STA517B13TR Package Power SO36 slug up Power SO36 slug up Packaging Tube Tape and reel
March 2007
Rev 2
1/13
www.st.com 1
Contents
STA517B
Contents
1 2 3 4 5 6 7 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 Pin lists . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Power supply and control sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Mechanical and package data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
2/13
STA517B
Introduction
1
Introduction
Figure 1. Application circuit (dual BTL)
VCC1A IN1A IN1A +3.3V VL CONFIG PWRDN R57 10K R59 10K C58 100nF TH_WAR IN1B VDD VDD VSS VSS C58 100nF C53 100nF C60 100nF IN2A VCCSIGN VCCSIGN IN2A GND-Reg GND-Clean 21 22 33 34 M17 35 8 9 36 31 20 19 M16 M15 REGULATORS 7 VCC2A C32 1F OUT2A OUT2A 6 GND2A PWRDN FAULT 23 24 25 27 26 TRI-STATE PROTECTIONS & LOGIC M5 28 30 M4 13 M2 29 M3 15 17 16 C30 1F OUT1A OUT1A 14 GND1A C52 330pF +VCC C55 1000F
L18 22H C20 100nF R98 6 C99 100nF C23 470nF C101 100nF
8
12
VCC1B C31 1F OUT1B OUT1B GND1B R63 20 R100 6 C21 100nF L19 22H
11 10
TH_WAR IN1B
L113 22H C110 100nF C109 330pF R103 6 R104 20
4
VCC2B C33 1F OUT2B OUT2B
R102 6 C111 100nF
3 2
C107 100nF C108 470nF C106 100nF
8
IN2B
IN2B GNDSUB
32 M14
L112 22H
1
5
GND2B
D00AU1148B
3/13
Pin lists
STA517B
2
Pin lists
Table 2.
Number 1 2, 3 4 5 6 7 8, 9 10, 11 12 13 14 15 16, 17 18 19 20 21, 22 23 24 25 26 27 28 29 30 31 32 33, 34 35, 36
Pin function
Pin GND-SUB OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT1B VCC1B GND1B GND1A VCC1A OUT1A NC GND-CLEAN GND-REG VDD VL CONFIG PWRDN TRI-STATE FAULT TH-WAR IN1A IN1B IN2A IN2B VSS VCC SIGN Substrate ground Output half bridge 2B Positive supply Negative supply Negative supply Positive supply Output half bridge 2A Output half bridge 1B Positive supply Negative supply Negative supply Positive supply Output half bridge 1A Not connected Logical ground Ground for regulator Vdd 5 V regulator referred to ground High logical state setting voltage Configuration pin Stand-by pin Hi-Z pin Fault pin advisor Thermal warning advisor Input of half bridge 1A Input of half bridge 1B Input of half bridge 2A Input of half bridge 2B 5 V regulator referred to +Vcc Signal positive supply Description
4/13
STA517B Table 3.
Pin name FAULT FAULT
(1)
Pin lists Functional pin status
Logical value 0 1 0 1 0 1 0 1 0 1 Status Fault detected (short circuit or thermal for example) Normal operation All powers in Hi-Z state Normal operation Low absorption Normal operation Temperature of the IC =130 oC Normal operation Normal operation OUT1A=OUT1B; OUT2A=OUT2B (IF IN1A = IN1B; IN2A = IN2B)
TRI-STATE TRI-STATE PWRDN PWRDN THWAR THWAR(1) CONFIG CONFIG(2)
1. The pin is open collector. To have the high logic value, it needs to be pulled up by a resistor. 2. CONFIG = 1 means connect Pin 24 (CONFIG) to Pins 21, 22 (Vdd)
Figure 2.
Pin connection
VCCSign VCCSign VSS VSS IN2B IN2A IN1B IN1A TH_WAR FAULT TRI-STATE PWRDN CONFIG VL VDD VDD GND-Reg GND-Clean
36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 20 19
D01AU1273
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18
GND-SUB OUT2B OUT2B VCC2B GND2B GND2A VCC2A OUT2A OUT2A OUT1B OUT1B VCC1B GND1B GND1A VCC1A OUT1A OUT1A N.C.
5/13
Electrical characteristics
STA517B
3
Table 4.
Symbol VCC Vmax Top Tstg, Tj
Electrical characteristics
Absolute maximum ratings
Parameter DC supply voltage (Pins 4,7,12,15) Maximum voltage on pins 23 to 32 Operating temperature range Storage and junction temperature 60 5.5 0 to 70 -40 to 150 Value V V C C Unit
Table 5.
Symbol Tj-case TjSD Twarn thSD
Thermal data
Parameter Thermal resistance junction to case (thermal pad) Thermal shut-down junction temperature Thermal warning temperature Thermal shut-down hysteresis Min. 1 150 130 25 Typ. Max. 2.5 Unit C/W C C C
Table 6.
Symbol RdsON Idss gN gP Dt_s Dt_d td ON td OFF tr tf VCC VIN-High VIN-Low IIN-H IIN-L
Electrical characteristics (VL= 3.3 V; Vcc = 50 V; Tamb = 25 C unless otherwise specified)
Parameter Power Pchannel/Nchannel MOSFET RdsON Power Pchannel/Nchannel leakage Idss Power Pchannel RdsON matching Power Nchannel RdsON matching Low current dead time (static) High current dead time (dynamic) Turn-on delay time Turn-off delay time Rise time Fall time Supply operating voltage High level input voltage Low level input voltage High level Input current Low level input current Pin voltage = VL Pin voltage = 0.3 V VL/2 -300mV 1 1 Id=1A Id=1A see Figure 4 L=22H, C = 470nF Rl = 8 Id=4.5A , see Figure 5 Resistive load Resistive load Resistive load see Figure 4 Resistive load see Figure 4 10 95 95 10 20 50 100 100 25 25 56 VL/2 +300mV
ns ns ns
Test conditions Id=1A
Min.
Typ. 200
Max. 240 100
Unit m
A % % ns ns
ns
V V V A A
6/13
STA517B Table 6.
Symbol
Electrical characteristics Electrical characteristics (continued) (VL= 3.3 V; Vcc = 50 V; Tamb = 25 C unless otherwise specified)
Parameter Test conditions VL= 3.3 V VL = 3.3 V VL = 3.3 V 0.8 1.7 3 Min. Typ. 35 Max.
Unit A V
IPWRDN-H High level PWRDN pin input current VLow VHigh IVCCPWRDN
Low logical state voltage VL (pin PWRDN, TRISTATE)(seeTable 7) High logical state voltage VH (pin PWRDN, TRISTATE)(seeTable 7)
V
Supply current from Vcc in power down PWRDN = 0 Output current pins FAULT -TH-WARN when FAULT CONDITIONS Supply current from Vcc in Tristate
mA
IFAULT IVCC-hiz
Vpin = 3.3 V Tristate = 0 Input pulse width = 50 % duty Switching frequency = 384 Khz; No LC filters 6.5
1 22
mA
mA mA
IVCC
Supply current from Vcc in operation both channel switching)
70
IOUT-SH VUV VOV tpw_min
Over current protection threshold Isc (short circuit current limit)1(1) Under voltage protection threshold Over voltage protection threshold Output minimum pulse width No load
8 7
10
A
V
60 25
70 40
V ns
1. See specific application note number: AN1994.
Table 7.
VLow, VHigh variation with VL
VL 2.7 3.3 5 VLow min 0.7 0.8 0.85 VHigh max 1.5 1.7 1.85 Unit V V V
Table 8.
Tristate 0 1 1 1 1
Logic truth table (see Figure 2)
INxA x 0 0 1 1 INxB x 0 1 0 1 Q1 OFF OFF OFF ON ON Q2 OFF OFF ON OFF ON Q3 OFF ON ON OFF OFF Q4 OFF ON OFF ON OFF Output mode Hi-Z DUMP NEGATIVE POSITIVE Not used
7/13
Power supply and control sequencing
STA517B
4
Power supply and control sequencing
To guarantee correct operation and reliability, a correct turn on/off sequence must be followed. Figure 3 shows the correct power on sequence. Figure 3.
V
Correct power-on sequence
Vcc
VL Vcc > VL t
PWRDN
t
IN
t
Vcc must turn on before VL in order to prevent uncontrolled current flowing through an internal protection diode connected between VL (logic supply) and Vcc (high power supply). Failure to do so could result in damage to the device. PWRDN must be released after VL is switched on. An input signal can then be sent to the power stage.
8/13
STA517B
Test
5
Test
Figure 4. Test circuit
OUTxY Vcc (3/4)Vcc Low current dead time = MAX(DTr,DTf) (1/2)Vcc (1/4)Vcc +Vcc t Duty cycle = 50%
M58
DTr OUTxY
M57
DTf
INxY
R 8
+ -
V67 = vdc = Vcc/2
D03AU1458
gnd
Figure 5.
Current dead time test circuit
High Current Dead time for Bridge application = ABS(DTout(A)-DTin(A))+ABS(DTOUT(B)-DTin(B)) +VCC Duty cycle=A Duty cycle=B
DTout(A) M58 Q1 OUTxA Rload=8 L67 22 C69 470nF DTout(B) L68 22 C70 470nF Q2 OUTxB M64
DTin(A) INxA
DTin(B) INxB
Iout=4.5A M57 Q3
Iout=4.5A Q4 M63
C71 470nF
Duty cycle A and B: Fixed to have DC output current of 4.5A in the direction shown in figure
D00AU1162
9/13
Test Figure 6.
STA517B Typical single BTL configuration to obtain 350 W @ THD 10 %, RL = 4 , VCC = 54 V (a)
+3.3V 100nF VL GND-Clean GND-Reg 10K 100nF X7R VDD VDD CONFIG TH_WAR nPWRDN 10K TH_WAR PWRDN FAULT TRI-STATE 100nF IN1A IN1B IN2A IN2B VSS VSS 100nF X7R 100nF X7R Add. VCCSIGN VCCSIGN GNDSUB 23 18 17 16 11 10 N.C. 12H 19 20 OUT1A OUT1A OUT1B OUT1B OUT2A 9 8 OUT2B 3 2 VCC1A 1F X7R OUT2B 12H +36V 2200F 63V OUT2A 330pF 22 1/2W 6.2 1/2W 6.2 1/2W 100nF FILM 100nF X7R 680nF FILM 100nF X7R 100nF FILM
21 22 24 28 25 27 26
4
15
29 30 31 32 33 34
12
VCC1B VCC2A
IN1A
7
+36V 1F X7R
IN1B
4 14
VCC2B GND1A GND1B
35
13 GND2A
36 1
6 GND2B 5
D04AU1545
Figure 7.
Typical quad half bridge configuration
VCC1P IN1A IN1A +3.3V VL CONFIG PWRDN R57 10K R59 10K C58 100nF TH_WAR IN1B VDD VDD VSS VSS C58 100nF C53 100nF C60 100nF IN2A VCCSIGN VCCSIGN IN2A GND-Reg GND-Clean 21 22 33 34 M17 35 8 9 36 31 20 19 M16 M15 OUTPR OUTPR 6 PGND2P R43 20 C43 330pF L13 22H C73 100nF R53 6 C83 100nF R66 5K REGULATORS 7 VCC2P PWRDN FAULT 23 24 25 27 26 TRI-STATE PROTECTIONS & LOGIC M5 28 30 M4 13 M2 29 M3 15 17 16 OUTPL OUTPL 14 PGND1P R41 20 C41 330pF L11 22H C71 100nF R51 6 C81 100nF R62 5K R61 5K +VCC C21 2200F C31 820F
C91 1F
4
12
VCC1N C51 1F OUTNL OUTNL PGND1N C61 100nF L12 22H R42 20 C42 330pF C72 100nF R52 6 C82 100nF R64 5K
11 10
TH_WAR IN1B
R63 5K
C32 820F
C92 1F
4
R65 5K
C33 820F
C93 1F
4
4
VCC2N C52 1F OUTNR OUTNR C62 100nF L14 22H R44 20 C44 330pF C74 100nF R54 6 C84 100nF R68 5K
3 2
IN2B
R67 5K
C34 820F
IN2B GNDSUB
32 M14
1
5
PGND2N
C94 1F
4
D03AU1474
For more information, refer to the application note "ST50X and STA51X digital power amplifiers".
a. A PWM modulator as driver is required. This result was obtained using the STA30X+STA50X demo board.
10/13
STA517B
Mechanical and package data
6
Mechanical and package data
Figure 8. Power SO36 (slug up) mechanical data and package dimension
mm TYP. inch TYP.
DIM. A A2 A4 A5 a1 b c D D1 D2 E E1 E2 E3 E4 e e3 G H h L N s
MIN. 3.25 3.1 0.8 0.030 0.22 0.23 15.8 9.4
MAX. 3.43 3.2 1 -0.040 0.38 0.32 16 9.8
MIN. 0.128 0.122 0.031 0.0011 0.008 0.009 0.622 0.37
MAX. 0.135 0.126 0.039 -0.0015 0.015 0.012 0.630 0.38
OUTLINE AND MECHANICAL DATA
0.2
0.008
1 13.9 10.9 5.8 2.9 0.65 11.05 0 15.5 0.8 0.075 15.9 1.1 1.1 10 8 0 0.61 0.031 14.5 11.1 2.9 6.2 3.2 0.547 0.429 0.228 0.114
0.039 0.57 0.437 0.114 0.244 1.259 0.026 0.435 0.003 0.625 0.043 0.043 10 8
PowerSO36 (SLUG UP)
(1) "D and E1" do not include mold flash or protusions. Mold flash or protusions shall not exceed 0.15mm (0.006") (2) No intrusion allowed inwards the leads.
7183931 D
11/13
Revision history
STA517B
7
Revision history
Table 9.
Date 01-Feb-2007 19-Mar-2007
Document revision history
Revision 1 2 Initial release Update to reflect product maturity. Changes
12/13
STA517B
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