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| 8 Bit Microcontroller TLCS-870/C Series TMP86C845UG TMP86C845UG The information contained herein is subject to change without notice. 021023 _ D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The Toshiba products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These Toshiba products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of Toshiba products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C The products described in this document may include products subject to the foreign exchange and foreign trade laws. 021023_F For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S (c) 2006 TOSHIBA CORPORATION All Rights Reserved Page 2 TMP86C845UG Difference between TMP86C845 and TMP86Cx47 series TMP86Cx47 series TMP86C847UG ROM RAM I/O port Package(Body size) Minumum command execution time Supply Voltage 8192bytes (MASK) 512bytes 35 pins LQFP44(10x10mm) TMP86CH47UG TMP86CH47AUG 16384bytes(MASK) 512bytes 35 pins LQFP44(10x10mm) 0.25sec at 16MHz 1.8V to 5.5V at 4.2MHz/32.768kHz 2.7V to 5.5V at 8.0MHz/32.768kHz 4.5V to 5.5V at 16MHz/32.768kHz 16-bit timer counter: 1ch 8-bit timer counter: 2ch 1ch 1ch 1ch Hi-Speed SIO : 1ch 4ch Analog-input : 8ch 6 kinds 16-bit timer counter: 1ch 8-bit timer counter: 2ch 1ch 1ch 1ch Hi-Speed SIO : 1ch 4ch Analog-input : 8ch 6 kinds 16-bit timer counter: 1ch 8-bit timer counter: 2ch 1ch 1ch 1ch Hi-Speed SIO : 1ch 4ch Analog-input : 8ch 6 kinds TMP86CM47UG TMP86CM47AUG 32768bytes(MASK) 1024bytes 35 pins LQFP44(10x10mm) TMP86C845 series TMP86C845UG 8192bytes(MASK) 256bytes 35 pins LQFP44(10x10mm) 0.5sec at 16MHz 2.7V to 5.5V at 8.0MHz/32.768kHz 8-bit timer counter: 2ch 1ch 1ch Hi-Speed SIO : 1ch Analog-input : 8ch 4 kinds P2 port and ,P00,P05,P06,P07, P10,P11,P12,P15 pins P3, P4 ports and P01,P02,P03,P04, P13,P14,P16,P17 pins RESET input only Timer counter Time base timer Watch dog timer UART SIO Key-on wakeup 10-bit AD converter Warming-up counter for releasing STOP mode Hysterisis input pin P0,P1,P2 ports P0,P1,P2 ports P0,P1,P2 ports I/O circuit CMOS input pin RESET P3,P4 ports P3,P4 ports P3,P4 ports pin Operating Temperature Package (P-LQFP44-1010-0.80A) Package (P-LQFP44-1010-0.80B) -40 to 85 Available N.A. Watch dog timer, Address trap and Systemclock reset output -40 to 85 (Note2) Available (86CH47) Available (86CH47A) -40 to 85 Available N.A. -40 to 85 Available N.A. Note 1: Please make sure to check the section "Pin Input/Output port" of TMP86C847/H47/M47 and TMP86C845. Note 2: With TMP86CH47AUG the operating temperature (Topr) is -20 to 85 when the supply voltage VDD is less than 2.0V. Page 3 TMP86C845UG Revision History Date 2006/6/13 2006/6/29 2006/6/29 2006/8/3 Revision 1 2 3 4 First Release Periodical updating.No change in contents. Periodical updating.No change in contents. Contents Revised Table of Contents TMP86C845UG 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. Operational Description 2.1 CPU Core Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Memory Address Map............................................................................................................................... 7 Program Memory (MaskROM).................................................................................................................. 7 Data Memory (RAM) ................................................................................................................................. 7 Clock Generator........................................................................................................................................ 8 Timing Generator .................................................................................................................................... 10 Operation Mode Control Circuit .............................................................................................................. 11 Single-clock mode Dual-clock mode STOP mode Configuration of timing generator Machine cycle 2.2 2.1.1 2.1.2 2.1.3 2.2.1 2.2.2 2.2.3 System Clock Controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 2.2.2.1 2.2.2.2 2.2.3.1 2.2.3.2 2.2.3.3 2.2.4.1 2.2.4.2 2.2.4.3 2.2.4.4 2.2.4 Operating Mode Control ......................................................................................................................... 16 STOP mode IDLE1/2 mode and SLEEP1/2 mode IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) SLOW mode 2.3 Reset Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 External Reset Input ............................................................................................................................... 29 Address trap reset .................................................................................................................................. 30 Watchdog timer reset.............................................................................................................................. 30 System clock reset.................................................................................................................................. 30 2.3.1 2.3.2 2.3.3 2.3.4 3. Interrupt Control Circuit 3.1 3.2 3.3 3.4 Interrupt latches (IL15 to IL2) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 33 Interrupt enable register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34 Interrupt Source Selector (INTSEL). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Interrupt acceptance processing is packaged as follows........................................................................ 37 Saving/restoring general-purpose registers ............................................................................................ 38 Using PUSH and POP instructions 3.2.1 3.2.2 Interrupt master enable flag (IMF) .......................................................................................................... 34 Individual interrupt enable flags (EF15 to EF4) ...................................................................................... 34 3.4.1 3.4.2 3.4.2.1 i 3.5 3.4.3 3.5.1 3.5.2 3.4.2.2 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Address Trap Interrupt (INTATRAP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 External Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Address error detection .......................................................................................................................... 41 Debugging .............................................................................................................................................. 41 Interrupt return ........................................................................................................................................ 40 Using data transfer instructions 3.6 3.7 3.8 4. Special Function Register (SFR) 4.1 SFR . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 5. I/O Ports 5.1 5.2 5.3 5.4 5.5 Port P0 (P07 to P00) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P1 (P17 to P10) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P2 (P22 to P20) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P3 (P37 to P30) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Port P4 (P47 to P40) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48 49 50 51 52 6. Time Base Timer (TBT) 6.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Configuration .......................................................................................................................................... 53 Control .................................................................................................................................................... 53 Function .................................................................................................................................................. 54 Configuration .......................................................................................................................................... 55 Control .................................................................................................................................................... 55 6.1.1 6.1.2 6.1.3 6.2.1 6.2.2 6.2 Divider Output (DVO) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 55 7. Watchdog Timer (WDT) 7.1 7.2 Watchdog Timer Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57 Watchdog Timer Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58 Malfunction Detection Methods Using the Watchdog Timer ................................................................... Watchdog Timer Enable ......................................................................................................................... Watchdog Timer Disable ........................................................................................................................ Watchdog Timer Interrupt (INTWDT)...................................................................................................... Watchdog Timer Reset ........................................................................................................................... Selection of Address Trap in Internal RAM (ATAS) ................................................................................ Selection of Operation at Address Trap (ATOUT) .................................................................................. Address Trap Interrupt (INTATRAP)....................................................................................................... Address Trap Reset ................................................................................................................................ 58 59 60 60 61 7.3 7.2.1 7.2.2 7.2.3 7.2.4 7.2.5 Address Trap . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 62 62 62 62 63 7.3.1 7.3.2 7.3.3 7.3.4 8. 8-Bit TimerCounter (TC3, TC4) 8.1 8.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 65 TimerCounter Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 66 ii 8.3 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 71 8-Bit Timer Mode (TC3 and 4) ................................................................................................................ 8-Bit Event Counter Mode (TC3, 4) ........................................................................................................ 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4)..................................................................... 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4).................................................................. 16-Bit Timer Mode (TC3 and 4) .............................................................................................................. 16-Bit Event Counter Mode (TC3 and 4) ................................................................................................ 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4).......................................................... 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) ............................................... Warm-Up Counter Mode......................................................................................................................... Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 8.3.9 71 72 72 75 77 78 78 81 83 8.3.9.1 8.3.9.2 9. Synchronous Serial Interface (SIO) 9.1 9.2 9.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 86 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 88 Serial clock ............................................................................................................................................. 88 Transfer bit direction ............................................................................................................................... 90 Transmit mode Receive mode Transmit/receive mode Transmit mode Receive mode Transmit/receive mode Clock source Shift edge 9.3.1.1 9.3.1.2 9.3.2.1 9.3.2.2 9.3.2.3 9.3.3.1 9.3.3.2 9.3.3.3 9.3.1 9.3.2 9.3.3 Transfer modes....................................................................................................................................... 91 10. 10-bit AD Converter (ADC) 10.1 10.2 10.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 103 Register configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 104 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107 Software Start Mode ........................................................................................................................... 107 Repeat Mode ...................................................................................................................................... 107 Register Setting ................................................................................................................................ 108 10.4 10.5 10.6 10.3.1 10.3.2 10.3.3 STOP/SLOW Modes during AD Conversion . . . . . . . . . . . . . . . . . . . . . . . . . . . 109 Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . 110 Precautions about AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 111 Analog input pin voltage range ........................................................................................................... 111 Analog input shared pins .................................................................................................................... 111 Noise Countermeasure ....................................................................................................................... 111 10.6.1 10.6.2 10.6.3 11. Input/Output Circuitry 11.1 11.2 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113 Input/Output Ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 114 12. Electrical Characteristics 12.1 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 iii 12.2 12.3 12.4 12.5 12.6 12.7 Recommended Operating Condition . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Recommended Oscillating Conditions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 117 118 119 120 120 121 13. Package Dimension This is a technical document that describes the operating functions and electrical specifications of the 8-bit microcontroller series TLCS-870/C (LSI). iv TMP86C845UG CMOS 8-Bit Microcontroller TMP86C845UG Product No. TMP86C845UG ROM (MaskROM) 8192 bytes RAM 256 bytes Package P-LQFP44-1010-0.80A FLASH MCU TMP86FH47AUG Emulation Chip TMP86C947XB 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C series - Instruction execution time : 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) - 132 types & 731 basic instructions 2. 15interrupt sources (External : 6 Internal : 9) 3. Input / Output ports (35 pins) Large current output: 19pins (Typ. 20mA), LED direct drive 4. Prescaler - Time base timer - Divider output function 5. Watchdog Timer 6. 8-bit timer counter : 2 ch - Timer, Event counter, Programmable divider output (PDO), Pulse width modulation (PWM) output, Programmable pulse generation (PPG) modes 7. High-Speed SIO: 1ch 8. 10-bit successive approximation type AD converter - Analog input: 8 ch 9. Clock operation 060116EBP * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. 021023_C * The products described in this document are subject to the foreign exchange and foreign trade laws. 021023_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S Page 1 1.1 Features TMP86C845UG Single clock mode Dual clock mode 10. Low power consumption operation STOP mode: Oscillation stops. (Battery/Capacitor back-up.) SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Release by falling edge of the source clock which is set by TBTCR 2.7 V to 5.5 V at 8MHz /32.768 kHz Release by Page 2 1.2 Pin Assignment VAREF AVDD AVSS P40 P41 P42 P43 P44 P45 P46 P47 34 35 36 37 38 39 40 41 42 43 44 VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 RESET Figure 1-1 Pin Assignment Page 3 (STOP/INT5) P20 (INT0) P00 (PDO4/PWM4/PPG4/TC4) P01 1 2 3 4 5 6 7 8 9 10 11 22 21 20 19 18 17 16 15 14 13 12 33 32 31 30 29 28 27 26 25 24 23 P37 (AIN7) P36 (AIN6) P35 (AIN5) P34 (AIN4) P33 (AIN3) P32 (AIN2) P31 (AIN1) P30 (AIN0) P10 (TC3/PDO3/PWM3) P11 (INT1) P12 (INT2) P13(DVO) P14 P15(INT3) P16 P17 P07(INT4) P06(SCK) P05(SI) P04(SO) P03 P02 TMP86C845UG 1.3 Block Diagram TMP86C845UG 1.3 Block Diagram Figure 1-2 Block Diagram Page 4 TMP86C845UG 1.4 Pin Names and Functions Table 1-1 Pin Names and Functions(1/2) Pin Name P07 INT4 P06 SCK Pin Number 17 Input/Output IO I IO IO IO I IO O IO IO IO I O IO I IO IO IO I IO IO O IO I IO I IO I O IO O PORT07 External interrupt 4 input PORT06 Serial clock input/output PORT05 Serial data input PORT04 Serial data output PORT03 PORT02 Functions 16 P05 SI P04 SO P03 P02 P01 TC4 PDO4/PWM4/PPG4 15 14 13 12 11 PORT01 TC4 input PDO4/PWM4/PPG4 output PORT00 External interrupt 0 input PORT17 PORT16 PORT15 External interrupt 3 input PORT14 PORT13 Divider Output PORT12 External interrupt 2 input PORT11 External interrupt 1 input PORT10 TC3 input PDO3/PWM3 output PORT22 Resonator connecting pins(32.768kHz) for inputting external clock PORT21 Resonator connecting pins(32.768kHz) for inputting external clock PORT20 External interrupt 5 input STOP mode release signal input PORT37 Analog Input7 PORT36 Analog Input6 PORT35 Analog Input5 P00 INT0 10 18 19 20 21 22 P17 P16 P15 INT3 P14 P13 DVO P12 INT2 P11 INT1 P10 TC3 PDO3/PWM3 23 24 25 P22 XTOUT 7 P21 XTIN P20 INT5 STOP 6 IO I IO I I IO I IO I IO I 9 P37 AIN7 P36 AIN6 P35 AIN5 33 32 31 Page 5 1.4 Pin Names and Functions TMP86C845UG Table 1-1 Pin Names and Functions(2/2) Pin Name P34 AIN4 P33 AIN3 P32 AIN2 P31 AIN1 P30 AIN0 P47 P46 P45 P44 P43 P42 P41 P40 XIN XOUT RESET Pin Number 30 Input/Output IO I IO I IO I IO I IO I IO IO IO IO IO IO IO IO I O I I I I I I I PORT34 Analog Input4 PORT33 Analog Input3 PORT32 Analog Input2 PORT31 Analog Input1 PORT30 Analog Input0 PORT47 PORT46 PORT45 PORT44 PORT43 PORT42 PORT41 PORT40 Functions 29 28 27 26 44 43 42 41 40 39 38 37 2 3 8 4 34 35 36 5 1 Resonator connecting pins for high-frequency clock Resonator connecting pins for high-frequency clock Reset signal Test pin for out-going test. Normally, be fixed to low. Analog Base Voltage Input Pin for A/D Conversion Analog Power Supply Analog Power Supply +5V 0(GND) TEST VAREF AVDD AVSS VDD VSS Page 6 TMP86C845UG 2. Operational Description 2.1 CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, and the reset circuit. 2.1.1 Memory Address Map The TMP86C845UG memory is composed MaskROM, RAM and SFR(Special function register). They are all mapped in 64-Kbyte address space. Figure 2-1 shows the TMP86C845UG memory address map. 0000H SFR 003FH 0040H 64 bytes SFR: RAM 013FH E000H 256 bytes RAM: Special function register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Program status word Random access memory includes: Data memory Stack MaskROM: Program memory MaskROM FFC0H FFDFH FFE0H FFFFH 8192 bytes Vector table for vector call instructions (32 bytes) Vector table for interrupts (32 bytes) Figure 2-1 Memory Address Map 2.1.2 Program Memory (MaskROM) The TMP86C845UG has a 8192 bytes (Address E000H to FFFFH) of program memory (MaskROM ). 2.1.3 Data Memory (RAM) The TMP86C845UG has 256bytes (Address 0040H to 013FH) of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Page 7 2. Operational Description 2.2 System Clock Controller TMP86C845UG Example :Clears RAM to "00H". (TMP86C845UG) LD LD LD SRAMCLR: LD INC DEC JRS HL, 0040H A, H BC, 00FFH (HL), A HL BC F, SRAMCLR ; Start address setup ; Initial value (00H) setup 2.2 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. Timing generator control register Clock generator XIN fc TBTCR 0036H High-frequency clock oscillator XOUT XTIN Timing generator fs Standby controller 0038H SYSCR1 0039H SYSCR2 Low-frequency clock oscillator XTOUT System clocks Clock generator control System control registers Figure 2-2 System Colck Control 2.2.1 Clock Generator The clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: One for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) clock and low-frequency (fs) clock can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected. Page 8 TMP86C845UG High-frequency clock XIN XOUT XIN XOUT (Open) XTIN Low-frequency clock XTOUT XTIN XTOUT (Open) (a) Crystal/Ceramic resonator (b) External oscillator (c) Crystal (d) External oscillator Figure 2-3 Examples of Resonator Connection Note:The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. Page 9 2. Operational Description 2.2 System Clock Controller TMP86C845UG 2.2.2 Timing Generator The timing generator generates the various system clocks supplied to the CPU core and peripheral hardware from the basic clock (fc or fs). The timing generator provides the following functions. 1. Generation of main system clock 2. Generation of divider output (DVO) pulses 3. Generation of source clocks for time base timer 4. Generation of source clocks for watchdog timer 5. Generation of internal source clocks for timer/counters 6. Generation of warm-up clocks for releasing STOP mode 2.2.2.1 Configuration of timing generator The timing generator consists of a 2-stage prescaler, a 21-stage divider, a main system clock generator, and machine cycle counters. An input clock to the 7th stage of the divider depends on the operating mode, SYSCR2 fc or fs Main system clock generator SYSCK DV7CK Machine cycle counters High-frequency clock fc Low-frequency clock fs 12 fc/4 S A 123456 B Y Divider 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 S B0 B1 A0 Y0 A1 Y1 Multiplexer Multiplexer Warm-up controller Watchdog timer Timer counter, Serial interface, Time-base-timer, divider output, etc. (Peripheral functions) Figure 2-4 Configuration of Timing Generator Page 10 TMP86C845UG Timing Generator Control Register TBTCR (0036H) 7 (DVOEN) 6 (DVOCK) 5 4 DV7CK 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DV7CK Selection of input to the 7th stage of the divider 0: fc/28 [Hz] 1: fs R/W Note 1: In single clock mode, do not set DV7CK to "1". Note 2: Do not set "1" on DV7CK while the low-frequency clock is not operated stably. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: In SLOW1/2 and SLEEP1/2 modes, the DV7CK setting is ineffective, and fs is input to the 7th stage of the divider. Note 5: When STOP mode is entered from NORMAL1/2 mode, the DV7CK setting is ineffective during the warm-up period after release of STOP mode, and the 6th stage of the divider is input to the 7th stage during this period. 2.2.2.2 Machine cycle Instruction execution and peripheral hardware operation are synchronized with the main system clock. The minimum instruction execution unit is called an "machine cycle". There are a total of 10 different types of instructions for the TLCS-870/C Series: Ranging from 1-cycle instructions which require one machine cycle for execution to 10-cycle instructions which require 10 machine cycles for execution. A machine cycle consists of 4 states (S0 to S3), and each state consists of one main system clock. 1/fc or 1/fs [s] Main system clock State S0 S1 S2 S3 S0 S1 S2 S3 Machine cycle Figure 2-5 Machine Cycle 2.2.3 Operation Mode Control Circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock. There are three operating modes: Single clock mode, dual clock mode and STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-6 shows the operating mode transition diagram. 2.2.3.1 Single-clock mode Only the oscillation circuit for the high-frequency clock is used, and P21 (XTIN) and P22 (XTOUT) pins are used as input/output ports. The main-system clock is obtained from the high-frequency clock. In the single-clock mode, the machine cycle time is 4/fc [s]. (1) NORMAL1 mode In this mode, both the CPU core and on-chip peripherals operate using the high-frequency clock. The TMP86C845UG is placed in this mode after reset. Page 11 2. Operational Description 2.2 System Clock Controller TMP86C845UG (2) IDLE1 mode In this mode, the internal oscillation circuit remains active. The CPU and the watchdog timer are halted; however on-chip peripherals remain active (Operate using the high-frequency clock). IDLE1 mode is started by SYSCR2 (3) IDLE0 mode In this mode, all the circuit, except oscillator and the timer-base-timer, stops operation. This mode is enabled by SYSCR2 2.2.3.2 Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 s at fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C is placed in the signal-clock mode during reset. To use the dual-clock mode, the lowfrequency oscillator should be turned on at the start of a program. (1) NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. (2) SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. As the SYSCR2 Page 12 TMP86C845UG Switching back and forth between SLOW1 and SLOW2 modes are performed by SYSCR2 2.2.3.3 STOP mode In this mode, the internal oscillation circuit is turned off, causing all system operations to be halted. The internal status immediately prior to the halt is held with a lowest power consumption during STOP mode. STOP mode is started by the system control register 1 (SYSCR1), and STOP mode is released by a inputting (Either level-sensitive or edge-sensitive can be programmably selected) to the STOP pin. After the warm-up period is completed, the execution resumes with the instruction which follows the STOP mode start instruction. Page 13 2. Operational Description 2.2 System Clock Controller TMP86C845UG IDLE0 mode Reset release RESET IDLE1 mode (a) Single-clock mode Note 2 SYSCR2 IDLE2 mode Interrupt NORMAL2 mode SYSCR2 SLEEP1 mode (b) Dual-clock mode SYSCR2 Note 1: NORMAL1 and NORMAL2 modes are generically called NORMAL; SLOW1 and SLOW2 are called SLOW; IDLE0, IDLE1 and IDLE2 are called IDLE; SLEEP0, SLEEP1 and SLEEP2 are called SLEEP. Note 2: The mode is released by falling edge of TBTCR Figure 2-6 Operating Mode Transition Diagram Table 2-1 Operating Mode and Conditions Oscillator Operating Mode High Frequency Low Frequency CPU Core TBT Other Peripherals Reset Operate 4/fc [s] Machine Cycle Time RESET NORMAL1 Single clock IDLE1 IDLE0 STOP NORMAL2 IDLE2 SLOW2 Dual clock SLEEP2 SLOW1 SLEEP1 SLEEP0 STOP Stop Stop Oscillation Stop Oscillation Reset Operate Stop Halt Reset Operate Halt Operate with high frequency Halt - 4/fc [s] Oscillation Halt Operate with low frequency Halt Operate with low frequency Operate Operate 4/fs [s] Halt Halt Halt - Page 14 TMP86C845UG System Control Register 1 SYSCR1 (0038H) 7 STOP 6 RELM 5 RETM 4 OUTEN 3 WUT 2 1 0 (Initial value: 0000 00**) STOP RELM RETM OUTEN STOP mode start Release method for STOP mode Operating mode after STOP mode Port output during STOP mode 0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) 0: Edge-sensitive release 1: Level-sensitive release 0: Return to NORMAL1/2 mode 1: Return to SLOW1 mode 0: High impedance 1: Output kept Return to NORMAL mode Return to SLOW mode 3 x 213/fs 213/fs 3 x 26/fs 26/fs R/W R/W R/W R/W WUT Warm-up time at releasing STOP mode 00 01 10 11 3 x 216/fc 216/fc 3 x 214/fc 214/fc R/W Note 1: Always set RETM to "0" when transiting from NORMAL mode to STOP mode. Always set RETM to "1" when transiting from SLOW mode to STOP mode. Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *; Don't care Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = "0", input value is fixed to "0"; therefore it may cause external interrupt request on account of falling edge. Note 6: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 7: The warmig-up time should be set correctly for using oscillator. System Control Register 2 SYSCR2 (0039H) 7 XEN 6 XTEN 5 SYSCK 4 IDLE 3 2 TGHALT 1 0 (Initial value: 1000 *0**) XEN XTEN High-frequency oscillator control Low-frequency oscillator control Main system clock select (Write)/main system clock monitor (Read) CPU and watchdog timer control (IDLE1/2 and SLEEP1/2 modes) TG control (IDLE0 and SLEEP0 modes) 0: Turn off oscillation 1: Turn on oscillation 0: Turn off oscillation 1: Turn on oscillation 0: High-frequency clock (NORMAL1/NORMAL2/IDLE1/IDLE2) 1: Low-frequency clock (SLOW1/SLOW2/SLEEP1/SLEEP2) 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2 and SLEEP1/2 modes) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0 and SLEEP0 modes) R/W R/W SYSCK IDLE TGHALT Note 1: A reset is applied if both XEN and XTEN are cleared to "0", XEN is cleared to "0" when SYSCK = "0", or XTEN is cleared to "0" when SYSCK = "1". Note 2: *: Don't care, TG: Timing generator, *; Don't care Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to "1" simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR Page 15 2. Operational Description 2.2 System Clock Controller TMP86C845UG 2.2.4 Operating Mode Control STOP mode STOP mode is controlled by the system control register 1, the STOP pin input. The STOP pin is also used both as a port P20 and an INT5 (external interrupt input 5) pin. STOP mode is started by setting SYSCR1 2.2.4.1 Note 1: During STOP period (from start of STOP mode to end of warm up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after STOP mode is released. Before starting STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. (1) Level-sensitive release mode (RELM = "1") In this mode, STOP mode is released by setting the STOP pin high. This mode is used for capacitor backup when the main power supply is cut off and long term battery backup. Even if an instruction for starting STOP mode is executed while STOP pin input is high, STOP mode does not start but instead the warm-up sequence starts immediately. Thus, to start STOP mode in the level-sensitive release mode, it is necessary for the program to first confirm that the STOP pin input is low. The following two methods can be used for confirmation. 1. Testing a port. 2. Using an external interrupt input INT5 (INT5 is a falling edge-sensitive input). Example 1 :Starting STOP mode from NORMAL mode by testing a port P20. LD SSTOPH: TEST JRS DI SET (SYSCR1). 7 (SYSCR1), 01010000B (P2PRD). 0 F, SSTOPH ; IMF 0 ; Starts STOP mode ; Sets up the level-sensitive release mode ; Wait until the STOP pin input goes low level Example 2 :Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST JRS LD DI SET SINT5: RETI (SYSCR1). 7 (P2PRD). 0 F, SINT5 (SYSCR1), 01010000B ; To reject noise, STOP mode does not start if port P20 is at high ; Sets up the level-sensitive release mode. ; IMF 0 ; Starts STOP mode Page 16 TMP86C845UG STOP pin XOUT pin NORMAL operation STOP operation Confirm by program that the STOP pin input is low and start STOP mode. VIH Warm up NORMAL operation STOP mode is released by the hardware. Always released if the STOP pin input is high. Figure 2-7 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. (2) Edge-sensitive release mode (RELM = "0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Example :Starting STOP mode from NORMAL mode DI LD (SYSCR1), 10010000B ; IMF 0 ; Starts after specified to the edge-sensitive release mode STOP pin XOUT pin NORMAL operation STOP mode started by the program. STOP operation VIH Warm up NORMAL operation STOP operation STOP mode is released by the hardware at the rising edge of STOP pin input. Figure 2-8 Edge-sensitive Release Mode STOP mode is released by the following sequence. 1. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and lowfrequency clock oscillators are turned on; when returning to SLOW1 mode, only the lowfrequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. 2. A warm-up period is inserted to allow oscillation time to stabilize. During warm up, all internal operations remain halted. Four different warm-up times can be selected with the SYSCR1 Page 17 2. Operational Description 2.2 System Clock Controller TMP86C845UG 3. When the warm-up time has elapsed, normal operation resumes with the instruction following the STOP mode start instruction. Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be "H" level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). Table 2-2 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz) Warm-up Time [ms] WUT Return to NORMAL Mode 00 01 10 11 12.288 4.096 3.072 1.024 Return to SLOW Mode 750 250 5.85 1.95 Note 1: The warm-up time is obtained by dividing the basic clock by the divider. Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered as an approximate value. Page 18 Turn off Oscillator circuit Turn on Main system clock a+3 SET (SYSCR1). 7 n+1 (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) n+2 n+3 n+4 Halt Program counter a+2 Instruction execution Divider n 0 Figure 2-9 STOP Mode Start/Release a+4 Instruction address a + 2 Page 19 0 1 (b) STOP mode release Warm up STOP pin input Oscillator circuit Turn off Turn on Main system clock a+5 Instruction address a + 3 Program counter a+3 a+6 Instruction address a + 4 Instruction execution Halt Divider 0 Count up 2 3 TMP86C845UG 2. Operational Description 2.2 System Clock Controller TMP86C845UG 2.2.4.2 IDLE1/2 mode and SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. 1. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts these modes. Starting IDLE1/2 and SLEEP1/2 modes by instruction CPU and WDT are halted Yes Reset input No No Interrupt request Yes "0" IMF Reset Normal release mode "1" (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE1/2 and SLEEP1/2 modes start instruction Figure 2-10 IDLE1/2 and SLEEP1/2 Modes Page 20 TMP86C845UG * Start the IDLE1/2 and SLEEP1/2 modes After IMF is set to "0", set the individual interrupt enable flag (EF) which releases IDLE1/2 and SLEEP1/2 modes. To start IDLE1/2 and SLEEP1/2 modes, set SYSCR2 Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started. Page 21 Main system clock 2.2 System Clock Controller 2. Operational Description Interrupt request a+2 SET (SYSCR2). 4 Operate Halt a+3 Program counter Instruction execution Watchdog timer (a) IDLE1/2 and SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a) Main system clock Interrupt request a+3 Instruction address a + 2 Operate Normal release mode a+4 Program counter Figure 2-11 IDLE1/2 and SLEEP1/2 Modes Start/Release Page 22 a+3 Acceptance of interrupt Operate Operate Interrupt release mode Instruction execution Halt Watchdog timer Halt Main system clock Interrupt request Program counter Instruction execution Halt Watchdog timer Halt TMP86C845UG (b) IDLE1/2 and SLEEP1/2 modes release TMP86C845UG 2.2.4.3 IDLE0 and SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. 1. Timing generator stops feeding clock to peripherals except TBT. 2. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. 3. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Note: Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) peripherals. Stopping peripherals by instruction Starting IDLE0, SLEEP0 modes by instruction CPU and WDT are halted Reset input No No TBT source clock falling edge Yes TBTCR Yes Reset No No (Normal release mode) Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0, SLEEP0 modes start instruction Figure 2-12 IDLE0 and SLEEP0 Modes Page 23 2. Operational Description 2.2 System Clock Controller TMP86C845UG * Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. To start IDLE0 and SLEEP0 modes, set SYSCR2 Note: IDLE0 and SLEEP0 modes start/release without reference to TBTCR (1) Normal release mode (IMF*EF6*TBTCR (2) Interrupt release mode (IMF*EF6*TBTCR Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR Page 24 Main system clock Interrupt request a+2 a+3 Program counter Instruction execution SET (SYSCR2). 2 Halt Watchdog timer Operate (a) IDLE0 and SLEEP0 modes start (Example: Starting with the SET instruction located at address a Main system clock TBT clock a+3 a+4 Program counter Figure 2-13 IDLE0 and SLEEP0 Modes Start/Release Page 25 Instruction address a + 2 Operate Normal release mode a+3 Instruction execution Halt Watchdog timer Halt Main system clock TBT clock Program counter Instruction execution Halt Acceptance of interrupt Operate Interrupt release mode (b) IDLE and SLEEP0 modes release TMP86C845UG Watchdog timer Halt 2. Operational Description 2.2 System Clock Controller TMP86C845UG 2.2.4.4 SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter. (1) Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2 Note: The high-frequency clock can be continued oscillation in order to return to NORMAL2 mode from SLOW mode quickly. Always turn off oscillation of high-frequency clock when switching from SLOW mode to stop mode. Example 1 :Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2 Example 2 :Switching to the SLOW1 mode after low-frequency clock has stabilized. SET LD LD LDW DI SET EI SET : PINTTC4: CLR SET (TC4CR). 3 (SYSCR2). 5 ; Stops TC4, 3 ; SYSCR2 Page 26 TMP86C845UG (2) Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2 Note: After SYSCK is cleared to "0", executing the instructions is continiued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. High-frequency clock Low-frequency clock Main system clock SYSCK Example :Switching from the SLOW1 mode to the NORMAL2 mode (fc = 16 MHz, warm-up time is 4.0 ms). SET LD LD LD DI SET EI SET : PINTTC4: CLR CLR (TC4CR). 3 (SYSCR2). 5 ; Stops TC4, 3 ; SYSCR2 Page 27 2.2 System Clock Controller 2. Operational Description Highfrequency clock Lowfrequency clock Main system clock Turn off SYSCK XEN CLR (SYSCR2). 7 SLOW2 mode (a) Switching to the SLOW mode Instruction execution SET (SYSCR2). 5 NORMAL2 mode SLOW1 mode Figure 2-14 Switching between the NORMAL2 and SLOW Modes Page 28 CLR (SYSCR2). 5 Warm up during SLOW2 mode (b) Switching to the NORMAL2 mode Highfrequency clock Lowfrequency clock Main system clock SYSCK XEN Instruction execution SET (SYSCR2). 7 TMP86C845UG SLOW1 mode NORMAL2 mode TMP86C845UG 2.3 Reset Circuit The TMP86C845UG has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Of these reset, the address trap reset, the watchdog timer and the system clock reset are a malfunction reset. When the malfunction reset request is detected, reset occurs during the maximum 24/fc[s]. The malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on. Therefore, reset may occur during maximum 24/fc[s] (1.5s at 16.0 MHz) when power is turned on. Table 2-3 shows on-chip hardware initialization by reset action. Table 2-3 Initializing Internal Status by Reset Action On-chip Hardware Program counter Stack pointer General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Jump status flag Zero flag Carry flag Half carry flag Sign flag Overflow flag Interrupt master enable flag Interrupt individual enable flags Interrupt latches (JF) (ZF) (CF) (HF) (SF) (VF) (IMF) (EF) (IL) (PC) (SP) Initial Value (FFFEH) Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Output latches of I/O ports Not initialized Not initialized 0 0 Control registers 0 RAM Refer to each of control register Not initialized Refer to I/O port circuitry Watchdog timer Enable Prescaler and divider of timing generator 0 On-chip Hardware Initial Value 2.3.1 External Reset Input The RESET pin contains a Schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH. VDD RESET Internal reset Watchdog timer reset Malfunction reset output circuit Address trap reset System clock reset Figure 2-15 Reset Circuit Page 29 2. Operational Description 2.3 Reset Circuit TMP86C845UG 2.3.2 Address trap reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1 Note:The operating mode under address trapped is alternative of reset or interrupt. The address trap area is alternative. Instruction execution Internal reset JP a Address trap is occurred Reset release Instruction at address r maximum 24/fc [s] 4/fc to 12/fc [s] 16/fc [s] Note 1: Address "a" is in the SFR or on-chip RAM (WDTCR1 Figure 2-16 Address Trap Reset 2.3.3 Watchdog timer reset Refer to Section "Watchdog Timer". 2.3.4 System clock reset If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the CPU. (The oscillation is continued without stopping.) - In case of clearing SYSCR2 Page 30 TMP86C845UG Page 31 2. Operational Description 2.3 Reset Circuit TMP86C845UG Page 32 TMP86C845UG 3. Interrupt Control Circuit The TMP86C845UG has a total of 15 interrupt sources excluding reset, of which 2 source levels are multiplexed. Interrupts can be nested with priorities. Four of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Interrupt Latch - - - IL2 IL3 IL4 IL5 IL6 IL7 IL8 IL9 IL10 IL11 IL12 IL13 IL14 Vector Address FFFE FFFC FFFC FFFA FFF8 FFF6 FFF4 FFF2 FFF0 FFEE FFEC FFEA FFE8 FFE6 FFE4 FFE2 Interrupt Factors Internal/External Internal Internal Internal Internal External External Internal External Internal Internal External Internal External External Internal (Reset) INTSWI (Software interrupt) INTUNDEF (Executed the undefined instruction interrupt) INTATRAP (Address trap interrupt) INTWDT (Watchdog timer interrupt) INT0 Enable Condition Non-maskable Non-maskable Non-maskable Non-maskable Non-maskable IMF* EF4 = 1, INT0EN = 1 IMF* EF5 = 1 IMF* EF6 = 1 IMF* EF7 = 1 IMF* EF8 = 1 IMF* EF9 = 1 IMF* EF10 = 1 IMF* EF11 = 1 IMF* EF12 = 1 IMF* EF13 = 1 IMF* EF14 = 1, IL14ER = 0 IMF* EF14 = 1, IL14ER = 1 IMF* EF15 = 1, IL15ER = 0 IMF* EF15 = 1, IL15ER = 1 Priority 1 2 2 2 2 5 6 7 8 9 10 11 12 13 14 15 INT1 INTTBT Reserved INT2 INTTC4 INTTC3 INT3 INTSIO Reserved INT4 (Don't set) INT5 IL15 FFE0 16 INTADC Note 1: The INTSEL register is used to select the interrupt source to be enabled for each multiplexed source level (see 3.3 Interrupt Source Selector (INTSEL)). Note 2: To use the address trap interrupt (INTATRAP), clear WDTCR1 3.1 Interrupt latches (IL15 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt and an executed the undefined instruction interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. The interrupt latch is cleared to "0" immediately after accepting interrupt. All interrupt latches are initialized to "0" during reset. The interrupt latches are located on address 003CH and 003DH in SFR area. Each latch can be cleared to "0" individually by instruction. However, IL2 and IL3 should not be cleared to "0" by software. For clearing the interrupt latch, load instruction should be used and then IL2 and IL3 should be set to "1". If the read-modify-write instructions such as bit manipulation or operation instructions are used, interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed. Interrupt latches are not set to "1" by an instruction. Page 33 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86C845UG Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Example 1 :Clears interrupt latches DI LDW EI (ILL), 1110100000111111B ; IMF 0 ; IL12, IL10 to IL6 0 ; IMF 1 Example 2 :Reads interrupt latchess LD WA, (ILL) ; W ILH, A ILL Example 3 :Tests interrupt latches TEST JR (ILL). 7 F, SSET ; if IL7 = 1 then jump 3.2 Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog interrupt). Nonmaskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 003AH and 003BH in SFR area, and they can be read and written by an instructions (Including read-modify-write instructions such as bit manipulation or operation instructions). 3.2.1 Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0". 3.2.2 Individual interrupt enable flags (EF15 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. During reset, all the individual interrupt enable flags (EF15 to EF4) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note:In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 34 TMP86C845UG Example 1 :Enables interrupts individually and sets IMF DI LDW : : EI ; IMF 1 (EIRL), 1110100010100000B ; IMF 0 ; EF15 to EF13, EF11, EF7, EF5 1 Note: IMF should not be set. Example 2 :C compiler description example unsigned int _io (3AH) EIRL; _DI(); EIRL = 10100000B; : _EI(); /* 3AH shows EIRL address */ Page 35 3. Interrupt Control Circuit 3.2 Interrupt enable register (EIR) TMP86C845UG Interrupt Latches (Initial value: 00000000 000000**) ILH,ILL (003DH, 003CH) 15 IL15 14 IL14 13 IL13 12 IL12 11 IL11 10 IL10 9 IL9 8 IL8 7 IL7 6 IL6 5 IL5 4 IL4 3 IL3 2 IL2 1 0 ILH (003DH) ILL (003CH) IL15 to IL2 Interrupt latches at RD 0: No interrupt request 1: Interrupt request at WR 0: Clears the interrupt request 1: (Interrupt latch is not set.) R/W Note 1: To clear any one of bits IL7 to IL4, be sure to write "1" into IL2 and IL3. Note 2: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers (Initial value: 00000000 0000***0) EIRH,EIRL (003BH, 003AH) 15 EF15 14 EF14 13 EF13 12 EF12 11 EF11 10 EF10 9 EF9 8 EF8 7 EF7 6 EF6 5 EF5 4 EF4 EIRL (003AH) 3 2 1 0 IMF EIRH (003BH) EF15 to EF4 IMF Individual-interrupt enable flag (Specified for each bit) Interrupt master enable flag 0: 1: 0: 1: Disables the acceptance of each maskable interrupt. Enables the acceptance of each maskable interrupt. Disables the acceptance of all maskable interrupts Enables the acceptance of all maskable interrupts R/W Note 1: *: Don't care Note 2: Do not set IMF and the interrupt enable flag (EF15 to EF4) to "1" at the same time. Note 3: In main program, before manipulating the interrupt enable flag (EF) or the interrupt latch (IL), be sure to clear IMF to "0" (Disable interrupt by DI instruction). Then set IMF newly again as required after operating on the EF or IL (Enable interrupt by EI instruction) In interrupt service routine, because the IMF becomes "0" automatically, clearing IMF need not execute normally on interrupt service routine. However, if using multiple interrupt on interrupt service routine, manipulating EF or IL should be executed before setting IMF="1". Page 36 TMP86C845UG 3.3 Interrupt Source Selector (INTSEL) Each interrupt source that shares the interrupt source level with another interrupt source is allowed to enable the interrupt latch only when it is selected in the INTSEL register. The interrupt controller does not hold interrupt requests corresponding to interrupt sources that are not selected in the INTSEL register. Therefore, the INTSEL register must be set appropriately before interrupt requests are generated. The following interrupt sources share their interrupt source level; the source is selected onnthe register INTSEL. 1. INT4 and (Don't set) share the interrupt source level whose priority is 15. 2. INT5 and INTADC share the interrupt source level whose priority is 16. Interrupt source selector INTSEL (003EH) 7 6 5 4 3 2 1 IL14ER 0 IL15ER (Initial value: **** **00) IL14ER IL15ER Selects INT4 or (Don't set) Selects INT5 or INTADC 0: INT4 1: (Don't set) 0: INT5 1: INTADC R/W R/W 3.4 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (2 s @16 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 3-1 shows the timing chart of interrupt acceptance processing. 3.4.1 Interrupt acceptance processing is packaged as follows. a. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. b. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". c. The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. d. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. e. The instruction stored at the entry address of the interrupt service program is executed. Note:When the contents of PSW are saved on the stack, the contents of IMF are also saved. Page 37 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86C845UG 1-machine cycle Interrupt service task Interrupt request Interrupt latch (IL) IMF Execute instruction a-1 Execute instruction Execute instruction Interrupt acceptance Execute RETI instruction PC a a+1 a b b+1 b+2 b + 3 c+1 c+2 a a+1 a+2 SP n n-1 n-2 n-3 n-2 n-1 n Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instruction is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10 cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 3-1 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Entry address Interrupt service program FFF2H FFF3H 03H D2H Vector D203H D204H 0FH 06H Figure 3-2 Vector table address,Entry address A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorten compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. 3.4.2 Saving/restoring general-purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following methods are used to save/restore the generalpurpose registers. Page 38 TMP86C845UG 3.4.2.1 Using PUSH and POP instructions If only a specific register is saved or interrupts of the same source are nested, general-purpose registers can be saved/restored using the PUSH/POP instructions. Example :Save/store register using PUSH and POP instructions PINTxx: PUSH WA ; Save WA register (interrupt processing) POP RETI WA ; Restore WA register ; RETURN Address (Example) SP A SP PCL PCH PSW At acceptance of an interrupt W PCL PCH PSW At execution of PUSH instruction SP PCL PCH PSW At execution of POP instruction SP b-5 b-4 b-3 b-2 b-1 b At execution of RETI instruction Figure 3-3 Save/store register using PUSH and POP instructions 3.4.2.2 Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example :Save/store register using data transfer instructions PINTxx: LD (GSAVA), A ; Save A register (interrupt processing) LD RETI A, (GSAVA) ; Restore A register ; RETURN Page 39 3. Interrupt Control Circuit 3.4 Interrupt Sequence TMP86C845UG Main task Interrupt acceptance Interrupt service task Saving registers Restoring registers Interrupt return Saving/Restoring general-purpose registers using PUSH/POP data transfer instruction Figure 3-4 Saving/Restoring General-purpose Registers under Interrupt Processing 3.4.3 Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI]/[RETN] Interrupt Return 1. Program counter (PC) and program status word (PSW, includes IMF) are restored from the stack. 2. Stack pointer (SP) is incremented by 3. As for address trap interrupt (INTATRAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Note:If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again.When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively. Example 1 :Returning from address trap interrupt (INTATRAP) service program PINTxx: POP LD PUSH WA WA, Return Address WA ; Recover SP by 2 ; ; Alter stacked data (interrupt processing) RETN ; RETURN Example 2 :Restarting without returning interrupt (In this case, PSW (Includes IMF) before interrupt acceptance is discarded.) PINTxx: INC INC INC SP SP SP ; Recover SP by 3 ; ; (interrupt processing) LD JP EIRL, data Restart Address ; Set IMF to "1" or clear it to "0" ; Jump into restarting address Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Page 40 TMP86C845UG Note 1: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (such as Example 2). Note 2: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 3.5 Software Interrupt (INTSW) Executing the SWI instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the SWI instruction only for detection of the address error or for debugging. 3.5.1 Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address trap reset is generated in case that an instruction is fetched from RAM or SFR areas. 3.5.2 Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 3.6 Undefined Instruction Interrupt (INTUNDEF) Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SWI) does. 3.7 Address Trap Interrupt (INTATRAP) Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (WDTCR). 3.8 External Interrupts The TMP86C845UG has 6 external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT4. The INT0/P00 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0/P00 pin function selection are performed by the external interrupt control register (EINTCR). Page 41 3. Interrupt Control Circuit 3.8 External Interrupts TMP86C845UG Source Pin Enable Conditions Release Edge (level) Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. INT0 INT0 IMF EF4 INT0EN=1 Falling edge INT1 INT1 IMF EF5 = 1 Falling edge or Rising edge INT2 INT2 IMF EF8 = 1 Falling edge or Rising edge INT3 INT3 IMF EF11 = 1 Falling edge or Rising edge INT4 INT4 IMF EF14 = 1 and IL14ER=0 Falling edge, Rising edge, Falling and Rising edge or H level INT5 INT5 IMF EF15 = 1 and IL15ER=0 Falling edge Note 1: In NORMAL1/2 or IDLE1/2 mode, if a signal with no noise is input on an external interrupt pin, it takes a maximum of "signal establishment time + 6/fs[s]" from the input signal's edge to set the interrupt latch. Note 2: When INT0EN = "0", IL4 is not set even if a falling edge is detected on the INT0 pin input. Note 3: When a pin with more than one function is used as an output and a change occurs in data or input/output status, an interrupt request signal is generated in a pseudo manner. In this case, it is necessary to perform appropriate processing such as disabling the interrupt enable flag. Page 42 TMP86C845UG External Interrupt Control Register EINTCR (0037H) 7 INT1NC 6 INT0EN 5 INT4ES 4 3 INT3ES 2 INT2ES 1 INT1ES 0 (Initial value: 0000 000*) INT1NC INT0EN Noise reject time select P00/INT0 pin configuration 0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P00 input/output port 1: INT0 pin (Port P00 should be set to an input mode) 00: Rising edge 01: Falling edge 10: Rising edge and Falling edge 11: H level 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge 0: Rising edge 1: Falling edge R/W R/W INT4 ES INT4 edge select R/W INT3 ES INT2 ES INT1 ES INT3 edge select INT2 edge select INT1 edge select R/W R/W R/W Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR). Note 3: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc. Note 4: In case RESET pin is released while the state of INT4 pin keeps "H" level, the external interrupt 4 request is not generated even if the INT4 edge select is specified as "H" level. The rising edge is needed after RESET pin is released. Page 43 3. Interrupt Control Circuit 3.8 External Interrupts TMP86C845UG Page 44 TMP86C845UG 4. Special Function Register (SFR) The TMP86C845UG adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR). The SFR is mapped on address 0000H to 003FH. This chapter shows the arrangement of the special function register (SFR) for TMP86C845UG. 4.1 SFR Address 0000H 0001H 0002H 0003H 0004H 0005H 0006H 0007H 0008H 0009H 000AH 000BH 000CH 000DH 000EH 000FH 0010H 0011H 0012H 0013H 0014H 0015H 0016H 0017H 0018H 0019H 001AH 001BH 001CH 001DH 001EH 001FH 0020H 0021H 0022H 0023H 0024H 0025H 0026H 0027H ADCDR2 ADCDR1 Reserved Reserved Reserved Reserved Reserved Reserved SIOCR1 SIOSR P2PRD Reserved Reserved P1CR P3CR P4CR Reserved Reserved Reserved Reserved Reserved Reserved TC3CR TC4CR TTREG3 TTREG4 PWREG3 PWREG4 ADCCR1 ADCCR2 P0PRD Reserved Read P0DR P1DR P2DR P3DR P4DR Reserved Reserved Reserved Write Page 45 4. Special Function Register (SFR) 4.1 SFR TMP86C845UG Address 0028H 0029H 002AH 002BH 002CH 002DH 002EH 002FH 0030H 0031H 0032H 0033H 0034H 0035H 0036H 0037H 0038H 0039H 003AH 003BH 003CH 003DH 003EH 003FH Read SIORDB Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved TBTCR EINTCR SYSCR1 SYSCR2 EIRL EIRH ILL ILH INTSEL PSW Write SIOTDB WDTCR1 WDTCR2 Note 1: Do not access reserved areas by the program. Note 2: - ; Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Page 46 TMP86C845UG 5. I/O Ports The TMP86C845UG has 5 parallel input/output ports (35 pins) as follows. Primary Function Port P0 Port P1 Port P2 Port P3 Port P4 8-bit I/O port 8-bit I/O port 3-bit I/O port 8-bit I/O port 8-bit I/O port Secondary Functions External interrupt input, serial and timer/counter input/output External interrupt input, timer/counter input/output, and divider output External interrupt input, and STOP mode release signal input Analog input Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several times before processing. Figure 5-1 shows input/output timing examples. External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port. Fetch cycle Fetch cycle Read cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Instruction execution cycle Ex: LD A, (x) Input strobe Data input (a) Input timing Fetch cycle Fetch cycle Write cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Instruction execution cycle Ex: LD (x), A Output strobe Data output Old (b) Output timing New Note: The positions of the read and write cycles may vary, depending on the instruction. Figure 5-1 Input/Output Timing (Example) Page 47 5. I/O Ports 5.1 Port P0 (P07 to P00) TMP86C845UG 5.1 Port P0 (P07 to P00) Port P0 is an 8-bit input/output port which is also used as an external interrupt input, serial interface input/output and timer/counter input/output. When used as an input port or a secondary function pins, the respective output latch (P0DR) should be set to "1". When used as an output port, the respective P0DR bit should be set data. During reset, the output latch is initialized to "1". P0 port output latch (P0DR) and P0 port terminal input (P0PRD) are located on their respective address. When read the output latch data, the P0DR should be read and when read the terminal input data, the P0PRD register should be read. P00 port (INT0) can be configured as either an I/O port or as external interrupt input with INT0EN (bit 6 in EINTCR). During reset, P00 port (INT0) is configured as an input port. Control input Port data (P0PRD) STOP OUTEN Output latch data (P0DR) Data output Control output a) P04 to P01 Control input Port data (P0PRD) STOP OUTEN Output latch data (P0DR) Data output Control output b) P07 to P05, P00 D Q D Q Output latch P0i Note: i = 4 to 1 Output latch P0j Note: j = 7 to 5, 0 Figure 5-2 Port 0 7 P0DR (0000H) R/W 6 5 4 3 2 1 P01 PWM4 0 P07 INT4 P06 SCK P05 SI P04 SO P03 P02 TC4 PDO4 PPG4 P00 INT0 (Initial value: 1111 1111) P0PRD (0008H) Read only 7 P07 6 P06 5 P05 4 P04 3 P03 2 P02 1 P01 0 P00 Page 48 TMP86C845UG 5.2 Port P1 (P17 to P10) Port P1 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port P1 input/output control register (P1CR). Port P1 is configured as an input if its corresponding P1CR bit is cleared to "0", and as an output if its corresponding P1CR bit is set to "1". During reset, the P1CR is initialized to "0" and port P1 is input mode. The P1 output latches are also initialized to "0". Port P1 is also used as an external interrupt input, a timer/counter input/output, and a divider output. When used as an input port, an external interrupt input or a timer/counter input, the corresponding bit of P1CR is cleared to "0". When used as an output port, a timer/counter output or divider output, the corresponding bit of P1CR is set to "1" and beforehand the corresponding output latch should be set to "1". Data can be written into the output latch regardless of P1CR contents, therefore initial output data should be written into the output latch before setting P1CR. Control input STOP OUTEN P1CRi input P1CRi D Q Output latch Data input Data output Control output a) P17 to 16, P14 to 13 Control input STOP OUTEN P1CRj input P1CRj D Q D Q P1i Note: i = 7 to 6, 4 to 3 Output latch Output latch Data input Data output Control output b) P15, P12 to 10 D Q P1j Note: j = 5, 2 to 0 Output latch Figure 5-3 Port P1 7 P1DR (0001H) R/W 6 5 P15 INT3 5 4 P14 PPG 3 P13 DVO 2 P12 INT2 2 1 P11 INT1 1 0 P10 PWM3 P17 P16 TC3 PDO3 (Initial value: 0000 0000) P1CR (000DH) 7 6 4 3 0 (Initial value: 0000 0000) P1CR I/O port for P1 port (specified for each bit) 0: Input mode 1: Output mode R/W Note: Ports set to the input mode read the pin states. Ports set to the output mode read the output latch. When input pin and output pin exist in port P1 together, the contents of the output latch which is specified as an input mode may be rewritten by executing the bit manipulation instructions. Page 49 5. I/O Ports 5.3 Port P2 (P22 to P20) TMP86C845UG 5.3 Port P2 (P22 to P20) Port P2 is a 3-bit input/output port. It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator connection pins. When used as an input port or a secondary function pins, respective output latch (P2DR) should be set to "1". During reset, the P2DR is initialized to "1". A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dualclock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports. It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse. P2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their respective address. When read the output latch data, the P2DR should be read and when read the terminal input data, the P2PRD register should be read. If a read instruction is executed for port P2, read data of bits 7 to 3 are unstable. Data input (P20PRD) Data input (P20) Data output D Q P20 (INT5, STOP) Output latch Control input Data input (P21PRD) Osc. enable Data input (P21) Data output Data input (P22PRD) Data input (P22) Data output D Q P22 (XTOUT) D Q P21 (XTIN) Output latch Output latch STOP OUTEN XTEN fs Figure 5-4 Port 2 P2DR (0002H) R/W P2PRD (000AH) Read only 7 6 5 4 3 2 P22 XTOUT 1 P21 XTIN 1 P21 0 P20 INT5 STOP (Initial value: **** *111) 7 6 5 4 3 2 P22 0 P20 Page 50 TMP86C845UG 5.4 Port P3 (P37 to P30) Port P3 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Port P3 is also used as an analog input. Input/output mode is specified by the corresponding bit in the port P3 input/output control register (P3CR), and AINDS (bit 4 in ADCCR1). During reset, P3CR are initialized to "0" and AINDS is set to "1", therefore port P3 is configured as an input. When used as an analog input, set an analog input channel to SAIN (bit 0, 1, 2 in ADCCR1) and clear AINDS to "0". When AINDS is "0", the pin which is specified as an analog input is used as analog input independent on the value of P3CR and P3DR. When used as an input port, the corresponding bit of P3CR is cleared to "0" without specifying as an analog input. When the AD converter is enabled (AINDS is "0"), the data of port which is selected as an analog input is read "0". and the data of port which is not selected as an analog input is read "0" or "1", depend on the voltage level. When used as an output port, the corresponding bit of P3CR is set to "1" without specifying as an analog input. Data can be written into the output latch regardless of P3CR contents, therefore initial output data should be written into the output latch before setting P3CR. The pins not used as analog input can be used as an input/output port. But output instructions should not be executed to keep a precision. In addition, a variable signal should not be input to an adjacent port to the analog input during AD conversion. Analog input STOP OUTEN AINDS SAIN P3CRi P3CRi input Data input (P3DR) D Q Output latch Data output (P3DR) D Q Output latch P3i Note: i = 7 to 0 Figure 5-5 Port 3 P3DR (0003H) R/W P3CR (000EH) 7 P37 AIN7 7 6 P36 AIN6 6 5 P35 AIN5 5 4 P34 AIN4 4 3 P33 AIN3 3 2 P32 AIN2 2 1 P31 AIN1 1 0 P30 AIN0 0 (Initial value: 0000 0000) (Initial value: 0000 0000) P3CR I/O control (Specified for each bit) 0: Input mode 1: Output mode R/W Note: Ports set to the input mode read the pin states. Ports set to the output mode read the output latch. When input pin and output pin exist in port P3 together, the contents of the output latch which is specified as an input mode may be rewritten by executing the bit manipulation instructions. Page 51 5. I/O Ports 5.5 Port P4 (P47 to P40) TMP86C845UG 5.5 Port P4 (P47 to P40) Port P4 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit under software control. Input/output mode is specified by the corresponding bit in the port P4 input/output control register (P4CR). Port P4 is configured as an input if its corresponding P4CR bit is cleared to "0", and as an output if its corresponding P4CR bit is set to "1". During reset, the P4CR is initialized to "0" and port P4 is input mode. The P4 output latches are also initialized to "0". When used as an input port, the corresponding bit of P4CR is cleared to "0". When used as an output port, the corresponding bit of P4CR is set to "1". Data can be written into the output latch regardless of P4CR contents, therefore initial output data should be written into the output latch before setting P4CR. STOP OUTEN P4CRi P4CRi input Data input (P4DR) D Q Data output D Q Output latch P4i Note: i = 7 to 0 Figure 5-6 Port P4 P4DR (0004H) R/W P4CR (000FH) 7 P47 7 6 P46 6 5 P45 5 4 P44 4 3 P43 3 2 P42 2 1 P41 1 0 P40 0 (Initial value: 0000 0000) (Initial value: 0000 0000) P4CR I/O control for port P4 (Specified for each bit) 0: Input mode 1: Output mode R/W Note: Ports set to the input mode read the pin states. Ports set to the output mode read the output latch. When input pin and output pin exist in port P4 together, the contents of the output latch which is specified as an input mode may be rewritten by executing the bit manipulation instructions. Page 52 TMP86C845UG 6. Time Base Timer (TBT) The time base timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). 6.1 Time Base Timer 6.1.1 Configuration MPX fc/223 or fs/215 fc/221 or fs/213 fc/216 or fs/28 fc/214 or fs/26 fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/29 or fs/2 Source clock Falling edge detector IDLE0, SLEEP0 release request INTTBT interrupt request 3 TBTCK TBTCR Time base timer control register TBTEN Figure 6-1 Time Base Timer configuration 6.1.2 Control Time Base Timer is controled by Time Base Timer control register (TBTCR). Time Base Timer Control Register 7 TBTCR (0036H) (DVOEN) 6 (DVOCK) 5 4 (DV7CK) 3 TBTEN 2 1 TBTCK 0 (Initial Value: 0000 0000) TBTEN Time Base Timer enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 fc/223 fc/221 fc/216 fc/2 14 DV7CK = 1 fs/215 fs/213 fs/28 fs/2 6 SLOW1/2 SLEEP1/2 Mode fs/215 fs/213 - - - - - - R/W TBTCK Time Base Timer interrupt Frequency select : [Hz] 010 011 100 101 110 111 fc/213 fc/2 12 fs/25 fs/2 4 fc/211 fc/2 9 fs/23 fs/2 Note 1: fc; High-frequency clock [Hz], fs; Low-frequency clock [Hz], *; Don't care Page 53 6. Time Base Timer (TBT) 6.1 Time Base Timer TMP86C845UG Note 2: The interrupt frequency (TBTCK) must be selected with the time base timer disabled (TBTEN="0"). (The interrupt frequency must not be changed with the disable from the enable state.) Both frequency selection and enabling can be performed simultaneously. Example :Set the time base timer frequency to fc/216 [Hz] and enable an INTTBT interrupt. LD LD DI SET (EIRL) . 6 (TBTCR) , 00000010B (TBTCR) , 00001010B ; TBTCK 010 ; TBTEN 1 ; IMF 0 Table 6-1 Time Base Timer Interrupt Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Time Base Timer Interrupt Frequency [Hz] TBTCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 010 011 100 101 110 111 1.91 7.63 244.14 976.56 1953.13 3906.25 7812.5 31250 NORMAL1/2, IDLE1/2 Mode DV7CK = 1 1 4 128 512 1024 2048 4096 16384 1 4 - - - - - - SLOW1/2, SLEEP1/2 Mode 6.1.3 Function An INTTBT ( Time Base Timer Interrupt ) is generated on the first falling edge of source clock ( The divider output of the timing generato which is selected by TBTCK. ) after time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period ( Figure 6-2 ). Source clock TBTCR INTTBT Interrupt period Enable TBT Figure 6-2 Time Base Timer Interrupt Page 54 TMP86C845UG 6.2 Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from DVO pin. 6.2.1 Configuration Output latch Data output D Q DVO pin fc/213 or fs/25 fc/212 or fs/24 fc/211 or fs/23 fc/210 or fs/22 MPX A B CY D S 2 DVOCK TBTCR Divider output control register (a) configuration DVOEN Port output latch TBTCR DVO pin output (b) Timing chart Figure 6-3 Divider Output 6.2.2 Control The Divider Output is controlled by the Time Base Timer Control Register. Time Base Timer Control Register 7 TBTCR (0036H) DVOEN 6 DVOCK 5 4 (DV7CK) 3 (TBTEN) 2 1 (TBTCK) 0 (Initial value: 0000 0000) DVOEN Divider output enable / disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV7CK = 1 fs/25 fs/24 fs/23 fs/22 SLOW1/2 SLEEP1/2 Mode fs/25 fs/24 fs/23 fs/22 R/W DVOCK Divider Output (DVO) frequency selection: [Hz] 00 01 10 11 fc/213 fc/212 fc/211 fc/210 R/W Note: Selection of divider output frequency (DVOCK) must be made while divider output is disabled (DVOEN="0"). Also, in other words, when changing the state of the divider output frequency from enabled (DVOEN="1") to disable(DVOEN="0"), do not change the setting of the divider output frequency. Page 55 6. Time Base Timer (TBT) 6.2 Divider Output (DVO) TMP86C845UG Example :1.95 kHz pulse output (fc = 16.0 MHz) LD LD (TBTCR) , 00000000B (TBTCR) , 10000000B ; DVOCK "00" ; DVOEN "1" Table 6-2 Divider Output Frequency ( Example : fc = 16.0 MHz, fs = 32.768 kHz ) Divider Output Frequency [Hz] DVOCK NORMAL1/2, IDLE1/2 Mode DV7CK = 0 00 01 10 11 1.953 k 3.906 k 7.813 k 15.625 k DV7CK = 1 1.024 k 2.048 k 4.096 k 8.192 k SLOW1/2, SLEEP1/2 Mode 1.024 k 2.048 k 4.096 k 8.192 k Page 56 TMP86C845UG 7. Watchdog Timer (WDT) The watchdog timer is a fail-safe system to detect rapidly the CPU malfunctions such as endless loops due to spurious noises or the deadlock conditions, and return the CPU to a system recovery routine. The watchdog timer signal for detecting malfunctions can be programmed only once as "reset request" or "interrupt request". Upon the reset release, this signal is initialized to "reset request". When the watchdog timer is not used to detect malfunctions, it can be used as the timer to provide a periodic interrupt. Note: Care must be taken in system design since the watchdog timer functions are not be operated completely due to effect of disturbing noise. 7.1 Watchdog Timer Configuration Reset release fc/2 or fs/2 fc/221 or fs/213 fc/219 or fs/211 fc/217 or fs/29 23 15 Selector Binary counters Clock Clear 1 2 Overflow WDT output R S Q Reset request INTWDT interrupt request 2 Interrupt request Internal reset Q SR WDTEN WDTT Writing disable code Writing clear code WDTOUT Controller 0034H WDTCR1 0035H WDTCR2 Watchdog timer control registers Figure 7-1 Watchdog Timer Configuration Page 57 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP86C845UG 7.2 Watchdog Timer Control The watchdog timer is controlled by the watchdog timer control registers (WDTCR1 and WDTCR2). The watchdog timer is automatically enabled after the reset release. 7.2.1 Malfunction Detection Methods Using the Watchdog Timer The CPU malfunction is detected, as shown below. 1. Set the detection time, select the output, and clear the binary counter. 2. Clear the binary counter repeatedly within the specified detection time. If the CPU malfunctions such as endless loops or the deadlock conditions occur for some reason, the watchdog timer output is activated by the binary-counter overflow unless the binary counters are cleared. When WDTCR1 Note:The watchdog timer consists of an internal divider and a two-stage binary counter. When the clear code 4EH is written, only the binary counter is cleared, but not the internal divider. The minimum binary-counter overflow time, that depends on the timing at which the clear code (4EH) is written to the WDTCR2 register, may be 3/ 4 of the time set in WDTCR1 Example :Setting the watchdog timer detection time to 221/fc [s], and resetting the CPU malfunction detection LD LD LD (WDTCR2), 4EH (WDTCR1), 00001101B (WDTCR2), 4EH : Clears the binary counters. : WDTT 10, WDTOUT 1 : Clears the binary counters (always clears immediately before and after changing WDTT). Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Within 3/4 of WDT detection time : : LD (WDTCR2), 4EH : Clears the binary counters. Page 58 TMP86C845UG Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 (ATAS) 4 (ATOUT) 3 WDTEN 2 WDTT 1 0 WDTOUT (Initial value: **11 1001) WDTEN Watchdog timer enable/disable 0: Disable (Writing the disable code to WDTCR2 is required.) 1: Enable NORMAL1/2 mode DV7CK = 0 DV7CK = 1 217/fs 215/fs 213/fs 211/fs SLOW1/2 mode 217/fs 215fs 213fs 211/fs Write only WDTT Watchdog timer detection time [s] 00 01 10 11 225/fc 223/fc 221fc 219/fc Write only WDTOUT Watchdog timer output select 0: Interrupt request 1: Reset request Write only Note 1: After clearing WDTOUT to "0", the program cannot set it to "1". Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 3: WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. If WDTCR1 is read, a don't care is read. Note 4: To activate the STOP mode, disable the watchdog timer or clear the counter immediately before entering the STOP mode. After clearing the counter, clear the counter again immediately after the STOP mode is inactivated. Note 5: To clear WDTEN, set the register in accordance with the procedures shown in "1.2.3 Watchdog Timer Disable". Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code 4EH: Clear the watchdog timer binary counter (Clear code) B1H: Disable the watchdog timer (Disable code) D2H: Enable assigning address trap area Others: Invalid Write only Note 1: The disable code is valid only when WDTCR1 7.2.2 Watchdog Timer Enable Setting WDTCR1 Page 59 7. Watchdog Timer (WDT) 7.2 Watchdog Timer Control TMP86C845UG 7.2.3 Watchdog Timer Disable To disable the watchdog timer, set the register in accordance with the following procedures. Setting the register in other procedures causes a malfunction of the microcontroller. 1. Set the interrupt master flag (IMF) to "0". 2. Set WDTCR2 to the clear code (4EH). 3. Set WDTCR1 Note:While the watchdog timer is disabled, the binary counters of the watchdog timer are cleared. Example :Disabling the watchdog timer DI LD LDW (WDTCR2), 04EH (WDTCR1), 0B101H : IMF 0 : Clears the binary coutner : WDTEN 0, WDTCR2 Disable code Table 7-1 Watchdog Timer Detection Time (Example: fc = 16.0 MHz, fs = 32.768 kHz) Watchdog Timer Detection Time[s] WDTT DV7CK = 0 00 01 10 11 2.097 524.288 m 131.072 m 32.768 m NORMAL1/2 mode DV7CK = 1 4 1 250 m 62.5 m SLOW mode 4 1 250 m 62.5 m 7.2.4 Watchdog Timer Interrupt (INTWDT) When WDTCR1 Example :Setting watchdog timer interrupt LD LD SP, 013FH (WDTCR1), 00001000B : Sets the stack pointer : WDTOUT 0 Page 60 TMP86C845UG 7.2.5 Watchdog Timer Reset When a binary-counter overflow occurs while WDTCR1 Note:When a watchdog timer reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. 219/fc [s] 217/fc Clock Binary counter Overflow INTWDT interrupt request (WDTCR1 (WDTT=11) 1 2 3 0 1 2 3 0 Internal reset (WDTCR1 A reset occurs Write 4EH to WDTCR2 Figure 7-2 Watchdog Timer Interrupt Page 61 7. Watchdog Timer (WDT) 7.3 Address Trap TMP86C845UG 7.3 Address Trap The Watchdog Timer Control Register 1 and 2 share the addresses with the control registers to generate address traps. Watchdog Timer Control Register 1 WDTCR1 (0034H) 7 6 5 ATAS 4 ATOUT 3 (WDTEN) 2 (WDTT) 1 0 (WDTOUT) (Initial value: **11 1001) ATAS Select address trap generation in the internal RAM area Select opertion at address trap 0: Generate no address trap 1: Generate address traps (After setting ATAS to "1", writing the control code D2H to WDTCR2 is reguired) 0: Interrupt request 1: Reset request Write only ATOUT Watchdog Timer Control Register 2 WDTCR2 (0035H) 7 6 5 4 3 2 1 0 (Initial value: **** ****) WDTCR2 Write Watchdog timer control code and address trap area control code D2H: Enable address trap area selection (ATRAP control code) 4EH: Clear the watchdog timer binary counter (WDT clear code) B1H: Disable the watchdog timer (WDT disable code) Others: Invalid Write only 7.3.1 Selection of Address Trap in Internal RAM (ATAS) WDTCR1 7.3.2 Selection of Operation at Address Trap (ATOUT) When an address trap is generated, either the interrupt request or the reset request can be selected by WDTCR1 7.3.3 Address Trap Interrupt (INTATRAP) While WDTCR1 Page 62 TMP86C845UG 7.3.4 Address Trap Reset While WDTCR1 Note:When an address trap reset is generated in the SLOW1 mode, the reset time is maximum 24/fc (high-frequency clock) since the high-frequency clock oscillator is restarted. However, when crystals have inaccuracies upon start of the high-frequency clock oscillator, the reset time should be considered as an approximate value because it has slight errors. Page 63 7. Watchdog Timer (WDT) 7.3 Address Trap TMP86C845UG Page 64 TMP86C845UG 8. 8-Bit TimerCounter (TC3, TC4) 8.1 Configuration PWM mode Overflow fc/211 or fs/23 INTTC4 interrupt request fc/2 5 fc/2 fc/23 fs 7 fc/2 fc TC4 pin TC4M TC4S TFF4 A B C D E F G H S Y A B S Y Clear 8-bit up-counter TC4S PDO, PPG mode A 16-bit mode 16-bit mode Y B S S A Y B Timer, Event Counter mode Toggle Q Set Clear Timer F/F4 PDO4/PWM4/ PPG4 pin TC4CK TC4CR TTREG4 PWREG4 PWM, PPG mode DecodeEN TFF4 PDO, PWM, PPG mode 16-bit mode TC3S PWM mode fc/211 or fs/23 fc/27 5 fc/2 3 fc/2 fs TC3 pin TC3M TC3S TFF3 fc/2 fc A B C D E F G H S Clear Y 8-bit up-counter Overflow 16-bit mode PDO mode INTTC3 interrupt request 16-bit mode Timer, Event Couter mode Toggle Q Set Clear Timer F/F3 PDO3/PWM3/ pin TC3CK TC3CR TTREG3 PWREG3 PWM mode DecodeEN TFF3 PDO, PWM mode 16-bit mode Figure 8-1 8-Bit TimerCouter 3, 4 Page 65 8. 8-Bit TimerCounter (TC3, TC4) 8.1 Configuration TMP86C845UG 8.2 TimerCounter Control The TimerCounter 3 is controlled by the TimerCounter 3 control register (TC3CR) and two 8-bit timer registers (TTREG3, PWREG3). TimerCounter 3 Timer Register TTREG3 (0018H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG3 (001AH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG3) setting while the timer is running. Note 2: Do not change the timer register (PWREG3) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 3 Control Register TC3CR (0016H) 7 TFF3 6 5 TC3CK 4 3 TC3S 2 1 TC3M 0 (Initial value: 0000 0000) TFF3 Time F/F3 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - fc (Note 8) R/W 000 001 TC3CK Operating clock selection [Hz] 010 011 100 101 110 111 TC3S TC3 start control 0: 1: 000: 001: TC3M TC3M operating mode select 010: 011: 1**: fc/211 fc/27 fc/25 fc/23 fs fc/2 fc R/W Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode 16-bit mode (Each mode is selectable with TC4M.) Reserved R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock[Hz] Note 2: Do not change the TC3M, TC3CK and TFF3 settings while the timer is running. Note 3: To stop the timer operation (TC3S= 1 0), do not change the TC3M, TC3CK and TFF3 settings. To start the timer operation (TC3S= 0 1), TC3M, TC3CK and TFF3 can be programmed. Note 4: To use the TimerCounter in the 16-bit mode, set the operating mode by programming TC4CR Page 66 TMP86C845UG Note 7: The timer register settings are limited depending on the timer operating mode. For the detailed descriptions, see Table 83. Note 8: The operating clock fc in the SLOW or SLEEP mode can be used only as the high-frequency warm-up mode. Page 67 8. 8-Bit TimerCounter (TC3, TC4) 8.1 Configuration TMP86C845UG The TimerCounter 4 is controlled by the TimerCounter 4 control register (TC4CR) and two 8-bit timer registers (TTREG4 and PWREG4). TimerCounter 4 Timer Register TTREG4 (0019H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) PWREG4 (001BH) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) Note 1: Do not change the timer register (TTREG4) setting while the timer is running. Note 2: Do not change the timer register (PWREG4) setting in the operating mode except the 8-bit and 16-bit PWM modes while the timer is running. TimerCounter 4 Control Register TC4CR (0017H) 7 TFF4 6 5 TC4CK 4 3 TC4S 2 1 TC4M 0 (Initial value: 0000 0000) TFF4 Timer F/F4 control 0: 1: Clear Set NORMAL1/2, IDLE1/2 mode DV7CK = 0 DV7CK = 1 fs/23 fc/27 fc/25 fc/2 fs fc/2 fc TC4 pin input 3 R/W SLOW1/2 SLEEP1/2 mode fs/23 - - - fs - - R/W 000 001 TC4CK Operating clock selection [Hz] 010 011 100 101 110 111 TC4S TC4 start control 0: 1: 000: 001: 010: TC4M TC4M operating mode select 011: 100: 101: 110: 111: fc/211 fc/27 fc/25 fc/2 fs fc/2 fc 3 Operation stop and counter clear Operation start 8-bit timer/event counter mode 8-bit programmable divider output (PDO) mode 8-bit pulse width modulation (PWM) output mode Reserved 16-bit timer/event counter mode Warm-up counter mode 16-bit pulse width modulation (PWM) output mode 16-bit PPG mode R/W R/W Note 1: fc: High-frequency clock [Hz] fs: Low-frequency clock [Hz] Note 2: Do not change the TC4M, TC4CK and TFF4 settings while the timer is running. Note 3: To stop the timer operation (TC4S= 1 0), do not change the TC4M, TC4CK and TFF4 settings. To start the timer operation (TC4S= 0 1), TC4M, TC4CK and TFF4 can be programmed. Note 4: When TC4M= 1** (upper byte in the 16-bit mode), the source clock becomes the TC4 overflow signal regardless of the TC3CK setting. Note 5: To use the TimerCounter in the 16-bit mode, select the operating mode by programming TC4M, where TC3CR Page 68 TMP86C845UG Note 6: To the TimerCounter in the 16-bit mode, select the source clock by programming TC3CR Table 8-1 Operating Mode and Selectable Source Clock (NORMAL1/2 and IDLE1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input - - - - - TC4 pin input - - - - - - - - Note 1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note 2: : Available source clock Table 8-2 Operating Mode and Selectable Source Clock (SLOW1/2 and SLEEP1/2 Modes) Operating mode fc/211 or fs/23 8-bit timer 8-bit event counter 8-bit PDO 8-bit PWM 16-bit timer 16-bit event counter Warm-up counter 16-bit PWM 16-bit PPG - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - - fc/27 fc/25 fc/23 fs fc/2 fc TC3 pin input - - - - - TC4 pin input - - - - - - - - Note1: For 16-bit operations (16-bit timer/event counter, warm-up counter, 16-bit PWM and 16-bit PPG), set its source clock on lower bit (TC3CK). Note2: : Available source clock Page 69 8. 8-Bit TimerCounter (TC3, TC4) 8.1 Configuration TMP86C845UG Table 8-3 Constraints on Register Values Being Compared Operating mode 8-bit timer/event counter 8-bit PDO 8-bit PWM 16-bit timer/event counter Warm-up counter 16-bit PWM 1 (TTREGn) 255 1 (TTREGn) 255 2 (PWREGn) 254 1 (TTREG4, 3) 65535 256 (TTREG4, 3) 65535 2 (PWREG4, 3) 65534 1 (PWREG4, 3) < (TTREG4, 3) 65535 16-bit PPG and (PWREG4, 3) + 1 < (TTREG4, 3) Register Value Note: n = 3 to 4 Page 70 TMP86C845UG 8.3 Function The TimerCounter 3 and 4 have the 8-bit timer, 8-bit event counter, 8-bit programmable divider output (PDO), 8bit pulse width modulation (PWM) output modes. The TimerCounter 3 and 4 (TC3, 4) are cascadable to form a 16bit timer. The 16-bit timer has the operating modes such as the 16-bit timer, 16-bit event counter, warm-up counter, 16-bit pulse width modulation (PWM) output and 16-bit programmable pulse generation (PPG) modes. 8.3.1 8-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. When a match between the up-counter and the timer register j (TTREGj) value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting. Note 1: In the timer mode, fix TCjCR Table 8-4 Source Clock for TimerCounter 3, 4 (Internal Clock) Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/27 fc/25 fc/23 DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - Resolution Repeated Cycle fc = 16 MHz fs = 32.768 kHz fc = 16 MHz fs = 32.768 kHz 128 s 8 s 2 s 500 ns 244.14 s - - - 32.6 ms 2.0 ms 510 s 127.5 s 62.3 ms - - - Example :Setting the timer mode with source clock fc/27 Hz and generating an interrupt 80 s later (TimerCounter4, fc = 16.0 MHz) LD DI SET EI LD LD (TC4CR), 00010000B (TC4CR), 00011000B : Sets the operating cock to fc/27, and 8-bit timer mode. : Starts TC4. (EIRH). 1 : Enables INTTC4 interrupt. (TTREG4), 0AH : Sets the timer register (80 s/27/fc = 0AH). Page 71 8. 8-Bit TimerCounter (TC3, TC4) 8.1 Configuration TMP86C845UG TC4CR Internal Source Clock Counter TTREG4 1 2 3 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 8-2 8-Bit Timer Mode Timing Chart (TC4) 8.3.2 8-Bit Event Counter Mode (TC3, 4) In the 8-bit event counter mode, the up-counter counts up at the falling edge of the input pulse to the TCj pin. When a match between the up-counter and the TTREGj value is detected, an INTTCj interrupt is generated and the up-counter is cleared. After being cleared, the up-counter restarts counting at the falling edge of the input pulse to the TCj pin. Two machine cycles are required for the low- or high-level pulse input to the TCj pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1/2 or IDLE1/2 mode, and fs/24 Hz in the SLOW1/2 or SLEEP1/2 mode. Note 1: In the event counter mode, fix TCjCR TC4CR Counter TTREG4 0 1 2 n-1 n0 1 2 n-1 n0 1 2 0 ? n Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 8-3 8-Bit Event Counter Mode Timing Chart (TC4) 8.3.3 8-Bit Programmable Divider Output (PDO) Mode (TC3, 4) This mode is used to generate a pulse with a 50% duty cycle from the PDOj pin. In the PDO mode, the up-counter counts up using the internal clock. When a match between the up-counter and the TTREGj value is detected, the logic level output from the PDOj pin is switched to the opposite state and the up-counter is cleared. The INTTCj interrupt request is generated at the time. The logic state opposite to the timer F/Fj logic level is output from the PDOj pin. An arbitrary value can be set to the timer F/Fj by TCjCR Page 72 TMP86C845UG Example :Generating 1024 Hz pulse using TC4 (fc = 16.0 MHz) Setting port LD LD LD (TTREG4), 3DH (TC4CR), 00010001B (TC4CR), 00011001B : 1/1024/27/fc/2 = 3DH : Sets the operating clock to fc/27, and 8-bit PDO mode. : Starts TC4. Note 1: In the programmable divider output mode, do not change the TTREGj setting while the timer is running. Since TTREGj is not in the shift register configuration in the programmable divider output mode, the new value programmed in TTREGj is in effect immediately after programming. Therefore, if TTREGi is changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PDO output, the PDOj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Page 73 8.1 Configuration 8. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Write of "1" Internal source clock n0 1 2 n0 1 2 n0 1 2 n0 1 2 3 0 Counter 0 1 2 Figure 8-4 8-Bit PDO Mode Timing Chart (TC4) Match detect Match detect Match detect Page 74 TTREG4 ? n Match detect Timer F/F4 Set F/F PDO4 pin INTTC4 interrupt request Held at the level when the timer is stopped TMP86C845UG TMP86C845UG 8.3.4 8-Bit Pulse Width Modulation (PWM) Output Mode (TC3, 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 8 bits of resolution. The up-counter counts up using the internal clock. When a match between the up-counter and the PWREGj value is detected, the logic level output from the timer F/Fj is switched to the opposite state. The counter continues counting. The logic level output from the timer F/Fj is switched to the opposite state again by the up-counter overflow, and the counter is cleared. The INTTCj interrupt request is generated at this time. Since the initial value can be set to the timer F/Fj by TCjCR Note 1: In the PWM mode, program the timer register PWREGj immediately after the INTTCj interrupt request is generated (normally in the INTTCj interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of the pulse different from the programmed value until the next INTTCj interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWMj pin holds the output status when the timer is stopped. To change the output status, program TCjCR Table 8-5 PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 [Hz] fc/2 fc/2 7 5 Resolution SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - fc = 16 MHz 128 s 8 s 2 s 500 ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 32.8 ms 2.05 ms 512 s 128 s 7.81 ms 32 s 16 s fs = 32.768 kHz 62.5 ms - - - 7.81 ms - - DV7CK = 1 fs/23 [Hz] fc/2 fc/2 7 5 fc/23 fs fc/2 fc fc/23 fs fc/2 fc Page 75 8.1 Configuration 8. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Internal source clock n Write to PWREG4 Counter 0 1 n+1 FF 0 1 n n+1 FF 0 1 m m+1 FF 0 1 p Write to PWREG4 Figure 8-5 8-Bit PWM Mode Timing Chart (TC4) m Shift Shift m Match detect Match detect Page 76 n One cycle period m PWREG4 ? n p Shift p Match detect Shift Shift registar ? n Match detect Timer F/F4 PWM4 pin n p INTTC4 interrupt request TMP86C845UG TMP86C845UG 8.3.5 16-Bit Timer Mode (TC3 and 4) In the timer mode, the up-counter counts up using the internal clock. The TimerCounter 3 and 4 are cascadable to form a 16-bit timer. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR Note 1: In the timer mode, fix TCjCR Table 8-6 Source Clock for 16-Bit Timer Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 DV7CK = 1 fs/23 fc/27 fc/25 fc/23 SLOW1/2, SLEEP1/2 mode fs/23 - - - Resolution fc = 16 MHz 128 s 8 s 2 s 500 ns fs = 32.768 kHz 244.14 s - - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms fs = 32.768 kHz 16 s - - - Example :Setting the timer mode with source clock fc/27 Hz, and generating an interrupt 300 ms later (fc = 16.0 MHz) LDW DI SET EI LD (TC3CR), 13H :Sets the operating cock to fc/27, and 16-bit timer mode (lower byte). : Sets the 16-bit timer mode (upper byte). : Starts the timer. (EIRH). 1 : Enables INTTC4 interrupt. (TTREG3), 927CH : Sets the timer register (300 ms/27/fc = 927CH). LD LD (TC4CR), 04H (TC4CR), 0CH TC4CR Internal source clock Counter TTREG3 (Lower byte) TTREG4 (Upper byte) 0 1 2 3 mn-1 mn 0 1 2 mn-1 mn 0 1 2 0 ? n ? m Match detect Counter clear Match detect Counter clear INTTC4 interrupt request Figure 8-6 16-Bit Timer Mode Timing Chart (TC3 and TC4) Page 77 8. 8-Bit TimerCounter (TC3, TC4) 8.1 Configuration TMP86C845UG 8.3.6 16-Bit Event Counter Mode (TC3 and 4) In the event counter mode, the up-counter counts up at the falling edge to the TC3 pin. The TimerCounter 3 and 4 are cascadable to form a 16-bit event counter. When a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected after the timer is started by setting TC4CR Note 1: In the event counter mode, fix TCjCR 8.3.7 16-Bit Pulse Width Modulation (PWM) Output Mode (TC3 and 4) This mode is used to generate a pulse-width modulated (PWM) signals with up to 16 bits of resolution. The TimerCounter 3 and 4 are cascadable to form the 16-bit PWM signal generator. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again by the counter overflow, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fs/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR Note 1: In the PWM mode, program the timer register PWREG4 and 3 immediately after the INTTC4 interrupt request is generated (normally in the INTTC4 interrupt service routine.) If the programming of PWREGj and the interrupt request occur at the same time, an unstable value is shifted, that may result in generation of pulse different from the programmed value until the next INTTC4 interrupt request is generated. Note 2: When the timer is stopped during PWM output, the PWM4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR Page 78 TMP86C845UG CLR (TC4CR).3: Stops the timer. CLR (TC4CR).7 : Sets the PWM4 pin to the high level. Note 3: To enter the STOP mode, stop the timer and then enter the STOP mode. If the STOP mode is entered without stopping of the timer when fc, fc/2 or fs is selected as the source clock, a pulse is output from the PWM4 pin during the warm-up period time after exiting the STOP mode. Table 8-7 16-Bit PWM Output Mode Source Clock NORMAL1/2, IDLE1/2 mode DV7CK = 0 fc/211 fc/27 fc/25 fc/23 fs fc/2 fc DV7CK = 1 fs/23 [Hz] fc/27 fc/25 fc/23 fs fc/2 fc SLOW1/2, SLEEP1/2 mode fs/23 [Hz] - - - fs - - Resolution fc = 16 MHz 128 s 8 s 2 s 500ns 30.5 s 125 ns 62.5 ns fs = 32.768 kHz 244.14 s - - - 30.5 s - - Repeated Cycle fc = 16 MHz 8.39 s 524.3 ms 131.1 ms 32.8 ms 2 s fs = 32.768 kHz 16 s - - - 2s - - 8.2 ms 4.1 ms Example :Generating a pulse with 1-ms high-level width and a period of 32.768 ms (fc = 16.0 MHz) Setting ports LDW LD (PWREG3), 07D0H (TC3CR), 33H : Sets the pulse width. : Sets the operating clock to fc/23, and 16-bit PWM output mode (lower byte). : Sets TFF4 to the initial value 0, and 16-bit PWM signal generation mode (upper byte). : Starts the timer. LD LD (TC4CR), 056H (TC4CR), 05EH Page 79 8.1 Configuration 8. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Internal source clock an Write to PWREG3 Counter 0 1 an+1 FFFF 0 1 an an+1 FFFF 0 1 bm bm+1 Write to PWREG3 FFFF 0 1 cp PWREG3 (Lower byte) ? Write to PWREG4 n m p Write to PWREG4 Figure 8-7 16-Bit PWM Mode Timing Chart (TC3 and TC4) Page 80 b Shift Shift bm Match detect an One cycle period PWREG4 (Upper byte) ? a c Shift cp Match detect Match detect Shift 16-bit shift register ? an Match detect Timer F/F4 PWM4 pin an bm cp INTTC4 interrupt request TMP86C845UG TMP86C845UG 8.3.8 16-Bit Programmable Pulse Generate (PPG) Output Mode (TC3 and 4) This mode is used to generate pulses with up to 16-bits of resolution. The timer counter 3 and 4 are cascadable to enter the 16-bit PPG mode. The counter counts up using the internal clock or external clock. When a match between the up-counter and the timer register (PWREG3, PWREG4) value is detected, the logic level output from the timer F/F4 is switched to the opposite state. The counter continues counting. The logic level output from the timer F/F4 is switched to the opposite state again when a match between the up-counter and the timer register (TTREG3, TTREG4) value is detected, and the counter is cleared. The INTTC4 interrupt is generated at this time. Two machine cycles are required for the high- or low-level pulse input to the TC3 pin. Therefore, a maximum frequency to be supplied is fc/24 Hz in the NORMAL1 or IDLE1 mode, and fc/24 to in the SLOW1/2 or SLEEP1/2 mode. Since the initial value can be set to the timer F/F4 by TC4CR Example :Generating a pulse with 1-ms high-level width and a period of 16.385 ms (fc = 16.0 MHz) Setting ports LDW LDW LD (PWREG3), 07D0H (TTREG3), 8002H (TC3CR), 33H : Sets the pulse width. : Sets the cycle period. : Sets the operating clock to fc/23, and16-bit PPG mode (lower byte). : Sets TFF4 to the initial value 0, and 16-bit PPG mode (upper byte). : Starts the timer. LD LD (TC4CR), 057H (TC4CR), 05FH Note 1: In the PPG mode, do not change the PWREGi and TTREGi settings while the timer is running. Since PWREGi and TTREGi are not in the shift register configuration in the PPG mode, the new values programmed in PWREGi and TTREGi are in effect immediately after programming PWREGi and TTREGi. Therefore, if PWREGi and TTREGi are changed while the timer is running, an expected operation may not be obtained. Note 2: When the timer is stopped during PPG output, the PPG4 pin holds the output status when the timer is stopped. To change the output status, program TC4CR Page 81 8.1 Configuration 8. 8-Bit TimerCounter (TC3, TC4) TC4CR TC4CR Write of "0" Internal source clock 1 mn mn+1 qr-1 qr 0 1 mn mn+1 1 qr-1 qr 0 mn mn+1 0 Counter 0 PWREG3 (Lower byte) ? n Figure 8-8 16-Bit PPG Mode Timing Chart (TC3 and TC40) Page 82 Match detect Match detect Match detect mn mn PWREG4 (Upper byte) ? m Match detect Match detect TTREG3 (Lower byte) ? r TTREG4 (Upper byte) ? q F/F clear Held at the level when the timer stops mn Timer F/F4 PPG4 pin INTTC4 interrupt request TMP86C845UG TMP86C845UG 8.3.9 Warm-Up Counter Mode In this mode, the warm-up period time is obtained to assure oscillation stability when the system clocking is switched between the high-frequency and low-frequency. The timer counter 3 and 4 are cascadable to form a 16-bit TimerCouter. The warm-up counter mode has two types of mode; switching from the high-frequency to low-frequency, and vice-versa. Note 1: In the warm-up counter mode, fix TCiCR 8.3.9.1 Low-Frequency Warm-up Counter Mode (NORMAL1 NORMAL2 SLOW2 SLOW1) In this mode, the warm-up period time from a stop of the low-frequency clock fs to oscillation stability is obtained. Before starting the timer, set SYSCR2 Table 8-8 Setting Time of Low-Frequency Warm-Up Counter Mode (fs = 32.768 kHz) Maximum Time Setting (TTREG4, 3 = 0100H) 7.81 ms Maximum Time Setting (TTREG4, 3 = FF00H) 1.99 s Example :After checking low-frequency clock oscillation stability with TC4 and 3, switching to the SLOW1 mode SET LD LD LD DI SET EI SET : PINTTC4: CLR SET (TC4CR).3 : (TC4CR).3 (SYSCR2).5 : Stops TC4 and 3. : SYSCR2 CLR RETI : VINTTC4: DW (SYSCR2).7 : PINTTC4 : INTTC4 vector table Page 83 8. 8-Bit TimerCounter (TC3, TC4) 8.1 Configuration TMP86C845UG 8.3.9.2 High-Frequency Warm-Up Counter Mode (SLOW1 SLOW2 NORMAL2 NORMAL1) In this mode, the warm-up period time from a stop of the high-frequency clock fc to the oscillation stability is obtained. Before starting the timer, set SYSCR2 Table 8-9 Setting Time in High-Frequency Warm-Up Counter Mode Minimum time (TTREG4, 3 = 0100H) 16 s Maximum time (TTREG4, 3 = FF00H) 4.08 ms Example :After checking high-frequency clock oscillation stability with TC4 and 3, switching to the NORMAL1 mode SET LD LD LD (SYSCR2).7 (TC3CR), 63H (TC4CR), 05H (TTREG3), 0F800H : SYSCR2 DI SET EI SET : PINTTC4: CLR CLR CLR (SYSCR2).6 RETI : VINTTC4: DW : PINTTC4 : INTTC4 vector table Page 84 TMP86C845UG 9. Synchronous Serial Interface (SIO) The serial interfaces connect to an external device via SI, SO, and SCK pins. When these pins are used as serial interface, the output latches for each port should be set to "1". 9.1 Configuration Internal data bus SIOCR1 SIOSR SIOTDB Shift clock Control circuit MSB/LSB selection Shift register on transmitter Port (Note) Port (Note) SO pin (Serial data output) SI pin Shift register on receiver SIORDB (Serial data input) To BUS Port (Note) SCK pin INTSIO interrupt Internal clock input (Serial data output) Note: Set the register of port correctly for the port assigned as serial interface pins. For details, see the description of the input/output port control register. Figure 9-1 Synchronous Serial Interface (SIO) Page 85 9. Synchronous Serial Interface (SIO) 9.2 Control TMP86C845UG 9.2 Control The SIO is controlled using the serial interface control register (SIOCR1). The operating status of the serial interface can be inspected by reading the status register (SIOCR1). Serial Interface Control Register SIOCR1 (0026H) 7 SIOS 6 SIOINH 5 SIOM 4 3 SIODIR 2 1 SCK 0 (Initial value: 0000 0000) SIOS SIOINH Specify start/stop of transfer Forcibly stops transfer (Note 1) 0: Stop 1: Start 0: - 1: Forcibly stop (Automatically cleared to "0" after stopping) 00: Transmit mode 01: Receive mode 10: Transmit/receive mode 11: Reserved 0: MSB (Transfer beginning with bit7) 1: LSB (Transfer beginning with bit0) NORMAL1/2 or IDLE1/2 modes TBTCR SIOM Selects transfer mode SIODIR Selects direction of transfer R/W SCK Selects serial clock 010 011 100 101 110 111 Note 1: When SIOCR1 Page 86 TMP86C845UG Serial Interface Status Register SIOSR (0027H) 7 SIOF 6 SEF 5 TXF 4 RXF 3 TXERR 2 RXERR 1 0 (Initial value: 0010 00**) SIOF SEF TXF RXF Serial transfer operation status monitor Number of clocks monitor Transmit buffer empty flag Receive buffer full flag 0: Transfer finished 1: Transfer in progress 0: 8 clocks 1: 1 to 7 clocks 0: Data exists in transmit buffer 1: No data exists in transmit buffer 0: No data exists in receive buffer 1: Data exists in receive buffer Read 0: - (No error exist) 1: Transmit buffer under run occurs in an external clock mode Write 0: Clear the flag 1: - (A write of "1" to this bit is ignored) Read 0: - (No error exist) 1: Receive buffer over run occurs in an external clock mode Write 0: Clear the flag 1: - (A write of "1" to this bit is ignored) Read only TXERR Transfer operation error flag R/W RXERR Receive operation error flag Note 1: The operation error flag (TXERR and RXERR) are not automatically cleared by stopping transfer with SIOCR1 Receive buffer register SIORDB (0028H) 7 6 5 4 3 2 1 0 Read only (Initial value: 0000 0000) Transmit buffer register SIOTDB (0028H) 7 6 5 4 3 2 1 0 Write only (Initial value: **** ****) Note 1: SIOTDB is write only register. A bit manipulation should not be performed on the transmit buffer register using a readmodify-write instruction. Note 2: The SIOTDB should be written after checking SIOSR Page 87 9. Synchronous Serial Interface (SIO) 9.3 Function TMP86C845UG 9.3 Function 9.3.1 Serial clock Clock source The serial clock can be selected by using SIOCR1 9.3.1.1 SIOCR1 Automatically wait SCK pin output SO pin SIOTDB A A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 B Automatic wait is released by writing SIOTDB Figure 9-2 Automatic-wait Function (Example of transmit mode) Table 9-1 Serial Clock Rate (fc = 16 MHz, fs = 32.768kHz) NORMAL1/2, IDLE1/2 Mode TBTCR Page 88 TMP86C845UG (2) External clock When an external clock is selected by setting SIOCR1 SCK pin tSCKL tSCKH tSCKL, tSCKH > 4/fc Figure 9-3 External Clock 9.3.1.2 Shift edge The leading edge is used to transmit data, and the trailing edge is used to receive data. (1) Leading edge shift Data is shifted on the leading edge of the serial clock (falling edge of the SCK pin input/output). (2) Trailing edge shift Data is shifted on the trailing edge of the serial clock (rising edge of the SCK pin input/output). SIOCR1 SCK pin Shift register 01234567 *0123456 Shift out **012345 ***01234 ****0123 *****012 ******01 *******0 ******** SO pin Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 (a) Leading edge shift (Example of MSB transfer) SIOCR1 SCK pin SI pin Shift register Bit7 ******** 7******* Bit6 67****** Bit5 567***** Bit4 4567**** Bit3 34567*** Bit2 Bit1 234567** Bit0 1234567* 01234567 (b) Trailing edge shift (Example of MSB transfer) Figure 9-4 Shift Edge Page 89 9. Synchronous Serial Interface (SIO) 9.3 Function TMP86C845UG 9.3.2 Transfer bit direction Transfer data direction can be selected by using SIOCR1 SIOCR1 SCK pin SIOTDB SO pin A Shift out A7 A6 A5 A4 A3 A2 A1 A0 (a) MSB transfer SIOCR1 SCK pin SIOTDB SO pin A Shift out A0 A1 A2 A3 A4 A5 A6 A7 (b) LSB transfer Figure 9-5 Transfer Bit Direction (Example of transmit mode) 9.3.2.1 Transmit mode (1) MSB transmit mode MSB transmit mode is selected by setting SIOCR1 9.3.2.2 Receive mode (1) MSB receive mode MSB receive mode is selected by setting SIOCR1 Page 90 TMP86C845UG (2) LSB receive mode LSB receive mode is selected by setting SIOCR1 9.3.2.3 Transmit/receive mode (1) MSB transmit/receive mode MSB transmit/receive mode are selected by setting SIOCR1 9.3.3 Transfer modes Transmit, receive and transmit/receive mode are selected by using SIOCR1 9.3.3.1 Transmit mode Transmit mode is selected by writing "00B" to SIOCR1 SCK pin. The data is transferred sequentially starting from SO pin with the direction of the bit specified by SIOCR1 Note 1: In internal clock operation, when SIOCR1 Page 91 9. Synchronous Serial Interface (SIO) 9.3 Function TMP86C845UG (2) During the transmit operation When data is written to SIOTDB, SIOSR (3) Stopping the transmit operation There are two ways for stopping transmits operation. * The way of clearing SIOCR1 Clearing SIOS SIOCR1 Start shift operation Start shift operation Start shift operation SCK pin outout Automatic wait SO pin SIOSR A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 A B C Writing transmit Writing transmit data A data B Writing transmit data C Figure 9-6 Example of Internal Clock and MSB Transmit Mode Page 92 TMP86C845UG Writing transmit data SIOCR1 Clearing SIOS SIOSR Start shift operation Start shift operation Start shift operation SIOSR SCK pin SO pin A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 C7 C6 C5 C4 C3 C2 C1 C0 SIOSR A B C Writing transmit data A Writing transmit data B Writing transmit data C Figure 9-7 Exaple of External Clock and MSB Transmit Mode SCK pin SIOSR SO pin tSODH 4/fc < tSODH < 8/fc Figure 9-8 Hold Time of the End of Transmit Mode (4) Transmit error processing Transmit errors occur on the following situation. * Shift operation starts before writing next transmit data to SIOTDB in external clock operation. If transmit errors occur during transmit operation, SIOSR Page 93 9. Synchronous Serial Interface (SIO) 9.3 Function TMP86C845UG SIOCR1 SCK pin Start shift operation Start shift operation Start shift operation SO pin SIOSR A7 A6 A5 A4 A3 A2 A1 A0 B7 B6 B5 B4 B3 B2 B1 B0 A B Unknown SIOCR1 Writing transmit data A Writing transmit data B Figure 9-9 Example of Transmit Error Processingme 9.3.3.2 Receive mode The receive mode is selected by writing "01B" to SIOCR Note: In internal clock operation, when the SIOCR1 (2) During the receive operation The SIOSR TMP86C845UG If received data is not read out from SIORDB receive error occurs immediately after shift operation is finished. Then INTSIO interrupt request is generated after SIOSR Clearing SIOS SIOCR1 |