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| TOSHIBA Original CMOS 16-Bit Microcontroller TLCS-900/L1 Series TMP91C824 Semiconductor Company Preface Thank you very much for making use of Toshiba microcomputer LSIs. Before use this LSI, refer the section, "Points of Note and Restrictions". Especially, take care below cautions. **CAUTION** How to release the HALT mode Usually, interrupts can release all halts status. However, the interrupts = (NMI , INT0 to INT3, INTRTC, INTALM0 to INTALM4), which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficultly. The priority of this interrupt is compare with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. TMP91C824 CMOS 16-Bit Microcontrollers TMP91C824F/JTMP91C824-S 1. Outline and Features TMP91C824 is a high-speed 16-bit microcontroller designed for the control of various mid- to large-scale equipment. TMP91C824F comes in a 100-pin flat package. JTMP91C824-S is a chip form product. Listed below are the features. (1) High-speed 16-bit CPU (900/L1 CPU) * * * * * Instruction mnemonics are upward-compatible with TLCS-90 16 Mbytes of linear address space General-purpose registers and register banks 16-bit multiplication and division instructions; bit transfer and arithmetic instructions Micro DMA: 4 channels (485 ns/2 bytes at 33 MHz) (2) Minimum instruction execution time: 121 ns (at 33 MHz) (3) Built-in RAM: 8 Kbytes Built-in ROM: None 91C824-1 2005-12-16 TMP91C824 (4) External memory expansion * * * Expandable up to 106 Mbytes (shared program/data area) Can simultaneously support 8-/16-bit width external data bus Dynamic data bus sizing Separate bus system (5) 8-bit timers: 4 channels (6) General-purpose serial interface: 2 channels * * * * UART/Synchronous mode: 2 channels IrDA Ver.1.0 (115.2 kbps) mode selectable: 1 channel I2C bus mode/clock synchronous mode selectable Based on TC8521A (7) Serial bus interface: 1 channel (8) Timer for real-time clock (RTC) (9) 10-bit AD converter: 8 channels (10) Watchdog timer (11) Melody/alarm generator * * * Melody: Output of clock 4 to 5461 Hz Alarm: Output of the 8 kinds of alarm pattern Output of the 5 kinds of interval interrupt (12) Chip select/wait controller: 4 channels (13) Memory management unit * * * * Expandable up to 106 Mbytes (4 local areas/8-bank method) 9 CPU interrupts: Software interrupt instruction and illegal instruction (14) Interrupts: 37 interrupts 23 internal interrupts: 7 priority levels are selectable 5 external interrupts: 7 priority levels are selectable (among 4 interrupts are selectable edge mode) (15) Input/output ports: 35 pins (at external 16-bit data bus memory) (16) Standby function Three HALT modes: IDLE2 (Programmable), IDLE1 and STOP (17) Triple-clock controller * * * * * * * Clock doubler (DFM) circuit is inside Clock gear function: Select a high-frequency clock fc/1 to fc/16 Slow mode (fs = 32.768 kHz) VCC = 2.7 V to 3.6 V (fc max = 33 MHz) VCC = 1.8 V to 3.6 V (fc max = 10 MHz) 100-pin QFP: P-LQFP100-1414-0.50F Chip form supply also available. For details, contact your local Toshiba sales representative. (18) Operating voltage (19) Package 91C824-2 2005-12-16 TMP91C824 ADTRG (P83) DVCC [2] 10-bit 8-channel AD converter XWA XBC XDE XHL XIX XIY XIZ XSP WA BC DE HL IX IY IZ SP 32 bits SR F AN0 to AN7 (P80 to P87) AVCC, AVSS VREFH, VREFL TXD0 (PC0) RXD0 (PC1) SCLK0/ CTS0 (PC2) TXD1 (PC3) RXD1 (PC4) SCLK1/ CTS1 (PC5) OPTRX0, SCK (P70) OPTTX0, SO/SDA(P71) SI/SCL (P72) TA0IN (PB0) DVSS [2] X1 H-OSC X2 Clock gear, Clock doubler L-OSC XT2 SCOUT (PD5) EMU0 EMU1 XT1 SIO/UART/IrDA (SIO0) SIO/UART (SIO1) RESET AM0 AM1 Serial bus I/F(SBI) D0 to D7 A0 to A7 A8 to A15 8-bit timer (TMRA0) 8-bit timer (TMRA1) 8-bit timer (TMRA2) Port 1 P10 to P17 (D8 to D15) TA1OUT (PB1) Port 2 P20 to P27 (A16 to A23) RD TA3OUT (PB2) 8-bit timer (TMRA3) Port 6 WDT (Watchdog timer) Port Z WR HWR (PZ2) R/ W (PZ3) BUSRQ (P54) Port 5 BUSAK (P55) WAIT (P56) Port 8 8-Kbyte RAM CS/WAIT controller (4 blocks) CS0 to CS3 (P60 to P63), CS2A to CS2E (P62, P64 to P67) MMU (P60 to P67) Port B Port C Port D Interrupt controller Melody/ Alarm-out NMI INT0 to INT3 (PB3 to PB6) MLDALM (PD7) RTC ALARM , MLDALM (PD6) ( ): Initial function after reset Figure 1.1 TMP91C824 Block Diagram 91C824-3 2005-12-16 TMP91C824 2. Pin Assignment and Functions The assignment of input/output pins for the TMP91C824, their names and functions are as follows: 2.1 Pin Assignment Diagram Figure 2.1 shows the pin assignment of the TMP91C824F. VREFH P67/CS2E P66/CS2D P65/EA25/CS2C P64/EA24/CS2B P63/CS3 P62/CS2/CS2A P61/CS1 P60/CS0 P56/WAIT PZ3/R/W PZ2/HWR WR RD 100 95 90 85 80 A8 A9 A0 A1 A2 A3 A4 A5 A6 A7 A10 VREFL AVSS AVCC P80/AN0 P81/AN1 P82/AN2 P83/AN3/ ADTRG P84/AN4 P85/AN5 P86/AN6 P87/AN7 P70/SCK/OPTRX0 P71/S0/SDA/OPTTX0 P72/SI/SCL PB0/TA0IN PB1/TA1OUT PB2/TA3OUT PB3/INT0 PB4/INT1 PB5/INT2 PB6/INT3 P54/ BUSRQ P55/ BUSAK AM0 DVCC1 1 75 5 70 A11 A12 A13 A14 A15 P20/A16 P21/A17 P22/A18 P23/A19 P24/A20 P25/A21 DVCC2 NMI 10 TMP91C824F 65 QFP100 15 Top view 60 20 55 25 45 35 30 40 50 DVSS2 P26/A22 P27/A23 P17/D15 P16/D14 P15/D13 P14/D12 P13/D11 P12/D10 P11/D9 P10/D8 D7 Figure 2.1 Pin Assignment Diagram (100-pin QFP) 91C824-4 PC3/TXD1 PC4/RXD1 PC5/SCLK1/CTS1 PD5/SCOUT PD6/ALARM/MLDALM PD7/MLDAL D0 D1 D2 D3 D4 D5 D6 DVSS1 X1 AM1 RESET PC0/TXD0 PC1/RXD0 PC2/SCLK0/CTS0 X2 XT1 XT2 EMU0 EMU1 2005-12-16 TMP91C824 2.2 Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 Pad Layout Unit: m Pin No. 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 (Chip size 4.37 mm x 4.37 mm) Name VREFL AVSS AVCC P80 P81 P82 P83 P84 P85 P86 P87 P70 P71 P72 PB0 PB1 PB2 PB3 PB4 PB5 PB6 P54 P55 AM0 VCC X2 VSS X1 AM1 RESET X Point Y Point -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -1551 -1330 -1205 -1075 -948 -822 -520 -394 -267 1721 1596 1470 1337 1209 1076 943 810 677 544 416 148 15 -118 -251 -384 -517 -650 -783 -916 -1049 -1182 -1315 -1448 -1581 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 Name PC0 PC1 PC2 PC3 PC4 PC5 PD5 PD6 PD7 D0 D1 D2 D3 D4 D5 D6 D7 P10 P11 P12 P13 P14 P15 P16 P17 P27 P26 VSS NMI X Point Y Point -140 -14 112 238 365 491 618 744 871 998 1124 1251 1377 1504 1630 1757 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -2050 -1750 -1614 -1478 -1341 -1205 -1069 -933 -796 -660 -524 -388 -234 -80 240 394 530 666 803 Pin No. 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 Name P21 P20 A15 A14 A13 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 RD X Point Y Point 2045 2045 2045 2045 2045 2045 2045 1720 1591 1464 1337 1197 1058 918 778 639 499 359 219 80 -59 -199 -338 -478 -618 -757 -897 -1037 -1176 -1316 -1456 -1725 939 1075 1207 1337 1464 1592 1721 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 2045 WR PZ2 PZ3 P56 P60 P61 P62 P63 P64 P65 P66 P67 VREFH VCC P25 P24 P23 P22 XT1 XT2 EMU0 EMU1 91C824-5 2005-12-16 TMP91C824 2.3 Pin Names and Functions The names of the input/output pins and their functions are described below. Table 2.3.1 Pin Names and Functions (1/3) Pin Name Number of Pins 8 8 I/O I/O I/O 8 8 8 1 Output Output Output Output Output I/O Functions Data (Lower): Bits 0 to 7 of data bus Port 1: I/O port that allows I/O to be selected at the bit level (when used to the external 8-bit bus) Data (Upper): bits 8 to15 of data bus Port 2: Output port Address: Bits 16 to 23 of address bus Address: Bits 8 to 15 of address bus Address: Bits 0 to 7 of address bus Read: Strobe signal for reading external memory RD is outputted by setting PZ D0 to D7 P10 to P17 D8 to D15 P20 to P27 A16 to A23 A8 to A15 A0 to A7 RD WR 1 1 1 1 1 1 1 1 1 Output I/O Output I/O Output I/O Output I/O Output I/O Input Output Output Output Output Output Output Output Write: Strobe signal for writing data to pins D0 to D7 Port Z2: I/O port (with pull-up resistor) High write: Strobe signal for writing data to pins D8 to D15 Port Z3: I/O port (with pull-up resistor) Read/write: 1 represents read or dummy cycle; 0 represents write cycle. Port 54: I/O port (with pull-up resistor) Bus request: High-impedance used to request bus release Port 55: I/O port (with pull-up resistor) Bus acknowledge: Signal used to acknowledge bus release Port 56: I/O port (with pull-up resistor) Wait: Pin used to request CPU bus wait ((1 + N) wait states) Port 60: Output port Chip select 0: Outputs 0 when address is within specified address area. Port 61: Output port Chip select 1: Outputs 0 when address is within specified address area Port 62: Output port Chip select 2: Outputs 0 when address is within specified address area Expand chip select 2A: Outputs 0 when address is within specified address area Port 63: Output port Chip select 3: Outputs 0 when address is within specified address area Port 64: Output port Address 24: Expand address Expand chip select 2B: Outputs 0 when address is within specified address area Port 65: Output port Address 25: Expand address Expand chip select 2C: Outputs 0 when address is within specified address area Port 66: Output port Expand chip select 2D: Outputs 0 when address is within specified address area Port 67: Outpt port Expand chip select 2E: Outputs 0 when address is within specified address area PZ2 HWR PZ3 R/ W P54 BUSRQ P55 BUSAK P56 WAIT P60 CS0 P61 CS1 P62 CS2 CS2A P63 CS3 1 1 Output Output Output Output Output P64 EA24 CS2B P65 EA25 CS2C 1 Output Output Output P66 CS2D 1 Output Output P67 CS2E 1 Output Output 91C824-6 2005-12-16 TMP91C824 Table 2.3.2 Pin Names and Functions (2/3) Pin Name P70 SCK OPTRX0 P71 SO SDA OPTTX0 P72 SI SCL P80 to P87 AN0 to AN7 ADTRG Number of Pins 1 I/O I/O I/O Port 70: I/O port Functions Serial bus interface clock I/O data at SIO mode Serial 0 receive data Port 71: I/O port Serial bus interface send data at SIO mode Serial bus interface send/receive data at I C bus mode Open-drain output mode by programmable (with pull up) Serial 0 send data Port 72: I/O port Serial bus interface recive data at SIO mode Serial bus interface clock I/O data at I C bus mode Open-drain output mode by programmable (with pull up) Port 80 to 87 port: Pin used to input ports Analog input 0 to 7: Pin used to input to AD conveter AD trigger: Signal used to request AD start (with used to P83) Port B0: I/O port 8-bit timer 0 input: Timer 0 input Port B1: I/O port 8-bit timer 1 output: Timer 0 output or timer 1 output Port B2: I/O port 8-bit timer 3 output: Timer 2 output or timer 3 output Port B0: I/O port Interrupt request pin0: Interrupt request pin with programmable rising /falling edge Port B4 to B6: I/O port Interrupt request pin1 to 3: Interrupt request pin with programmable rising /falling edge Port C0: I/O port Serial 0 send data: Open-drain output pin by programmable Port C1: I/O port Serial 0 receive data 2 2 Input 1 I/O Output I/O Output 1 I/O Input I/O 8 Input Input Input 1 1 1 1 I/O Input I/O Output I/O Output I/O Input 3 I/O Input 1 1 I/O Output I/O Input PB0 TA0IN PB1 TA1OUT PB2 TA3OUT PB3 INT0 PB4 to PB6 INT1 to INT3 PC0 TXD0 PC1 RXD0 91C824-7 2005-12-16 TMP91C824 Table 2.3.3 Pin Names and Functions (3/3) Pin Name PC2 SCLK0 CTS0 Number of Pins 1 I/O I/O I/O Port C2: I/O port Serial 0 clock Functions Input 1 I/O Output 1 1 I/O Input I/O I/O Input 1 1 1 1 Input Output Output Output Output Output Output 1 1 2 Output Output Input Input Serial data send enable 0 (Clear to send) Port C3: I/O port Serial 1 send data Open-drain output pin by programmable Port C4: I/O port Serial 1 receive data Port C5: I/O port Serial clock I/O 1 Serial 1 data send enable (Clear to send) Low-frequency oscillator connecting pin Low-frequency oscillator connecting pin Port D5: Output port System clock output: fSYS or fs output Port D6: Output port RTC alarm output pin Port D7: Output port Melody/alarm output pin Non-maskable interrupt request pin: Interrupt request pin with programmable falling edge level or with both edge levels programmable Operation mode: Fixed to AM1 = 0, AM0 = 1 16-bit external bus or 8-/16-bit dynamic sizing. Fixed to AM1 = 0, AM0 = 0 8-bit external bus fixed. PC3 TXD1 PC4 RXD1 PC5 SCLK1 CTS1 XT1 XT2 PD5 SCOUT PD6 ALARM MLDALM PD7 MLDALM NMI AM0 to AM1 EMU0 EMU1 RESET 1 1 1 1 1 1 1 2 2 2 Output Output Input Input Input Open pin Open pin Reset: Initializes TMP91C824 (with pull-up resistor). Pin for reference voltage input to AD converter (H) Pin for reference voltage input to AD converter (L) Power supply pin for AD converter GND pin for AD converter (0 V) High-frequency oscillator connection pins Power supply pins (All VCC pins should be connecyed with the power Supply pin.) GND pins (0 V) (All pins shuold be connected with GND (0 V).) VREFH VREFL AVCC AVSS X1/X2 DVCC DVSS 91C824-8 2005-12-16 TMP91C824 3. Operation This following describes block by block the functions and operation of the TMP91C824. Notes and restrictions for eatch book are outlined in 6 "Precautions and Restrictions" at the end of this manual. 3.1 CPU The TMP91C824 incorporates a high-performance 16-bit CPU (the 900/L1 CPU). For CPU operation, see the TLCS-900/L1 CPU. The following describe the unique function of the CPU used in the TMP91C824; these functions are not covered in the TLCS-900/L1 CPU section. 3.1.1 Reset When resetting the TMP91C824 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then set the RESET input to low level at least for 10 system clocks (10 s at 33 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks. Clock gear is initialized 1/16 mode by reset operation. It means that the system clock mode fSYS is set to fc/32 (= fc/16 x 1/2). When the reset is accept, the CPU: * Sets as follows the program counter (PC) in accordance with the reset vector stored at address FFFF00H to FFFF02H: PC<0:7> PC<15:8> PC<23:16> * * * Value at FFFF00H address Value at FFFF01H address Value at FFFF02H address Sets the stack pointer (XSP) to 100H. Sets bits * * * Initializes the internal I/O registers. Sets the port pins, including the pins that also act as internal I/O, to generalpurpose input or output port mode. Note: The CPU internal register (except to PC, SR, XSP) and internal RAM data do not change by resetting. Figure 3.1.1 is a reset timing chart of the TMP91C824. 91C824-9 2005-12-16 fFPH Sampling Sampling RESET A23 to A0 0FFFF00H CS0, CS1, CS3 CS2 D0 to D15 Data-in Data-in Read Figure 3.1.1 TMP91C824 Reset Timing Chart 91C824-10 (PZ2 input mode) RD (After reset released, startting 2 waits read cycle) D0 to D15 Data-out Write WR HWR Pull up (Internal) TMP91C824 2005-12-16 High-Z TMP91C824 3.2 Memory Map Figure 3.2.1 is a memory map of the TMP91C824. 000000H Internal I/O (4 Kbytes) 000100H 000FE0H 001000H Internal RAM (8 Kbytes) 003000H 64-Kbyte area (nn) Direct area (n) 010000H External memory 16-Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn) FFFF00H Vector table (256 bytes) FFFFFFH ( = Internal area) Figure 3.2.1 Memory Map Note: Address 000FE0H to 00FFFH is assigned for the TOSHIBA reserve area, user can't use. 91C824-11 2005-12-16 TMP91C824 3.3 Triple Clock Function and Standby Function TMP91C824 contains (1) clock gear, (2) clock doubler (DFM), (3) standby controller and (4) noise-reduction circuit. It is used for low-power and low-noise systems. This chapter is organized as follows: 3.3.1 Block Diagram of System Clock 3.3.2 SFR 3.3.3 System Clock Controller 3.3.4 Prescaler Clock Controller 3.3.5 Clock Doubler (DFM) 3.3.6 Noise Reduction Circuits 3.3.7 Standby Controller 91C824-12 2005-12-16 TMP91C824 The clock operating modes are as follows: (a) Single clock mode (X1, X2 pins only), (b) Dual clock mode (X1, X2, XT1 and XT2 pins) and (c) Triple clock mode (The X1, X2, XT1 and XT2 pins and DFM). Figure 3.3.1 shows a transition figure. Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt (a) Release reset NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) Single clock mode transition figure Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Instruction Interrupt Instruction Interrupt (b) Release reset NORMAL mode (fOSCH/gear value/2) Instruction Interrupt STOP mode (Stops all circuits) SLOW mode (fs/2) Dual clock mode transition fiigure Reset (fOSCH/32) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Instruction Interrupt Instruction Interrupt Release reset NORMAL mode (fOSCH/gear value/2) (Note) STOP mode (Stops all circuits) Instruction Instruction Note Instruction Interrupt Instruction IDLE2 mode (I/O operate) Instruction Interrupt Instruction NORMAL mode (4 x fOSCH/gear value/2) IDLE1 mode Instruction (Operate oscillator and DFM) Interrupt SLOW mode (fs/2) Interrupt Instruction IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) Using DMF (c) Triple clock mode trasision Figure Note 1: It's prohiibited to control DFM in SLOW mode when shifting from SLOW mode to NORMAL mode with use of DFM. (DFM start up/stop/change write to DFMCR0 91C824-13 2005-12-16 TMP91C824 3.3.1 Block Diagram of System Clock SYSCR0 /2 /4 SYSCR0 /2 fc/2 fc/4 fc/8 fc/16 /8 /16 fSYS SYSCR0 SYSCR1 SYSCR1 Clock gear DFMCR0 fSYS TMRA0 to TMRA3 T0 Prescaler CPU RAM Interrupt controller SIO0 to SIO1 ADC Prescaler WDT SBI T I/O ports CS/WAIT Controller RTC fs MLD/ALM Figure 3.3.2 Block Diagram of System Clock 91C824-14 2005-12-16 TMP91C824 3.3.2 SYSCR0 (00E0H) SFR 7 6 XTEN 1 Lowfrequency oscillator (fs) 0: Stop 1: Oscillation (Note 1) Highfrequency oscillator (fc) after release of STOP mode 0: Stop 1: Oscillation 5 RXEN 1 Low- 4 RXTEN R/W 0 frequency oscillator (fs) after release of STOP mode 0: Stop 1: Oscillation 3 RSYSCK 0 2 WUEF 0 1 PRCK1 0 0 PRCK0 0 Bit symbol Read/Write After reset Function XEN 1 Highfrequency oscillator (fc) 0: Stop 1: Oscillation Selects clock Warm-up timer Select prescaler clock 00: fFPH (Note 2) after release 0: Write Don't care of STOP 01: Reserved 1: Write mode 10: fc/16 start timer 0: fc 11: Reserved 0: Read 1: fs end warm up 1: Read do not end warm up 7 SYSCR1 (00E1H) Bit symbol Read/Write After reset Function 6 5 4 3 SYSCK 0 Select system clock 0: fc 1: fs 2 GEAR2 R/W 1 000: fc 001: fc/2 010: fc/4 011: fc/8 100: fc/16 101: (Reserved) 110: (Reserved) 111: (Reserved) 1 GEAR1 0 0 GEAR0 0 Select gear value of high frequency (fc) 7 SYSCR2 (00E2H) Bit symbol Read/Write After reset Function 0: fs 6 SCOSEL R/W 0 1: fSYS 5 WUPTM1 R/W 1 Warm-up timer 00: Reserved 4 WUPTM0 R/W 0 3 HALTM1 R/W 1 HALT mode 00: Reserved 01: STOP mode 10: IDLE1 mode 11: IDLE2 mode 2 HALTM0 R/W 1 1 SELDRV R/W 0 0 DRVE R/W 0 Pin state control in STOP/IDLE1 mode 0: I/O off 1: Remains the state before halt 01: 2 inputted frequency 10: 2 11: 2 14 16 8 Note 1: By reset, low-frequency oscillator is enable. Note 2: In case of using built-in SBI circuit, it must set SYSCR0 Figure 3.3.3 SFR for System Clock 91C824-15 2005-12-16 TMP91C824 7 DFMCR0 (00E8H) Bit symbol Read/Write After reset Function ACT1 R/W 0 DFM LUP 6 ACT0 R/W 0 select fFPH 5 DLUPFG R 0 Lockup status flag 0: LUP end 1: LUP not end D5 R/W 0 12 10 4 DLUPTM R/W 0 Lockup time 0: 2 /fOSCH 1: 2 /fOSCH 3 2 1 0 00 STOP STOP fOSCH 01 RUN RUN fOSCH 10 RUN 11 RUN DFMCR1 (00E9H) Bit symbol Read/Write After reset Function D7 R/W 0 STOP fDFM STOP fOSCH D6 R/W 0 D4 R/W 1 D3 R/W 0 D2 R/W 0 D1 R/W 1 D0 R/W 1 DFM revision Input frequency 4 to 8.25 MHz (at 2.7 V to 3.6 V): write "0BH" Input frequency 2 to 2.5 MHz (at 2.0 V 10%): write "1BH" Figure 3.3.4 SFR for DFM Limitation point on the use of DFM 1. It's prohibited to execute DFM enable/disable control in the SLOW mode (fs). (Write to DFMCR0 LD LD (DFMCR0), C0H (DFMCR0), 00H ; ; Change the clock fDFM to fOSCH DFM stop 3. If you stop high-frequency oscillator during using DFM (DFMCR0 91C824-16 2005-12-16 TMP91C824 7 EMCCR0 (00E3H) Bit symbol Read/Write After reset Function PROTECT R 0 Protect flag 0: OFF 1: ON EMCCR1 Bit symbol (00E4H) Read/Write After reset Function EMCCR2 Bit symbol (00E5H) Read/Write After reset Function EMCCR3 (00E6H) Bit symbol Read/Write After reset Function 6 - R/W 0 Always write 0 5 - R/W 1 Always write 1 4 - R/W 0 Always write 0 3 - R/W 0 Always write 0 2 EXTIN R/W 0 1: External clock 1 DRVOSCH 0 DRVOSCL R/W 1 fc oscillator driver ability 1: Normal 0: Weak R/W 1 fs oscillator driver ability 1: Normal 0: Weak Switching the protect ON/OFF by write to following 1st-KEY,2nd-KEY 1st-KEY: EMCCR1 = 5AH, EMCCR2 = A5H in succession write 2nd-KEY: EMCCR1 = A5H, EMCCR2 = 5AH in succession write ENFROM R/W 0 CS1A area detect control 0: Disable 1: Enable ENDROM R/W 0 CS2B-2G area detect control 0: Disable 1: Enable ENPROM R/W 0 CS2A area detect control 0: Disable 1: Enable FFLAG R/W 0 CS1A write DFLAG PFLAG R/W 0 R/W 0 CS2B-2G write CS2A write operation flag operation flag operation flag When reading 0: Not written 1: Written When writing 0: Clear flag Note1: In case restarting the oscillator in the stop oscillation state (e.g. Restart the oscillator in STOP mode), set EMCCR0 91C824-17 2005-12-16 TMP91C824 3.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O. It contains two oscillation circuits and a clock gear circuit for highfrequency (fc) operation. The register SYSCR1 Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warmup timer is not needed. Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time. Table 3.3.1 Warm-up Times Warm-up Time SYSCR2 01 (2 /frequency) 10 (2 /frequency) 11 (2 /frequency) 16 14 8 Change to NORMAL Mode 8 (s) 0.496 (ms) 1.986 (ms) Change to SLOW Mode 7.8 (ms) 500 (ms) 2000 (ms) at fOSCH = 33 MHz, fs = 32.768 kHz 91C824-18 2005-12-16 TMP91C824 Example 1: Setting the clock Changing from high frequency (fc) to low frequency (fs). SYSCR0 SYSCR1 SYSCR2 WDMOD EQU EQU EQU EQU LD SET SET WUP: BIT JR SET 00E0H 00E1H 00E2H 005CH (SYSCR2), X-11- - - -B ; Sets warm-up time to 2 /fs. 16 6, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) ; Enables low-frequency oscillation. ; Clears and starts warm-up timer. ; ; Detects stopping of warm-up timer. ; Changes fSYS from fc to fs. ; Disables high-frequency oscillation. RES 7, (SYSCR0) X: Don't care, -: No change Warm-up timer End of warm-up timer Counts up by fSYS Counts up by fs fc fs Enables low frequency Clears and starts warm-up timer Chages fSYS from fc to fs End of warm-up timer Disabiles high frequency 91C824-19 2005-12-16 TMP91C824 Example 2: Setting the clock Changing from low frequency (fs) to high frequency (fc). SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET WUP: BIT JR RES RES 00E0H 00E1H 00E2H (SYSCR2), X-10- - - -B ; Sets warm-up time to 214/fc. 7, (SYSCR0) 2, (SYSCR0) 2, (SYSCR0) NZ, WUP 3, (SYSCR1) 6, (SYSCR0) ; Enables high-frequency oscillation. ; Clears and starts warm-up timer. ; ; Detects stopping of warm-up timer. ; Changes fSYS from fs to fc. ; Disables low-frequency oscillation. X: Don't care, -: No change Warm-up timer End of warm-up timer Counts up by fSYS Counts up by fOSCH fs fc Enables high frequency Clears and starts warm-up timer Chages fSYS from fs to fc End of warm-up timer Disables low frequency 91C824-20 2005-12-16 TMP91C824 (2) Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1 SYSCR1 X: Don't care EQU LD 00E1H (SYSCR1),XXXX0000B ; Changes fSYS to fc/2. (High-speed clock gear changing) To change the clock gear, write the register value to the SYSCR1 Example: SYSCR1 EQU LD LD 00E1H (SYSCR1),XXXX0001B (DUMMY), 00H ; Changes fSYS to fc/4. ; Dummy instruction Instruction to be executed after clock gear has changed (3) Internal clock terminal out function It can out internal clock (fSYS or fs) from PD5/SCOUT. PD5 pin function is set to SCOUT output by the following bit setting. : PDFC HALT Mode SCOUT Select NORMAL SLOW fSYS clock out IDLE2 fs clock out HALT Mode IDLE1 0 or 1 fix out STOP 91C824-21 2005-12-16 TMP91C824 3.3.4 Prescaler Clock Controller For the internal I/O (TMRA01 to TMRA23, SIO0 to SIO1) there is a prescaler which can divide the clock. The T0 clock input to the prescaler is either the clock fFPH divided by 4 or the clock fc/16 divided by 4. The setting of the SYSCR0 3.3.5 Clock Doubler (DFM) DFM outputs the fDFM clock signal, which is four times as fast as fOSCH. It can use the low-frequency oscillator, even though the internal clock is high frequency. A reset initializes DFM to stop status, setting to DFMCR0 register is needed before use. Like an oscillator, this circuit requires time to stabilize. This is called the lockup time. The following example shows how DFM is used. DFMCR0 DFMCR1 EQU EQU LD LD LUP: BIT JR LD X: Don't care ACT1:0 DFM output: fDFM Lockup timer Counts up by fOSCH 00E8H 00E9H (DFMCR1), 00001011B (DFMCR0), 01-0XXXXB 5, (DFMCR0) NZ, LUP (DFMCR0), 10-0XXXXB ; ; ; ; DFM parameter setting Set lockup time to 2 /4 MHz Enables DFM operation and starts lockup Detects end of lockup Changes fc from 4 MHz to 16 MHz Changes fSYS from 2 MHz to 8 MHz 12 01 10 During lockup After lockup Note: Input frequency limitation and correction for DFM Recommend to use input frequency (High-speed oscillation) for DFM in the following condition. fOSCH = 4 to 8.25 MHz (Vcc = 2.7 V to 3.6 V): Write 0BH to DFMCR1 fOSCH = 2 to 2.5 MHz (Vcc = 2.0 V 10%): Write 1BH to DFMCR1 91C824-22 2005-12-16 TMP91C824 Limitation point on the use of DFM 1. it's prohibited to execute DFM enable/disable control in the SLOW mode (fs). You should control DFM in the NORMAL mode. 2. If you stop DFM operation during using DFM (DFMCR0 LD LD (DFMCR0), C0H (DFMCR0), 00H ; ; Change the clock fDFM to fOSCH DFM stop 3. If you stop high-frequency oscillator during using DFM (DFMCR0 (OK) Low-frequency oscillator operation mode (fs) (High-frequency oscillator STOP) High-frequency oscillator start up High-frequency oscillator operation mode (fOSCH) DFM start up DFM use mode (fDFM) LD WUP: BIT JR LD LD LUP: BIT JR LD (SYSCR0), 11---1--B 2, (SYSCR0) NZ, WUP (SYSCR1), ----0---B (DFMCR0), 01-0----B 5, (DFMCR0) NZ, LUP (DFMCR0), 10-0----B ; ; ; ; ; ; ; ; High-frequency oscillator start up/warm-up start Check for the flag of warm-up end Change the system clock fs to fOSCH DFM start up/lockup start Check for the flag of lockup end Change the system clock fOSCH to fDFM (OK) Low-frequency oscillator operation mode (fs) (High-frequency oscillator operate) High-frequency oscillator operation mode (fOSCH) DFM start up DFM use mode (fDFM) LD LD LUP: BIT JR LD (SYSCR1), ----0---B (DFMCR0), 01-0----B 5, (DFMCR0) NZ, LUP (DFMCR0), 10-0----B ; ; ; ; ; Change the system clock fs to fOSCH DFM start up/lockup start Check for the flag of lockup end Change the system clock fOSCH to fDFM (Error) Low-frequency oscillator operation mode (fs) (High-frequency oscillator STOP) High-frequency oscillator start up DFM start up DFM use mode (fDFM) LD WUP: BIT JR LD LUP: BIT JR LD LD (SYSCR0), 11---1--B 2, (SYSCR0) NZ, WUP (DFMCR0), 01-0----B 5, (DFMCR0) NZ, LUP (DFMCR0), 10-0----B (SYSCR1), ----0---B ; ; ; ; ; ; ; ; High-frequency oscillator start up/warm-up start Check for the flag of warm-up end DFM start up/lockup start Check for the flag of lockup end Change the clock fOSCH to fDFM Change the internal clock fs to fDFM 91C824-23 2005-12-16 TMP91C824 (2) Change/stop control (OK) DFM use mode (fDFM) High-frequency oscillator operation mode (fOSCH) DFM stop Low-frequency oscillator operation mode (fs) High-frequency oscillator stop LD LD LD LD (DFMCR0), 11------B (DFMCR0), 00------B (SYSCR1), ----1---B (SYSCR0), 0-------B ; ; ; ; Change the system clock fDFM to fOSCH DFM stop Change the system clock fOSCH to fs High-frequency oscillator stop (Error) DFM use mode (fDFM) Low-frequency oscillator operation mode (fs) DFM stop High-frequency oscillator stop LD LD LD LD (SYSCR1), ----1---B (DFMCR0), 11------B (DFMCR0), 00------B (SYSCR0), 0-------B ; ; ; ; Change the system clock fDFM to fs Change the internal clock (fc) fDFM to fOSCH DFM stop High-frequency oscillator stop (OK) DFM use mode (fDFM) Set the STOP mode High-frequency oscillator operation mode (fOSCH) DFM stop HALT (High-frequency oscillator stop) LD LD LD HALT (SYSCR2), ----01--B (DFMCR0), 11------B (DFMCR0), 00------B ; ; ; ; Set the STOP mode (This command can execute before use of DFM) Change the system clock fDFM to fOSCH DFM stop Shift to STOP mode (Error) DFM use mode (fDFM) Set the STOP mode HALT (High-frequency oscillator stop) LD HALT (SYSCR2), ----01--B ; ; Set the STOP mode (This command can execute before use of DFM) Shift to STOP mode 91C824-24 2005-12-16 TMP91C824 3.3 3.3.6 Noise Reduction Circuits Noise reduction circuits are built in, allowing implementation of the following features. (1) Reduced drivability for high-frequency oscillator (2) Reduced drivability for low-frequency oscillator (3) Single drive for high-frequency oscillator (4) SFR protection of register contents (5) ROM protection of register contents (1) Reduced drivability for high-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) fOSCH C1 Resonator EMCCR0 (Setting method) The drivability of the oscillator is reduced by writing 0 to EMCCR0 91C824-25 2005-12-16 TMP91C824 (2) Reduced drivability for low-frequency oscillator (Purpose) Reduces noise and power for oscillator when a resonator is used. (Block diagram) C1 Resonator EMCCR0 (Setting method) The drivability of the oscillator is reduced by writing 0 to the EMCCR0 fOSCH X1 pin Enable oscillation (STOP + EMCCR0 EMCCR0 X2 pin (Setting method) The oscillator is disabled and starts operation as buffer by writing 1 to EMCCR0 Note: Do not write EMCCR0 91C824-26 2005-12-16 TMP91C824 (4) Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is it in the state which is fetch impossibility by stopping of clock, memory control register (CS/WAIT controller, MMU) is changed. And error handling in runaway becomes easy by INTP0 interruption. Specified SFR list 1. CS/WAIT controller B0CS, B1CS, B2CS, B3CS, BEXCS, MSAR0, MSAR1, MSAR2, MSAR3, MAMR0, MAMR1, MAMR2, MAMR3 2. MMU LOCAL0/1/2/3 3. Clock gear (only EMCCR1, EMCCR2 can be written to) SYSCR0, SYSCR1, SYSCR2, EMCCR0, EMCCR3 4. DFM DFMCR0, DFMCR1 (Operation explanation) Execute and release of protection (write operation to specified SFR) become possible by setting up a double key to EMCCR1 and EMCCR2 register. (Double key) 1st-KEY: Succession writes in 5AH at EMCCR1 and A5H at EMCCR2 2nd-KEY: Succession writes in A5H at EMCCR1 and 5AH at EMCCR2 A state of protection can be confirmed by reading EMCCR0 91C824-27 2005-12-16 TMP91C824 (5) Runaway provision with ROM protection register (Purpose) Provision in runaway of program by noise mixing. (Operation explanation) When write operation was executed for external three kinds of ROM by runaway of program, INTP1 is occurred and detects runaway function. Three kinds of ROM is fixed as for flash ROM (Option program ROM), data ROM, program ROM are as follows on the logical address memory map. 1. Flash ROM: 2. Data ROM: Address 400000H to 7FFFFFH Address 800000H to BFFFFFH 3. Program ROM: Address C00000H to FFFFFFH For these address, admission/prohibition of detection of write operation sets it up with EMCCR3 91C824-28 2005-12-16 TMP91C824 3.3.7 Standby Controller (1) HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 TMRA01 TMRA23 SIO0 SIO1 AD converter WDT SBI SFR TA01RUN b. c. IDLE1: Only the oscillator and the RTC (Real time clock) and MLD continue to operate. STOP: All internal circuits stop operating. The operation of each of the different HALT modes is described in Table 3.3.3. Table 3.3.3 I/O Operation during HALT Modes HALT Mode SYSCR2 CPU I/O ports TMRA SIO, SBI AD converter WDT RTC, MLD IDLE2 11 Stop Keep the state when the HALT instruction was executed. IDLE1 10 STOP 01 See Table 3.3.6, Table 3.3.7 Block Available to select operation block Stop Possible to operate 91C824-29 2005-12-16 TMP91C824 (2) How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The HALT release sources are determined by the combination between the states of interrupt mask register The operating released from the HALT mode depends on the interrupt enabled status. When the interrupt request level set before executing the HALT instruction exceeds the value of interrupt mask register, the interrupt due to the source is processed after releasing the HALT mode, and CPU status executing an instruction that follows the HALT instruction. When the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the HALT mode is not executed. (In non-maskable interrupts, interrupt processing is processed after releasing the HALT mode regardless of the value of the mask register.) However only for INT0 to INT3 and INTRTC and INTALM interrupts, even if the interrupt request level set before executing the HALT instruction is less than the value of the interrupt mask register, releasing the the HALT mode is executed. In this case, interrupt processing, and CPU starts executing the instruction next to the HALT instruction, but the interrupt request flag is held at 1. Note: Usually, interrupts can release all halts status. However, the interrupts ( NMI , INT0 to INT3, INTRTC, INTALM0 to INTALM4) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compared with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. * Releasing by resetting Releasing all halt status is executed by resetting. When the STOP mode is released by reset, it is necessry enough resetting time (See Table 3.3.5) to set the operation of the oscillator to be stable. When releasing the HALT mode by resetting, the internal RAM data keeps the state before the HALT instruction is executed. However the other settings contents are initialized. (Releasing due to interrupts keeps the state before the HALT instruction is executed.) 91C824-30 2005-12-16 TMP91C824 Table 3.3.4 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt HALT Mode Source of Halt State Clearance NMI INTWDT INT0 to INT3 (Note 1) Interrupt INTALM0 to INTALM4 INTTA0 to INTTA3 INTRX0 to INTRX1, TX0 to TX1 INTAD INTRTC INTSBI RESET Interrupt Enabled Interrupt Disabled (Interrupt level) (Interrupt mask) (Interrupt level) < (Interrupt mask) IDLE2 IDLE1 STOP x x x x x *1 IDLE2 - - IDLE1 STOP - - - - x *1 x x x x x x x x x x x x *1 x x x x x x x x Reset initializes the LSI : After clearing the HALT mode, CPU starts interrupt processing. After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. It can not be used to release the HALT mode. The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. Releasing the HALT mode is executed after passing the warm-up time. : x: -: *1: Note: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold level "H" until starting interrupt processing. If level "L" is set before holding level "L", interrupt processing is correctly started. (Example: Clearing IDLE1 mode) An INT0 interrupt clears the halt state when the device is in IDLE1 mode. Address 8200H 8203H 8206H 8209H 820BH 820EH INT0 LD LD LD EI LD HALT (PBFC), 08H (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ; Sets PB3 to INT0. ; Selects INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets interrupt level to 5 for CPU. ; Sets HALT mode to IDLE1 mode. ; Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX 91C824-31 2005-12-16 TMP91C824 (3) Operation a. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 3.3.6 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt for release IDLE2 mode Figure 3.3.6 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt b. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC, MLD continue to operate. The system clock in the MCU stops. The pin status in the IDLE1 mode is depended on setting the register SYSCR2 X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt for release IDLE1 mode Figure 3.3.7 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt 91C824-32 2005-12-16 TMP91C824 c. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator pin status in STOP mode depends on the settings in the SYSCR2 Warm-up time X1 A0 to A23 D0 to D15 RD WR Data Data Interrupt for release STOP mode Figure 3.3.8 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 3.3.5 Sample Warm-up Times after Clearance of STOP Mode at fOSCH = 33 MHz, fs = 32.768 kHz SYSCR0 0 (fc) 1 (fs) SYSCR2 8 s 7.8 ms 8 10 (214) 0.496 ms 500 ms 11 (216) 1.986 ms 2000 ms 91C824-33 2005-12-16 TMP91C824 Example: The STOP mode is entered when the low-frequency operates, and high-frequency operates after releasing due to NMI. Address SYSCR0 SYSCR1 SYSCR2 8FFDH 9000H 9002H 9005H NMI EQU EQU EQU LD LD LD HALT 00E0H 00E1H 00E2H (SYSCR1), 08H (SYSCR2), X-1001-1B (SYSCR0), 011000 - -B ; fSYS = fs/2 ; Sets warm-up time to 2 /fOSCH ; Operates high frequency after released 14 Clears and starts hit warm-up timer (High frequency) End NMI Interrupt routine 9006H - : No change LD XX, XX RETI Note: When different modes are used before and after STOP mode as the above mentioned, there is possible to release the HALT mode without changing the operation mode by acceptance of the halt release interrupt request during execution of HALT instruction (during 6 states). In the system which accepts the interrupts during execution HALT instruction, set the same operation mode before and after the STOP mode. 91C824-34 2005-12-16 TMP91C824 Table 3.3.6 Input Buffer State Table Input Buffer State When the CPU is In HALT mode(IDLE1/STOP) Condition A (Note) When Used as function Pin OFF OFF - Port Name Input Function Name operating During Reset When Used as function Pin When Used as Input Port - In HALT mode(IDLE2) When Used as function Pin OFF ON - Condition B (Note) When Used as function Pin OFF ON - When Used as Input Port - OFF When Used as Input Port - When Used as Input Port - OFF ON OFF D0-D7 P10-P17 P54(*1) P55(*1) P56(*1) P70 P71(*1) P72(*1) P80-P82(*2) P83(*2) P84-P87(*2) PB0 PB1 PB2 PB3 PB4 PB5 PB6 PC0 PC1 PC2 PC3 PC4 PC5 PZ2(*1) PZ3(*1) NMI RESET AM0,AM1 X1,XT1 - D8-D15 BUSRQ OFF ON OFF ON upon external read ON - ON ON OFF - WAIT SCK OPTRX0 SDA SI SCL - - OFF ON - ON ON - ON upon port read - ON - ON - ON OFF ON - ON - OFF - ON ON ON ON ON OFF ON - ON - ON - ON OFF ON ON ON ON ON OFF OFF ON ON ADTRG - TA0IN - - INT0 INT1 INT2 INT3 - RXD0 SCLK0 CTS0 - RXD1 SCLK1 CTS1 - - - - - - OFF OFF OFF - ON ON ON - - - - ON - ON OFF OFF - ON - ON ON ON OFF ON OFF - - OFF - - OFF ON ON - ON - ON - ON - IDLE1 : ON , STOP : OFF *1: Port having a pull-up/pull-down resistor. *2: AIN input does not cause a current to flow through the buffer. ON: The buffer is always turned on. A current flows the input buffer if the input pin is not driven. OFF: The buffer is always turned off. -: No applicable Note: Condition A/B are as follows. SYSCR2 register setting 91C824-35 2005-12-16 TMP91C824 Table 3.3.7 Output buffer State Table Output Buffer State Port Name Output Function Name When the CPU is Operating During Reset When Used as function Pin ON upon external write When Used as Output Port - OFF ON ON OFF ON ON - ON - - OFF - - ON - OFF In HALT mode(IDLE2) When Used as function Pin When Used as Output Port - In HALT mode (IDLE1/STOP) Condition A (Note) Condition B (Note) When When When When Used as Used as Used as Used as function Output function Output Pin Port Pin Port - OFF ON - D0-D7 P10-P17 P20-P27 A0-A15 RD WR - D8-15 A16-23 - - - - OFF P54(*1) P55(*1) P56(*1) P60 P61 P62 P63 P64 P65 P66 P67 P70 P71(*1) P72(*1) PB0 PB1 PB2 PB3-PB6 PC0 PC1 PC2 PC3 PC4 PC5 PD5 PD6 PD7 PZ2(*1) PZ3(*1) X2 XT2 - OFF ON - - ON - - ON - BUSAK - CS0 CS1 CS 2 , CS 2 A CS 3 EA24 CS 2B EA25 ON CS 2C CS 2D CS 2E SCK SDA SO OPTTX0 SCL - TA1OUT TA3OUT - TXD0 - SCLK0 TXD1 - SCLK1 SCOUT OFF ON ON OFF ON ON - ON - ON - ON - - ON - ON - ON - ON - OFF - OFF - OFF - OFF - ON - ON - ON - ON ALARM MLDALM MLDALM ON ON OFF ON - - ON OFF ON HWR R/W - - IDLE1 : ON , STOP : output "H" level IDLE1 : ON , STOP : High-Z ON: The buffer is always turned on. When the bus is *1: Port having a pull-up/pull-down resistor. released, however, output buffers for some pins are turned off. OFF: The buffer is always turned off. -: No applicable Note: Condition A/B are as follows. SYSCR2 register setting 91C824-36 2005-12-16 TMP91C824 3.4 Interrupts Interrupts are controlled by the CPU interrupt mask register SR A (Fixed) individual interrupt vector number is assigned to each interrupt. One of six (Variable) priority level can be assigned to each maskable interrupt. The priority level of non-maskable interrupts are fixed at 7 as the highest level. When an interrupt is generated, the interrupt controller sends the piority of that interrupt to the CPU. If multiple interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for non-maskable interrupts.) The CPU compares the priority level of the interrupt with the value of the CPU interrupt mask register 91C824-37 2005-12-16 TMP91C824 Interrupt processing Micro DMA soft start request Yes Interrupt specified by micro DMA start vector? No Clear interrupt request flag Interrupt vector value V read Interrupt request F/F clear General-purpose interrupt processing Data transfer by micro DMA PUSH PC PUSH SR SR Count Count - 1 Micro DMA processing Count = 0 No Yes Clear vector register generating micro DMA transfer and interrupt (INTTC0 to INTTC3) PC (FFFF00H + V) Interrupt processing program RETI instruction POP SR POP PC INTNEST INTNEST - 1 End Figure 3.4.1 Overall Interrupt Processing Flow 91C824-38 2005-12-16 TMP91C824 3.4.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. (1) The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt: The smaller vector value has the higher priority level.) (2) The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (Indicated by XSP). (3) The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1) to the interrupt mask register 91C824-39 2005-12-16 TMP91C824 Table 3.4.1 TMP91C824 Interrupt Vectors Table Default Priority 1 2 3 4 5 6 7 8 9 10 - 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 Maskable Non maskable Type Interrupt Source and Source of Micro DMA Request Reset or "SWI 0" instruction "SWI 1" instruction INTUNDEF: Illegal instruction or "SWI 2" instruction "SWI 3" instruction "SWI 4" instruction "SWI 5" instruction "SWI 6" instruction "SWI 7" instruction Vector Value (V) 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H - 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H 005CH 0060H 0064H 0068H 006CH 0074H 0078H 0080H 0084H 0088H 008CH 0090H 0094H 0098H : 00FCH Vector Micro DMA Reference Start Vector Address FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H - FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF74H FFFF78H FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H FFFF94H FFFF98H : FFFFFCH - - - - - - - - - - - 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H 17H 18H 19H 1AH 1BH 1DH 1EH 20H 21H - - - - - : - NMI pin INTWD: Watchdog timer Micro DMA (MDMA) INT0 pin INT1 pin INT2 pin INT3 pin INTALM0: ALM0 (8 kHz) INTALM1: ALM1 (512 Hz) INTALM2: ALM2 (64 Hz) INTALM3: ALM3 (2 Hz) INTALM4: ALM4 (1 Hz) INTTA0: INTTA1: INTTA2: INTTA3: INTRX0: INTTX0: INTRX1: INTTX1: INTAD: INTSBI: INTP0: INTP1: INTTC0: INTTC1: INTTC2: INTTC3: : (Reserved) 8-bit timer 0 8-bit timer 1 8-bit timer 2 8-bit timer 3 Serial reception (Channel 0) Serial transmission (Channel 0) Serial reception (Channel 1) Serial transmission (Channel 1) AD conversion end SBI interrupt Protect 0 (WR to special SFR) Protect 1 (WR to ROM) Micro DMA end (Channel 0) Micro DMA end (Channel 1) Micro DMA end (Channel 2) Micro DMA end (Channel 3) INTRTC: RTC (Alarm interrupt) (Reserved) 91C824-40 2005-12-16 TMP91C824 3.4.2 Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91C824 supprots a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (Level 6) among maskable interrupts, regardless of the priority level of the particular interrupt source. Micro. The micro DMA has 4 channels and is possible continuous transmission by specifing the say later burst mode. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU goes to a standby mode by HALT instruction, the requirement of micro DMA will be ignored (Pending). (1) Micro DMA operation When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request in spite of any interrupt source's level. The micro DMA is ignored on Note: If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt specified by micro DMA start vector" (in the Figure 3.4.1) and reading interrupt vector with setting below. The vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because cheking of micro DMA has finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA 91C824-41 2005-12-16 TMP91C824 If a micro DMA request is set for more than one channel at the same time, the priority is not based on the interrupt priority level but on the channel number. The smaller channel number has the higher priority (Channel 0 (High) > Channel 3 (Low)). While the register for setting the transfer source/transfer destination addresses is a 32-bit control register, this register can only effectively output 24-bit addresses. Accordingly, micro DMA can access 16 Mbytes (The upper 8 bits of the 32 bits are not valid). Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (One word) transfer, and 4-byte transfer. After a transfer in any mode, the transfer source/destination addresses are increased, decreased, or remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the transfer modes, see 3.4.2 (4) "Detailed description of the transfer mode register". As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source. (The micro DMA processing count is maximized when the transfer counter initial value is set to 0000H.) Micro DMA processing can be started by the 24 interrupts shown in the micro DMA start vectors of Table 3.4.1 and by the micro DMA soft start, making a total of 25 interrupts. Figure 3.4.2 shows the word transfer micro DMA cycle in transfer destination address INC mode (except for counter mode, the same as for other modes). (The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer source/transfer destination addresses both even-numberd values.) 1 state (Note 1) DM2 DM3 DM4 DM5 DM6 (Note 2) DM7 DM8 DM1 X1 A0 to A23 RD WR / HWR Transfer source address Transfer destination address D0 to D15 Input Output Figure 3.4.2 Timing for Micro DMA Cycle States 1 to 3: Instruction fetch cycle (gets next address code). If 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. States 4 to 5: Micro DMA read cycle State 6: Dummy cycle (The address bus remains unchanged from state 5) States 7 to 8: Micro DMA write cycle Note 1: If the source address area is an 8-bit bus, it is increased by two states. If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. Note 2: If the destination address area is an 8-bit bus, it is increased by two states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. 91C824-42 2005-12-16 TMP91C824 (2) Soft start function In addition to starting the micro DMA function by interrupts, TMP91C824 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing "1" to each bit of DMAR register causes micro DMA once (If write "0" to each bit, micro DMA doesn't operate). At the end of transfer, the corresponding bit of the DMAR register which support the end channel are automatically cleared to "0". Only one-channel can be set for DMA request at once. (Do not write "1" to plural bits.) When writing again "1" to the DMAR register, check whether the bit is "0" before writing "1". If read "1", micro DMA transfer isn't started yet. When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is "0" after start up of the micro DMA. If execute soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn't change. Don't use Read-modify-write instruction to avoid writing to other bits by mistake. Symbol Name DMA DMAR request register Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 0 2 DMAR2 0 R/W 1 DMAR1 0 0 DMAR0 0 DMA request (3) Transfer control registers The transfer source address and the transfer destination address are set in the following registers in CPU. Data setting for these registers is done by an LDC cr, r instruction. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0 DMA counter register 0 DMA mode register 0 : Only use LSB 24 bits : 1 to 65536 DMA destination address register 0 : Only use LSB 24 bits Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 8 bits 16 bits 32 bits DMA source address register 3 DMA destination address register 3 DMA counter register 3 DMA mode register 3 91C824-43 2005-12-16 TMP91C824 (4) Detailed description of the transfer mode register 8 bits DMAM0 to DMAM3 0 0 0 Mode Note: When setting a value in this register, write 0 to the upper 3 bits. Number of Transfer Bytes 000 (Fixed) 01 10 001 00 01 10 010 00 01 10 011 00 01 10 100 00 01 10 101 00 Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Byte transfer Word transfer 4-byte transfer Counter mode 000 00 Byte transfer Mode Description Transfer destination address INC mode ............................................. I/O to memory (DMADn+) (DMASn) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer destination address DEC mode ............................................. I/O to memory (DMADn-) (DMASn) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer source address INC mode ............................................. Memory to I/O (DMADn) (DMASn+) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Transfer source address DEC mode ............................................. Memory to I/O (DMADn) (DMASn-) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Fixed address mode ...................................................... I/O to I/O (DMADn) (DMASn-) DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. Minimum Number of Execution Time Execution States at fc = 33 MHz 8 states 485 ns 12 states 727 ns 8 states 12 states 485 ns 727 ns 8 states 12 states 485 ns 727 ns 8 states 12 states 485 ns 727 ns 8 states 12 states 485 ns 727 ns ................... for counting number of times interrupt is generated DMASn DMASn + 1 DMACn DMACn - 1 If DMACn = 0, then INTTCn is generated. 5 states 303 ns Note 1: "n" is the corresponding micro DMA channels 0 to 3 DMADn+/DMASn+: Post-increment (Increment register value after transfer) DMADn-/DMASn-: Post-decrement (Decrement register value after transfer) The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC) addresses. Note 2: Execution time is under the condition of: 16-bit bus width (Both translation and destination address area)/0 waits/fc = 33 MHz/selected high-frequency mode (fc x 1) Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in the above table. 91C824-44 2005-12-16 TMP91C824 3.4.3 Interrupt Controller Operation The block diagram in Figure 3.4.3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For each of the 36 interrupt channels there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to 0 in the following cases: * * * * * when reset occurs when the CPU reads the channel vector after accepted its interrupt when executing an instruction that clears the interrupt (Write DMA start vector to INTCLR register) when the CPU receives a micro DMA request (when micro DMA is set) when the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE12). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (NMI pin interrupts and watchdog timer interrupts) is fixed at 7. If interrupt request with the same level are generated at the same time, the default priority (The interrupt with the lowest priority or, in other words, the interrupt with the lowest vector value) is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request with the highest priority among the simulateous interrupts and its vector address to the CPU. The CPU compares the priority value 91C824-45 2005-12-16 Interrupt controller CPU 1 NMI V = 20H V = 24H RESET interrupt vector read Interrupt mask F/F RESET Interrupt request signal to CPU IFF2:0 3 3 INTRQ2 to 0 3 Interrupt level detect EI1 to 7 DI Interrupt request F/F S Q R INTWD D CLR 6 Q Priority setting register Dn Dn + 1 Dn + 2 Decoder Y1 A Y2 B Y3 C Y4 Y5 Y6 Dn + 3 Priority encoder 1 1 2 Highest A 7 B 3 priority 6 4 interrupt C 5 level select 6 7 if INTRQ2 to 0 IFF 2 to 0 then 1. D0 D1 32 Interrupt vector generator D2 D3 D4 D5 D6 D7 Interrupt request signal INT0 R Interrupt request F/F Interrupt vector read Micro DMA acknowledge Reset Interrupt request F/F S Q INT1 INT2 INT3 INTALM0 INTALM1 INTALM2 INTALM3 INTALM4 INTTA0 Interrupt vector read V = 28H V = 2CH V = 30H V = 34H V = 38H V = 3CH V = 40H V = 44H V = 48H V = 4CH During IDLE1 During STOP Figure 3.4.3 Block Diagram of Interrupt Controller 91C824-46 V = 84H V = 88H V = 8CH V = 90H V = 94H 4 input OR 34 S 6 Selector 0 1 INTTC0 DMA0V DMA1V DMA2V DMA3V 2 3 A B Micro DMA channel priority encoder 2 Soft start 4 DQ CLR HALT release RESET INT0, 1, 2, 3, RTC, ALM NMI Micro DMA request if IFF = 7 then 0 2 Micro DMA counter zero interrupt INTP1 INTTC0 INTTC1 INTTC2 INTTC3 Micro DMA start vector setting register D5 D4 D3 D2 D1 D0 RESET Micro DMA channel specification TMP91C824 2005-12-16 TMP91C824 (1) Interrupt level setting registers Symbol Name INT0 & Address 7 IADC R 0 6 INTAD IADM2 0 INT2 5 IADM1 R/W 0 4 IADM0 0 3 I0C R 0 2 INT0 I0M2 0 INT1 1 I0M1 R/W 0 0 I0M0 0 INTE0AD INTAD enable 90H INT1 & INTE12 INT2 enable 91H I2C R 0 I2M2 0 I2M1 R/W 0 I2M0 0 I1C R 0 I1M2 0 INT3 I1M1 R/W 0 I1M0 0 INT3 & INTE3ALM4 INTALM4 INTALM4 92H IA4C R 0 0 INTALM1 93H IA1C R 0 0 INTALM3 94H IA3C R 0 0 IA3M2 IA3M1 R/W 0 0 INTTA1 (TMRA1) 95H ITA1C R 0 0 ITA1M2 ITA1M1 R/W 0 0 INTTA3 (TMRA3) 96H ITA3C R 0 0 ITA3M2 ITA3M1 R/W 0 0 ITA3M0 ITA2C R 0 0 ITA1M0 ITA0C R 0 0 IA3M0 IA2C R 0 0 IA1M2 IA1M1 R/W 0 0 IA1M0 IA0C R 0 0 IA4M2 IA4M1 R/W 0 0 IA4M0 I3C R 0 0 I3M2 I3M1 R/W 0 I3M0 0 enable INTALM0 & INTEALM01 INTALM1 INTALM0 IA0M2 IA0M1 R/W 0 INTALM2 IA2M2 IA2M1 R/W 0 0 INTTA0 (TMRA0) ITA0M2 ITA0M1 R/W 0 0 INTTA2 (TMRA2) ITA2M2 ITA2M1 R/W 0 INTRTC 0 ITA2M0 ITA0M0 IA2M0 0 IA0M0 enable INTALM2 & INTEALM23 INTALM3 enable INTTA0 & INTETA01 INTTA1 enable INTTA2 & INTETA23 INTTA3 enable INTERTC INTRTC enable 97H IRC R 0 IRM2 0 IRM1 R/W 0 IRM0 0 Interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91C824-47 2005-12-16 TMP91C824 Symbol Name Interrupt Address 7 ITX0C R 0 6 INTTX0 ITX0M2 0 INTTX1 ITX1M2 0 5 ITX0M1 R/W 0 ITX1M1 R/W 0 4 ITX0M0 0 ITX1M0 0 3 IRX0C R 0 IRX1C R 0 ISBIC R 0 2 INTRX0 IRX0M2 0 INTRX1 IRX1M2 0 INTSBI ISBIM2 0 INTTC0 ITC0M2 0 INTTC2 ITC2M2 0 INTP0 IP0M2 0 1 IRX0M1 R/W 0 IRX1M1 R/W 0 ISBIM1 R/W 0 ITC0M1 R/W 0 ITC2M1 R/W 0 IP0M1 R/W 0 0 IRX0M0 0 IRX1M0 0 ISBIM0 0 ITC0M0 0 ITC2M0 0 IP0M0 0 INTES0 Enable serial 0 98H INTRX1 & INTES1 INTTX1 enable 99H ITX1C R 0 INTES2 INTESBI enable 9AH INTTC1 INTTC0 & INTETC01 INTTC1 enable 9BH ITC1C R 0 ITC1M2 0 ITC1M1 R/W 0 ITC1M0 0 ITC3M0 0 IP1M0 0 ITC0C R 0 ITC2C R 0 IP0C R 0 INTTC3 INTTC2 & INTETC23 NTTC3 enable 9CH ITC3C R 0 ITC3M2 0 ITC3M1 R/W 0 INTP0 & INTP1 9DH IP1C R 0 0 IP1M2 IP1M1 R/W 0 INTEP01 NTP1 enable Interrupt request flag lxxM2 0 0 0 0 1 1 1 1 lxxM1 0 0 1 1 0 0 1 1 lxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests 91C824-48 2005-12-16 TMP91C824 (2) External interrupt control Symbol Name Address 7 - 0 Always write 0 6 - 0 Always write 0 5 I3EDGE 0 0: Rising 1: Falling 4 I2EDGE W 3 I1EDGE 0 0: Rising 1: Falling 2 I0EDGE 0 0: Rising 1: Falling 1 I0LE 0 0: Edge 1: Level 0 NMIREE 0 even on rising/ falling edge of NMI Interrupt IIMC input mode control 8CH (Prohibit RMW) 0 0: Rising 1: Falling INT3EDGE INT2EDGE INT1EDGE INT0EDGE INT0 mode 1: Operates INT0 level enable 0 1 0 1 edge detect INT H level INT INT request generation at falling edge INT request generation at rising/falling edge NMI rising edge enable (3) Interrupt request flag clear register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 3.4.1, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH: Clears interrupt request flag INT0. Symbol Name Address Interrupt INTCLR clear control 88H (Prohibit RMW) 7 6 5 CLRV5 0 4 CLRV4 0 3 CLRV3 W 0 2 CLRV2 0 1 CLRV1 0 0 CLRV0 0 Interrupt vector (4) Micro DMA start vector registers This register assigns micro DMA processing to which interrupt source. The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source. When the micro DMA transfer counter value reaches zero, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the channel with the lowest number has a higher priority. Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel is not set again, the next micro DMA is started for the channel with the higher number (Micro DMA chaining). 91C824-49 2005-12-16 TMP91C824 Symbol Name DMA0 Address 7 6 5 DMA0V5 4 DMA0V4 0 DMA1V4 0 DMA2V4 0 DMA3V4 0 3 DMA0V3 0 DMA1V3 0 DMA2V3 0 DMA3V3 0 R/W 2 DMA0V2 0 DMA1V2 0 DMA2V2 0 DMA3V2 0 1 DMA0V1 0 DMA1V1 0 DMA2V1 0 DMA3V1 0 0 DMA0V0 0 DMA1V0 0 DMA2V0 0 DMA3V0 0 DMA0V start vector 80H 0 DMA1V5 DMA0 start vector DMA1 DMA1V start vector 81H R/W 0 DMA2V5 82H 0 DMA3V5 83H 0 DMA1 start vector DMA2 DMA2V start vector R/W DMA2 start vector DMA3 DMA3V start vector R/W DMA3 start vector (5) Micro DMA burst specification Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register reaches zero after micro DMA start. Setting a bit which corresponds to the micro DMA channel of the DMAB registers mentioned below to 1 specifies a burst. Symbol Name DMA DMAR software request register DMA DMAB burst register 8AH 0 0 Address 89H (Prohibit RMW) 7 6 5 4 3 DMAR3 R/W 0 DMAB3 2 DMAR2 R/W 0 DMAB2 1 DMAR1 R/W 0 DMAB1 R/W 0 0 DMAR0 R/W 0 DMAB0 0 1: DMA software request 1: DMA burst request 91C824-50 2005-12-16 TMP91C824 (6) Attention point The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag (Note) between accepting and reading the interrupt vector. In this case, the CPU reads the default vector 0008H and reads the interrupt vector address FFFF08H. To avoid the avobe plogram, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 1-instructions (e.g., "NOP" x 1 times). In the case of changing the value of the interrupt mask register INT0 Level Mode In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H; Switches interrupt input mode from level mode to edge mode. LD (INTCLR), 0AH; Clears interrupt request flag. NOP EI ; Wait EI instruction INTRX The interrupt request flip-flop can only be cleared by a reset or by reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register. Note: The following instructions or pin input state changes are equivalent to instructions that clear the interrupt request flag. INT0: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input change from high to low after interrupt request has been generated in level mode. (H L) INTRX: Instruction which read the receive buffer 91C824-51 2005-12-16 TMP91C824 3.5 Port Functions The TMP91C824 features 56-bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 3.5.1 lists the functions of each port pin. Table 3.5.2 lists I/O registers and their specifications. Table 3.5.1 Port Functions (R: PU = with programmable pull-up resistor/U = with pull-up resistor) Port Name Port 1 Port 2 Port 5 Pin Name P10 to P17 P20 to P27 P54 P55 P56 P60 P61 P62 P63 P64 P65 P66 P67 Number of Pins 8 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 8 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Direction I/O Output I/O I/O I/O Output Output Output Output Output Output Output Output I/O I/O I/O Input I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O I/O Output Output Output I/O I/O R - - PU PU PU - - - - - - - - - PU PU - - - - - - - - - - - - - - - - - PU PU Direction Setting Unit Bit (Fixed) Bit Bit Bit (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) (Fixed) Bit Bit Bit (Fixed) Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit (Fixed) (Fixed) (Fixed) Bit Bit Pin Name for Built-in Function D8 to D15 A16 to A23 BUSRQ BUSAK WAIT Port 6 CS0 CS1 CS2 , CS2A CS3 EA24, CS2B EA25, CS2C CS2D CS2E Port 7 P70 P71 P72 SCK,OPTRX0 SO/SDA,OPTTX0 SI/SCL AN0 to AN7, ADTRG (P83) TA0IN TA1OUT TA3OUT INT0 INT1 INT2 INT3 TXD0 RXD0 SCLK0/ CTS0 TXD1 RXD1 SCLK1/ CTS1 SCOUT ALARM , MLDALM MLDALM Port 8 Port B P80 to P87 PB0 PB1 PB2 PB3 PB4 PB5 PB6 PC0 PC1 PC2 PC3 PC4 PC5 PD5 PD6 PD7 PZ2 PZ3 Port C Port D Port Z HWR R/W 91C824-52 2005-12-16 TMP91C824 Table 3.5.2 I/O Registers and Specifications (1/2) Port Port 1 (Note 1) Port 2 Port 5 P20 to P27 P54 to P56 Pin Name P10 to P17 Input port Output port Specification I/O Register Pn X X X X X 0 1 X 0 1 X 0 1 X X X X X X X X X X X X 0 1 X X X 0 0 1 0 1 0 0 1 1 1 0 0 1 None PnCR 0 1 X None 0 0 1 0 0 1 0 0 PnFC PnFC2 None 0 1 0 0 0 1 1 1 None 0 1 1 1 X 1 1 X 1 X 0 0 0 0 0 0 1 X 0 1 1 X 0 0 1 0 None 0 1 None 0 1 0 1 1 1 0 0 0 0 0 1 0 0 0 1 0 0 0 None D8 to D15 bus Output port A16 to A23 output Input port (without PU) Input port (with PU) Output port P54 P55 P56 Port 6 P60 to P64 P60 P61 P62 BUSRQ input (without PU) BUSRQ input (with PU) BUSAK output WAIT input (without PU) WAIT input (with PU) Output port CS0 output CS1 output CS2 output CS2A output P63 P64 P65 P66 P67 Port 7 P70 to P72 CS3 output EA24 output CS2B output EA25 output CS2C output CS2D output CS2E output Input port (without PU) Input port (with PU) Output port P70 SCK input SCK output OPTRX0 input (Note 2) (Note 3) (Note 2) 1 X X X 1 X X P71 SDA input SDA output SO output OPTTX0 output P72 SI input SCL input SCL output (Note 3) X X: Don't care 91C824-53 2005-12-16 TMP91C824 Table 3.5.3 I/O Registers and Specifications (2/2) Port Port 8 Pin Name P80 to P87 P83 Input port Specification Pn X X X X X X X X X X X X X X I/O Register PnCR PnFC PnFC2 None AN0 to 7 input ADTRG input (Note 4) (Note 5) Port B PB0 to PB6 PB0 PB1 PB2 PB3 PB4 PB5 PB6 Input port Output port TA0IN input TA1OUT output TA3OUT output INT0 input INT1 input INT2 input INT3 input Input port Output port TXD0 output RXD0 input SCLK0 input SCLK0 output CTS0 input 0 1 0 1 1 0 0 0 0 0 1 1 0 0 1 0 1 0 0 1 0 0 0 None 1 1 1 1 1 1 0 0 1 None 0 1 0 1 None 0 1 0 0 1 None Port C PC0 to PC5 PC0 PC1 PC2 (Note 2) (Note 2) (Note 6) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) (Note 2) 1 1 1 1 1 1 1 1 1 1 X X 1 0 X 0 1 X X X PC3 PC4 PC5 TXD1 output RXD1 input SCLK1 input SCLK1 output CTS1 input Port D PD5 to PD7 PD5 PD6 PD7 Output port SCOUT output ALARM output MLDALM output None 1 1 1 MLDALM output Input port (without PU) Input port (with PU) Output port Port Z PZ2 to PZ3 0 0 1 1 1 0 0 0 1 1 PZ2 PZ3 X: Don't care HWR output R / W output Note 1: Port 1 is only use for Port or DATA bus (D8 to D15) by setting AM1 and AM0 pins. Note 2: As for input ports of SIO0 and SIO1 (OPTRX0, OPTTX0, TXD0, RXD0, SCLK0, CTS0 , TXD1, RXD1, SCLK1, CTS1 ), logical selection for output data or input data is determined by the output latch register Pn of each port. Note 3: In case using P71 and P72 for SDA and SCL as open-drain ports, set to P7ODE 91C824-54 2005-12-16 TMP91C824 Note about bus release and programmable pull-up I/O port pins When the bus is released (e.g., when BUSAK = 0), the output buffers for D0 to D15, A0 to A23, and the control signals ( RD , WR , HWR , R / W and CS0 to CS3 , EA24, EA25, CS2A to 2E ) are off and are set to high impedance. However, the output of built-in programmable pull-up resistors are kept before the bus is released. These programmable pull-up resistors can be selected ON/OFF by programmable when they are used as the input ports. When they are used as output ports, they cannot be turned ON/OFF in software. Table 3.5.4 shows the pin states after the bus has been released. Table 3.5.4 Pin States (after bus release) Pin Name D0 to D7 D8 to D15 (P10 to P17) The state is not changed. (Do not become to high impedance (High-Z).) A0 to A15 A16 to 23 (P20 to P27) The state is not changed. (Do not become to high impedance (High-Z).) RD WR The Pin State (when the bus is released) Port Mode Function Mode Become high impedance (High-Z). First sets all bits to high, then sets them to high impedance (High-Z). PZ2 ( HWR ), PZ3 (R/ W ), The state is not changed. (Do not become to high impedance (High-Z).) First sets all bits to high, then the output buffer is OFF. The programmable pull-up resistor is ON irrespective of the output latch. First sets all bits to high, then sets them to high impedance (High-Z). P60 ( CS0 ), P61 ( CS1 ), P62 ( CS2 , CS2A ), P63 ( CS3 ), 91C824-55 2005-12-16 TMP91C824 3.5.1 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Resetting the control register P1CR to 0 and sets port 1 to input mode. In addition to functioning as a general-purpose I/O port, port 1 can also function as an address data bus (D8 to D15). When AM1 = 0 and AM0 = 1, port 10 to 17 always operate data bus function even if it changes P1CR setting. Reset Direction control (on bit basis) P1CR write Output latch Internal data bus Output buffer P1 write Port 1 P10 to P17 (D8 to D15) P1 read Figure 3.5.1 Port 1 91C824-56 2005-12-16 TMP91C824 3.5.2 Port 2 (P20 to P27) Port 2 is an 8-bit output port. In addition to functioning as a output port, port 2 can also function as an address bus (A16 to A23). Each bit can be set individually for address bus using the function register P2FC. Resetting sets all bits of the function register P2FC to 1 and sets port 2 to address bus. Reset S Function control Internal data bus (on bits basis) P2FC write S Output latch B P2 write A Selector Port 2 P20 to P27 (A16 to A23) Output buffer P2 read Internal A16 to A23 Figure 3.5.2 Port 2 91C824-57 2005-12-16 TMP91C824 Port 1 Register 7 P1 P0 (0001H) (0000H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W 3 P13 2 P12 1 P11 0 P10 Data from external port (Output latch register is cleared to 0.) Port 1 Control Register 7 P1CR (0004H) Bit symbol Read/Write After reset Function 0 0 0 0 0: Input P17C 6 P16C 5 P15C 4 P14C W 3 P13C 0 1: Output 2 P12C 0 1 P11C 0 0 P10C 0 Port 1 I/O setting 0 1 Input Output Port 2 Register 7 P2 (0006H) Bit symbol Read/Write After reset 1 1 1 1 P27 6 P26 5 P25 4 P24 R/W 3 P23 1 2 P22 1 1 P21 1 0 P20 1 Port 2 Function Register 7 P2FC (0009H) Bit symbol Read/Write After reset Function 1 1 1 0: Port 1 P27F 6 P26F 5 P25F 4 P24F W 3 P23F 1 2 P22F 1 1 P21F 1 0 P20F 1 1: Address bus (A23 to A16) Note: Read-modify-write is prohibited for P1CR and P2FC. Figure 3.5.3 Registers for Ports 1 and 2 91C824-58 2005-12-16 TMP91C824 3.5.3 Port 5 (P54 to P56) Port 5 is an 3-bit general-purpose I/O port. I/O is set using control register P5CR and P5FC. Resetting resets all bits of the output latch P5 to 1, the control register P5CR and the function register P5FC to 0 and sets P54 to P56 to input mode with pull-up resistor. In addition to functioning as a general-purpose I/O port, port 5 also functions as I/O for the CPU's control/status signal. Reset Direction control (on bit basis) P5CR write Function control Internal data bus (on bit basis) P5FC write S Selector S Output latch P5 write BUSAK P-ch (Programmable pull up) A B P55( BUSAK ) Output buffer P5 read Figure 3.5.4 Port 5 (P55) 91C824-59 2005-12-16 TMP91C824 Reset Direction control (on bit basis) P5CR write Internal data bus S Output latch P5 write P-ch (Programmable pull up) P56 ( WAIT ) Output buffer Internal WAIT Reset P5 read Direction control (on bit basis) P5CR write Function control Internal data bus (on bit basis) P5FC write S Output latch P5 write P-ch (Programmable pull up) P54 ( BUSRQ ) Internal BUSRQ P5 read Figure 3.5.5 Port 5 (P56, P54) 91C824-60 2005-12-16 TMP91C824 Port 5 Register 7 P5 (000DH) Bit symbol Read/Write After reset 6 P56 5 P55 R/W 4 P54 3 2 1 0 Data from external port (Output latch register is set to "1".) 0(Output latch register) : Pull-up resistor OFF 1(Output latch register) : Pull-up resistor ON Function Port 5 Control Register 7 P5CR (000AH) Bit symbol Read/Write After reset Function 0 0: Input 6 P56C 5 P55C W 0 1: Output 4 P54C 0 3 2 1 0 I/O setting 0 Input 1 Output Port 5 Function Register 7 P5FC (000BH) Bit symbol Read/Write After reset Function 0 0: Port 1: BUSAK 6 5 P55F W 4 P54F 0 0: Port 1: BUSRQ 3 2 1 0 Note 1: Read-modify-write is prohibited for register P5CR, P5FC. Note 2: When port 5 is used in the input mode, P5 register controls the built-in pull-up resistor. Readmodify-write is prohibited in the input mode or the I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Note 3: When P56 pin is used as a WAIT pin, set P5CR Figure 3.5.6 Register for Port 5 91C824-61 2005-12-16 TMP91C824 3.5.4 Port 6 (P60 to P67) Port 60 to 67 are 8-bit output ports. Resetting sets output latch of P62 to 0 and output latches of P60 to P61, P63 to P67 to 1. Port 6 also function as chip-select output ( CS0 to CS3 ), extend address output (EA24). Writing 1 in the corresponding bit of P6FC, P6FC2 enables the respective functions. Resetting resets the P6FC, P6FC2 to 0, and sets all bits to output ports. If set port 6, be careful of a setting because of chip select function. Starting memory connects to CS2 pin, but this signal function as P62 after reset. Therefore initialized value of output data of P62 is set to "0". If manage chip select by connection many memory to outside, after program started, must to change port function to chip select function in this program. If outputted "1" remain port function, program is not run. Therefore data setting (P6) must to execute after function changing (P6FC). Reset Function control 2 (on bit basis) P6FC2 write Funtion control (on bit basis) P6FC write S Output lacth P6 write A B Selector C P60 ( CS0 ), P61 ( CS1 ), P62 ( CS2 , CS2A ) P63 ( CS3 ), P64 (EA24, CS2B ) P65 (EA25, CS2C ) P66 ( CS2D ) P67 ( CS2E ) Internal data bus P6 read 1, 1, CS2A , 1, CS2B CS0 , CS1 , CS2 , CS3 , EA24, EA25 Figure 3.5.7 Port 6 91C824-62 2005-12-16 TMP91C824 Port 6 Register 7 P6 (0012H) Bit symbol Read/Write After reset 1 P67 6 P66 1 5 P65 1 4 P64 R/W 1 3 P63 1 2 P62 0 1 P61 1 0 P60 1 Port 6 Function Register 7 P6FC (0015H) Bit symbol Read/Write After reset Function 0 - 6 - 0 5 P65F 0 0:Port 1:EA25 4 P64F W 0 0: Port 1: EA24 3 P63F 0 0: Port 1: CS3 2 P62F 0 0: Port 1: CS2 1 P61F 0 0: Port 1: CS1 0 P60F 0 0: Port 1: CS0 Always write 0 Port 6 Function Register 2 7 P6FC2 (001BH) Bit symbol Read/Write After reset Function 0 1: CS2E P67F2 6 P66F2 W 0 1: CS2D 5 P65F2 0 1: CS2C 4 P64F2 0 1: CS2B 3 - W 0 Always write 0 2 P62F2 W 0 0: 1 - W 0 0 - W 0 0: Always write 0 Note: Read-modify-write is prohibited for P6FC and P6FC2. Figure 3.5.8 Register for Port 6 91C824-63 2005-12-16 TMP91C824 3.5.5 Port 7 (P70 to P72) Port 7 is a 3-bit general-purpose I/O port. I/O can be set on bit basis using the control register. Resetting sets port 7 to input port and all bits of output latch to 1. In addition to functioning as a general-purpose I/O port, port 7 also functions as follows. 1. Input/output function for serial bus interface (SCK, SO/SDA.SI/SCL) 2. Input/output function for IrDA (OPTRX0, OPTTX0) Writing 1 in the corresponding bit of P7FC, P7FC2 enables the respective functions. Resetting resets the P7FC, P7FC2, and P7CR to 0, and sets all bits to input ports. (1) Port 70 (SCK, OPTRX0) Port 70 is a general-purpose I/O port. It is also used as SCK (Clock signal for SIO mode) and OPTRX0 (Receive input for IrDA mode of SIO0). Used as OPTRX0, it is possible to logical invert by P7 Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write S Output latch P7 write SCK output A S Internal data bus P70 (SCK, OPTRX0) Selector B SB Selector P7 read Function control 2 (on bit basis) P7FC2 write RXD0 (to SIO0) A SCK input logical invert B Selector A RXD0PC1 (from PORTC1) S Figure 3.5.9 Port 70 91C824-64 2005-12-16 TMP91C824 (2) Port 71 (SO/SDA/OPTTX0) Port 71 is a general-purpose I/O port. It is also used as SDA (Data input for I2C mode), SO (Data output for SIO mode) for serial bus interface and OPTTX0 (Transmit output for IrDA mode of SIO0). Used as OPTTX0, it is possible to logical invert by P7 Reset Function control 2 (on bit basis) P7FC2 write Direction control (on bit basis) Internal data bus P7CR write Function control (on bit basis) P7FC write P-ch S Output latch P7 write SO output TXD0 output Logical invert SB Selector P7 read SDA input A A B C S Programable pull up Selector Open-drain possible: P7ODE P71 (SO/SDA, OPTTX0) Figure 3.5.10 Port 71 91C824-65 2005-12-16 TMP91C824 (3) Port 72 (SI/SCL) Port 72 is a general-purpose I/O port. It is also used as SI (Data input for SIO mode), SCL (Clock input/output for I2C mode) for serial bus interface and input for release hard protect. Reset Direction control (on bit basis) P7CR write Function control (on bit basis) P7FC write P-ch Internal data bus S Output latch P7 write SCL output B A S P72 (SI/SCL) Open-drain possible: P7ODE Programable pull up Selector SB Selector P7 read SI input SCL input A Figure 3.5.11 Port 72 91C824-66 2005-12-16 TMP91C824 Port 7 Register 7 P7 (0013H) Bit symbol Read/Write After reset Function 6 5 4 3 2 P72 1 P71 R/W 0 P70 Data from external port (Output latch register is set to "1".) 0(Output latch register) : Pull-up resistor ON 1(Output latch register) : Pull-up resistor OFF - Port 7 Control Register 7 P7CR (0016H) Bit symbol Read/Write After reset Function 0 0: Input 6 5 4 3 2 P72C 1 P71C W 0 1: Output 0 P70C 0 Port 7 Function Register 7 P7FC (0017H) Bit symbol Read/Write After reset Function 0 0: Port 1: SCL output 6 5 4 3 2 P72F 1 P71F W 0 0: Port output 0 P70F 0 0: Port output 1: SDA/SO 1: SCK Port 7 Function Register 2 7 P7FC2 (001CH) Bit symbol Read/Write After reset Function 0 Always write 0 6 5 4 3 2 - 1 P71F2 W 0 0: 0 P70F2 0 SIO0 RXD pin select 0: RXD0 (PC1) 1: OPTRX0 (P70) output Port 7 ODE Register 7 P7ODE (001FH) Bit symbol Read/Write After reset Function 0 0: 3 states 1: Open drain 6 5 4 3 2 ODEP72 W 1 ODEP71 0 0 Note: Read-modify-write is prohibited for P7CR, P7FC, P7FC2 and P7ODE. Figure 3.5.12 Register for Port 7 91C824-67 2005-12-16 TMP91C824 3.5.6 Port 8 (P80 to P87) Port 8 is an 8-bit input port and can also be used as the analog input pins for the internal AD converter. P83 can also be used as ADTRG pin for the AD converter. Port 8 Internal data bus Port 8 read P80 to P87 (AN0 to AN7) Conversion result register AD read AD converter Channel selector ADTRG (for P83 only) Figure 3.5.13 Port 8 Port 8 Register 7 P8 (0018H) Bit symbol Read/Write After reset P87 6 P86 5 P85 4 P84 R 3 P83 2 P82 1 P81 0 P80 Data from external port Note: The input channel selection of AD converter and the permission of ADTRG input are set by AD converter mode register ADMOD1. Figure 3.5.14 Register for Port 8 91C824-68 2005-12-16 TMP91C824 3.5.7 Port B (PB0 to PB6) Port B0 to PB6 is a 7-bit general-purpose I/O port. Each bit can be set individually for input or output. Resetting sets port B to be an input port. In addition to functioning as a general-purpose I/O port, port B0 has clock input terminal TA0IN of 8-bit timer 0, and port B1, B2 each has facility of 8-bit timer listing TA1OUT, TA3OUT terminal. And, port B3 to B6 has each external interruption input facility of INT0 to INT3. Edge selection of external interruption is establishes by IIMC register in the interrupt controller. Timer output function and external interrupt function can be enabled by writing 1 to the corresponding bits in the port B function register (PBFC). Resetting resets all bits of the registers PBCR and PBFC to 0, and sets all bits to be input ports. (1) PB0 to PB2 Reset Direction control (on bits basis) PBCR write S Output latch PB write PB read A TA0IN Reset Direction Control (on bits basis) PB0 (TA0IN) S B Selector Internal data bus PBCR write Function control (on bits basis) PBFC write S Output latch A PB write Timer F/F OUT TA1OUT: TMRA1 TA3OUT: TMRA3 S PB1 (TA1OUT) PB2 (TA3OUT) Selector B B Selector PB read SA Figure 3.5.15 Port B0 to B2 91C824-69 2005-12-16 TMP91C824 (2) PB3 (INT0), PB4 (INT1) to PB6 (INT3) Reset Direction control (on bits basis) PBCR write Internal data bus Function control (on bits basis) PBFC write S Output latch PB write SB Selector PB read A Level/edge select & Rising/falling select IIMC INT0 Figure 3.5.16 Port B3 Reset Direction control (on bits basis) PBCR write Internal data bus Function control (on bits basis) PBFC write S Output latch PB write SB Selector PB read A Rising/falling edge detection PB4 to PB6 (INT1 to INT3) INT0 to INT3 IIMC Figure 3.5.17 Port B4 to B6 91C824-70 2005-12-16 TMP91C824 Port B Register 7 PB (0022H) Bit symbol Read/Write After reset 6 PB6 5 PB5 4 PB4 3 PB3 R/W 2 PB2 1 PB1 0 PB0 Data from external port (Output latch register is set to "1".) Port B Control Register 7 PBCR (0024H) Bit symbol Read/Write After reset Function 0 0 0 0: Input 6 PB6C 5 PB5C 4 PB4C 3 PB3C W 0 1: Output 2 PB2C 0 1 PB1C 0 0 PB0C 0 Port B Function Register 7 PBFC (0025H) Bit symbol Read/Write After reset Function 0 0: Port 1: INT3 0 0: Port 1: INT2 0 0: Port 1: INT1 6 PB6F 5 PB5F 4 PB4F W 3 PB3F 0 0: Port 1: INT0 2 PB2F 0 0: Port 1: TA3OUT 1 PB1F 0 0: Port 1: TA1OUT 0 Note 1: Read-Modify-Write is prohibited for the registers PBCR and PBFC. Note 2: PB0/TA0IN pin does not have a register changing PORT/FUNCTION. For example, when it is used as an input port, the input signal is inputted to 8-bit timer. Figure 3.5.18 Register for Port B 91C824-71 2005-12-16 TMP91C824 3.5.8 Port C (PC0 to PC5) Port C0 to C5 are 6-bit general-purpose I/O ports. Each bit can be set individually for input or output. Resetting sets PC0 to PC5 to be an input ports. It also sets all bits of the output latch register to 1. In addition to functioning as general-purpose I/O port pins, PC0 to PC5 can also function as the I/O for serial channels 0 and 1. A pin can be enabled for I/O by writing 1 to the corresponding bit of the port C function register (PCFC). Resetting resets all bits of the registers PCCR and PCFC to 0 and sets all pins to be input ports . (1) Port C0, C3 (TXD0/TXD1) As well as functioning as I/O port pins, port C0 and C3 can also function as serial channel TXD output pins. In case of use TXD0/TXD1, it is possible to logical invert by setting the register PC Reset Ditection control (on bit basis) PCCR write Internal data bus Function control (on bit basis) PCFC write S Output latch PC write TXD0, TXD1 A Logical invert B S PC0 (TXD0) PC3 (TXD1) Selector Open-drain set possible PCODE S PC read B Selector A Figure 3.5.19 Port C0 and C3 91C824-72 2005-12-16 TMP91C824 (2) Port C1, C4 (RXD0, RXD1) Port C1 and C4 are I/O port pins and can also is used as RXD input for the serial channels. In case of use RXD0/RXD1, it is possible to logical invert by setting the register PC Reset Ditection control (on bit basis) Internal data bus PCCR write S Output latch PC write PC read RXD0PC1, RXD1 Logical invert PC1 (RXD0) PC4 (RXD1) S B Selector A Figure 3.5.20 Port C1 and C4 (3) Port C2 ( CTS0 , SCLK0), C5 ( CTS1 , SCLK1) Port C2 and C4 are I/O port pins and can also is used as CTS input or SCLK input/output for the serial channels. In case of use CTS , SCLK, it is possible to logical invert by setting the register PC Reset Ditection control (on bit basis) PCCR write Function control Internal data bus (on bit basis) PCFC write S Output latch PC write Logical invert SCLK0, SCLK1 output A S Selector B PC2 (SCLK0, CTS0 ) PC5 (SCLK1, CTS1 ) SB Selector PC read CTS0 , CTS1 SCLK0, SCLK1 input A Logical invert Figure 3.5.21 Port C2 and C5 91C824-73 2005-12-16 TMP91C824 Port C Register 7 PC (0023H) Bit symbol Read/Write After reset 6 5 PC5 4 PC4 3 PC3 R/W 2 PC2 1 PC1 0 PC0 Data from external port (Output latch register is set to "1".) Port C Control Register 7 Bit symbol PCCR (0026H) Read/Write After reset Function 0 0 0 0: Input 6 5 PC5C 4 PC4C 3 PC3C W 2 PC2C 0 1: Output 1 PC1C 0 0 PC0C 0 Port C Functon Register 7 PCFC (0027H) Bit symbol Read/Write After reset Function 6 5 PC5F W 0 0: Port 1: SCLK1 output 4 3 PC3F W 0 0: Port 1: TXD1 2 PC2F W 0 0: Port 1: SCLK0 output 1 0 PC0F W 0 0: Port 1: TXD0 Port C ODE Register 7 Bit symbol PCODE (0028H) Read/Write After reset Function 6 5 4 3 ODEPC3 W 0 TXD1 0: CMOS 1: Open drain 2 1 0 ODEPC0 W 0 TXD0 0: CMOS 1: Open drain Note 1: Read-modify-write is prohibited for the registers PCCR, PCFC and PCODE. Note 2: PC1/RXD0, PC4/RXD1 pins do not have a register changing PORT/FUNCTION. For example, when it is used as an input port, the input signal is inputted to SIO as the cereal receive data. Figure 3.5.22 Register for Port C 91C824-74 2005-12-16 TMP91C824 3.5.9 Port D (PD0 to PD7) Port D is an 8-bit output port. Resetting sets the output latch PD to 1, and PD5 to PD7 pin output 1. In addition to functioning as output port, port D also function as output pin for output pin for internal clock (SCOUT), output pin for RTC alarm ( ALARM ) and output pin for melody/alarm generator (MLDALM, MLDALM ). Above setting is used the function register PDFC. Only PD6 has two output functions which ALARM and MLDALM . This selection is used PD Reset Function control Internal data bus (on bit basis) PDFC write S Output latch Selector A B PD write MLDALM PD read PD7 (MLDALM) Output buffer Figure 3.5.23 Port D Reset Function control (on bit basis) PDFC write Internal data bus S Output latch S A Y Selector B PD5 (SCOUT) PD write PD read Fs clock fSYS clock A Y Selector B S SYSCR2 Figure 3.5.24 Port D 91C824-75 2005-12-16 TMP91C824 Reset Function control (on bit basis) PDFC write Internal data bus S Output latch S A Y Selector B PD6 ( ALARM , MLDALM ) PD write PD read MLDALM ALARM AS Y Selector B Figure 3.5.25 Port D Port D Register 7 PD (0029H) Bit symbol Read/Write After reset 1 PD7 6 PD6 R/W 1 5 PD5 1 4 3 2 1 0 Port D Function Register 7 PDFC (002AH) Bit symbol Read/Write After reset Function 0 0: Port 1: MLDALM 6 PD6F W 0 0: Port 1: ALARM at 5 PD5F 0 0: Port 1: SCOUT 4 3 2 1 0 PD7F Note: Read-modify-write is prohibited for the registers PDFC. Figure 3.5.26 Register for Port D 91C824-76 2005-12-16 TMP91C824 3.5.10 Port Z (PZ2 to PZ3) Port Z is the 2-bit general-purpose I/O port. I/O is set using control register PZCR and PZFC. Resetting resets all bits of the output latch PZ to 1. In addition to functioning as a general-purpose I/O port, port Z also functions as output for the CPU's control/status signal. Resetting initializes PZ2 and PZ3 pins to input mode with pull-up resistor. When the PZ 91C824-77 2005-12-16 TMP91C824 Reset Direction control (on bit basis) PZCR write Function conrtol Internal data bus (on bit basis) PZFC write S Selector S Output latch PZ write HWR P-ch (Programmable pull up) A B PZ2 ( HWR ) Output buffer PZ read Reset Direction control (on bit basis) PZCR write Function conrtol (on bit basis) Internal data bus PZFC write S Selector S Output latch PZ write A B PZ3 (R/ W ) Output buffer P-ch (Programmable pull up) R/ W PZ read Figure 3.5.27 Port Z (PZ2, PZ3) 91C824-78 2005-12-16 TMP91C824 Port Z Register 7 PZ (007DH) Bit symbol Read/Write After reset 6 5 4 3 PZ3 R/W 2 PZ2 1 0 RDE R/W 1 Data from external port (Output latch register is set to "1".) 0(Output latch register) : Pull-up resistor OFF 1(Output latch register) : Pull-up resistor ON Function Port Z Control Register 7 PZCR (007EH) Bit symbol Read/Write After reset Function 0 0: Input 6 5 4 3 PZ3C W 2 PZ2C 0 1: Output 1 0 Port Z Function Register 7 PZFC (007FH) Bit symbol Read/Write After reset Function - W 0 Always write 0 0 0: Port 1: R/ W 6 5 4 3 PZ3F W 2 PZ2F 0 0: Port 1: HWR 1 0 HWR setting PZFC 1 PZCR Note 1: Read-modify-write is prohibited for registers PZCR and PZFC. Note 2: When port Z is used in input mode, the PZ register controls the built-in pull-up resistor. Readmodify-write is prohibited in input mode or I/O mode. Setting the built-in pull-up resistor may be depended on the states of the input pin. Figure 3.5.28 Port Register for Port Z 91C824-79 2005-12-16 TMP91C824 3.6 Chip Select/Wait Controller On the TM91C824, four user-specifiable address areas (CS0 to CS3) can be set. The data bus width and the number of waits can be set independently for each address area (CS0 to CS3 and others). The pins CS0 to CS3 (which can also function as port pins P60 to P63) are the respective output pins for the areas CS0 to CS3. When the CPU specifies an address in one of these areas, the corresponding CS0 to CS3 pin outputs the chip select signal for the specified address area (in ROM or SRAM). However, in order for the chip select signal to be output, the port 6 function register P6FC must be set. CS2A To CS2E (CS pin except CS0 to CS3 ) are made by MMU. These pins are CS pin that area and BANK value is fixed without concern in setting of CS/WAIT controller. The areas CS0 to CS3 are defined by the values in the memory start address registers MSAR0 to MSAR3 and the memory address mask registers MAMR0 to MAMR3. The chip select/wait control registers B0CS to B3CS and BEXCS should be used to specify the master enable/disable status the data bus width and the number of waits for each address area. The input pin controlling these states is the bus wait request pin ( WAIT ). 3.6.1 Specifying an Address Area The CS0 to CS3 address areas are specified using the start address registers (MSAR0 to MSAR3) and memory address mask registers (MAMR0 to MAMR3). At each bus cycle, a compare operation is performed to determine if the address on the specified a location in the CS0 to CS3 area. If the result of the comparison is a match, this indicates an access to the corresponding CS area. In this case, the CS0 to CS3 pin outputs the chip select signal and the bus cycle operates in accordance with the settings in chip select/wait control register B0CS to B3CS. (See 3.6.2 "Chip Select/Wait Control Registers".) 91C824-80 2005-12-16 TMP91C824 (1) Memory start address registers Figure 3.6.1 shows the memory start address registers. The memory start address registers MSAR0 to MSAR3 set the start addresses for the CS0 to CS3 areas. Set the upper 8 bits (A23 to A16) of the start address in Memory Start Address Registers (for areas CS0 to CS3) 7 MSAR0 (00C8H) MSAR2 (00CCH) MSAR1 Bit symbol (00CAH) Read/Write MSAR3 After reset (00CEH) Function S23 1 6 S22 1 5 S21 1 4 S20 R/W 1 3 S19 1 2 S18 1 1 S17 1 0 S16 1 Determines A23 to A16 of start address. Sets start addresses for areas CS0 to CS3. Figure 3.6.1 Memory Start Address Register Address 000000H 64 Kbytes Start address Value in start address register (MSAR0 to MSAR3) 000000H ...................... 00H 010000H ...................... 01H 020000H ...................... 02H 030000H ...................... 03H 040000H ...................... 04H 050000H ...................... 05H 060000H ...................... 06H to to FFFFFFH FF0000H ...................... FFH Figure 3.6.2 Relationship between Start Address and Start Address Register Value 91C824-81 2005-12-16 TMP91C824 (2) Memory address mask registers Figure 3.6.3 shows the memory address mask registers. Memory address mask registers MAMR0 to MAMR3 are used to set the size of the CS0 to CS3 areas by specifying a mask for each bit of the start address set in memory start address registers MAMR0 to MAMR3. The compare operation used to determine if an address is in the CS0 to CS3 areas is only performed for bus address bits corresponding to bits set to 0 in these registers. Also, the address bits that can be masked by MAMR0 to MAMR3 differ between CS0 to CS3 areas. Accordingly, the size that can be each area is different. Memory Address Mask Register (for CS0 area) 7 MAMR0 (00C9H) Bit symbol Read/Write After reset Function 1 1 1 1 Sets size of CS0 area V20 6 V19 5 V18 4 V17 R/W 3 V16 1 2 V15 1 1 V14 to V9 1 0 V8 1 0: Used for address compare Range of possible settings for CS0 area size: 256 bytes to 2 Mbytes Memory Address Mask Register (CS1) 7 MAMR1 (00CBH) Bit symbol Read/Write After reset Function 1 1 1 1 Sets size of CS1 area V21 6 V20 5 V19 4 V18 R/W 3 V17 1 2 V16 1 1 V15 to V9 1 0 V8 1 0: Used for address compare Range of possible settings for CS1 area size: 256 bytes to 4 Mbytes. Memory Address Mask Register (CS2, CS3) 7 MAMR2 (00CDH) MAMR3 Bit symbol (00CFH) Read/Write After reset Function V22 1 6 V21 1 5 V20 1 4 V19 R/W 1 3 V18 1 2 V17 1 1 V16 1 0 V15 1 Sets size of CS2 or CS3 area 0: Used for address compare Range of possible settings for CS2 and CS3 area sizes: 32 Kbytes to 8 Mbytes. Figure 3.6.3 Memory Address Mask Registers 91C824-82 2005-12-16 TMP91C824 (3) Setting memory start addresses and address areas Figure 3.6.4 show an example of specifying a 64-Kbyte address area starting from 010000H using the CS0 areas. Set 01H in memory start address register MSAR0 0 0 0 0 0 0 0 1 0 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 1 1 F 1 1 H Memory end address CS0 area size (64 Kbytes) H Memory start address V14 to V9 V8 S23 S22 S21 S20 S19 S18 S17 S16 MSAR0 0 0 0 0 0 0 0 1 0 1 V20 V19 V18 V17 V16 V15 MSMR0 0 0 0 0 0 0 0 0 0 1 1 1 1 7 1 1 1 1 1 H 1 1 1 1 1 1 1 Memory address mask register setting Setting of 07H specifies a 64-Kbyte area. Figure 3.6.4 Example Showing How to Set the CS0 Area After a reset, MSAR0 to MSAR3 and MAMR0 to MAMR3 are set to FFH. B0CS 91C824-83 2005-12-16 TMP91C824 (4) Address area size specification Table 3.6.1 shows the relationship between CS area and area size. "" indicates areas that cannot be set by memory start address register and address mask register combinations. When setting an area size using a combination indicated by "", set the start address mask register in the desired steps starting from 000000H. If the CS2 area is set to 16-Mbytes or if two or more areas overlap, the smaller CS area number has the higher priority. Example: To set the area size for CS0 to 128 Kbytes: a. Valid start addresses 000000H 020000H 040000H 060000H 128 Kbytes 128 Kbytes 128 Kbytes Any of these addresses may be set as the start address. b. Invalid start addresses 000000H 010000H 030000H 050000H 64 Kbytes 128 Kbytes 128 Kbytes This is not an integer multiple of the desired area size setting. Hence, none of these addresses can be set as the start address. Table 3.6.1 Valid Area Sizes for Each CS Area Size (Bytes) 256 CS Area CS0 CS1 CS2 CS3 512 32 K 64 K 128 K 256 K 512 K 1M 2M 4M 8M Note: "" indicates areas that cannot be set by memory start address register and address mask register combinations. 3.6.2 Chip Select/Wait Control Registers Figure 3.6.5 lists the chip select/wait control registers. The master enable/disable, chip select output waveform, data bus width and number of wait states for each address area (CS0 to CS3 and others) are set in their respective chip select/wait control registers, B0CS to B3CS and BEXCS. 91C824-84 2005-12-16 TMP91C824 7 B0CS (00C0H) Readmodifywrite instructions are prohibited. 6 5 B0OM1 0 4 B0OM0 0 3 B0BUS W 0 Data bus width 0: 16 bits 1: 8 bits 2 B0W2 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 1 B0W1 0 0 B0W0 0 100: Reserved 101: 3 waits 111: 8 waits Bit symbol Read/Write After reset Function B0E W 0 0: Disable 1: Enable Chip select output waveform selection 00: For ROM/SRAM 01: 10: 11: Don't care B1OM0 0 010: (1 + N) waits 110: 4 waits B1CS (00C1H) Readmodifywrite instructions are prohibited. Bit symbol Read/Write After reset Function B1E W 0 0: Disable 1: Enable B1OM1 0 B1BUS W 0 Data bus width 0: 16 bits 1: 8 bits B1W2 0 B1W1 0 B1W0 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: 11: Don't care B2OM0 W 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 100: Reserved 101: 3 waits 111: 8 waits B2W1 0 B2W0 0 100: Reserved 101: 3 waits 111: 8 waits B3W1 0 B3W0 0 100: Reserved 101: 3 waits 111: 8 waits BEXW1 W 0 BEXW0 0 100: Reserved 101: 3 waits 111: 8 waits 010: (1 + N) waits 110: 4 waits B2CS (00C2H) Bit symbol Read/Write After reset B2E 1 0: Disable 1: Enable B2M 0 CS2 area selection area 1: CS area B2OM1 0 B2BUS 0 Data bus width 0: 16 bits 1: 8 bits B2W2 0 Readmodifywrite instructions are prohibited. Functions Chip select output waveform selection 01: 10: 11: B3OM1 0 Don't care B3OM0 0 Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 0: 16-Mbyte 00: For ROM/SRAM 010: (1 + N) waits 110: 4 waits B3CS (00C3H) Readmodifywrite instructions are prohibited. Bit symbol Read/Write After reset Functions B3E W 0 0: Disable 1: Enable B3BUS W 0 Data bus width 0: 16 bits 1: 8 bits B3W2 0 Chip select output waveform selection 00: For ROM/SRAM 01: 10: 11: Don't care Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 010: (1 + N) waits 110: 4 waits BEXCS (00C7H) Bit symbol Read/Write After reset BEXBUS 0 Data bus width 0: 16 bits 1: 8 bits BEXW2 0 Readmodifywrite instructions are prohibited. Functions Number of waits 000: 2 waits 001: 1 wait 011: 0 waits 010: (1 + N) waits 110: 4 waits Master enable bit 0 1 Enable Disable Chip select output waveform selection 00 For ROM/SRAM 01 10 Don't care 11 Number of address area waits (See 3.6.2, (3) Wait control.) Data bus width selection 0 1 16-bit data bus 8-bit data bus CS2 area selection 0 1 16-Mbyte area Specified address area Figure 3.6.5 Chip Select/Wait Control Registers 91C824-85 2005-12-16 TMP91C824 (1) Master enable bits Bit 7 ( Table 3.6.2 Dynamic Bus Sizing Operand Data Operand Start Memory Data Bus Width Address Bus Width 8 bits 2n + 0 (Even number) 2n + 1 (Odd number) 16 bits 2n + 0 (Even number) 16 bits 2n + 1 (Odd number) 16 bits 32 bits 2n + 0 (Even number) 8 bits 8 bits 8 bits 16 bits 8 bits 16 bits 8 bits CPU Address 2n + 0 2n + 0 2n + 1 2n + 1 2n + 0 2n + 1 2n + 0 2n + 1 2n + 2 2n + 1 2n + 2 2n + 0 2n + 1 2n + 2 2n + 3 CPU Data D15 to D8 xxxxx xxxxx xxxxx b7 to b0 xxxxx xxxxx b15 to b8 xxxxx xxxxx b7 to b0 xxxxx xxxxx xxxxx xxxxx xxxxx b15 to b8 b31 to b24 xxxxx xxxxx xxxxx xxxxx b7 to b0 b23 to b16 xxxxx D7 to D0 b7 to b0 b7 to b0 b7 to b0 xxxxx b7 to b0 b15 to b8 b7 to b0 b7 to b0 b15 to b8 xxxxx b15 to b8 b7 to b0 b15 to b8 b23 to b16 b31 to b24 b7 to b0 b23 to b16 b7 to b0 b15 to b8 b23 to b16 b31 to b24 xxxxx b15 to b8 b31 to b24 16 bits 2n + 1 (Odd number) 8 bits 2n + 0 2n + 2 2n + 1 2n + 2 2n + 3 2n + 4 16 bits 2n + 1 2n + 2 2n + 4 Note: xxxxx indicates that the input data from these bits are ignored during a read. During a write, indicates that the bus for these bits goes too high impedance; also, that the write strobe signal for the bus remains inactive. 91C824-86 2005-12-16 TMP91C824 (3) Wait control Bits 0 to 2 ( Table 3.6.3 Wait Operation Settings 000 001 010 Number of Waits 2 1 (1 + N) Wait Operation Inserts a wait of 2 states, irrespective of the WAIT pin state. Inserts a wait of 1 state, irrespective of the WAIT pin state. Samples the state of the WAIT pin after inserting a wait of 1 state. If the WAIT pin is low, the waits continue and the bus cycle is extended until the pin goes high. 011 100 101 110 111 0 Reserved 3 4 8 Ends the bus cycle without a wait, regardless of the WAIT pin state. Invalid setting Inserts a wait of 3 states, irrespective of the WAIT pin state. Inserts a wait of 4 states, irrespective of the WAIT pin state. Inserts a wait of 8 states, irrespective of the WAIT pin state. A reset sets these bits to 000 (2 waits). (4) Bus width and wait control for an area other than CS0 to CS3 The chip select/wait control register BEXCS controls the bus width and number of waits when memory locations which are not in one of the four user-specified address areas (CS0 to CS3) are accessed. The BEXCS register settings are always enabled for areas other than CS0 to CS3. (5) Selecting 16-Mbyte area/specified address area Setting B2CS 91C824-87 2005-12-16 TMP91C824 (6) Procedure for setting chip select/wait control When using the chip select/wait control function, set the registers in the following order: 1. 2. 3. Set the memory start address registers MSAR0 to MSAR3. Set the start addresses for CS0 to CS3. Set the memory address mask registers MAMR0 to MAMR3. Set the sizes of CS0 to CS3. Set the chip select/wait control registers B0CS to B3CS. Set the chip select output waveform, data bus width, number of waits and master enable/disable status for CS0 to CS3 . The CS0 to CS3 pins can also function as pins P60 to P63. To output a chip select signal using one of these pins, set the corresponding bit in the port 6 function register P6FC to 1. If a CS0 to CS3 address is specified which is actually an internal I/O and RAM area address, the CPU accesses the internal address area and no chip select signal is output on any of the CS0 to CS3 pins. Setting example: In this example CS0 is set to be the 64-Kbyte area 010000H to 01FFFFH. The bus width is set to 16 bits and the number of waits is set to 0. MSAR0 = 01H MAMR0 = 07H B0CS = 83H Start address: 010000H Address area: 64 Kbytes ROM/SRAM, 16-bit data bus, 0 waits, CS0 area settings enabled. 91C824-88 2005-12-16 TMP91C824 3.6.3 Connecting External Memory Figure 3.6.6 shows an example of how to connect external memory to the TMP91C824. In this example the ROM is connected using a 16-bit bus. The RAM and I/O are connected using an 8-bit bus. TMP91C824 CS0 CS1 CS2 Address bus CS Upper byte ROM OE CS Lower byte ROM OE CS CS A0 to A23 8-bit RAM OE WE 8-bit I/O OE WE D8 to D15 D0 to D7 RD WR Figure 3.6.6 Example of External Memory Connection (ROM uses 16-bit bus; RAM and I/O use 8-bit bus.) A reset clears all bits of the port 6 control register P6CR and the port 6 function register P6FC to 0 and disables output of the CS signal. To output the CS signal, the appropriate bit must be set to 1. TMP91C824F 16-bit SRAM RD WR HWR OE LDS 74AC08 UDS R/W CS0 R/W CE D [15:0] A0 A1 A2 A3 Not connect I/O [16:1] A0 A1 A2 Figure 3.6.7 Example of External Memory Connection (RAM and I/O use 16-bit bus) 91C824-89 2005-12-16 TMP91C824 3.7 8-Bit Timers (TMRA) The TMP91C824 features 4 channel (TMRA0 to TMRA3) built-in 8-bit timers. These timers are paired into 2 modules: TMRA01 and TMRA23. Each module consists of 2 channels and can operate in any of the following 4 operating modes. * * * * 8-bit interval timer mode 16-bit interval timer mode 8-bit programmable square wave pulse generation output mode (PPG: Variable duty cycle with variable period) 8-bit pulse width modulation output mode (PWM: Variable duty cycle with constant period) Figure 3.7.1 to Figure 3.7.2 show block diagrams for TMRA01 and TMRA23. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flop condition are controlled by 5-byte registers. We call control registers SFRs: Special function registers. Each of the two modules (TMRA01 and TMRA23) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. The contents of this chapter are as follows. 3.7.1 Block Diagrams 3.7.2 Operation of Each Circuit 3.7.3 SFRs 3.7.4 Operation in Each Mode (1) 8-bit timer mode (2) 16-bit timer mode (3) 8-bit PPG (Programmable pulse generation) output mode (4) 8-bit PWM (Pulse width modulation) output mode (5) Settings for each mode Table 3.7.1 Registers and Pins for Each Module Module Input pin for external clock External pin Output pin for timer flip-flop Timer run register SFR (Address) Timer register Timer mode register Timer flip-flop control register TMRA01 TA0IN (shared with PB0) TA1OUT (shared with PB1) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TMRA23 None TA3OUT (shared with PB2) TA23RUN (0108H) TA2REG (010AH) TA3REG (010BH) TA23MOD (010CH) TA3FFCR (010DH) 91C824-90 2005-12-16 3.7.1 Prescaler 2 T1 Timer Timer flip-flop flip-flop TA1FF Selector 8-bit up counter (UC0) 2n Overflow Prescaler clock: T0 4 T4 T16 T256 8 16 32 64 128 256 512 Block Diagrams Run/clear TA01RUN TA01RUN output: TA1OUT External input clock: TA0IN TA1FFCR Figure 3.7.1 TMRA01 Block Diagram 91C824-91 8-bit comparator (CP0) Match detect TA0TRG TA01MOD Match 8-bit comparator detect (CP1) 8-bit timer register Internal bus TMRA1 interrupt output: INTTA1 TMP91C824 2005-12-16 Prescaler 2 T1 T4 T16 T256 Timer flip-flop TA3FF Selector 8-bit up counter (UC2) 2 Overflow TA23MOD n Prescaler clock: T0 4 8 16 32 64 128 256 512 TA23RUN Run/clear TA23RUN TA23RUN Timer flip-flop output: TA3OUT Figure 3.7.2 TMRA23 Block Diagram 91C824-92 8-bit comparator detect (CP2) Match TA2TRG TA23MOD Match 8-bit comparator detect (CP3) 8-bit timer register TA2REG 8-bit timer register TA3REG Register buffer 2 TA23RUN Internal bus TMRA2 interrupt output: INTTA2 TMRA2 match output: TA2TRG Internal bus TMRA3 interrup output: INTTA3 TMP91C824 2005-12-16 TMP91C824 3.7.2 Operation of Each Circuit (1) Prescalers A 9-bit prescaler generates the input clock to TMRA01. The T0 as the input clock to prescaler is a clock divided by 4 which selected using the prescaler clock selection register SYSCR0 at fc = 33 MHz, fs = 32.768 kHz System Clock Selection SYSCR1 (fc/16 clock) Prescaler Clock Selection SYSCR0 Gear Value SYSCR1 3 Prescaler Output Clock Resolution T1 2 /fs (244 s) 2 /fc (0.2 s) 3 4 5 5 T4 2 /fs (977 s) 2 /fc (1.0 s) 5 6 7 8 7 T16 11 T256 2 /fs (3.9 ms) 2 /fs (62.5 ms) 2 /fc (3.9s) 8 9 7 2 /fc (62.1 s) 11 12 13 2 /fc (0.5 s) 2 /fc (1.0 s) 2 /fc (1.9 s) 2 /fc (3.9 s) 2 /fc (3.9 s) 7 7 6 2 /fc (1.9 s) 2 /fc (3.9 s) 9 2 /fc (7.8 s) 2 /fc (248.2 s) 2 /fc (15.5 s) 2 /fc (496.5 s) 10 11 14 15 2 /fc (7.8 s) 2 /fc (31.0 s) 2 /fc (1024 s) 2 /fc (15.5 s) 2 /fc (62.1 s) 2 /fc (993 s) 2 /fc (15.5 s) 2 /fc (62.1 s) 2 /fc (993 s) 9 11 15 xxx: Don't care (2) Up counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks T1, T4 or T16. The clock setting is specified by the value set in TA01MOD 91C824-93 2005-12-16 TMP91C824 (3) Timer registers (TA0REG and TA1REG) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TA01RUN Timer registers 0 (TA0REG) Y Shift trigger Register buffers 0 Write Internal data bus Selector B Matching detection in PPG cycle n 2 overflow of PWM Write to TA0REG A S TA01RUN Figure 3.7.3 Configuration of TA0REG Note: The same memory address is allocated to the timer register and the register buffer. When The address of each timer register is as follows. TA0REG: 000102H TA2REG: 00010AH TA1REG: 000103H TA3REG: 00010BH All these registers are write only and cannot be read. 91C824-94 2005-12-16 TMP91C824 (4) Comparator (CP0) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to zero and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. (5) Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR Note: When the double buffer is enabled for an 8-bit timer in PWM or PPG mode, caution is required as explained below. If new data is written to the register buffer immediately before an overflow occurs by a match between the timer register value and the up-counter value, the timer flip-flop may output an unexpected value. For this reason, make sure that in PWM mode new data is written to the register buffer by six cycles (fSYS x 6) before the next overflow occurs by using an overflow interrupt. In the case of using PPG mode, make sure that new data is written to the register buffer by six cycles before the next cycle compare match occurs by using a cycle compare match interrupt. Example when using PWM mode Match between TA0REG and up-counter 2 overflow interrupt (INTTA0) TA1OUT tPWM (PWM cycle) n Desired PWM cycle change point Write new data to the register buffer before the next overflow occurs by using an overflow interrupt 91C824-95 2005-12-16 TMP91C824 3.7.3 SFRs TMRA01 Run Register 7 TA01RUN (0100H) Bit symbol Read/Write After reset Function TA0RDE R/W 0 Double buffer 0: Disable 1: Enable TA0REG double buffer control 0 1 Disable Enable Timer run/stop control 0 1 Stop and clear Run (Count up) 0 IDLE2 0: Stop 1: Operate 0 6 5 4 3 I2TA01 2 TA01PRUN 1 TA1RUN 0 R/W 0 TA0RUN 0 8-bit timer run/stop control 0: Stop and clear 1: Run (Count up) I2TA01: TA1RUN: TA0RUN: Operation in IDLE2 mode Run TMRA1 Run TMRA0 TA01PRUN: Run prescaler Note: The values of bits 4, 5, 6 of TA01RUN are undefined when read. TMRA23 Run Register 7 TA23RUN (0108H) Bit symbol Read/Write After reset Function TA2RDE R/W 0 Double buffer 0: Disable 1: Enable TA2REG double buffer control 0 1 Disable Enable Timer run/stop control 0 1 Stop and clear Run (Count up) 0 IDLE2 0: Stop 0 0: Stop and clear 6 5 4 3 I2TA23 2 TA23PRUN 1 TA3RUN 0 R/W 0 TA2RUN 0 8-bit timer run/stop control 1: Operate 1: Run (Count up) I2TA23: TA3RUN: TA2RUN: Operation in IDLE2 mode Run TMRA3 Run TMRA2 TA23PRUN: Run prescaler Note: The values of bits 4, 5, 6 of TA23RUN are undefined when read. Figure 3.7.4 TMRA Registers 91C824-96 2005-12-16 TMP91C824 TMRA01 Mode Register 7 TA01MOD Bit symbol (0104H) Read/Write After reset Function TA01M1 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 6 TA01M0 0 5 PWM01 0 PWM cycle 00: Reserved 01: 2 6 7 8 4 PWM00 0 R/W 3 TA1CLK1 0 00: TA0TRG 01: T1 10: T16 11: T256 2 TA1CLK0 0 1 TA0CLK1 0 00: TA0IN pin 01: T1 10: T4 11: T16 0 TA0CLK0 0 Source clock for TMRA1 Source clock for TMRA0 10: 2 11: 2 TMRA0 source clock selection 00 01 10 11 TA0IN (External input) T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) TMRA1 source clock selection TA01MOD Comparator output from TMRA0 TA01MOD Overflow output from TMRA0 T1 T16 T256 Reserved 2 x source clock 6 7 8 (16-bit timer mode) PWM cycle selection 2 x source clock 2 x source clock TMRA01 operation mode selection 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA0) + 8-bit timer (TMRA1) Figure 3.7.5 TMRA Registers 91C824-97 2005-12-16 TMP91C824 TMRA23 Mode Register 7 TA23MOD (010CH) Bit symbol Read/Write After reset Function 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 PWM cycle 00: Reserved 01: 2 6 7 8 6 TA23M0 5 PWM21 4 PWM20 0 R/W 3 TA3CLK1 0 00: TA2TRG 01: T1 10: T16 11: T256 2 TA3CLK0 0 1 TA2CLK1 0 00: Reserved 01: T1 10: T4 11: T16 0 TA2CLK0 0 TA23M1 TMRA3 clock for TMRA3 TMRA2 clock for TMRA2 10: 2 11: 2 TMRA2 source clock selection 00 01 10 11 Do not set T1 (Prescaler) T4 (Prescaler) T16 (Prescaler) TMRA3 source clock selection TA23MOD PWM cycle selection 00 01 10 11 Reserved 2 x source clock 6 7 8 2 x source clock 2 x source clock TMRA23 operation mode selection 00 01 10 11 Two 8-bit timers 16-bit timer 8-bit PPG 8-bit PWM (TMRA2) + 8-bit timer (TMRA3) Figure 3.7.6 TMRA Registers 91C824-98 2005-12-16 TMP91C824 TMRA1 Flip-Flop Control Register 7 TA1FFCR (0105H) Readmodify-write instructions are prohibited. 6 5 4 3 TA1FFC1 1 R/W 2 TA1FFC0 1 1 TA1FFIE 0 TA1FF control for inversion 0: Disable 1: Enable R/W 0 TA1FFIS 0 TA1FF inversion select 0: TMRA0 1: TMRA1 Bit symbol Read/Write After reset Function 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don't care Inverse signal for timer flip-flop 1 (TA1FF) (Don't care except in 8-bit timer mode) 0 1 Inversion by TMRA0 Inversion by TMRA1 Inversion of TA1FF 0 1 Disabled Enabled Control of TA1FF 00 01 10 11 Inverts the value of TA1FF Sets TA1FF to 1 Clears TA1FF to 0 Don't care Figure 3.7.7 TMRA Registers 91C824-99 2005-12-16 TMP91C824 TMRA3 Flip-Flop Control Register 7 TA3FFCR Bit symbol (010DH) Read/Write Readmodify-write instructions are prohibited. 6 5 4 3 TA3FFC1 1 R/W 2 TA3FFC0 1 1 TA3FFIE 0 TA3FF control for inversion 0: Disable 1: Enable R/W 0 TA3FFIS 0 TA3FF inversion select 0: TMRA2 1: TMRA3 After reset Function 00: Invert TA3FF 01: Set TA3FF 10: Clear TA3FF 11: Don't care Inverse signal for timer flip-flop 3 (TA3FF) (Don't care except in 8-bit timer mode) 0 1 Inversion by TMRA2 Inversion by TMRA3 Inversion of TA3FF 0 1 Disabled Enabled Control of TA3FF 00 01 10 11 Inverts the value of TA3FF Sets TA3FF to 1 Clears TA3FF to 0 Don't care Figure 3.7.8 TMRA Registers 91C824-100 2005-12-16 TMP91C824 TMRA register 7 TA0REG (0102H) TA1REG (0103H) TA2REG (010AH) TA3REG (010BH) bit Symbol Read/Write After reset bit Symbol Read/Write After reset bit Symbol Read/Write After reset bit Symbol Read/Write After reset 6 5 4 - W Undefined - W Undefined - W Undefined - W Undefined 3 2 1 0 Note: The above registers are prohibited read-modify-write instruction. Figure 3.7.9 TMRA Registers 91C824-101 2005-12-16 TMP91C824 3.7.4 Operation in Each Mode (1) 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. Setting its function or counter data for TMRA0 and TMRA1 after stop these registers. a. Generating interrupts at a fixed interval (using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 10 seconds at fc = 33 MHz, set each register as follows: * Clock state System clock: High frequency (fc) Prescaler clock: fFPH MSB 7 TA01RUN TA01MOD TA1REG INTETA01 TA01RUN - 0 0 - - 6 X 0 0 1 X 5 X X 1 0 X 4 X X 0 1 X 3 - 1 1 - - 2 - 0 0 - 1 LSB 1 0 X 0 - 1 0 - X 0 - - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 ((2 /fc)s at fc = 33 MHz) as the input clock. 3 Set TA1REG to 10 s / T1 (2 /fc)s 40 = 28H. 3 Enable INTTA1 and set it to level 5. Start TMRA1 counting. X: Don't care, -: No change Select the input clock using in Table 3.7.2. Note: The input clocks for TMRA0 and TMRA1 are different from as follows. TMRA0: TA0IN input, T1, T4 or T16 TMRA1: Match output of TMRA0, T1, T16, T256 91C824-102 2005-12-16 TMP91C824 b. Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 1.5 s square wave pulse from the TA1OUT pin at fc = 33 MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used. * Clock state System clock: Clock gear: High frequency (fc) 1 (fc) Prescaler clock: fFPH 7 TA01RUN TA01MOD TA1REG TA1FFCR PBCR PBFC TA01RUN - 0 0 X X X - 6 X 0 0 X - - X 5 X X 0 X - - X 4 X X 0 X - - X 3 - 0 0 1 - - - 2 - 1 0 0 - - 1 1 0 - 1 1 1 1 1 0 - - 1 1 - X - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 ((2 /fc)s at fc = 33 MHz) as the input clock. 3 Set the timer register to 1.5 s / T1(2 /fc)s / 2 3. 3 Clear TA1FF to 0 and set it to invert on the match detects signal from TMRA1. Set PB1 to function as the TA1OUT pin. Start TMRA1 counting. X: Don't care, -: No change T1 TA01RUN 0 1 2 3 0 1 2 3 0 1 2 3 0 Comparator timing Comparator output (Match detect) INTTA1 UC1 clear TA1FF TA1OUT 0.75 s at fc = 33 MHz Figure 3.7.10 Square Wave Output Timing Chart (50% duty) 91C824-103 2005-12-16 TMP91C824 c. Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparaot output (TMRA0 match) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) TMRA1 match output 1 2 3 1 4 5 1 2 3 2 4 5 1 2 1 3 Figure 3.7.11 TMRA1 Count up on Signal from TMRA0 91C824-104 2005-12-16 TMP91C824 (2) 16-bit timer mode A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD System clock: Clock gear: High frequency (fc) 1 (fc) * Clock state Prescaler clock: fFPH If T16 ((27/fc)s at 33 MHz) is used as the input clock for counting, set the following value in the registers: 0.24 s / (27/fc)s 62500 = F424H (e.g., set TA1REG to F4H and TA0REG to 24H). As a result, INTTA1 interrupt can be generated every 0.24 [s]. The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not be cleared and also INTTA0 is not generated. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparators TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TA1FF is inverted. Example: When TA1REG = 04H and TA0REG = 80H Value of up counter (UC1, UC0) TMRA0 comparator match detect signal TMRA0 comparator match detect signal INTTA0 INTTA1 TA1OUT 0080H 0180H 0280H 0380H 0480H 0080H Inversion Figure 3.7.12 Timer Output by 16-Bit Timer Mode 91C824-105 2005-12-16 TMP91C824 (3) 8-bit PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active-Low or active-High. In this mode TMRA1 cannot be used. TMRA0 outputs pulses on the TA1OUT pin. tH When tL tH Example when Figure 3.7.13 8-Bit PPG Output Waveforms 91C824-106 2005-12-16 TMP91C824 In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN TA1OUT TA0IN T1 T4 T16 Selector TA01RUN Inversion INTTA0 Comparator INTTA1 TA01MOD Comparator Selector TA0REG-WR TA0REG Shift trigger Register buffer TA1REG TA01RUN Figure 3.7.14 Block Diagram of 8-Bit PPG Output Mode If the TA0REG double buffer is enabled in this mode, the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0. Use of the double buffer facilitates the handling of low-duty waves (when duty is varied). Match with TA0REG and up counter Match with TA1REG TA0REG (Value to be compared) Register buffer Q1 Q2 Shift to register buffer Q2 Q3 TA0REG (Register buffer) write (Up counter = Q1) (Up countner = Q2) Figure 3.7.15 Operation of Register Buffer 91C824-107 2005-12-16 TMP91C824 Example: To generate 1/4-duty 50-kHz pulses (at fc = 33 MHz) 20 s * Clock state System clock: Clock gear: High frequency (fc) 1 (fc) Prescaler clock: fFPH Calculate the value which should be set in the timer register. To obtain a frequency of 50 kHz, the pulse cycle t should be: t = 1/50 kHz = 20 s T1 = (23/fc)s (at 33 MHz); 20 s / (23/fc)s 83 Therefore set TA1REG = 83 = 53H The duty is to be set to 1/4: t x 1/4 = 20 s x 1/4 = 5 s 5 s / (23/fc)s 10 Therefore, set TA0REG = 21 =15H. 7 TA01RUN TA01MOD TA0REG TA1REG TA1FFCR PBCR PBFC TA01RUN - 1 0 0 X X X 1 6 X 0 0 1 X - - X 5 X X 0 0 X - - X 4 X X 1 1 X - - X 3 - X 0 0 0 - - - 2 0 X 1 0 1 - - 1 1 0 0 0 1 1 1 1 1 0 0 1 1 1 X - X 1 Stop TMRA0 and TMRA01 and clear it to 0. Set the 8-bit PPG mode, and select T1 as input clock. Write 15H Write 53H Set TA1FF, enabling both inversion and the double buffer. Writing 10 provides negative logic pulse. Set PB1 as the TA1OUT pin. Start TMRA0 and TMRA01 counting. X: Don't care, -: No change 91C824-108 2005-12-16 TMP91C824 (4) 8-bit PWM (Pulse width modulation) output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin. TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7 or 8 as specified by TA01MOD TA0REG and UC0 match 2 overflow (INTTA0 interrupt) TA1OUT tPWM (PWM cycle) n Figure 3.7.16 8-Bit PWM Waveforms Figure 3.7.17 shows a block diagram representing this mode. TA01RUN TA0IN T1 T4 T16 TA1OUT TA1FFCR Selector 8-bit up counter (UC0) Clear 2 n TAFF1 Invert TA01MOD TA01MOD overflow control Comparator Overflow INTTA0 TA0REG Selector TA0REG-WR Shift trigger Register buffer TA01RUN Figure 3.7.17 Block Diagram of 8-Bit PWM Mode 91C824-109 2005-12-16 TMP91C824 In this mode, the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG Up counter = Q1 2 overflow TA0REG (Value to be compared) Register buffer Q1 Q2 Shift into TA0REG Q2 Q3 TA0REG (Register buffer) write n Up counter = Q2 Figure 3.7.18 Register Buffer Operation Example: To output the following PWM waves on the TA1OUT pin at fc = 33MHz: 17.9 s 31.0 s * Clock state System clock: Clock gear: High frequency (fc) 1 (fc) Prescaler clock: fFPH To achieve a 31.0 s PWM cycle by setting T1 = (23/fc)s (at fc = 33 MHz): 31.0 s / (23/fc)s 128 = 2n Therefore n should be set to 7. Since the low-level period is 37.0 s when T1 = (23/fc)s, set the following value for TA0REG: 17.9 s / (23/fc)s 74 = 4AH MSB 7 TA01RUN TA01MOD TA0REG TA1FFCR PBCR PBFC TA01RUN - 1 0 X X X 1 6 X 1 1 X - - X 5 X 1 0 X - - X 4 X 0 0 X - - X 3 - - 1 1 - - - 2 - - 0 0 - - 1 LSB 1 - 0 1 1 1 1 - 0 0 1 0 X - X 1 Stop TMRA0 and clear it to 0. Select 8-bit PWM mode (Cycle: 2 ) and select T1 as the 7 input clock. Write 4AH. Clear TA1FF to 0, enable the inversion and double buffer. Set PB1 and the TA1OUT pin. Start TMRA0 counting. X: Don't care, -: No change 91C824-110 2005-12-16 TMP91C824 Table 3.7.3 PWM Cycle at fc = 33 MHz, fs = 32.768 kHz Select System Clock PWM Cycle 2 T1 15.6 ms 15.5 s 31.0 s 32.1 s 124.1 s 248.2 s 248.2 s 6 27 T16 250 ms 248.2 s 496.5 s 993.0 s 1986 s 3972 s 3972 s 28 T16 500 ms 496.5 s 993.0 s 1986 s 3972 s 7944 s 7944 s T4 62.5 ms 62.1 s 124.1 s 248.2 s 496.5 s 993.0 s 993.0 s T1 31.3 ms 31.0 s 62.1 s 124.1 s 248.2 s 496.5 s 496.5 s T4 125 ms 124.1 s 248.2 s 496.5 s 993.0 s 1986 s 1986 s T1 62.5 ms 62.1 s 124.1 s 248.2 s 496.5 s 993 s 993 s T4 250 ms 248.2 s 496.5 s 993.0 s 1986 s 3972 s 3972 s T16 1000 ms 993.0 s 1986 s 3972 s 7944 s 15888 s 15888 s (5) Settings for each mode Table 3.7.4 shows the SFR settings for each mode. Table 3.7.4 Timer Mode Setting Registers Register Name 6 7 8 TA1FFCR TA1FFIS Timer F/F Invert Signal Select 0: Lower timer output 1: Upper timer output - - External clock - T1, T16, T256 (01, 10, 11) T1, T4, T16 (00, 01, 10, 11) - Output disabled - (01, 10, 11) - 8-bit Timer x 1 channel -: Don't care 11 91C824-111 2005-12-16 TMP91C824 3.8 External Memory Extension Function (MMU) This is MMU function which can expand program/data area to 106 Mbytes by having 4 local areas. Address pins to external memory are 2 extended address bus pins (EA24, EA25) and 8 extended chip select pins ( CS2A to CS2E ) in addition to 24 address bus pins (A0 to A23) which are common specification of TLCS-900 family and 4 chip select pins ( CS0 to CS3 ) output from CS/WAIT controller. The feature and the recommendation setting method of two types are shown below. In addition, AH in the table is the value which number address 23 to 16 displayed as hex. (A): For Standard Extended Memory (B): For Many Pieces Extended Memory Purpose Item Maximum memory size 2 Mbytes: COMMON2 + 14 Mbytes: bank (16 Mbytes x 1 pcs) LOCAL2 (AH = C0 - DF: 2 Mbytes x 7 BANK) Setup AH = C0 - FF to CS2 CS2 Program ROM Used local area, BANK number Setting CS/WAIT Used CS pin Maximum memory size Used local area, BANK number Setup AH = 80 - FF to CS2 CS2A 64 Mbytes (64 Mbytes x 1 pcs) LOCAL3 (AH = 80 - BF: 4 Mbytes x 16 BANK) Setup AH = 80 - BF to CS3 CS3 , EA24, EA25 64 Mbytes (16 Mbytes x 4 pcs) LOCAL3 (AH = 80 - BF: 4 Mbytes x 16 BANK) Setup AH = 80 - FF to CS2 CS2B , CS2C , CS2D , CS2E Data ROM Setting CS/WAIT Used CS pins Maximum memory size Option program ROM Used local area, BANK number Setting CS/WAIT Used CS pin Maximum memory size Data RAM Used local area, BANK number Setting CS/WAIT Used CS pin Maximum memory size Extended memory 1 Used local area, BANK number Setting CS/WAIT Used CS pin Total memory size 2 Mbytes: COMMON1 + 14 Mbytes : bank (16 Mbytes x 1 pcs) LOCAL1 (AH = 40 - 5F: 2 Mbytes x 7 BANK) Setup AH = 40 - 7F to CS1 CS1 1 Mbyte : COMMON0 + 7 Mbytes: bank (8 Mbytes x 1 pcs) LOCAL0 (AH = 10 - 1F: 1 Mbyte x 7 BANK) Setup AH = 00 - 3F to CS0 CS0 Setup AH = 00 - 1F to CS3 CS3 COMMON0 Overlapped data RAM Setup AH = 00 - 3F to CS0 CS0 2 Mbytes (2 Mbytes x 1 pcs) None Setup AH = 20 - 3F to CS0 CS0 16M + 64M + 16M + 8M = 104 16M + (16M + 16M + 16M + Mbytes 16M) + 16M + 8M + 2M = 106 Mbytes 91C824-112 2005-12-16 TMP91C824 3.8.1 Recommendable Memory Map The recommendation logic address memory map at the time of varieties extension memory correspondence is shown in Figure 3.8.1. And, a physical-address map is shown in Figure 3.8.2. However, when memory area is less than 16 Mbytes and is not expanded, please refer to section of CS/WAIT controller. Setting of register in MMU is not necessary. Since it is being fixed, the address of a local area cannot be changed. BANK Address 000000H Size Memory map COMMON0 LOCAL0 (COMMON0 Pin set A case) 01234567 LOCAL1 01234567 (CS/WAIT) Pin set A (CS/WAIT) Pin set B 1 Mbyte 100000H 1 Mbyte 200000H 2 Mbytes 400000H 2 Mbytes 600000H 2 Mbytes 800000H (CS0) CS0 (CS3) CS3 (CS0) CS0 (CS0) CS0 (CS1) CS1 (CS1) CS1 COMMON1 012 ... 14 15 (CS3) CS3 (CS2) CS2B (BANK0 to BANK3) CS2C (BANK4 to BANK7) CS2D (BANK8 to BANK11) CS2E (BANK12 to BANK15) 4 Mbytes LOCAL3 EA24 EA25 C00000H 2 Mbytes E00000H 2 Mbytes FFFF00H 256 bytes FFFFFFH Vector area COMMON2 LOCAL2 01234567 (CS2) CS2 (CS2) CS2A : Internal area : Overlapped with COMMON area Figure 3.8.1 Logical Address Map 91C824-113 2005-12-16 TMP91C824 LOCAL0 CS3 LOCAL1 CS1 LOCAL2 CS2A LOCAL3 for data RAM (8 Mbytes) 000000H BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 for option program ROM (16 Mbytes) BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 for data ROM for program ROM (16 Mbytes x 6) CS2B (16 Mbytes) CS2E BANK0 BANK1 BANK2 BANK3 BANK4 BANK5 BANK6 BANK7 CS2C BANK0 BANK12 Internal I/O & RAM BANK1 BANK13 800000H BANK2 BANK14 1000000H BANK7 BANK3 BANK15 000000H Reset & interrupt vector area BANK4 BANK5 BANK6 BANK7 1000000H CS2D 000000H BANK8 BANK9 : Internal area : Overlapped with COMMON area BANK10 BANK11 1000000H Figure 3.8.2 Physical Address Map 91C824-114 2005-12-16 TMP91C824 3.8.2 Control Registers Setup bank value and bank use in bank setting register of each local area of LOCAL register in common area. Moreover, in that case, a combination pin is set up and mapping is simultaneously setup by the CS/WAIT controller. When CPU outputs logical address of the local area, MMU outputs physical address to the outside address bus pin according to value of bank setting register. Access of external memory becomes possible therefore. LOCAL0 Register 7 LOCAL0 (0350H) Bit symbol Read/Write After reset Function L0E R/W 0 BANK for LOCAL0 0: Disable 1: Enable "000" setting is prohibited because it pretend COMMON 0 area 0 6 5 4 3 2 L0EA22 1 L0EA21 R/W 0 0 L0EA20 0 Setting BANK number for LOCAL0 LOCAL1 Register 7 LOCAL1 (0351H) Bit symbol Read/Write After reset Function L1E R/W 0 BANK for LOCAL1 0: Disable 1: Enable "001" setting is prohibited because it pretend COMMON 0 area 0 6 5 4 3 2 L1EA23 1 L1EA22 R/W 0 0 L1EA21 0 Setting BANK number for LOCAL1 LOCAL2 Register 7 LOCAL2 (0352H) Bit symbol Read/Write After reset Function L2E R/W 0 BANK for LOCAL2 0: Disable 1: Enable "111" setting is prohibited because it pretend COMMON 0 area 0 6 5 4 3 2 L2EA23 1 L2EA22 R/W 0 0 L2EA21 0 Setting BANK number for LOCAL2 LOCAL3 Register 7 LOCAL3 (0353H) Bit symbol Read/Write After reset Function L3E R/W 0 BANK LOCAL3 0: Disable 1: Enable for 6 5 4 L3EA26 R/W 3 L3EA25 R/W 2 L3EA24 R/W 1 L3EA23 R/W 0 L3EA22 R/W 0 0 0 01000 to 01011: CS2D 00000 to 00011: CS2B 00100 to 00111: CS2C 0 0 01100 to 01111: CS2E 10000 to 11111: Set prohibition Note: In case of this TMP91C824, because most upper address bit of physical address is EA25, most upper address bit of BANK register is meaningless. 4 bits of upper 5-bit address means 16 BANKs. 91C824-115 2005-12-16 TMP91C824 Data/Stack RAM CS0 SRAM CS0 8 Mbytes 8 bits 000000H to 1FFFFFH (Logical) 000000H to 7FFFFFH (Physical) CS1 Optional ROM CS1 FLASH Data Address TMP91C824 RD , ( WR , HWR : SRAM) 400000H to 7FFFFFH (Logical) 000000H to FFFFFFH (Physical) 16 Mbytes 16 bits MROM 16 Mbytes 16 bits CS2 Program ROM CS2 C00000H to FFFFFFH (Logical) 000000H to FFFFFFH (Physical) EA24, EA25 CS3 MROM 64 Mbytes 16 bits Data ROM CS3 800000H to BFFFFFH (Logical) 0000000H to 3FFFFFFH (Physical) * In case of 16-bit bus memory * In case of 8-bit bus memory TMP91C824 Control signals D [0:15] A0 A1 A2 A16 Memory Control signals D [0:15] Open A0 A1 A15 TMP91C824 Control signals D [0:7] A0 A1 A2 A7 Memory Control signals D [0:7] A0 A1 A2 A7 : : : : * In case of 16-bit bus memory, address connection is ... : CPU A1 = Memory A0, CPU A2 = Memory A1... * In case of 8-bit bus memory, address connection is ... : CPU A0 = Memory A0, CPU A1 = Memory A1... Figure 3.8.3 H/W Setting Example 91C824-116 2005-12-16 TMP91C824 At Figure 3.8.3, it shows example of connection TMP91C824 and some memories: Program ROM: MROM, 16 Mbytes, data ROM: MROM, 64 Mbytes, data RAM: SRAM, 8 Mbytes, 8-bit bus, option ROM: Flash, 16 Mbytes. In case of 16-bit bus memory connection, it need to shift 1-bit address bus from TMP91C824 and 8-bit bus case, direct connection address bus from TMP91C824. In that figure, logical address and physical address are shown. And each memory allot each chip select signal, RAM: CS0 , FLASH ROM: CS1 , program MROM: CS2 , data MROM: CS3 . In case of this example, as data MROM is 64 Mbytes, this MROM connect to EA24 and EA25. Initial condition after reset, because TMP91C824 access from CS2 area, CS2 area allot to program ROM. It can set free setting except program ROM. ;Initial Setting ;CS0 LD (MSAR0),00H LD (MAMR0),FFH LD (B0CS),89H ;CS1 LD (MSAR1),40H LD (MAMR1),FFH LD (B1CS),80H ;CS2 LD (MSAR2),C0H LD (MAMR2),7FH LD (B2CS),C3H ;CS3 LD (MSAR3),80H LD (MAMR3),7FH LD (B3CS),85H ;CSX LD (BEXCS),00H ;Port LD (P6FC), 3FH ; Logical address area: 000000H to 1FFFFFH ; Logical address size: 2 Mbytes ; Condition: 8 bits, 1 wait (8 Mbytes, SRAM) ; Logical address area: 400000H to 7FFFFFH ; Logical address size: 4 Mbytes ; Condition: 16 bits, 2 waits (16 Mbytes, Flash ROM) ; Logical address area: C00000H to FFFFFFH ; Logical address size: 4 Mbytes ; Condition: 16 bits, 0 waits (16 Mbytes, MROM) ; Logical address area: 800000H to BFFFFFH ; Logical address size: 4 Mbytes ; Condition: 16 bits, 3 waits (64 Mbytes, MROM) ; Other : 16 bits, 2 waits (Don't care) ; CS0 to CS3 , EA24, EA25: Port 6 setting Figure 3.8.4 BANK Operation S/W Example 1 Secondly, it shows example of initial setting at Figure 3.8.4. Because CS0 connect to RAM: 8-bit bus, 8 Mbytes, it need to set 8-bit bus. At this example, it set 1-wait setting. In the same way CS1 set to 16-bit bus and 2 waits, CS2 set 16-bit bus and 0 waits, CS3 set 16-bit bus and 3 waits. By CS/WAIT controller, each chip selection signal's memory size, don't set actual connect memory size, need to set that logical address size: fitting to each local area. Actual physical address is set by each area's BANK register setting. CSX setting of CS/WAIT controller is except above CS0 to CS3's setting. This program example isn't used CSX setting. Finally pin condition is set. Port 60 to 65 set to CS0 , CS1 , CS2 , CS3 , EA24, EA25. 91C824-117 2005-12-16 TMP91C824 ;BANK Operation ;***** CS2 ***** ORG 000000H ORG 200000H ORG 400000H ORG 600000H ORG 800000H ORG a00000H ORG c00000H ORG E00000H LD (LOCAL3),85H LDW HL,(800000H) LD (LOCAL3),88H LDW BC,(800000H) ~ ORG FFFFFFH ;***** ORG ORG ORG ORG ORG ORG ; Program ROM: Start address at BANK0 of LOCAL2 ; Program ROM: Start address at BANK1 of LOCAL2 ; Program ROM: Start address at BANK2 of LOCAL2 ; Program ROM: Start address at BANK3 of LOCAL2 ; Program ROM: Start address at BANK4 of LOCAL2 ; Program ROM: Start address at BANK5 of LOCAL2 ; Program ROM: Start address at BANK6 of LOCAL2 ; Program ROM: Start address at BANK7 (= COMMON2) of LOCAL2 ; Logical address E00000H to FFFFFFH ; Physical address 0E00000H to 0FFFFFFH ; LOCAL3 BANK5 set 14xxxxH ; Load data (5555H) form BANK5 (140000H: Physical address) of LOCAL3 ( CS3 ) ; LOCAL3 BANK8 set 20xxxxH ; Load data (AAAAH) form BANK8 (200000H: Physical address) of LOCAL3 ( CS3 ) ; Program ROM: End address at BANK7 (= COMMON2) of LOCAL2 ~ ORG 1800000H ORG 1C00000H ORG 2000000H dw AAAAH ~ ORG 2400000H ORG 2800000H ORG 2C00000H ORG 3000000H ORG 3400000H ORG 3800000H ORG 3C00000H ORG 3FFFFFFH CS3 ***** 0000000H 0400000H 0800000H 0C00000H 1000000H 1400000H dw 5555H ; Data ROM: Start address at BANK0 of LOCAL3 ; Data ROM: Start address at BANK1 of LOCAL3 ; Data ROM: Start address at BANK2 of LOCAL3 ; Data ROM: Start address at BANK3 of LOCAL3 ; Data ROM: Start address at BANK4 of LOCAL3 ; Data ROM: Start address at BANK5 of LOCAL3 ; Data ROM: Start address at BANK6 of LOCAL3 ; Data ROM: Start address at BANK7 of LOCAL3 ; Data ROM: Start address at BANK8 of LOCAL3 ; Data ROM: Start address at BANK9 of LOCAL3 ; Data ROM: Start address at BANK10 of LOCAL3 ; Data ROM: Start address at BANK11 of LOCAL3 ; Data ROM: Start address at BANK12 of LOCAL3 ; Data ROM: Start address at BANK13 of LOCAL3 ; Data ROM: Start address at BANK14 of LOCAL3 ; Data ROM: Start address at BANK15 of LOCAL3 ; Data ROM: End address at BANK15 of LOCAL3 Figure 3.8.5 BANK Operation S/W Example 2 Here shows example of data access between one BANK and other BANK. Figure 3.8.5 is one software example. A dot line square area shows one memory and each dot line square shows CS2 's program ROM and CS3 's data ROM. Program start from E00000H address, firstly, write to BANK register of LOCAL3 area upper 5-bit address of access point. In case of this TMP91C824, because most upper address bit of physical address is EA25, most upper address bit of BANK register is meaningless. 4 bits of upper 5-bit address means 16 BANKs. After setting BANK5, accessing 800000H to BFFFFFH address: Logical LOCAL3 address, actually access to physical 1400000H to 1700000H address. 91C824-118 2005-12-16 TMP91C824 ;BANK Operation ;***** CS2 ***** ORG 000000H ORG 200000H NOP ~ JP E00100H ORG 400000H ORG 600000H NOP ~ JP E00200H ORG 800000H ORG a00000H ORG c00000H !!!! Program Start !!!! ORG E00000H LD JP (LOCAL2),81H C00000H ; Program ROM: Start address at BANK0 of LOCAL2 ; Program ROM: Start address at BANK1 of LOCAL2 ; Operation at BANK1of LOCAL2 ; Jump to BANK7 (= COMMON2) of LOCAL2 ; Program ROM: Start address at BANK2 of LOCAL2 ; Program ROM: Start address at BANK3 of LOCAL2 ; Operation at BANK3 of LOCAL2 ; Jump to BANK7 (= COMMON2) of LOCAL2 ; Program ROM: Start address at BANK4 of LOCAL2 ; Program ROM: Start address at BANK5 of LOCAL2 ; Program ROM: Start address at BANK6 of LOCAL2 ; Program ROM: Start address at BANK7 (= COMMON2) of LOCAL2 ; Logical address E00000H to FFFFFFH ; Physical address 0E00000H to 0FFFFFFH ; LOCAL2 BANK1 set 20xxxxH ; Jump to BANK1 (200000H: Physical address) of LOCAL2 ; LOCAL2 BANK3 set 60xxxxH ; Jump to BANK3 (600000H: Physical address) of LOCAL2 ; LOCAL1 BANK4 set 80xxxxH ; Jump to BANK4 (800000H: Physical address) of LOCAL1 ; Program ROM: End address at BANK7 (= COMMON2) of LOCAL2 ~ ORG E00100H LD (LOCAL2),83H JP C00000H ~ ORG E00200H LD (LOCAL1),84H JP 400000H ORG FFFFFFH ;***** ORG ORG ORG ORG CS1 ***** 000000H 200000H 400000H 600000H LD (LOCAL1),87H JP 400000H ORG 800000H NOP ~ JP 600000H ORG a00000H ORG c00000H ORG E00000H LD (LOCAL1),80H JP 400000H ; Program ROM: Start address at BANK0 of LOCAL1 ; Program ROM: Start address at BANK1 of LOCAL1 ; Program ROM: Start address at BANK2 of LOCAL1 ; Program ROM: Start address at BANK3 (= COMMON1) of LOCAL1 ; LOCAL1 BANK7 set E0xxxxH ; Jump to BANK7 (E00000H: Physical address) of LOCAL1 ; Program ROM: Start address at BANK4 of LOCAL1 ; Operation at BANK4 of LOCAL1 ; Jump to BANK3 (= COMMON1) of LOCAL1 ; Program ROM: Start address at BANK5 of LOCAL1 ; Program ROM: Start address at BANK6 of LOCAL1 ; Program ROM: Start address at BANK7 of LOCAL1 ; LOCAL1 BANK0 set 00xxxxH ; Jump to BANK0 (000000H: Physical address) of LOCAL1 It's prohibit to set other BANK setting in except common area Program run away ORG FFFFFFH ; Program ROM: End address at BANK7 of LOCAL1 Figure 3.8.6 BANK Operation S/W Example 3 91C824-119 2005-12-16 TMP91C824 At Figure 3.8.6, it shows example of program jump. In the same way with before example, two dot line squares show each CS2 's program ROM and CS1 's option ROM. Program start from E00000H common address, firstly, write to BANK register of LOCAL2 area upper 3-bit address of jumping point. After setting BANK1, jumping C00000H to DFFFFFH address: Logical LOCAL2 address, actually jump to physical 2000000H to 3FFFFFH address. When return to common area, it can only jump to E00000H to FFFFFFH without writing to BANK register of LOCAL2 area. By a way of setting of BANK register, the setting that BANK address and common address conflict with is possible. When two kinds or more logical addresses to show common area exist, management of BANK is confused. We recommend not using The BANK setting, BANK address and common address conflict with. When it jumps to one memory from other different memory, it can set same as the last time setting. It needs to write to BANK register of local1 area upper 3-bit address of jumping point. After setting BANK4, jumping 400000H to 5FFFFFH address: Logical LOCAL1 address, actually jump to physical 8000000H to 9FFFFFH address. It is a mark paid attention to here, it needs to go by way of common area by all means when moves from a bank to a bank. In other words, it must write to BANK register only in common area and It is prohibit writing the BANK register in BANK area. If it modify the BANK register's data in BANK area, program run-away. 91C824-120 2005-12-16 TMP91C824 3.9 Serial Channels TMP91C824 includes 2 serial I/O channels. For both channels either UART mode (Asynchronous transmission) or I/O interface mode (Synchronous transmission) can be selected. * I/O interface mode Mode 0: For transmitting and receiving I/O data using the synchronizing signal SCLK for extending I/O. Mode 1: 7-bit data Mode 2: 8-bit data Mode 3: 9-bit data * UART mode In mode 1 and mode 2, a parity bit can be added. Mode 3 has a wakeup function for making the master controller start slave controllers via a serial link (A multi-controller system). Figure 3.9.2, Figure 3.9.3 are block diagrams for each channel. Serial channels 0 and 1 can be used independently. Both channels operate in the same fashion except for the following points; hence only the operation of channel 0 is explained below. Table 3.9.1 Differences between Channels 0 to 1 Channel 0 Pin Name TXD0 (PC0) RXD0 (PC1) CTS0 /SCLK0 (PC2) Yes Channel 1 TXD1 (PC3) RXD1 (PC4) CTS1 /SCLK1 (PC5) No IrDA Mode This chapter contains the following sections: 3.9.1 3.9.2 3.9.3 3.9.4 3.9.5 Block Diagrams Operation of Each Circuit SFRs Operation in Each Mode Support for IrDA 91C824-121 2005-12-16 TMP91C824 * Mode 0 (I/O interface mode) Bit0 1 2 3 4 5 6 7 Transfer direction * Mode 1 (7-bit UART mode) No parity Start Bit0 1 2 3 4 5 6 Stop Parity Start Bit0 1 2 3 4 5 6 Parity Stop * Mode 2 (8-bit UART mode) No parity Start Bit0 1 2 3 4 5 6 7 Stop Parity Start Bit0 1 2 3 4 5 6 7 Parity Stop * Mode 3 (9-bit UART mode) Start Bit0 1 2 3 4 5 6 7 8 Stop Wakeup function Start Bit0 1 2 3 4 5 6 7 Bit8 Stop When Bit8 = 1, address (Select code) is denoted. When Bit8 = 0, data is denoted. Figure 3.9.1 Data Formats 91C824-122 2005-12-16 TMP91C824 3.9.1 Block Diagrams Figure 3.9.2 is a block diagram representing serial channel 0. Prescaler 2 4 8 16 32 64 T2 T8 T32 Serial clock generation circuit BR0CR BR0CR BR0ADD T0 TA0TRG (from TMRA0) T0 T2 T8 T32 Prescaler Selector Selector Selector UART mode SIOCLK BR0CR SC0MOD0 SC0MOD0 Selector I/O interface mode SC0CR Parity control SCLK0 Concurrent with PC2 (UART only / 16) Receive counter (UART only / 16) Transmision counter RXDCLK SC0MOD0 Receive control CTS0 SC0MOD0 Concurrent with PC2 RXD0 Concurrent with PC1 Receive buffer 1 (Shift register) RB8 Receive buffer 2 (SC0BUF) Error flag TB8 Transmission buffer (SC0BUF) SC0CR TXD0 Concurrent with PC0 Figure 3.9.2 Block Diagram of the Serial Channel 0 (SIO0) 91C824-123 2005-12-16 TMP91C824 Prescaler T0 2 4 8 16 32 64 T2 T8 T32 Serial clock generation circuit BR1CR |