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| ASAHI KASEI [AKD4121A] AKD4121A AK4121A Evaluation Board Rev.0 GENERAL DESCRIPTION The AKD4121A is the evaluation board for the AK4121A, 96kHz asynchronous sample rate converter. This board has the optical connectors to interface with other digital audio equipments and serial interfaces for AKM AD/DA evaluation boards. The AKD4121A achieves quick evaluation of AK4121A Ordering guide AKD4121A --Evaluation board for AK4121A FUNCTION Optical fiber connectors (for Digital Audio Interface. input x 1, output x 1.) 10pin Header (for AKM AD/DA evaluation board. input x 1, output x 1.) On board X'tal Oscillator (input x 1, output x 1.) 5V or 3.3V JACK +3.3V REG JP10 3.3V JP1 IMCLK PORT1 IMCLK IBICK ILRCK SDTI 10pin Header PORT2 DIR (AK4112B) Optical Input 2 OUT IN 3 +3.3V OUT T1 48M003F D5V IN GND JP11 Bypass JP6 DIT-SOURCE +3.3V D5V DIR PORT3 OMCLK OBICK OLRCK SDTO 10pin Header JP5 SRC-MCLK PORT3 3 PORT3 D5V 3 JP2 ~ 4 3 DIT AK4121A +3.3V D5V Clock Generator PORT4 3 JP7~9 3 3 2 3 DIT (AK4114) Optical Output SW1 PDN SW2 SMUTE SW3 fsi-DIR SW4 CMODE SW5 fso Figure 1. AKD4121A Block Diagram *Circuit diagram and PCB layout are attached at the end of this manual. 2007/03 ASAHI KASEI [AKD4121A] Evaluation Board Manual Contents Operating Sequence --------------------------------------------------------------------------------------- p. 3 1. Jumper Setting for Power Supply: JP10(REG) 2. Power Supply Line Setting 3. DIP switch and Jumper pin Setting 4. Power-on DIP switch and Jumper pin Setting -----------------------------------------------------------------1. Setting of fsi (input fs) block -------------------------------------------------------------------------1-1. In case of using optical Input. 1-2. All clock are fed through the 10-pin port. 1-3. SDTI is fed through the 10-pin port and others are fed from the DIR(AK4112B). 2. Setting of fso (output fs) block ---------------------------------------------------------------------2-1. In case of providing clock from DIT. 2-2. In case of providing clock from 10pin PORT 2-2-1. AK4121A Master Mode. 2-2-2. AK4121A Slave Mode. 3. Bypass Mode --------------------------------------------------------------------------------------------------4. Setting of the others -------------------------------------------------------------------------------------4-1. De-emphasis filter. 4-2. Soft Mute. p. 4 p. 4 p. 9 p.22 p.22 Jumper List --------------------------------------------------------------------------------------------------- p.21 DIP switch list --------------------------------------------------------------------------------------------------- p.21 Toggle switch list --------------------------------------------------------------------------------------------- p.22 LED ---------------------------------------------------------------------------------------------------------------- p.22 --------------------------------------------------------------------------------------- p.23 Measurement Results Important Notice Circuit diagram PCB layout --------------------------------------------------------------------------------------------- p.29 2007/03 ASAHI KASEI [AKD4121A] Operating Sequence Please use the AKD4121A according to the following sequence. 1. Jumper Setting for Power Supply: JP10(3.3V) The JP10 (3.3V) selects power supply of the AKD4121A.(3.3V or 5V.) JACK : REG : Providing power supply voltage with 3.3V. Opticlal input is not avaible. Providing power supply voltage with 5V. (3.3V is supplied via regulator on board.) 2. Power Supply Line Setting Each supply line should be distributed directly from the power supply unit with low impedance connection. 5V or 3.3V : For power supply jack. 5V or 3.3V. (Power supply voltage is selectrd by JP10.) GND : Groung of the board. 0V. 3. DIP Switch and Jumper Pins Setting (refer next page) 4. Power-on(After power is on, SW1 should be reset by setting "L""H" once.) * The reset is done by SW1 during opertion. The AK4121A is powered down during SW1 is "L".The power down state is canceld by briging the SW1 to "H", at the same time, the AK4121A is reset. 2007/03 ASAHI KASEI [AKD4121A] DIP switch and Jumper pin setting 1. Setting of fsi (input fs) block 1-1. Optical input(PORT2) 1-1-a. Jumper setting Parts No. Setting JP1 (don't care) JP2 SHORT JP3 SHORT JP4 SHORT SW3-4 OFF X1 (don't care) Table 1. Jumper Setting (Refer following figures) JP1 OUT JP2 JP3 JP4 IN IMCLK IBICK SDTI ILRCK Figure 2. Jumper Setting 1-1-b. Audio Interface Format setting(IIS only) IDIF2 IDIF1 IDIF0 DIR-CM0 MCLK 1/2MCLK 12345 fsi-DIR SW3 Figure 3. DIP switch (SW3) setting 2007/03 ASAHI KASEI [AKD4121A] 1-2. All clock are fed through the 10-pin port 1-2-a. Jumper setting Parts No. Setting JP1 (don't care) JP2 OPEN JP3 OPEN JP4 OPEN SW3-4 (don't care) X1 (don't care) Table 2. Jumper Setting (Refer following figures) JP1 OUT JP2 JP3 JP4 IN IMCLK IBICK SDTI ILRCK Figure 4. Jumper Setting 1-2-b. Audio Interface Format setting SRC:AK4121A SW3-1 SW3-2 SW3-3 DIF2 DIF1 DIF0 0 0 0 16bit, Right justified 0 0 1 20bit, Right justified 0 1 0 Left justified 2 0 1 1 IS 1 0 0 24bit, Right justified Table 3. DIP switch (SW3) setting(Refer following figures) Audio Interface Format DIR-CM0 IDIF2 IDIF1 IDIF0 IDIF2 IDIF1 IDIF0 DIR-CM0 MCLK 12345 12345 fsi-DIR SW3 1/2MCLK fsi-DIR SW3 1/2MCLK 16bit, Right justified 20bit, Right justified MCLK 2007/03 ASAHI KASEI [AKD4121A] DIR-CM0 IDIF2 IDIF1 IDIF0 IDIF2 IDIF1 IDIF0 DIR-CM0 MCLK 12345 12345 fsi-DIR 1/2MCLK SW3 fsi-DIR SW3 1/2MCLK Left justified IDIF2 IDIF1 IDIF0 DIR-CM0 MCLK I2S 12345 fsi-DIR SW3 1/2MCLK 24bit, Right justified Figure 5. DIP switch Setting MCLK 2007/03 ASAHI KASEI [AKD4121A] 1-3. SDTI is fed through the 10-pin port and other clocks are fed from the AK4112B. The X1(X'tal) or external clock (via PORT1) can be used as the system clock of the input block. Please remove X1 when unsed. The system clock can be selected as 256fsi or 512fsi. This clock is not used for the AK4121A directly. 1-3-a. Jumper setting Setting OPEN: Using X'tal JP1 IN : System clock providing from 10port JP2 SHORT JP3 OPEN JP4 SHORT Table 4. DIP switch (SW3) setting(Refer following figures) JP1 OUT Parts No. JP2 JP3 JP4 IN IMCLK IBICK SDTI ILRCK Using X'tal setting JP1 OUT JP2 JP3 JP4 IN IMCLK IBICK SDTI ILRCK Using external clock Figure 6. Jumper Setting 2007/03 ASAHI KASEI [AKD4121A] DIP SW3 setting DIR-CM0 OCKS0 SW3-4 SW3-5 1 256fs ON 1/2 MCLK 2 512fs ON MCLK Table 5. DIR(AK4112B)'s clock setting(Refer following figures) No. X'tal / External clock (Max: 24.576MHz) DIR-CM0 IDIF2 IDIF1 IDIF0 IDIF2 IDIF1 IDIF0 DIR-CM0 MCLK 12345 12345 fsi-DIR SW3 1/2MCLK fsi-DIR 1/2MCLK SW3 MCLK:256fsi MCLK:512fsi Figure 7. DIP SW(SW3) setting(Refer following figures) 1-3-b Audio Interface Format setting Refer "1-2-b Refer Audio Interface Format setting" MCLK 2007/03 ASAHI KASEI [AKD4121A] 2. Setting of fso (output fs) block 2-1. Optical Output(PORT4). Clocks are fed from AK4114 (DIT). (IIS Master Mode only.) The X2(X'tal) or external clock via PORT3 can be used as the system clock of the output block. Please remove X2 when unused. 2-1-a. Jumper setting Parts No. JP5 Setting DIT OPEN: Using X'tal on board JP6 PORT3: Clock input form PORT3 (DIR: Using clock from DIR for Bypass Mode) JP7 SHORT JP8 SHORT JP9 SHORT JP11 OPEN Table 6. Jumper setting(Refer following figures) JP5 DIT JP6 PORT3 JP8 JP9 JP7 JP11 PORT3 DIR SRC-MCLK DIT-SOURCE OBICK OLRCK ILRCK 10pin Bypass Output Using on-board X'tal JP5 DIT JP6 PORT3 JP8 JP9 JP7 JP11 PORT3 DIR SRC-MCLK DIT-SOURCE OBICK OLRCK ILRCK 10pin Bypass Output Using External Clock Figure 8. Jumper setting 2007/03 ASAHI KASEI [AKD4121A] 2-1-b. DIP SW setting X2 or External Clock SW4-1 SW4-2 SW4-3 SW5-3 CMODE2 CMODE1 CMODE0 OCKS0 256fs L L L 1/2 MCLK 512fs L H L MCLK Table 7. Clock setting(Refer following figures) ODIF1 ODIF0 MCLK CMODE2 CMODE1 CMODE0 DEM1 CMODE2 CMODE1 CMODE0 DEM1 DEM0 12345 123 DEM0 12345 123 CMODE SW4 fso 1/2 MCLK SW5 CMODE SW4 256fso 512fso Figure 9. DIP switch setting ODIF1 ODIF0 MCLK fso 1/2 MCLK SW5 2007/03 ASAHI KASEI [AKD4121A] 2-2. Clocks are fed through the 10-pin port(PORT3) 2-2-1. AK4121A in Master Mode 2-2-1-a. Jumper setting Parts No. Setting JP5 PORT3 JP6 OPEN JP8 OPEN JP9 OPEN JP7 OPEN JP11 OPEN Table 8. Jumper setting(Refer following figures) JP5 DIT JP6 PORT3 JP8 JP9 JP7 JP11 PORT3 DIR SRC-MCLK DIT-SOURCE OBICK OLRCK SDTO 10pin Bypass Output Using X'tal on-board Figure 10. Jumper setting 2-2-1-b. Audio Interface Format Mod e 0 1 2 3 SW4-1 CMODE2 L L L L SW4-2 SW4-3 MCLK Master/Slave (Output Port) CMODE1 CMODE0 L L 256fso (fso~96kHz) Master L H 384fso (fso~96kHz) Master H L 512fso (fso~48kHz) Master H H 768fso (fso~48kHz) Master Table 9. AK4121A System Clock setting 2007/03 ASAHI KASEI [AKD4121A] Mode 0 1 2 3 SW5-1 ODIF1 L L H H SW5-2 SDTO Format OBICK (Slave) OBICK (Master) ODIF0 L 16bit LSB Justified 64fs 64fs H 20bit LSB Justified 64fs 64fs L 20bit MSB Justified 64fs 40fs 2 H 20bit I S Compatible 64fs 40fs or 32fs Table 10. AK4121A Audio Interface Format setting ODIF1 ODIF0 MCLK ODIF1 ODIF0 MCLK 123 fso 1/2 MCLK SW5 123 fso 1/2 MCLK SW5 16bit, Right justified ODIF1 ODIF0 MCLK 20bit, Right justified ODIF1 ODIF0 MCLK 123 fso 1/2 MCLK SW5 123 fso 1/2 MCLK SW5 Left justified Figure 11. DIP switch setting I2S 2007/03 ASAHI KASEI [AKD4121A] 2-2-2. AK4121A in Slave Mode 2-2-2-a. Jumper setting Parts No. Setting JP5 PORT3 JP6 OPEN JP8 OPEN JP9 OPEN JP7 OPEN JP11 OPEN Table 11. Jumper setting(Refer following figures) JP5 DIT JP6 PORT3 JP8 JP9 JP7 JP11 PORT3 DIR SRC-MCLK DIT-SOURCE OBICK OLRCK SDTO 10pin Bypass Output Using External Clock Figure 12. Jumper setting 2-2-2-b. Audio Interface Format Mod e 4 SW4-1 CMODE2 H SW4-2 SW4-3 MCLK Master/Slave (Output Port) CMODE1 CMODE0 L L Not used. Set to DVSS Slave Table 12. AK4121A System Clock setting CMODE2 CMODE1 CMODE0 DEM1 DEM0 12345 CMODE SW4 Figure 13. DIP switch setting 2007/03 ASAHI KASEI [AKD4121A] Mode 0 1 2 3 SW5-1 ODIF1 L L H H SW5-2 SDTO Format OBICK (Slave) OBICK (Master) ODIF0 L 16bit LSB Justified 64fs 64fs H 20bit LSB Justified 64fs 64fs L 20bit MSB Justified 64fs 40fs H 20bit I2S Compatible 64fs 40fs or 32fs Table 13. AK4121A Audio Interface Format setting ODIF1 ODIF0 MCLK ODIF1 ODIF0 MCLK 123 fso 1/2 MCLK SW5 123 fso 1/2 MCLK SW5 16bit, Right justified ODIF1 ODIF0 MCLK 20bit, Right justified ODIF1 ODIF0 MCLK 123 fso 1/2 MCLK SW5 123 fso 1/2 MCLK SW5 Left justified Figure 14. DIP switch setting I2S 2007/03 ASAHI KASEI [AKD4121A] 3. Bypass Mode In case of Bypass Mode, please set DIP switch (SW3) as follows. Mod e 7 SW4-1 CMODE2 H SW4-2 SW4-3 MCLK Master/Slave (Output Port) CMODE1 CMODE0 H H Not used. Set to DVSS Master(Bypass) Table 14. AK4121A System Clock setting CMODE2 CMODE1 CMODE0 DEM1 12345 CMODE SW4 Figure 13. DIP switch setting 3-1. Setting of input block 3-1-1. Optical Input(PORT2) 3-1-1-a. Jumper setting Parts No. Setting JP1 OUT JP2 SHORT JP3 SHORT JP4 SHORT X1 (don't care) Table 15. Jumper setting(Refer following figures) JP1 OUT JP2 JP3 DEM0 JP4 IN IMCLK IBICK SDTI ILRCK Figure 14. Jumper setting 3-1-1-b. Audio Interface Format setting (IIS only) IDIF2 IDIF1 IDIF0 DIR-CM0 MCLK 1/2MCLK 12345 fsi-DIR SW3 Figure 15. DIP switch (SW3) setting 2007/03 ASAHI KASEI [AKD4121A] 3-1-2. All clock are fed through the 10-pin port 3-1-2-a. Jumper setting Parts No. Setting JP1 OUT JP2 OPEN JP3 OPEN JP4 OPEN X1 (don't care) Table 16. Jumper setting(Refer following figures) JP1 OUT JP2 JP3 JP4 IN IMCLK IBICK SDTI ILRCK Figure 16. Jumper setting 3-1-2-b. Audio Interface Format SRC:AK4121A SW3-1 SW3-2 DIF2 DIF1 0 0 16bit, Right justified 0 0 20bit, Right justified 0 1 Left justified 2 0 1 IS 1 0 24bit, Right justified Table 17. DIP switch (SW3) setting Audio Interface Format DIR-CM0 SW3-3 DIF0 0 1 0 1 0 DIR-CM0 IDIF2 IDIF1 IDIF0 IDIF2 IDIF1 IDIF0 MCLK 12345 12345 fsi-DIR SW3 1/2MCLK fsi-DIR SW3 1/2MCLK 16bit, Right justified 20bit, Right justified MCLK 2007/03 ASAHI KASEI [AKD4121A] DIR-CM0 IDIF2 IDIF1 IDIF0 IDIF2 IDIF1 IDIF0 DIR-CM0 MCLK 12345 12345 fsi-DIR SW3 1/2MCLK fsi-DIR SW3 1/2MCLK Left justified IDIF2 IDIF1 IDIF0 DIR-CM0 MCLK I2S 12345 fsi-DIR SW3 1/2MCLK 24bit, Right justified Figure 17. DIP switch (SW3) setting MCLK 2007/03 ASAHI KASEI [AKD4121A] 3-2. Setting of output block 3-2-1. Optical Output(PORT4). Clock are fed from AK4114 (DIT). (IIS Master Mode only.) 3-2-1-a. Jumper setting Parts No. JP8 JP9 JP7 JP5 JP6 JP11 X2 Setting SHORT SHORT SHORT (don't care) DIR OPEN Remove Table 18. Jumper setting JP5 DIT JP6 PORT3 JP8 JP9 JP7 JP11 PORT3 DIR SRC-MCLK (don't care) DIT-SOURCE OBICK OLRCK ILRCK 10pin Bypass Output Figure 18. Jumper setting No. 1 2 X1or External Clock (PORT1) (Max: 24.576MHz) DIP SW3 setting OCKS0 SW3-5 256fs 1/2 MCLK 512fs MCLK Table 19. DIR/DIT Clock setting ODIF1 ODIF0 MCLK DIP SW5 setting OCKS0 SW5-3 1/2 MCLK MCLK 123 123 fso 1/2 MCLK SW5 MCLK:256fso MCLK:512fso Figure 19. DIP switch setting ODIF1 ODIF0 MCLK fso 1/2 MCLK SW5 2007/03 ASAHI KASEI [AKD4121A] 3-2-2. Clock are fed through the 10-pin port(PORT3) 3-2-2-a. Jumper setting parts No. JP8 JP9 JP7 JP5 JP6 JP11 X2 setting OPEN OPEN OPEN (don't care) OPEN OPEN (don't care) Table20. Jumper setting JP5 DIT JP6 PORT3 JP8 JP9 JP7 JP11 PORT3 DIR SRC-MCLK (don't care) DIT-SOURCE OBICK OLRCK ILRCK 10pin Bypass Output Figure 20. Jumper setting 3-2-2-b. Audio Interface Format Mode 0 1 2 3 SW5-1 SW5-2 SDTO Format OBICK (Master) ODIF1 ODIF0 L L 16bit LSB Justified 64fs L H 20bit LSB Justified 64fs H L 20bit MSB Justified 64fs H H 20bit I2S Compatible 64fs Table 21. AK4121A Audio Interface Format setting ODIF1 ODIF0 MCLK ODIF1 ODIF0 MCLK 123 fso 1/2 MCLK SW5 123 fso 1/2 MCLK SW5 16bit, Right justified ODIF1 ODIF0 MCLK 20bit, Right justified ODIF1 ODIF0 MCLK 123 fso 1/2 MCLK SW5 123 fso 1/2 MCLK SW5 Left justified Figure 21. DIP switch setting I2S 2007/03 ASAHI KASEI [AKD4121A] 4. The other setting 4-1. De-emphasis filter SW4-4 and SW4-5 control the de-emphasis filter. Mode 0 1 2 3 SW4-4 SW4-5 De-emphasis filter DEM1 DEM0 L L 44.1kHz L H OFF H L 48kHz H H 32kHz Table22. De-emphasis filter setting 4-2. Soft Mute Toggle switch SW2 controls the soft mute. Mode SW2 Soft Mute SMUTE 0 OFF OFF 1 ON ON Table23. Soft Mute setting 2007/03 ASAHI KASEI [AKD4121A] Jumper List No. Jumper Name Default Function Power supply select for AKD4121A REG : Power supply for AKD4121A is 5V. The VDD(3.3V) of AK4121A is supplied from the regulator. JACK : Power supply for AKD4121A is 3.3V. Optical link is NOT available. MCLK select for fsi port. IN on-board X'tal(X1). OUT : external clock. Input select for fsi port. Open : PORT2 clock. Short : DIR clock. MCLK select for fso port. DIT : DIT (AK4114) clock. PORT3 : external clock. DIT-SORUCE select. Open on-board X'tal(X2). DIR : DIR(AK4112B) clock. PORT3: PORT3 clock. Bypass mode select. Short : Setting for bypass mode. Open : for other modes. Output select for fso port. Open : Use only PORT3. Not use DIT (AK4114) clock. Short : Use DIT clock. 10 3.3V REG 1 IMCLK IBICK, ILRCK, SDTI SRC-MCLK IN 2, 3, 4 Short 5 DIT 6 DIT-SORUCE Open 11 10 pin Bypass Output OBICK, OLRCK, SDTO Open 7, 8, 9 Short 2007/03 ASAHI KASEI [AKD4121A] DIP switch list SW3(fsi-DIR) No. Switch Name 1, 2, 3 IDIF2, 1, 0 4 DIR-CM0 MCLK 1/2MCLK Default OFF, ON, ON (IIS) OFF (Optical) 5 MCLK Function fsi data format. Refer Table 3. DIR clock mode. ON : X'tal mode OFF : Optical mode DIR MCLK select. MCLK : 512fs 1/2MCLK : 256fs SW4(CMODE) No. Switch Name 1, 2, 3 4, 5 CMODE2, 1, 0 DEM1, 0 Default Function OFF, ON, OFF System clock selects. Refer Table 9, Table 12 and Table 14 (Master, 512fso) OFF, ON (off) De-emphasis control. Refer Table 12. SW5(fso) No. Switch Name 1,2 ODIF1, 0 3 MCLK 1/2MCLK Default ON, ON (IIS) MCLK Function fso data format. Refer Table 10. DIT MCLK select. MCLK : 512fs 1/2MCLK : 256fs Toggle switch list (SW1 and SW2) SW1 is reset switch for AK4121A, AK4112B(DIR) and AK4114(DIT). Set to "H" during Normal operation. Bring to "L" once after the power is supplied. SW2 is SMUTE control switch. Refer Table 23. LED Bright when ERF pin of AK4112B goes to "H". This indicates the UNLOCK state, etc. (Refer AK4112B datasheet). 2007/03 ASAHI KASEI [AKD4121A] MEASUREMENT RESULTS [Measurement Conditions] Measurement unit VDD TVDD Input Data Output Data Interface : : : : : : Audio Precision System Two Cascade 3.3V 5V 44.1kHz, 20bit, I2S 48kHz; 20bit, I2S Optical fiber Parameter THD+N DR DR Input signal 1kHz, 0dB 1kHz, -60dB 1kHz, -60dB Measurement filter fs/2 fs/2 fs/2, A-weighted Results -113.5 dB 115.2 dB 117.6 dB 2007/03 ASAHI KASEI [AKD4121A] AKM AK4121 AK4121A SRC FFT (fsi=44.1kHz, fso=48kHz; fin=1kHz, 0dBFS input) FFT points 16384, Avg.=8, Window=Equiripple +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k AKM AK4121 AK4121A SRC FFT (fsi=44.1kHz, fso=48kHz; fsi=1kHz, -60dBFS input) FFT points 16384, Avg.=8, Window=Equiripple +0 -20 -40 -60 d B F S -80 -100 -120 -140 -160 -180 20 50 100 200 500 Hz 1k 2k 5k 10k 20k 2007/03 ASAHI KASEI [AKD4121A] AKM -90 -92.5 -95 -97.5 -100 -102.5 -105 d B F S -107.5 -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130 20 50 AK4121A SRC THD+N vs. Input Frequency (fsi=44.1kHz, fso=48kHz; 0dBFS input) AK4121 100 200 500 Hz 1k 2k 5k 10k 20k AKM -90 -92.5 -95 -97.5 -100 -102.5 -105 d B F S -107.5 -110 -112.5 -115 -117.5 -120 -122.5 -125 -127.5 -130 20 50 AK4121A SRC THD+N vs. Input Frequency (fsi=44.1kHz, fso=48kHz; -60dBFS input) AK4121 100 200 500 Hz 1k 2k 5k 10k 20k 2007/03 ASAHI KASEI [AKD4121A] AKM -100 -102 -104 -106 -108 -110 -112 d B F S -114 -116 -118 -120 -122 -124 -126 -128 -130 -130 -120 AK4121 AK4121A SRC THD+N vs. Input Level (fsi=44.1kHz, fso=48kHz; fin=1kHz) -110 -100 -90 -80 -70 dBFS -60 -50 -40 -30 -20 -10 +0 AKM +0 -10 -20 -30 -40 -50 d B F S -60 -70 -80 -90 -100 -110 -120 -130 -140 -140 AK4121A SRC Linearity (fsi=44.1kHz, fso=48kHz; fin=1kHz) AK4121 -130 -120 -110 -100 -90 -80 -70 dBFS -60 -50 -40 -30 -20 -10 +0 2007/03 ASAHI KASEI [AKD4121A] AKM -0.15 AK4121 AK4121A SR C Frequency Response (fsi=44.1kHz, fso=48kHz, 0dBFS input) -0.16 -0.17 -0.18 -0.19 d B F S -0.2 -0.21 -0.22 -0.23 -0.24 -0.25 2k 4k 6k 8k 10k 12k Hz 14k 16k 18k 20k 22k 24k AK4121A Frequency Response (Blue:fsi=48kHz, Red:fsi=96kHz) AK4121 VDD=3.3V, TVDD=5.0V, fso=48kHz -0 -1 -2 fsi=48kHz -3 -4 -5 d B F S -6 -7 -8 -9 -10 -11 -12 -13 -14 2k 4k 6k 8k 10k 12k Hz 14k 16k 18k 20k 22k fsi=96kHz 2007/03 ASAHI KASEI [AKD4121A] AKM -0 -2 -4 -6 -8 d B F S -10 -12 -14 -16 -18 -20 -22 2k AK4121A Frequency Response (Blue:fsi=44.1kHz, Red:fsi=48kHz, Gray:fsi=96kHz) AK4121 VDD=3.3V, TVDD=5.0V, fso=44.1kHz fsi=44.1kHz fsi=48kHz fsi=96kHz 4k 6k 8k 10k Hz 12k 14k 16k 18k 20k 22k 2007/03 ASAHI KASEI [AKD4121A] Revision History Date (YY/MM/DD) 07/03/22 Manual Revision KM088800 Board Revision 0 Reason First Edition Contents IMPORTANT NOTICE * These products and their specifications are subject to change without Notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification. 2007/03 5 4 3 2 1 5V or 3.3V JP10 3.3V 3 D L1 10u T1 TA48M033F GND 1 OUT IN 2 D JACK +3V 1 2 JP1 2 PORT1 IBICK ILRCK SDTI 220k 220k 220k R21 R22 R23 R24 100 100 100 100 IMCLK IBICK ILRCK SDTI 1 2 3 4 5 10 9 8 7 6 REG C29 0.1u + OUT IN C30 47u D5V + 1 3 IMCLK C31 47u C32 0.1u C1 0.1u 3 D5V R29 R30 R31 R1 10k R2 +3V short C 1 C2 10u DVDD CM0/CDTO 28 + DIR-CM0 C C3 0.1u 2 DVSS CM1/CDTI 27 D5V C6 open D5V PDN 2 5 XTI D1 HSU119 R3 10k U5A 1 2 3 U5B 4 C7 open 7 PDN DAUX 22 1 L 3 1 H SW1 PDN 2 74HC14 74HC14 C8 0.1u +3V C9 10u B + L2 47u D5V PORT2 6 5 6 5 GND VCC GND OUT 4 3 2 1 + R5 11 RX1 ERF 18 5 470 D5V 12 RX2/DIF0 FS96 17 C11 0.1u C12 10u DIR1 A 5 4 + C4 10u C5 0.1u 3 TVDD OCKS1/CCLK 26 DIR-OCKS1 4 V/TX OCKS0/CSN 25 U1 MCKO1 24 MCLK12 X1 22.5792MHz 6 XTO MCKO2 23 R4 8 R AK4112B BICK 21 9 AVDD SDTO 20 BCK12 JP2 IBICK JP3 SDTI JP4 ILRCK IBICK 18k SDTO12 C10 0.1u 10 AVSS LRCK 19 SDTI B LRCK12 ILRCK U5C 6 R6 1k LED1 ERF 74HC14 13 RX3/DIF1 P/S 16 D5V 14 RX4/DIF2 AUTO 15 A Title Size A3 Date: 3 2 Document Number AKD4121A AK4112B Tuesday, March 20, 2007 Sheet 1 Rev 0 1 of 3 5 4 3 2 1 OMCLK 3 D 10PIN-PORT3 OMCLK OBICK OLRCK SDTO D5V 220k 220k 220k R25 R26 R27 R28 R8 100 100 100 100 10k 1 2 3 4 5 PORT3 10 9 8 7 6 D PORT3 DIT 1 JP5 2 SRC-MCLK SRC-MCLK DIT-MCLK JP11 R32 R33 10pin Bypass DIR Output (OPEN X'tal) R34 MCLK12 1 DIR R7 +3V short C13 10u + JP6 2 PORT3 3 DIT-SOURCE C14 0.1u C15 XTI 2 C16 X2 + C OPEN C17 OPEN DIT XTO 48 47 46 45 44 43 42 41 40 39 38 37 0.47u C R9 18k 24.576 MHz 1 D5V +3V 1 2 3 4 5 6 7 8 9 10 11 12 RX3 AVSS RX2 TEST1 RX1 AVSS RX0 AVSS VCOM R AVDD INT1 TVDD DVSS TX0 TX1 BOUT COUT UOUT VOUT DVDD DVSS MCKO1 LRCK IPS0/RX4 AVSS DIF0/RX5 TEST2 DIF1/RX6 AVSS DIF2/RX7 IPS1/IIC P/SN XTL0 XTL1 VIN U3 AK4114 INT0 OCKS0/CSN OCKS1/CCLK CM1/CDTI CM0/CDTO PDN XTI XTO DAUX MCKO2 BICK SDTO 36 35 34 33 32 31 30 29 28 27 26 25 DIT-OCKS1 D5V PDN XTI XTO SDTI14 BCK14 LRCK14 JP7 JP8 JP9 SDTO SDTO OBICK OBICK OLRCK OLRCK SDTO OBICK OLRCK B 13 14 15 16 17 18 19 20 21 22 23 24 B DIT-MCLK C19 0.1u + C20 0.1u + C18 10u C22 10u D5V PORT4 5 6 5 6 IN VCC IF GND 4 3 2 1 OPT D5V R10 1k C21 0.1u TOTX176 A +3V A Title Size A3 Date: 5 4 3 2 Document Number AKD4121A AK4114 Tuesday, March 20, 2007 Sheet 1 Rev 0 2 of 3 5 4 3 2 1 R11 560 D 1 FLIT VDD 24 +3V C24 0.1u + D D5V C25 4.7u C26 1.0n 2 AVSS DVSS 23 C23 10u U4 R12 10k R13 9 C27 0.1u TVDD 22 PDN U2D 8 3 PDN D5V 4 SMUTE MCLK 21 SRC-MCLK 3 1 ON 1k OFF + 74HC14 DEM0 C28 1u DEM1 6 DEM1 OBICK 19 5 DEM0 OLRCK 20 SW2 SMUTE 2 OLRCK OBICK AK4121A ILRCK 7 ILRCK SDTO 18 SDTO C IBICK 8 IBICK ODIF1 17 ODIF1 C SDTI 9 SDTI ODIF0 16 ODIF0 IDIF0 10 IDIF0 CMODE2 15 CMODE2 IDIF1 11 IDIF1 CMODE1 14 CMODE1 IDIF2 12 IDIF2 CM0DE0 13 CMODE0 D5V B SW4 SW3 IDIF2 IDIF1 IDIF0 DIR-CM0 MCLK 1 2 3 4 5 10 9 8 7 6 10 9 8 7 6 1 2 3 4 5 B CMODE2 CMODE1 CMODE0 DEM1 DEM0 CMODE2 CMODE1 CMODE0 DEM1 DEM0 R35 R36 R37 47k 47k 47k ODIF1 1 ODIF0 2 MCLK 3 SW5 6 5 4 fso 1/2MCLK 1/2MCLK CMODE R43 R44 R45 R46 R47 IDIF2 IDIF1 IDIF0 DIR-CM0 DIR-OCKS1 47k 47k 47k 47k 47k ODIF1 ODIF0 DIT-OCKS1 fsi-DIR R38 R39 R40 R41 R42 47k 47k 47k 47k 47k A A Title Size A3 Date: 5 4 3 2 Document Number AKD4121A AK4121A Thursday, March 22, 2007 Sheet 1 Rev 0 3 of 3 |
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