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ASAHI KASEI
[AKD5384]
AKD5384
AK5384 Evaluation Board Rev.A
GENERAL DESCRIPTION AKD5384 is an evaluation board for the digital audio 24bit 96kHz 4ch A/D converter, AK5384. The AKD5384 includes the input circuit and also has a digital interface transmitter. Further, the AKD5384 can achieve the interface with digital audio systems via opt-connector. Ordering guide
AKD5384 --AK5384 Evaluation Board
FUNCTION * DIT with optical output * BNC connector for an external clock input
AVDD,DVDD AGND,DGND TVDD Opt Out LIN1/2 AK4101 (DIT) Opt Out
RIN1/2
Input Buffer
AK5384
Clock Generator
DSP Data 10pin Header
Figure 1. AKD5384 Block Diagram * Circuit diagram and PCB layout are attached at the end of this manual.
-1-
2005/10
ASAHI KASEI
[AKD5384]
Operation sequence
1) Set up the power supplies lines. [AVDD] (red) = 4.75 5.25V [DVDD] (red) = 4.75 5.25V [TVDD] (orange) = 3.0 5.25V [+15V] (green) = +15V [-15V] (blue) = -15V [VCC] (red) = 5V [AGND] (black) = 0V [DGND] (black) = 0V
: for AVDD of AK5384 (typ. 5.0V) : for DVDD of AK5384 (typ. 5.0V) : for TVDD of AK5384 (typ. 5.0V) : for Op-amp : for Op-amp : for logic : for analog ground : for logic ground
Each supply line should be distributed from the power supply unit. 2) Set up the evaluation mode, jumper pins and DIP switches. (See the followings.) 3) Power on. The AK5384 and AK4101 should be reset once bringing SW1 = "L" upon power-up. Note: When the AK5384 is TDM mode, the AK4101 does not support TDM mode. So, PORT1 (DIT1) and PORT2 (DIT2) are not used. PORT3 (DSP) should be used.
Evaluation mode
(1) Slave Mode (1-1) A/D evaluation using DIT function of AK4101 PORT1 (DIT1) and PORT2 (DIT2) are used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX176). It is possible to connect AKM's D/A converter evaluation boards on the digital-amplifier, which equips DIR input. Nothing should be connected to PORT3 (DSP). In case of using external clock through a BNC connector (J5), select EXT on JP8 (CLK) and short JP5 (XTE) and open JP10 (EXT).
JP3 BICK JP4 LRCK JP5 XTE JP8 CLK JP10 EXT
XTL
EXT
(1-2) Feeding all clocks from PORT3 (DSP) Under the following set-up, all external clocks (MCLK, BICK, LRCK) can be fed through PORT3 (DSP). The A/D converted data is output from SDTO1/SDTO2 of PORT3 (DSP). Also, the A/D converted data is output through optical connector (TOTX176).
JP3 BICK JP4 LRCK JP5 XTE JP8 CLK JP10 EXT
XTL
EXT
-2-
2005/10
ASAHI KASEI
[AKD5384]
(2) Master Mode (2-1) A/D evaluation using DIT function of AK4101 PORT1 (DIT1) and PORT2 (DIT2) are used. DIT generates audio bi-phase signal from received data and which is output through optical connector (TOTX176). It is possible to connect AKM's D/A converter evaluation boards on the digital-amplifier, which equips DIR input. Nothing should be connected to PORT3 (DSP). In case of using external clock through a BNC connector (J5), select EXT on JP8 (CLK) and short JP5 (XTE) and open JP10 (EXT).
JP3 BICK JP4 LRCK JP5 XTE JP8 CLK JP10 EXT
XTL
EXT
Other jumper pins set up
1. JP1 (GND) : Analog ground and Digital ground OPEN : Separated. SHORT : Common. (The connector "DGND" can be open.) 2. JP2 (AVDD) : Select AVDD for AK5384 AVDD : Supply from AVDD connector REG : Supply from regulator. AVDD connector should be supplied +15V. 3. JP6 (BCFS) : Select BICK frequency 64 : In case of MCLK=256fs/512fs/768fs 128 : In case of MCLK=384fs or BICK frequency of TDM128 mode 256 : BICK frequency of TDM256 mode 4. JP7 (MCLK) : Supply MCLK frequency for 74HC4040 256 : In case of MCLK=256fs 512 : In case of MCLK=512fs 384/768 : In case of MCLK=384fs/768fs 5. JP9 (LRFS) : Select LRCK frequency 256 : In case of MCLK=256fs/512fs/768fs 384 : In case of MCLK=384fs
-3-
2005/10
ASAHI KASEI
[AKD5384]
Clock Setting
Mode fs 8kHz MCLK JP6(BCFS) JP7(MCLK) 256fs = 2.048MHz 64 256 384fs = 3.072MHz 128 384/768 512fs = 4.096MHz 64 512 768fs = 6.144MHz 64 384/768 256fs = 8.192MHz 64 256 384fs = 12.288MHz 128 384/768 512fs = 16.384MHz 64 512 768fs = 24.576MHz 64 384/768 256fs = 11.2896MHz 64 256 384fs = 16.9344MHz 128 384/768 512fs = 22.5792MHz 64 512 768fs = 33.8688MHz 64 384/768 256fs = 12.288MHz 64 256 384fs = 18.432MHz 128 384/768 512fs = 24.576MHz 64 512 768fs = 36.864MHz 64 384/768 256fs = 22.5792MHz 64 256 384fs = 33.8688MHz 128 384/768 256fs = 24.576MHz 64 256 384fs = 36.864MHz 128 384/768 512fs = 4.096MHz 256 512 512fs = 16.384MHz 256 512 512fs = 22.5792MHz 256 512 512fs = 24.576MHz 256 512 256fs = 2.048MHz 128 256 512fs = 4.096MHz 128 512 256fs = 8.192MHz 128 256 512fs = 16.384MHz 128 512 256fs = 11.2896MHz 128 256 512fs = 22.5792MHz 128 512 256fs = 12.288MHz 128 256 512fs = 24.576MHz 128 512 256fs = 22.5792MHz 128 256 256fs = 24.576MHz 128 256 Table 1. Clock Setting JP9(LRFS) 256 384 256 256 256 384 256 256 256 384 256 256 256 384 256 256 256 384 256 384 256 256 256 256 256 256 256 256 256 256 256 256 256 256
32kHz
Normal
44.1kHz
48kHz
Default
88.2kHz 96kHz 8kHz 32kHz 44.1kHz 48kHz 8kHz 32kHz TDM128 44.1kHz 48kHz 88.2kHz 96kHz
TDM256
-4-
2005/10
ASAHI KASEI
[AKD5384]
DIP Switch set up
[SW2] (MODE): Setting the evaluation mode for AK5384 and AK4101 ON is "H", OFF is "L". No. 1 2 3 4 5 6 7 Name DIF TDM1 TDM0 M/S CKS CKS1 CKS0 OFF ("L") MSB justified ON ("H") I2S Compatible Default OFF ("L") OFF ("L") OFF ("L") OFF ("L") ON ("H") ON ("H") OFF ("L")
See Table 3 Slave mode MCLK = 256fs Master mode MCLK = 512fs
See Table 4 Table 2. Mode Setting
TDM1 L L H H
TDM0 Mode BICK L Normal 48 128fs H TDM256 256fs L N/A N/A H TDM128 128fs Table 3. Mode Setting of AK5384
Default
Mode 0 1 2 3
CKS1 CKS0 MCLK fs L L 256fs 96kHz L H N/A N/A H L 512fs 48kHz H H 384fs 48kHz Table 4. MCLK Frequency Setting of AK4101
Default
Note: AK4101 does not support MCLK=768fs.
The function of the toggle SW
Upper-side is "H" and lower-side is "L". [SW1] (PDN): Resets the AK5384 and AK4101. Keep "H" during normal operation.
-5-
2005/10
ASAHI KASEI
[AKD5384]
Input Circuit
Analog signal is input to LIN1-2/RIN1-2 pins via J1 J4 connectors. R11, R18, R25 and R32 should be changed depending on the output impedance of signal source.
R6 4.7k R7 5.1k OP_AMP18 4 8 4 8 4 8
OP_AMP18 4 8 4 8 4 8
R10 330 LIN1+
C18 10u +
5
U2B NJM5532
U2A NJM5532
OP_AMP1+
R12 330 LIN1-
C28 10u +
R13 4.7k
R14 5.1k OP_AMP1R16 4.7k
2 3
OP_AMP1R17 330 RIN1+ C30 10u +
6 5 1
U3B NJM5532
U3A NJM5532
OP_AMP1+
R19 330 RIN1-
C31 10u +
R20 4.7k
R21 5.1k OP_AMP1R23 4.7k
2 3
OP_AMP1R24 330 LIN2+ C33 10u +
6 5 1
U4B NJM5532
U4A NJM5532
OP_AMP1+
R26 330 LIN2-
C43 10u +
R27 4.7k
R28 5.1k OP_AMP1R30 4.7k
2 3
OP_AMP1R31 330 RIN2+ C45 10u +
6 5 1
U5B NJM5532
U5A NJM5532
OP_AMP1+
R33 330 RIN2-
C46 10u +
Figure 2. LIN1-2/RIN1-2 Input circuits
* AKM assumes no responsibility for the trouble when using the circuit examples.
-6-
+
7
+
+
7
+
+
7
+
+
7
3
+
6
R9 4.7k
4
2
R8 10k
C17 22u
1
4
J1 LIN1
R11 560 OP_AMP1+
+ + + +
R15 10k
C29 22u
J2 RIN1
R18 560 OP_AMP1+
R22 10k
C32 22u
J3 LIN2
R25 560 OP_AMP1+
R29 10k
C44 22u
J4 RIN2
R32 560 OP_AMP1+
2005/10
ASAHI KASEI
[AKD5384]
MEASUREMENT RESULTS
[Measurement condition] * Measurement unit * MCLK * BICK * fs * Bit * Power Supply * Interface * Temperature [Measurement Results] Parameter ADC Analog Input Characteristics S/(N+D) (fs=48kHz, -1dBFS) (fs=96kHz, -1dBFS) D-Range (fs=48kHz, -60dBFS, A-weighted) (fs=96kHz, -60dBFS) S/N (fs=48kHz, A-weighted) (fs=96kHz) Interchannel Isolation Result LIN1 / RIN1 LIN2 / RIN2 100.8 / 100.7 96.4 / 95.1 107.6 / 107.5 102.4 / 102.4 107.6 / 107.5 102.4 / 102.4 119.5 / 122.4 101.3 / 101.2 95.4 / 94.4 107.6 / 107.4 102.4 / 102.4 107.6 / 107.4 102.4 / 102.4 120.5 / 124.0 Unit
: Audio Precision, System Two Cascade : 256fs : 64fs : 48kHz, 96kHz : 24bit : AVDD = DVDD = TVDD = 5.0V : DIT : Room
dB dB dB dB dB dB dB
-7-
2005/10
ASAHI KASEI
[AKD5384]
[ADC Plot : fs=48kHz]
AKM
-90 -91 -92 -93 -94 -95 -96 -97 -98 d B F S -99 -100 -101 -102 -103 -104 -105 -106 -107 -108 -109 -110 -120 -110 -100 -90
AK5384 THD+N vs. Input Level AVDD=DVDD=TVDD=5.0V, fs=48kHz, fin=1kHz
-80
-70
-60 dBr
-50
-40
-30
-20
-10
+0
Figure 1. THD+N vs. Input Level
AKM
-90 -91 -92 -93 -94 -95 -96 -97 -98 d B F S -99 -100 -101 -102 -103 -104 -105 -106 -107 -108 -109 -110 20 50 100
AK5384 THD+N vs. Input Frequency AVDD=DVDD=TVDD=5.0V, fs=48kHz, Input=-1.0dBr
200
500 Hz
1k
2k
5k
10k
20k
Figure 2. THD+N vs. Input Frequency
-8-
2005/10
ASAHI KASEI
[AKD5384]
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -140
AK5384 Linearity AVDD=DVDD=TVDD=5.0V, fs=48kHz, fin=1kHz
-130
-120
-110
-100
-90
-80
-70 dBr
-60
-50
-40
-30
-20
-10
+0
Figure 3. Linearity
AKM
-0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 d B F S -0.9 -1 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -1.9 -2 20 50 100
AK5384 Frequency Response AVDD=DVDD=TVDD=5.0V, fs=48kHz, Input=-1.0dBr
200
500 Hz
1k
2k
5k
10k
20k
Figure 4. Frequency Response
-9-
2005/10
ASAHI KASEI
[AKD5384]
AKM
-80 -85 -90 -95 -100 -105 -110 -115 d B -120 -125 -130 -135 -140 -145 -150 -155 -160 20 50 100
AK5384 Crosstalk AVDD=DVDD=TVDD=5.0V, fs=48kHz, Input=-1.0dBr
200
500 Hz
1k
2k
5k
10k
20k
Figure 5. Crosstalk
AKM
+0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50
AK5384 FFT Plot AVDD=DVDD=TVDD=5.0V, fs=48kHz, Input=-1.0dBr, fin=1kHz
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 6. FFT Plot
- 10 -
2005/10
ASAHI KASEI
[AKD5384]
AKM
+0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50
AK5384 FFT Plot AVDD=DVDD=TVDD=5.0V, fs=48kHz, Input=-60dBr, fin=1kHz
100
200
500 Hz
1k
2k
5k
10k
20k
Figure 7. FFT Plot
AKM
+0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100
AK5384 FFT Plot AVDD=DVDD=TVDD=5.0V, fs=48kHz, fin=None
200
500 Hz
1k
2k
5k
10k
20k
Figure 8. FFT Plot
- 11 -
2005/10
ASAHI KASEI
[AKD5384]
[ADC Plot : fs=96kHz]
AKM
-90 -91 -92 -93 -94 -95 -96 -97 -98 d B F S -99 -100 -101 -102 -103 -104 -105 -106 -107 -108 -109 -110 -140 -130 -120 -110
AK5384 THD+N vs. Input Level AVDD=DVDD=TVDD=5.0V, fs=96kHz, fin=1kHz
-100
-90
-80
-70 dBr
-60
-50
-40
-30
-20
-10
+0
Figure 9. THD+N vs. Input Level
AKM
-90 -91 -92 -93 -94 -95 -96 -97 -98 d B F S -99 -100 -101 -102 -103 -104 -105 -106 -107 -108 -109 -110 20 50 100
AK5384 THD+N vs. Input Frequency AVDD=DVDD=TVDD=5.0V, fs=96kHz, Input=-1.0dBr
200
500
1k Hz
2k
5k
10k
20k
40k
Figure 10. THD+N vs. Input Frequency
- 12 -
2005/10
ASAHI KASEI
[AKD5384]
AKM
+0 -10 -20 -30 -40 -50 -60 d B F S -70 -80 -90 -100 -110 -120 -130 -140 -140
AK5384 Linearity AVDD=DVDD=TVDD=5.0V, fs=96kHz, fin=1kHz
-130
-120
-110
-100
-90
-80
-70 dBr
-60
-50
-40
-30
-20
-10
+0
Figure 11. Linearity
AKM
-0 -0.1 -0.2 -0.3 -0.4 -0.5 -0.6 -0.7 -0.8 d B F S -0.9 -1 -1.1 -1.2 -1.3 -1.4 -1.5 -1.6 -1.7 -1.8 -1.9 -2 20 50 100
AK5384 Frequency Response AVDD=DVDD=TVDD=5.0V, fs=96kHz, Input=-1.0dBr
200
500
1k Hz
2k
5k
10k
20k
40k
Figure 12. Frequency Response
- 13 -
2005/10
ASAHI KASEI
[AKD5384]
AKM
-80 -85 -90 -95 -100 -105 -110 -115 d B -120 -125 -130 -135 -140 -145 -150 -155 -160 20 50 100
AK5384 Crosstalk AVDD=DVDD=TVDD=5.0V, fs=96kHz, Input=-1.0dBr
200
500
1k Hz
2k
5k
10k
20k
40k
Figure 13. Crosstalk
AKM
+0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50
AK5384 FFT Plot AVDD=DVDD=TVDD=5.0V, fs=96kHz, Input=-1.0dBr, fin=1kHz
100
200
500
1k Hz
2k
5k
10k
20k
40k
Figure 14. FFT Plot
- 14 -
2005/10
ASAHI KASEI
[AKD5384]
AKM
+0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50
AK5384 FFT Plot AVDD=DVDD=TVDD=5.0V, fs=96kHz, Input=-60dBr, fin=1kHz
100
200
500
1k Hz
2k
5k
10k
20k
40k
Figure 15. FFT Plot
AKM
+0 -10 -20 -30 -40 -50 -60 -70 d B F S -80 -90 -100 -110 -120 -130 -140 -150 -160 -170 -180 20 50 100
AK5384 FFT Plot AVDD=DVDD=TVDD=5.0V, fs=96kHz, fin=None
200
500
1k Hz
2k
5k
10k
20k
40k
Figure 16. FFT Plot
- 15 -
2005/10
ASAHI KASEI
[AKD5384]
Revision History
Date (YY/MM/DD) 02/11/01 05/10/17 Manual Revision KM070100 KM070101 Board Revision 0 1 Reason Contents
First edition Circuit Change
Condenser: Capacitance Value Change:
C57,C58: open 5p
IMPORTANT NOTICE * These products and their specifications are subject to change without notice. Before considering any use or application, consult the Asahi Kasei Microsystems Co., Ltd. (AKM) sales office or authorized distributor concerning their current status. * AKM assumes no liability for infringement of any patent, intellectual property, or other right in the application or use of any information contained herein. * Any export of these products, or devices or systems containing them, may require an export license or other official approval under the law and regulations of the country of export pertaining to customs and tariffs, currency exchange, or strategic materials. * AKM products are neither intended nor authorized for use as critical components in any safety, life support, or other hazard related device or system, and AKM assumes no responsibility relating to any such use, except with the express written consent of the Representative Director of AKM. As used here: (a) A hazard related device or system is one designed or intended for life support or maintenance of safety or for applications in medicine, aerospace, nuclear energy, or other fields, in which its failure to function or perform may reasonably be expected to result in loss of life or in significant injury or damage to person or property. (b) A critical component is one whose failure to function or perform may reasonably be expected to result, whether directly or indirectly, in the loss of the safety or effectiveness of the device or system containing it, and which must therefore meet very high standards of performance and reliability. * It is the responsibility of the buyer or distributor of an AKM product who distributes, disposes of, or otherwise places the product with a third party to notify that party in advance of the above content and conditions, and the buyer or distributor agrees to assume any and all responsibility and liability for and hold AKM harmless from any and all claims arising from the use of said product in the absence of such notification.
- 16 -
2005/10
A
B
C
D
E
E
E
JP1 GND DGND AGND
CN1
U1
CN2
LIN2+ T1 NJM78M05FA
D
1
1
LIN2+
LIN1+
28
28
LIN1+
C1 1.5n +15V
1
C2 1.5n
2 LIN2LIN127 27
LIN2-
2
LIN1-
D
OUT
GND
3
IN
C3 0.1u
C4 0.1u
RIN2+
3
3
RIN2+
RIN1+
26
26
RIN1+
2
C5 1.5n RIN24 4 RIN2RIN125
C6 1.5n
25
RIN1-
5
5
TEST
M/S
24
24
M/S DVDD L1 (short)
6
6
VCOM
CKS
23
23
CKS
1 2
C7 2.2u REG
7
+ C8 0.1u
7 AVSS PDN 22 22
PDN
C
AVDD L2 (short)
1 1 2
JP2 AVDD AVDD DIF
8
TVDD
20 1
9
9
DIF
DVDD
20
+ C14 47u
2
C15 0.1u TDM1
10 10 TDM1 TVDD 19 19 1
L3 (short)
2
+ C16 47u SDTO1
2
R1 TDM0
11 11 TDM0 SDTO1 18 18
51
R2
12 12 TDMIN SDTO2 17 17
51 SDTO2 5384_SBICK JP3 BICK BICK
R3 MCLK
B
51
13 13 MCLK BICK 16 16
R4
51
R5
14 14 OVF LRCK 15 15
51 5384_SLRCK JP4 LRCK
2
TEST1 OVF
AK5384
A
A
B
C
+
+
C9 10u
C10 0.1u
8 AVDD DVSS 21 21
1
C12 0.1u
C13 10u
+ C11 47u
C
B
LRCK
A
Title Size Document Number
AKD5384
AK5384
Sheet
E
Rev
A3
Date:
D
A 1
of
Monday, October 17, 2005
4
A
B
C
D
E
R6 4.7k
E
R7 5.1k OP_AMP1E
OP_AMP16 5 1
+
8
U2B NJM5532
8
LIN1+ R13 4.7k R14 5.1k OP_AMP1OP_AMP16 5 1
C19 47u
C20 C21 C22 C23 C24 C25 C26 C27 10u 0.1u 10u 0.1u 10u 0.1u 10u 0.1u
D
D
+
8
U3B NJM5532
8
R19 330
C
C31 10u +
C
RIN1R20 4.7k R21 5.1k OP_AMP1OP_AMP16 5 1
+
8
U4B NJM5532
8
B
R26 330 LIN2-
C43 10u +
R27 4.7k
+
8
U5B NJM5532
8
A
R33 330 RIN2-
C46 10u +
A
B
+
RIN2+
5
U5A NJM5532
OP_AMP1+
C
+
7
3
+
6
1
-
-
R31 330
C45 10u
R30 4.7k
4
4
+
LIN2+
U4A NJM5532
OP_AMP1+ +15V for NJM5532 OP_AMP1+ C34 47u R28 5.1k OP_AMP1R29 10k
2
B
OP_AMP1-
+
7
3
+
-
-
R24 330
C33 10u
R23 4.7k
4
4
+
RIN1+
U3A NJM5532
OP_AMP1+
+
7
3
+
-
-
R17 330
C30 10u
R16 4.7k
4
R15 10k
2
C29 22u
4
J2 RIN1
R18 560 OP_AMP1+
R22 10k
2
C32 22u
J3 LIN2
R25 560 OP_AMP1+
+
+
+
+
+
C35 C36 C37 C38 C39 C40 C41 C42 10u 0.1u 10u 0.1u 10u 0.1u 10u 0.1u
C44 22u
J4 RIN2
R32 560 OP_AMP1+
A
Title Size Document Number
AKD5384
INPUT
Sheet
E
A3
Date:
D
Monday, October 17, 2005
+
+
+
+
+
R12 330
C28 10u
+
LIN1+
U2A NJM5532
OP_AMP1+ -15V for NJM5532 OP_AMP1-
+
7
3
+
-
-
R10 330
C18 10u
R9 4.7k
4
R8 10k
2
C17 22u
4
J1 LIN1
R11 560 OP_AMP1+
Rev
A 2
of
4
A
B
C
D
E
VCC
2
VCC D1 HSU119 R34 10k U6A
1 2 3
1
E
U6B
4
E
PDN
2
74HC14 L
3 1
74HC14
C47 10u
1
H SW1 PDN
2
+
C48 0.1u
C49 0.1u
DIF
44 41 40 39 43 42 38 37 36 35
TRANS
DIF2
DIF1
VDD
DIF0
U4
U3
U2
V34
V12
U1
U8
VCC
U7
34
PORT1
TXP1 33 4 3 2 1 IN VCC IF GND 5 6 5 6
1
G1
VCC
20
1
PDN
D
C50 0.1u
19 G2 GND 10
MCLK
2
MCLK
TXN1
32
C51 0.1u
R35 1k
D
DIT1
SDTO1
2
A1
Y1
18
3
SDTI1
TXP2
31
VCC PORT2
30 4 3 2 1 IN VCC IF GND 5 6 5 6
SDTO2
3
A2
Y2
17
4
SDTI2
TXN2
BICK
A3
Y3
SDTI3
VSS
2
4
16
5
29
LRCK
A4
Y4
SDTI4
VDD
A5
Y5
1
6
C
14
7
VDD
TXP3
27
C
+
A6 Y6 2 7 13
C55 C56 10u 0.1u
8 VSS TXN3 26
8
A7
Y7
12
9
BICK
TXP4
25
9
A8
Y8
11
10
LRCK
TXN4
24
11
CKS0
74ACT541
FS0 ANS VSS BLS FS1 FS2 FS3
CKS1
23
C1
C2
C3
12
13
14
15
16
17
18
C4
19
20
21
B
22
1
5
15
VCC
6
28
PORT3 MCLK MCLK BICK LRCK SDTO1 SDTO2
1 2 3 4 5 10 9 8 7 6
VCC DIF TDM1 TDM0 M/S CKS CKS1 CKS0 SW2
1 2 3 4 5 6 7 14 13 12 11 10 9 8
DSP
MODE
RP1
A
6 5 4 3 2 1
DIF TDM1 TDM0 M/S CKS
Title Size Document Number
47k
A3
Date:
A B C D
+
AK4101
C53 0.1u
C54 10u
C52 0.1u
R36 1k
DIT2
B
A
AKD5384
DIT
Sheet
E
Rev
A 3
of
Monday, October 17, 2005
4
A
B
C
D
E
E
E
X1 24.576MHz MCLK R37 VCC JP5 XTE
1
1M U9A
2 3
U9B
4
256 XTL
2 D CLK CL Q 6 4
U11A 74AC74
Q 5
JP7 256 512 384/768 MCLK 256fs 10
11
U10
CLK RST Q1 Q2 Q3 Q4 Q5 Q6 Q7 Q8 Q9 Q10 Q11 Q12 9 7 6 5 3 2 4 13 12 14 15 1
JP6 BCFS 64fs
74HCU04 C57 5p
D
74HCU04 C58 5p
JP8 CLK EXT
3
PR
128 64 JP9 LRFS fs 256
384
D
J5 EXT
1
74HC4040 R38 51 JP10 EXT VCC U12 U13
3 4 5 6 7 10 2 9 1 A B C D ENP ENT CLK LOAD CLR QA QB QC QD RCO 14 13 12 11 15
VCC
20 VCC DIR 1
M/S
C59 0.1u
10 GND G 19
C
18
B1
A1
2
C
74AC163
17 6 5 B2 A2 3
RP2
6 5 4 3 2 1 16 B3 A3 4 6 5 4 3 2 1
RP3
U6C 74HC14
15
B4
A4
5
47k
14 B5 A5 6
47k
13
B6
A6
7
B
U9C VCC for 74HC14, 74HCU04, 74HC4040, 74AC74 74AC163
10 8 9 5 6 12
B
VCC U6D 74HC14
11 9
B7
A7
8
5384_SLRCK
74HCU04 U9D
8 11 10
U9E
12 13 11 10 11
D CLK
PR
C60 47u
+
C61 0.1u
C62 0.1u
C63 0.1u
C64 0.1u
C65 0.1u
U11B 74AC74
Q 9
B8
A8
9
5384_SBICK
U6E 74HC14
74HCU04
12
74ACT245
8
U6F 74HC14
13
CL 13
74HCU04 U9F
12
Q
74HCU04
A
A
Title Size Document Number
AKD5384
LOGIC
Sheet
E
Rev
A3
Date:
A B C D
A 4
of
Monday, October 17, 2005
4

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