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19-0848; Rev 0; 10/07
KIT ATION EVALU E AILABL AV
Complete Single-Conversion Television Tuner
General Description
The MAX3540 complete single-conversion television tuner is designed for use in analog/digital terrestrial applications and digital set-top boxes. This television tuner draws only 760mW of power from a +3.3V supply voltage. The MAX3540 is designed to convert NTSC or ATSC signals in the 54MHz to 860MHz band to a 44MHz intermediate frequency (IF). The MAX3540 includes a variable-gain low-noise amplifier (LNA), multiband tracking filters, a harmonic-rejection mixer, a low-noise IF amplifier, an IF power detector, and a variable-gain IF amplifier. The MAX3540 also includes fully monolithic VCOs and tank circuits as well as a complete frequency synthesizer. This highly integrated design allows for low-power tuner-on-board applications without the cost and power-dissipation issues of dual-conversion tuner solutions. The MAX3540 is specified for operation in the 0C to +85C temperature range and is available in a leadless 48-pin flip-chip (fcLGA) package.
Features
Low Power Consumption: 760mW (typ) from a +3.3V Supply Voltage Integrated Tracking Filters ATSC A/74 Compliant 40dB Adjacent Channel Protection Ratio (ACPR) 4.4dB (typ) Low Noise Figure Small, 7mm x 7mm, fcLGA Leadless Package 256-QAM-Compatible Phase-Noise Performance IF Overload Detector Controls RF Variable-Gain Amplifier 2-Wire I2C-Compatible Serial Control Interface
MAX3540
Ordering Information
PART MAX3540ULM#G42 TEMP RANGE PINPACKAGE PKG CODE
Applications
Televisions Analog/Digital Terrestrial Receivers Digital Set-Top Boxes Cable Modems VOIP Gateways
0C to +85C 48 fcLGA-EP* L4877A-E
*EP = Exposed paddle.
Pin Configuration
GND_TUNE ADDR2 ADDR1 VTUNE XTALN XTALP MUX LDO 38 VCC VCC VCC 37 36 IFOUT1IFOUT1+ IFOVLD VCC VCC GND IFIN+ IFINVCC GND IFAGC IFOUT2+ 35 34 VCO DIVIDER 33 32 VREF + 31 30 29 28 27 26 25 13 GND 14 GND 15 GND 16 GND 17 GND 18 GND 19 GND 20 GND 21 GND 22 GND 23 VCC 24 IFOUT2-
48
47
46
45
44
43
CP
42
41
40
39
+
SCL SDA VCC UHF_IN VHF_IN RFGND2 LEXT RFGND3 RFAGC 1 2 3 4 5 6 7 8 9 SERIAL INTERFACE
/R
PD CP
/N
VCC 10 GND 11 GND 12
MAX3540
EP
________________________________________________________________ Maxim Integrated Products
1
For pricing, delivery, and ordering information, please contact Maxim Direct at 1-888-629-4642, or visit Maxim's website at www.maxim-ic.com.
Complete Single-Conversion Television Tuner MAX3540
ABSOLUTE MAXIMUM RATINGS
VCC to GND ..............................................................-0.3V, +3.6V RFIN, IFIN_, IFOUT1_, IFOUT2_, IFAGC, RFAGC, VTUNE, LDO, MUX, CP, XTAL to GND ..-0.3V to (VCC + 0.3V) SDA, SCL, ADDR2, ADDR1 to GND......................-0.3V to +3.6V IFOUT__ Short-Circuit Duration .....................................Indefinite RF Input Power ...............................................................+10dBm Continuous Power Dissipation (TA = +70C) 48-Pin fcLGA (derate 25mW/C above +70C) ...............1.4W Operating Temperature Range...............................0C to +85C Junction Temperature ......................................................+150C Storage Temperature Range .............................-65C to +165C Lead Temperature (soldering, 10s) .................................+240C
Stresses beyond those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
CAUTION! ESD SENSITIVE DEVICE
DC ELECTRICAL CHARACTERISTICS
(MAX3540 Evaluation Kit, VCC = +3.1V to +3.5V, no RF signals at RF inputs, default register settings, VRFAGC = VIFAGC = +3V (minimum attenuation), TA = 0C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER SUPPLY VOLTAGE AND CURRENT Supply Voltage Supply Current RF and IF AGC Input Bias Current RF and IF AGC Control Voltage (Note 1) Digital Input Logic-Level Low Digital Input Logic-Level High SERIAL INTERFACE Input Logic-Level Low Input Logic-Level High Input Hysteresis SDA, SCL Input Current Output Logic-Level Low Output Logic-Level High 3mA sink current VCC 0.5 -10 0.7 x VCC 0.05 x VCC +10 0.4 0.3 x VCC V V V A V V 0.7 x VCC Receive mode Shutdown mode At +0.5V and +3V Minimum attenuation Maximum attenuation -50 +3 +0.5 0.3 x VCC +3.1 240 5 +50 +3.5 275 V mA A V V V CONDITIONS MIN TYP MAX UNITS
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Complete Single-Conversion Television Tuner
AC ELECTRICAL CHARACTERISTICS
(MAX3540 Evaluation Kit, VCC = +3.1V to +3.5V, 75 system impedance, default register settings, VRFAGC = VIFAGC = +3V (minimum attenuation), TA = 0C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER RF INPUT TO IFOUT1_ OUTPUT CONDITIONS MIN TYP MAX UNITS
MAX3540
VHF_IN, LPF enabled, INPT = 00 Operating Frequency Range (See Table 7) Output Frequency VHF_IN, LPF disabled, INPT = 01 UHF_IN, INPT = 10 Analog channel PIX carrier Digital channel center frequency Source impedance = 75, load impedance = 200 Gain specification met across these frequency bands Maximum gain, VRFAGC = 3V, 54MHz to 860MHz Maximum gain, VRFAGC = 3V, broadcast channels Minimum gain, VRFAGC = 0.5V VHF_IN UHF_IN
54 100 300 45.75 44 34 28.0 34 -11 54 300 8 4.4 15 29 -13 5 11 -24.5 -3 -60 -60 -40 -40
100 300 860 MHz MHz
Voltage Gain
45.5
dB
300 MHz 860 dB dB dBm dBm
Operating Frequency Range Input Return Loss Noise Figure Input IP2 (In-Band and Out-of-Band Tones) Input IP3 (In-Band and Out-of-Band Tones) Input P1dB Beats Within Output Beats, Converted to Output Gain Flatness Isolation Port-to-Port Isolation Image Rejection
Worst case, selected channel Maximum gain, VRFVGC = 3V (Note 1) Maximum gain, VRFVGC = 3V At 12.5dB of gain Maximum gain, VRFVGC = 3V At 12.5dB of gain Maximum gain, VRFVGC = 3V At 12.5dB of gain, CW tone at fC - 36MHz, tested at Ch 69 in UHF band 0dBmV PIX carrier level (Note 1) VHF_IN from 150MHz to 960MHz VHF_IN from 960MHz to 1400MHz UHF_IN from 600MHz to 1400MHz 54MHz to 60MHz 5MHz to 50MHz, RF input to IF output, relative to desired channel Isolation between RF input ports at 215MHz Measured at 91.5MHz above desired channel's center frequency 5MHz to 65MHz 65MHz to 878MHz 10kHz offset 100kHz offset, 1.5kHz loop bandwidth 1MHz offset, 1.5kHz loop bandwidth Balanced 50 load 54MHz to 860MHz Broadcast channels, TA = +25C 66
dBm dBc dBc 1.5 dBP-P dBc dB dBc
60 30 70
Spurious Leakage at RF Input
-40 -40 -85 -105 -125 9
dBmV
Phase Noise (Single-Sideband) Output Return Loss
dBc/Hz dB
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Complete Single-Conversion Television Tuner MAX3540
AC ELECTRICAL CHARACTERISTICS (continued)
(MAX3540 Evaluation Kit, VCC = +3.1V to +3.5V, 75 system impedance, default register settings, VRFAGC = VIFAGC = +3V (minimum attenuation), TA = 0C to +85C, unless otherwise noted. Typical values are at VCC = +3.3V, TA = +25C, unless otherwise noted.)
PARAMETER IF VARIABLE-GAIN AMPLIFIER Input Impedance Output Impedance Balanced Balanced (Note 1) Source load = 300, output load = 300 40MHz to 48MHz (Note 1) VIFAGC = 3V (Note 1) VIFAGC = 3V to 0.5V (Note 1) At 44MHz, maximum gain, VIFAGC = 3V (Note 1) < 0.35 VOUT = 1.5VP-P, 40dB < gain < 60dB (Note 1) -54 0.7 1 Negative polarity, overload reduces VDET (open collector, 0.3mA sink) 0.5 70 3.0 Maximum gain setting, VIFAGC = 3V Minimum gain setting, VIFAGC = 0.5V 54 56 2000 300 65 dB 21 1.2 2 30 7.3 dB VP-P dB/V nV/Hz dB/dB dBc VP-P dB V V/V CONDITIONS MIN TYP MAX UNITS
Passband Voltage Gain
Passband Gain Flatness Output Voltage AGC Gain Slope Equivalent Input Voltage Noise Density Noise Figure Change vs. Attenuation IM3 Output Overload Attack Point Attack-Point Accuracy Detector Output Voltage Range Detector Gain FREQUENCY SYNTHESIZER REFERENCE OSCILLATOR Frequency DIVIDERS RF N-Divider Ratio RF R-Divider Ratio
IF OVERLOAD DETECTOR (see the IF Overload Detector section)
4 256 8 31.50 CP = 00 0.5 1 1.5 2 5 5 Tank frequency Tank oscillator gain 2160 4400 500 400 CP = 01 CP = 10 CP = 11 32,767 127 250.00
MHz
LO PHASE DETECTOR AND CHARGE PUMP Comparison Frequency kHz
Charge-Pump Current
mA
Charge-Pump Three-State Current Charge-Pump Current Matching LOCAL OSCILLATOR (OSCILLATOR WITH NARROW BAND LOOP) VCO Tuning Range VCO Tuning Gain 2-WIRE SERIAL INTERFACE Clock Frequency
nA % MHz MHz/V kHz
Note 1: Guaranteed by design and characterization. 4 _______________________________________________________________________________________
Complete Single-Conversion Television Tuner
Pin Description
PIN 1 2 3, 10, 23, 28, 32, 33, 37, 41, 44 4 5 6 7 8 9 11-22, 27, 31 24 25 26 29 30 34 35 36 38 39 40 42 43 45 46 47 48 EP NAME SCL SDA VCC UHF_IN VHF_IN RFGND2 LEXT RFGND3 RFAGC GND IFOUT2IFOUT2+ IFAGC IFINIFIN+ IFOVLD IFOUT1+ IFOUT1LDO GND_TUNE VTUNE MUX CP XTALN XTALP ADDR1 ADDR2 EP FUNCTION 2-Wire Serial-Clock Interface. Requires a pullup resistor to VCC. 2-Wire Serial-Data Interface. Requires a pullup resistor to VCC. Power-Supply Connections. Bypass each supply pin to ground with a 1000pF capacitor. UHF RF Input. Matched to 75 over the operating band. Requires a DC-blocking capacitor. VHF RF Input. Matched to 75 over the operating band. Requires a DC-blocking capacitor. RF Ground. Bypass to the PCB's ground plane with a 1000pF capacitor. Do not connect RFGND2 and RFGND3 together. RF VGA Supply Voltage. Connect through a 270nH pullup inductor to VCC. RF Ground. Bypass to the PCB's ground plane with a 1000pF capacitor. Do not connect RFGND2 and RFGND3 together. RF AGC Gain-Control Voltage. Accepts a DC voltage from 0.5V (minimum gain) to 3V (maximum gain). Ground. Connect to the PCB's ground plane. Inverting IF-VGA Output. Connect to the input of an anti-aliasing filter. Requires a DC-blocking capacitor. Noninverting IF-VGA Output. Connect to the input of an anti-aliasing filter. Requires a DC-blocking capacitor. IF AGC Gain-Control Voltage. Accepts a DC voltage from 0.5V (minimum gain) to 3V (maximum gain). Inverting IF-VGA Input. Connect to the output of an IF-SAW filter. Noninverting IF-VGA Input. Connect to the output of an IF-SAW filter. IF Power Detector Open-Collector Output. Requires a 10k pullup resistor to VCC. Noninverting IF-LNA Output. Requires a DC-blocking capacitor. Inverting IF-LNA Output. Requires a DC-blocking capacitor. VCO LDO Bypass. Bypass to ground with a 0.47F capacitor. VTUNE Ground Connection. Connect to the PCB ground plane. All loop filter component GND must be connected to this pin (see the Typical Application Circuit). VCO Tuning Input. Connect to the PLL loop filter output. Test Output. Leave this pin unconnected during normal operation. Charge-Pump Output. Connect to the PLL loop filter input. Crystal Oscillator Feedback. See the Typical Application Circuit. Crystal Input. Requires a DC-blocking capacitor. 2-Wire Serial-Interface Address Line 1. This pin along with ADDR2 sets the device address for the I2C-compatible serial interface. 2-Wire Serial-Interface Address Line 2. This pin along with ADDR1 sets the device address for the I2C-compatible serial interface. Exposed Paddle. Solder evenly to the PCB ground plane for proper operation.
MAX3540
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Complete Single-Conversion Television Tuner MAX3540
Detailed Description
Register Descriptions
The MAX3540 includes 11 programmable registers and two read-only registers. The 11 programmable registers include two N-divider registers, an R-divider register, a VCO register, an RSSI/charge-pump/filter-select register, a control register, a shutdown register, and trackingfilter control registers. These 11 programmable registers are also readable. The read-only registers include a status register and a ROM table data register. Recommended default bit settings are provided for user convenience only and are not guaranteed. The user must write all registers after power-up and no earlier than 100s after power-up.
Table 1. Register Configuration
MSB REGISTER READ/ REGISTER NAME WRITE ADDRESS D7 N-DIV High N-DIV Low R-DIV VCO IFOVLD, Charge Pump, and Filter Select Control Shutdown Tracking Filter Series Cap Tracking Filter Parallel Cap Tracking Filter ROM Address Reserved ROM Table Data Readback Status Both Both Both Both 0x00 0x01 0x02 0x03 0 N7 0 VCO4 D6 N14 N6 R6 VCO3 D5 N13 N5 R5 VCO2 DATA BYTE D4 N12 N4 R4 VCO1 D3 N11 N3 R3 VCO0 D2 N10 N2 R2 LD D1 N9 N1 R1 D0 N8 N0 R0 LSB
VDIV1 VDIV0
Both
0x04
0
IFOVLD2
IFOVLD1
IFOVLD0
CP1
CP0
TF1
TF0
Both Both Both
0x05 0x06 0x07
0
0
0
0
SHDN_RF
SHDN_IFAGC INPT1 INPT0 0 TFS2 0 TFS1 0 TFS0
SH DN _MIX1 SH DN _MIX0 SH DN _I F SH DN _P D SH DN _S YN TFS7 TFS6 TFS5 TFS4 TFS3
Both
0x08
FLD
0
TFP5
TFP4
TFP3
TFP2
TFP1
TFP0
Both Both Read Read
0x09 0x0A 0x0B 0x0C
0 X TFR7 POR
0 X TFR6 LD2
0 X TFR5 LD1
0 X TFR4 LD0
TFA3 X TFR3 X
TFA2 X TFR2 X
TFA1 X TFR1 X
TFA0 X TFR0 X
Table 2. N-DIV High Register (Address: 0000b)
BIT NAME RESERVED N[14:8] BIT LOCATION (0 = LSB) 7 6-0 RECOMMENDED DEFAULT 0 001 0010 Must be set to 0. Sets the most significant bits of the PLL integer divider (N). Default integer divider value is N = 4688. N can range from 256 to 32,767. FUNCTION
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Complete Single-Conversion Television Tuner MAX3540
Table 3. N-DIV Low Register (Address: 0001b)
BIT NAME N[7:0] BIT LOCATION (0 = LSB) 7-0 RECOMMENDED DEFAULT 0101 0000 FUNCTION Sets the least significant bits of the PLL integer divider (N). Default integer divider value is N = 4688. N can range from 256 to 32,767.
Table 4. R-DIV Register (Address: 0010b)
BIT NAME RESERVED R[6:0] BIT LOCATION (0 = LSB) 7 6-0 RECOMMENDED DEFAULT 0 100 0000 Must be set to 0. Sets the PLL reference divider (R). Default reference divider value is R = 64. R can range from 16 to 127. FUNCTION
Table 5. VCO Register (Address: 0011b)
BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT FUNCTION VCO select. Selects one of three possible VCOs. 00 = VCOs shut down 01 = selects VCO1 10 = selects VCO2 11 = selects VCO3 VCO sub-band select. Selects one of eight possible VCO sub-bands. 000 = selects SB0 001 = selects SB1 010 = selects SB2 011 = selects SB3 100 = selects SB4 101 = selects SB5 110 = selects SB6 111 = selects SB7 Lock-detect enable. 0 = disabled 1 = enabled VCO divider ratio select. 00 = sets VCO divider to 4 01 = sets VCO divider to 8 10 = sets VCO divider to 16 11 = sets VCO divider to 32
VCO[4:3]
7, 6
01
VCO[2:0]
5, 4, 3
101
LD
2
1
VDIV[1:0]
1, 0
01
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Complete Single-Conversion Television Tuner MAX3540
Table 6. RSSI, Charge Pump, and Filter Select Register (Address: 0100b)
BIT NAME RESERVED IFOVLD[2:0] BIT LOCATION (0 = LSB) 7 6, 5, 4 RECOMMENDED DEFAULT 0 000 Must be set to 0. Write content of ROM register OD[2:0] to this location. Selects the typical charge-pump current. 00 = 0.5mA 01 = 1mA 10 = 1.5mA 11 = 2mA Selects the tracking filter band of operation. 00 = VHF low 01 = VHF high 10 = UHF 11 = factory use only FUNCTION
CP[1:0]
3, 2
00
TF[1:0]
1, 0
00
Table 7. Control Register (Address: 0101b)
BIT NAME RESERVED SHDN_RF BIT LOCATION (0 = LSB) 7-4 3 RECOMMENDED DEFAULT 0000 0 Must be set to 0000. RF shutdown. 0 = RF circuitry enabled 1 = RF circuitry disabled IF VGA shutdown. 0 = IF VGA enabled 1 = IF VGA disabled Selects the RF input. 00 = selects VHF_IN with LPF 01 = selects VHF_IN, no LPF 10 = selects UHF_IN 11 = factory use only FUNCTION
SHDN_IFV GA
2
1
INPT[1:0]
1, 0
00
8
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Complete Single-Conversion Television Tuner MAX3540
Table 8. Shutdown Register (Address: 0110b)
BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT Mixer shutdown. 00 = mixer enabled 01, 10 = factory use only 11 = mixer disabled IF shutdown. 0 = IF section enabled 1 = IF section disabled IF OVLD shutdown. 0 = power detector enabled 1 = power detector disabled Frequency synthesizer shutdown. 0 = synthesizer enabled 1 = synthesizer disabled Must be set to 000. FUNCTION
SHDN_MIX
7, 6
0
SHDN_IF
5
0
SHDN_PD
4
0
SHDN_SYN RESERVED
3 2, 1, 0
0 000
Table 9. Tracking-Filter Series Cap Register (Address: 0111b)
BIT NAME TFS[7:0] BIT LOCATION (0 = LSB) 7-0 RECOMMENDED DEFAULT 00000000* FUNCTION Programs series capacitor values in the tracking filter.
Table 10. Tracking-Filter Parallel Cap Register (Address: 1000b)
BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT FUNCTION
FLD Reserved TFP[5:0]
7 6 5-0
0 0 000000*
Filter load bit. A 0 to 1 transition of this bit forces the loading of the ROM table data readback register. Must be set to 0. Programs parallel capacitor values in the tracking filter.
Table 11. Tracking-Filter ROM Address Register (Address: 1001b)
BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT FUNCTION
Reserved TFA[3:0]
7-4 3-0
0000 0000*
Must be set to 0000. Address bits of the ROM register to be read.
*See the RF Tracking Filter section.
Table 12. Reserved Register (Address: 1010b)
BIT NAME Reserved BIT LOCATION (0 = LSB) 7-0 RECOMMENDED DEFAULT N/A FUNCTION Reserved. Do not program these bits during normal operation.
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Complete Single-Conversion Television Tuner MAX3540
Table 13. ROM Table Data Readback Register (Address: 1011b)
BIT NAME TFR[7:0] BIT LOCATION (0 = LSB) 7-0 RECOMMENDED DEFAULT 00000000* FUNCTION Tracking-filter data bits read from the device's ROM table.
*See the RF Tracking Filter section.
Table 14. Status Register (Address: 1100b)
BIT NAME BIT LOCATION (0 = LSB) RECOMMENDED DEFAULT 0 FUNCTION Power-on reset. 0 = status register has been read 1 = power reset since last status register read VCO tuning voltage indicators. 000 = PLL not in lock, tune to the next lowest sub-band 001-110 = PLL in lock 111 = PLL not in lock, tune to the next higher sub-band Reserved.
POR
7
LD[2:0]
6, 5, 4
000
Reserved
3-0
0000
2-Wire Serial Interface
The MAX3540 uses a 2-wire I2C-compatible serial interface consisting of a serial-data line (SDA) and a serialclock line (SCL). SDA and SCL facilitate bidirectional communication between the MAX3540 and the master at clock frequencies up to 400kHz. The master initiates a data transfer on the bus and generates the SCL signal to permit data transfer. The MAX3540 behaves as a slave device that transfers and receives data to and from the master. Pull SDA and SCL high with external pullup resistors (1k or greater) for proper bus operation. One bit is transferred during each SCL clock cycle. A minimum of nine clock cycles is required to transfer a byte in or out of the MAX3540 (8 data bits and an ACK/NACK). The data on SDA must remain stable during the high period of the SCL clock pulse. Changes in SDA while SCL is high and stable are considered control signals (see the START and STOP Conditions section). Both SDA and SCL remain high when the bus is not busy.
Table 15. MAX3540 Address Configurations
ADDR2 0 0 1 1 ADDR1 0 1 0 1 WRITE ADDRESS 0xC0 0xC2 0xC4 0xC6 READ ADDRESS 0xC1 0xC3 0xC5 0xC7
START and STOP Conditions The master initiates a transmission with a START condition (S), which is a high-to-low transition on SDA while SCL is high. The master terminates a transmission with a STOP condition (P), which is a low-to-high transition on SDA while SCL is high. Acknowledge and Not-Acknowledge Conditions Data transfers are framed with an acknowledge bit (ACK) or a not-acknowledge bit (NACK). Both the master and the MAX3540 (slave) generate acknowledge bits. To generate an acknowledge, the receiving device
10
must pull SDA low before the rising edge of the acknowledge-related clock pulse (ninth pulse) and keep it low during the high period of the clock pulse. To generate a not-acknowledge condition, the receiver allows SDA to be pulled high before the rising edge of the acknowledge-related clock pulse, and leaves SDA high during the high period of the clock pulse. Monitoring the acknowledge bits allows for detection of unsuccessful data transfers. An unsuccessful data transfer happens if a receiving device is busy or if a system fault has occurred. In the event of an unsuccessful data transfer, the bus master must reattempt communication at a later time.
Slave Address The MAX3540 has a 7-bit slave address that must be sent to the device following a START condition to initiate communication. The slave address is determined by the state of the ADDR2 and ADDR1 pins and is equal to 11000[ADDR2][ADDR1]. The 8th bit (R/W) following the 7-bit address determines whether a read or write operation will occur. Table 15 shows the possible address configurations.
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Complete Single-Conversion Television Tuner
The MAX3540 continuously awaits a START condition followed by its slave address. When the device recognizes its slave address, it acknowledges by pulling the SDA line low for one clock period. It is ready to accept or send data depending on the R/W bit (Figure 1). Figure 2 illustrates an example in which registers 0 through 2 are written with 0x0E, 0xD8, and 0xE1, respectively.
MAX3540
Write Cycle When addressed with a write command, the MAX3540 allows the master to write to a single register or to multiple successive registers. A write cycle begins with the bus master issuing a START condition followed by the 7 slave address bits and a write bit (R/W = 0). The MAX3540 issues an ACK if the slave address byte is successfully received. The bus master must then send to the slave the address of the first register it wishes to write to. If the slave acknowledges the address, the master can then write one byte to the register at the specified address. Data is written beginning with the most significant bit. The MAX3540 again issues an ACK if the data is successfully written to the register. The master can continue to write data to the successive internal registers with the MAX3540 acknowledging each successful transfer, or it can terminate transmission by issuing a STOP condition. The write cycle does not terminate until the master issues a STOP condition.
SLAVE ADDRESS
Read Cycle A read cycle begins with the bus master issuing a START condition followed by the seven slave address bits and a write bit (R/W = 0). The MAX3540 issues an ACK if the slave address byte is successfully received. The master then sends the 8-bit address of the first register that it wishes to read. The MAX3540 then issues another ACK. Next, the master must issue a START condition followed by the 7 slave address bits and a read bit (R/W = 1). The MAX3540 issues an ACK if it successfully recognizes its address and begins sending data from the specified register address starting with the most significant bit (MSB). Data is clocked out of the MAX3540 on the rising edge of SCL. On the 9th rising edge of SCL, the master can issue an ACK and continue reading successive registers or it can issue a NACK followed by a STOP condition to terminate transmission. The read cycle does not terminate until the master issues a STOP condition. Figure 3 illustrates an example in which registers 0 and 1 are read back.
S SDA
1
1
0
0
0
ADDR2
ADDR1
R/W
ACK
P
SCL
1
2
3
4
5
6
7
8
9
NOTE: TIMING PARAMETERS CONFORM WITH I2C BUS SPECIFICATIONS.
Figure 1. MAX3540 Slave Address Byte
WRITE DEVICE ADDRESS 11000[ADDR2][ADDR1] WRITE REGISTER ADDRESS 0x00 WRITE DATA TO REGISTER 0x00 0x0E WRITE DATA TO REGISTER 0x01 0xD8 WRITE DATA TO REGISTER 0x02 0xE1
START
R/W 0
ACK --
ACK --
ACK --
ACK --
ACK --
STOP
Figure 2. Example: Write registers 0 through 2 with 0x0E, 0xD8, and 0xE1, respectively.
START
WRITE DEVICE ADDRESS 110000[ADDR2][ADDR1]
R/W 0
ACK --
WRITE 1st REGISTER ADDRESS 0x00
ACK --
START
WRITE DEVICE ADDRESS 110000[ADDR2][ADDR1]
R/W ACK 1 --
READ DATA REG 0 D7-D0
ACK --
READ DATA REG 1 D7-D0
NACK --
STOP
Figure 3. Example: Read data from registers 0 through 1.
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Complete Single-Conversion Television Tuner MAX3540
Applications Information
RF Inputs
The MAX3540 features separate UHF and VHF inputs that are matched to 75. Both inputs require a DC-blocking capacitor. The input registers select the active inputs. In addition, the input registers enable or disable the lowpass filter, which can be used when the VHF input is selected. For 54MHz to 100MHz, select the VHF_IN with the LPF filter enabled (INPT = 00). For 100MHz to 300MHz, select VHF_IN with LPF disabled (INPT = 01). For 300MHz to 860MHz, select UHF_IN (INPT = 10). quency of each tracking filter is selected by a switchedcapacitor array, which is programmed by the TFS[7:0] bits in the Tracking-Filter Series Cap register and the TFP[5:0] bits in the Tracking-Filter Parallel Cap register. To accommodate part-to-part variations each part is factory-calibrated by Maxim. During calibration the y-intercept and slope for the series and parallel tracking capacitor arrays is calculated and written into an internal ROM table. The user must read the ROM table upon power-up and store the data in local memory (8 bytes total) to calculate the optimal TFS[7:0] and TFP[5:0] settings for each channel. Table 16 shows the address and bits for each ROM table entry. See the Interpolating Tracking Filter Coefficients section for more information on how to calculate the required values.
RF Gain Control
The gain of the RF low-noise amplifier can be adjusted over a typical 45dB range by the RFAGC pin. The RFAGC input accepts a DC voltage from 0.5V to 3V, with 3V providing maximum gain. This pin can be controlled with the IF power-detector output to form a closed RF gain-control loop. See the Closed-Loop RF Gain Control section for more information.
Reading the ROM Table Each ROM table entry must be read using a two-step process. First, the address of the ROM bits to be read must be programmed into the TFA[3:0] bits in the Tracking Filter ROM Address register (Table 11).
Once the address has been programmed, the data stored in that address is transferred to the TFR[7:0] bits in the ROM Table Data Readback register (Table 13). The ROM data at the specified address can then be read from the TFR[7:0] bits and stored in the microprocessor's local memory.
RF Tracking Filter
The MAX3540 includes a programmable tracking filter for each band of operation to optimize rejection of out-ofband interference while minimizing insertion loss for the desired received signal. VHF low, VHF high, or UHF tracking filter is selected by the TF register. The center fre-
Table 16. ROM Table
MSB DESCRIPTION IFOVLD VHF Low Series/ Parallel Y-Intercept VHF High Series/ Parallel Y-Intercept UHF Series/ Parallel Y-Intercept VHF Low Series Slope VHF High Parallel Slope VHF Low Parallel Slope VHF High Parallel Slope UHF Parallel Slope ADDRESS D7 0x0 0x1 0x2 0x3 0x4 0x5 0x6 0x7 0x8 OD2 LS0[5] LS1[1] LP1[3] HS1[3] HP1[3] US0[3] US1[1] UP0[1] D6 OD1 LS0[4] LS1[0] LP1[2] HS1[2] HP1[2] US0[2] US1[0] UP0[0] D5 OD0 LS0[3] LP0[5] LP1[1] HS1[1] HP1[1] US0[1] UP0[7] UP1[5] DATA BYTE D4 X LS0[2] LP0[4] LP1[0] HS1[0] HP1[0] US0[0] UP0[6] UP1[4] D3 X LS0[1] LP0[3] HS0[3] HP0[3] US0[7] US1[5] UP0[5] UP1[3] D2 X LS0[0] LP0[2] HS0[2] HP0[2] US0[6] US1[4] UP0[4] UP1[2] D1 X LS1[3] LP0[1] HS0[1] HP0[1] US0[5] US1[3] UP0[3] UP1[1] D0 X LS1[2] LP0[0] HS0[0] HP0[0] US0[4] US1[2] UP0[2] UP1[0] LSB
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Complete Single-Conversion Television Tuner
Interpolating Tracking Filter Coefficients The TFS[7:0] and TFP[5:0] bits must be reprogrammed for each channel frequency to optimize performance. The optimal settings for each channel can be calculated from the ROM table data using the equations below. VHF LO filter:
LS0 LS1 TFS = 10 (2.4 + x 0.6) + (-8.5 + x 2) x f RF x 10 -3 16 64
LP0 LP1 -3 [(1.6 + 64 x 0.4) + (-6 + 16 x 2 ) x f RF x 10 ] TFP = INT 10
The nominal full-scale current sunk by the IFOVLD pin is 300A. The IFOVLD pin requires a 10k pullup resistor to VCC. The IF overload detector is calibrated at the factory to attack at 0.6VP-P at IFOUT1. Upon power-up, the baseband processor must read OD[2:0] from the ROM table and store it in the IFVOLD register.
MAX3540
Closed-Loop RF Gain Control
Closed-loop RF gain control can be implemented by connecting the IFOVLD output to the RFAGC input. Using a 10k pullup resistor on the IFOVLD pin, as shown in the Typical Application Circuit, results in a nominal 0.5V to 3V control voltage range.
VHF High filter:
HS0 HS1 -3 [(2.8 + 16 x 0.8) + (-4.2 + 16 x 0.8 ) x f RF x 10 ] TFS = INT 10 - 20 HP0 HP1 -3 [(1.6 + 16 x 0.8) + (-1.5 + 16 x 0.6 ) x f RF x 10 ] TFP = INT 10 - 10
VCO and VCO Divider Selection
The MAX3540 frequency synthesizer includes three VCOs and eight VCO sub-bands to guarantee a 2160MHz to 4400MHz VCO frequency range. The frequency synthesizer also features an additional VCO frequency divider, which must be programmed to either 4, 8, 16, or 32 through the VDIV[1:0] bits in the VCO register based on the channel being received. Table 5 describes how the VDIV[1:0] bits should be programmed for each band of operation. To ensure PLL, lock the proper VCO and VCO sub-band for the channel being received, which must be chosen by iteratively selecting a VCO and VCO sub-band then reading the LD[2:0] bits to determine if the PLL is locked. Any reading from 001 to 110 indicates the PLL is locked. If LD[2:0] reads 000, the PLL is unlocked and the selected VCO is at the bottom of its tuning range; a lower VCO subband must be selected. If LD[2:0] reads 111, the PLL is unlocked and the selected VCO is at the top of its tuning range; a higher VCO sub-band must be selected. The VCO and VCO sub-band settings should be progressively increased or decreased until the LD[2:0] reading falls in the 001 to 110 range. Due to overlap between VCO sub-band frequencies, it is possible that multiple VCO settings can be used to tune to the same channel frequency. System performance at a given channel should be similar between the various possible VCO settings, so it is sufficient to select the first VCO and VCO sub-band that provides lock.
UHF filter:
US0 US1 -3 [(3 + 256 ) + (-2.6 + 64 x 0.8 ) x f RF x 10 ] TFS = INT 10 - 20
UP0 UP1 -3 [(1.6 + 256 x 0.8) + (-1.4 + 64 x 0.8 ) x f RF x 10 ] TFP = INT 10 - 10
Where: fRF = operating frequency in MHz TFS = decimal value of the optimal TFS[7:0] setting (Table 9) for the given operating frequency TFP = decimal value of the optimal TFP[5:0] setting (Table 10) for the given operating frequency LS0, LS1, LP0, LP1, HS0, HS1, HP0, HP1, US0, US1, UP0, and UP1 = the decimal values of the ROM table coefficients (Table 16).
Layout Considerations
The MAX3540 EV kit can serve as a guide for PCB layout. Keep RF signal lines as short as possible to minimize losses and radiation. Use controlled impedance on all high-frequency traces. The exposed paddle must be soldered evenly to the board's ground plane for proper operation. Use abundant vias beneath the exposed paddle for maximum heat dissipation. Use abundant ground vias between RF traces to minimize undesired coupling.
13
IF Overload Detector
The MAX3541 includes a broadband IF overload detector, which provides an indication of the total power present at the RF input. The overload-detector output voltage is compared to a reference voltage and the difference is amplified. This error signal drives an opencollector transistor whose collector is connected to the IFOVLD pin, causing the IFOVLD pin to sink current.
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Complete Single-Conversion Television Tuner MAX3540
To minimize coupling between different sections of the IC, the ideal power-supply layout is a star configuration, which has a large decoupling capacitor at the central VCC node. The VCC traces branch out from this node, with each trace going to separate VCC pins of the MAX3540. Each V CC pin must have a bypass capacitor with a low impedance to ground at the frequency of interest. Do not share ground vias among multiple connections to the PCB ground plane.
Typical Application Circuit
270 4700pF 1.3k * 0.033F VCC * 22pF 1000pF 100pF 100pF ADDRESS1 GND_TUNE VCC ADDRESS2 ADDR2 ADDR1 VTUNE XTALN XTALP MUX VCC VCC CP * 1000pF LDO VCC VCC 1000pF 1000pF 47F 1000pF VCC * 470pF
SAW DRIVER AMPLIFIER
680nH
2.7k SCLK SDATA 100 1000pF
2.7k SCL SDA VCC UHF_IN VHF_IN 1 2 3 4 5 6 7 8 9 10 11 12
48
47
46
45
44
43
42
41
40
39
38
37 36 IFOUT1IFOUT1+ IFOVLD VCC VCC GND IFIN+ IFINVCC GND IFAGC IFOUT2+
VCC IF-SAW FILTER 0.1F 10k IFOVLD VCC VCC
VCC
/R
SERIAL INTERFACE
PD CP
35 34 VCO DIVIDER 33 32 VREF 31 30 + 29 28
/N
VCC 470nF 1000pF 2.7 IFOVLD 0.1F
1000pF
RFGND2 LEXT
1000pF
1000pF
1000pF
RFGND3 RFAGC
2.2pF
VCC
VCC
VCC GND
MAX3540
EP
27 26 25
1000pF 2.7k VIFAGC 0.1F
1000pF
GND
13 GND
14 GND
15 GND
16 GND
17 GND
18 GND
19 GND
20 GND
21 GND
22 GND
23 VCC
24 IFOUT2IFOUT+ IFOUTANTI-ALIASING FILTER
VCC
1000pF *CONNECT TO COMMON GROUND POINT AT PIN 39.
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Complete Single-Conversion Television Tuner
Package Information
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
48L LGA.EPS
MAX3540
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Complete Single-Conversion Television Tuner MAX3540
Package Information (continued)
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to www.maxim-ic.com/packages.)
Maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a Maxim product. No circuit patent licenses are implied. Maxim reserves the right to change the circuitry and specifications without notice at any time.
16 ____________________Maxim Integrated Products, 120 San Gabriel Drive, Sunnyvale, CA 94086 408-737-7600 (c) 2007 Maxim Integrated Products is a registered trademark of Maxim Integrated Products, Inc.

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