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| VN5050AJ-E Single channel high side driver with analog current sense for automotive applications Features Max supply voltage Operating voltage range Max On-State resistance Current limitation (typ) Off state supply current VCC VCC RON ILIMH IS 41 V 4.5 to 36V 50 m 16.5 A 2 A PowerSSO-12 - Reverse battery protection ( see Application schematic) - Electrostatic discharge protection General features - Inrush current active management by power limitation - Very low stand-by current - 3.0V CMOS compatible input - Optimized electromagnetic emission - Very low electromagnetic susceptibility - In compliance with the 2002/95/EC European directive Diagnostic functions - Proportional load current sense - High current sense precision for wide range currents - Current sense disable - Thermal shutdown indication - Very low current sense leakage Protection - Undervoltage shut-down - Overvoltage clamp - Load current limitation - Self limiting of fast thermal transients - Protection against loss of ground and loss of VCC - Thermal shut down Device summary Application All types of resistive, inductive and capacitive loads Suitable as LED driver Description The VN5050AJ-E is a monolithic device made using STMicroelectronics VIPower technology. It is intended for driving resistive or inductive loads with one side connected to ground. Active VCC pin voltage clamp protects the device against low energy spikes (see ISO7637 transient compatibility table). This device integrates an analog current sense which delivers a current proportional to the load current (according to a known ratio) when CS_DIS is driven low or left open. When CS_DIS is driven high, the CURRENT SENSE pin is in a high impedance condition. Output current limitation protects the device in overload condition. In case of long overload duration, the device limits the dissipated power to safe level up to thermal shut-down intervention. Thermal shut-down with automatic restart allows the device to recover normal operation as soon as fault condition disappears. Table 1. Order codes Package Tube PowerSSO-12 VN5050AJ-E Tape and Reel VN5050AJTR-E September 2007 Rev 4 1/32 www.st.com 32 Contents VN5050AJ-E Contents 1 2 Block diagram and pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 2.1 2.2 2.3 2.4 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Electrical characteristics curves . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 3 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 3.1 GND protection network against reverse battery . . . . . . . . . . . . . . . . . . . 22 3.1.1 3.1.2 Solution 1: resistor in the ground line (RGND only). . . . . . . . . . . . . . . . 22 Solution 2: diode (DGND) in the ground line. . . . . . . . . . . . . . . . . . . . . . 23 3.2 3.3 3.4 Load dump protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 MCU I/O protection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Maximum demagnetization energy (VCC = 13.5V) . . . . . . . . . . . . . . . . . 24 4 Package and PCB thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 4.1 PowerSSO-12 thermal data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 5 Package information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 5.1 5.2 5.3 ECOPACK(R) packages . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Packing information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 6 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 2/32 VN5050AJ-E List of tables List of tables Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 9. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Device summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Suggested connections for unused and n.c. pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Power section . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Switching (VCC=13V, Tj=25C) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Logic input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Protection and diagnostics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 Current sense (8V List of figures VN5050AJ-E List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 Figure 2. Configuration diagram (top view) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Figure 3. Current and voltage conventions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Figure 4. Current sense delay characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Figure 5. Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .13 Figure 6. IOUT/ISENSE Vs. IOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 7. Maximum current sense ratio drift vs load current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 Figure 8. Switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Figure 9. Output voltage drop limitation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Figure 10. Waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Figure 11. Off state output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 12. High level input current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 13. Input clamp voltage. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 14. Input low level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 15. Input high level . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 16. Input hysteresis voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Figure 17. On state resistance vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 18. On state resistance vs. VCC. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 19. Undervoltage shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 20. Turn-on voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 21. ILIMH Vs. Tcase . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 22. Turn-off voltage slope . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Figure 23. CS_DIS high level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 24. CS_DIS clamp voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 25. CS_DIS low level voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Figure 26. Application schematic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Figure 27. Maximum turn off current versus inductance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Figure 28. PowerSSO-12 PC Board . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition . . . . . . . . . . . . . . . . . . . . . 25 Figure 30. PowerSSO-12 thermal impedance junction ambient single pulse . . . . . . . . . . . . . . . . . . . 26 Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12 . . . . . . . . . . . . . . . . . . . . 26 Figure 32. PowerSSO-12TM package dimensions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Figure 33. PowerSSO-12 tube shipment (no suffix) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 Figure 34. PowerSSO-12 tape and reel shipment (suffix "TR") . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 30 4/32 VN5050AJ-E Block diagram and pin description 1 Block diagram and pin description Figure 1. Block diagram VCC VCC CLAMP UNDERVOLTAGE PwCLAMP DRIVER OUTPUT ILIM VDSLIM GND LOGIC INPUT PwrLIM OVERTEMP. IOUT CS_DIS K CURRENT SENSE Table 2. Name VCC Pin function Function Battery connection Power output Ground connection. Must be reverse battery protected by an external diode/resistor network Voltage controlled input pin with hysteresis, CMOS compatible. Controls output switch state OUTPUT GND INPUT CURRENT SENSE Analog current sense pin, delivers a current proportional to the load current CS_DIS Active high CMOS compatible pin, to disable the current sense pin 5/32 Block diagram and pin description Figure 2. Configuration diagram (top view) VN5050AJ-E TAB = Vcc N.C. GND INPUT CURRENT SENSE CS_DIS N.C. 1 2 3 4 5 6 12 11 10 9 8 7 N.C. OUTPUT OUTPUT OUTPUT OUTPUT N.C. Table 3. Suggested connections for unused and n.c. pins Current sense N.R. Through 1k resistor N.C. X X Output X N.R.(1) Input X Through 10k resistor CS_DIS X Through 10k resistor Connection / Pin Floating To Ground 1. Not recommended 6/32 VN5050AJ-E Electrical specifications 2 Electrical specifications Figure 3. Current and voltage conventions IS VCC VF ICSD IIN VCSD VIN IOUT CS_DIS OUTPUT VCC INPUT CURRENT SENSE GND IGND VSENSE ISENSE VOUT Note: VF = VOUT - VCC during reverse battery condition 2.1 Absolute maximum ratings Stressing the device above the rating listed in the "Absolute maximum ratings" table may cause permanent damage to the device. These are stress ratings only and operation of the device at these or any other conditions above those indicated in the Operating sections of this specification is not implied. Exposure to the conditions in table below for extended periods may affect device reliability. Refer also to the STMicroelectronics SURE Program and other relevant quality document. Table 4. Symbol VCC -VCC - IGND IOUT - IOUT IIN ICSD DC supply voltage Reverse DC supply voltage DC reverse ground pin current DC output current Reverse DC output current DC input current DC current sense disable input current Absolute maximum ratings Parameter Value 41 0.3 200 Internally limited 30 -1 to 10 -1 to 10 200 VCC-41 +VCC 104 Unit V V mA A A mA mA mA V V mJ -ICSENSE DC Reverse CS pin current VCSENSE Current sense maximum voltage EMAX Maximum switching energy (single pulse) (L= 3mH; RL=0; Vbat=13.5V; Tjstart=150C; IOUT = IlimL(Typ.) ) 7/32 Electrical specifications Table 4. Symbol VN5050AJ-E Absolute maximum ratings Parameter Electrostatic discharge (Human Body Model: R=1.5k; C=100pF) - INPUT - CURRENT SENSE - CS_DIS - OUTPUT - VCC Charge device model (CDM-AEC-Q100-011) Junction operating temperature Storage temperature Value 4000 2000 4000 5000 5000 750 -40 to 150 -55 to 150 Unit V V V V V V C C VESD VESD Tj Tstg 2.2 Thermal data Table 5. Symbol Thermal data Parameter Max value 2.7 See Figure 29. Unit C/W C/W Rthj-case Thermal resistance junction-case (MAX) Rthj-amb Thermal resistance junction-ambient (MAX) 8/32 VN5050AJ-E Electrical specifications 2.3 Electrical characteristics Values specified in this section are for 8V < VCC < 36V; -40C < Tj < 150C, unless otherwise specified Table 6. Symbol VCC VUSD VUSDhyst Power section Parameter Operating supply voltage Undervoltage shutdown Undervoltage shutdown hysteresis On state resistance Clamp voltage Supply current IOUT=2A; Tj=25C IOUT=2A; Tj=150C IOUT=2A; VCC=5V; Tj=25C IS=20mA Off State; VCC=13V; Tj=25C; VIN=VOUT=VSENSE=VCSD=0V On State; VCC=13V; VIN=5V; IOUT=0A VIN=VOUT=0V; VCC=13V; Tj=25C VIN=VOUT=0V; VCC=13V; Tj=125C -IOUT=2A; Tj=150C 0 0 41 46 2(1) 1.5 0.01 Test conditions Min. Typ. Max. 4.5 13 3.5 0.5 50 100 65 52 5(1) 3 3 5 0.7 36 4.5 Unit V V V m m m V A mA A V RON Vclamp IS IL(off) VF Off state output current Output - VCC diode voltage 1. PowerMOS leakage included Table 7. Symbol td(on) td(off) Switching (VCC=13V, Tj=25C) Parameter Turn-on delay time Turn-off delay time Test conditions RL= 6.5 (see Figure 8.) RL= 6.5 (see Figure 8.) RL= 6.5 RL= 6.5 RL= 6.5 (see Figure 8.) RL= 6.5 (see Figure 8.) Min. Typ. 20 40 See Figure 20 See Figure 22 0.20 0.3 Max. Unit s s V/ s V/ s mJ mJ (dVOUT/dt)on Turn-on voltage slope (dVOUT/dt)off Turn-off voltage slope WON WOFF Switching energy losses during twon Switching energy losses during twoff 9/32 Electrical specifications Table 8. Symbol VIL IIL VIH IIH VI(hyst) VICL VCSDL ICSDL VCSDH ICSDH VN5050AJ-E Logic input Parameter Input low level voltage Low level input current Input high level voltage High level input current Input hysteresis voltage Input clamp voltage CS_DIS low level voltage Low level CS_DIS current CS_DIS high level voltage High level CS_DIS current VCSD=2.1V 0.25 ICSD=1mA ICSD=-1mA 5.5 -0.7 7 VCSD=0.9V 1 2.1 10 IIN=1mA IIN=-1mA VIN=2.1V 0.25 5.5 -0.7 0.9 7 VIN=0.9V 1 2.1 10 Test conditions Min. Typ. Max. 0.9 Unit V A V A V V V V A V A V V V VCSD(hyst) CS_DIS hysteresis voltage VCSCL CS_DIS clamp voltage Table 9. Symbol IlimH IlimL TTSD TR TRS THYST VDEMAG VON Protection and diagnostics(1) Parameter DC Short circuit current Test conditions VCC = 13V 5V TRS + 1 TRS + 5 135 1. To ensure long term reliability under heavy overload or short circuit conditions, protection and related diagnostic signals must be used together with a proper software strategy. If the device operates under abnormal conditions this software must limit the duration and number of activation cycles 10/32 VN5050AJ-E Table 10. Symbol K0 Electrical specifications Current sense (8V K1 IOUT/ISENSE dK1/K1 (1) IOUT=1A; VSENSE= 0.5V; Current sense ratio VCSD=0V; drift TJ=-40 C to 150 C IOUT=2A; VSENSE=4V; VCSD=0V; Tj=-40C...150C IOUT=2A; VSENSE=4V; VCSD=0V; Tj=25C...150C -10 +10 % 1770 2000 2310 1800 2000 2200 K2 IOUT/ISENSE dK2/K2(1) IOUT=2 A; VSENSE= 4 V; Current sense ratio VCSD=0V; drift TJ=-40 C to 150 C IOUT=4A; VSENSE=4V; VCSD=0V; Tj=-40C...150C IOUT=4A; VSENSE=4V; VCSD=0V; Tj=25C...150C -6 +6 % 1860 1970 2140 1870 1970 2120 K3 IOUT/ISENSE dK3/K3 (1) IOUT=4 A; VSENSE= 4 V; Current sense ratio VCSD=0V; drift TJ=-40 C to 150 C IOUT=0A; VSENSE=0V; VCSD=5V; VIN=0V; Tj=-40C...150C VCSD=0V; VIN=5V; Tj=-40C...150C IOUT=2A; VSENSE=0V; VCSD=5V; VIN=5V; Tj=-40C...150C -3 +3 % ISENSE0 Analog sense leakage current 0 0 1 2 A A 0 5 1 A V VSENSE Max analog sense output voltage Analog sense output voltage in overtemperature condition Analog sense output current in overtemperature condition IOUT=2A; VCSD=0V VSENSEH VCC=13V; RSENSE=10K 9 V ISENSEH VCC=13V, VSENSE=5V 8 mA VSENSE<4V, 0.5A 100 s 11/32 Electrical specifications Table 10. Symbol VN5050AJ-E Current sense (8V VSENSE<4V, 0.5A 20 s 80 300 s 60 s 100 250 s 1. Parameter guaranteed by design; it is not tested. Figure 4. INPUT CS_DIS Current sense delay characteristics LOAD CURRENT SENSE CURRENT tDSENSE2H tDSENSE1L tDSENSE1H tDSENSE2L 12/32 VN5050AJ-E Figure 5. Electrical specifications Delay response time between rising edge of ouput current and rising edge of current sense (CS enabled) VIN tDSENSE2H t IOUT IOUTMAX 90% IOUTMAX t ISENSE ISENSEMAX 90% ISENSEMAX t 13/32 Electrical specifications Figure 6. IOUT/ISENSE Vs. IOUT (see Table 10. for details) VN5050AJ-E Iout / Isense 2800 2600 max Tj = -40 C to 150 C 2400 2200 max Tj = 25 C to 150 C 2000 typical value 1800 min Tj = 25 C to 150 C 1600 min Tj = -40 C to 150 C 1400 1200 1 1,5 2 2,5 3 3,5 4 4,5 5 IOUT (A) Figure 7. Maximum current sense ratio drift vs load current dk/k(%) 15 10 5 0 -5 -10 -15 1 2 3 IOUT (A) 4 5 Note: Parameter guaranteed by design; it is not tested 14/32 VN5050AJ-E Table 11. Truth table INPUT L H L H L H L H H L H L OUTPUT L H L L L L L L L H H L Electrical specifications Conditions Normal operation Overtemperature Undervoltage Short circuit to GND (Rsc 10 m) Short circuit to VCC Negative output voltage clamp SENSE (VCSD=0V)(1) 0 Nominal 0 VSENSEH 0 0 0 0 if Tj < TTSD VSENSEH if Tj > TTSD 0 < Nominal 0 1. If the VCSD is high, the SENSE output is at a high impedance, its potential depends on leakage currents and external circuit Figure 8. Switching characteristics VOUT tWon 80% tWoff 90% dVOUT/dt(off) dVOUT/dt(on) tr 10% tf t INPUT td(on) td(off) t 15/32 Electrical specifications Figure 9. Output voltage drop limitation Vcc-Vout Tj=150oC Tj=25oC Tj=-40oC VN5050AJ-E Von Iout Von/Ron(T) 16/32 VN5050AJ-E Table 12. ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b(2) ISO 7637-2: 2004(E) Test pulse 1 2a 3a 3b 4 5b(2) III C C C C C C III -75V +37V -100V +75V -6V +65V Electrical specifications Electrical transient requirements Test levels IV -100V +50V -150V +100V -7V +87V Number of pulses or test times 5000 pulses 5000 pulses 1h 1h 1 pulse 1 pulse Test level results(1) IV C C C C C C Burst cycle/pulse repetition time 0.5 s 0.2 s 90 ms 90 ms 5s 5s 100 ms 100 ms Delays and Impedance 2 ms, 10 50 s, 2 0.1 s, 50 0.1 s, 50 100 ms, 0.01 400 ms, 2 1. The above test levels must be considered referred to VCC = 13.5V except for pulse 5b 2. Valid in case of external load dump clamp: 40V maximum referred to ground. Class C E Contents All functions of the device are performed as designed after exposure to disturbance. One or more functions of the device are not performed as designed after exposure to disturbance and cannot be returned to proper operation without replacing the device. 17/32 Electrical specifications Figure 10. Waveforms VN5050AJ-E NORMAL OPERATION INPUT CS_DIS LOAD CURRENT SENSE CURRENT UNDERVOLTAGE VUSDhyst VUSD VCC INPUT CS_DIS LOAD CURRENT SENSE CURRENT SHORT TO VCC INPUT CS_DIS LOAD VOLTAGE LOAD CURRENT SENSE CURRENT current power limitation limitation thermal cycling SHORTED LOAD NORMAL LOAD 18/32 VN5050AJ-E Electrical specifications 2.4 Electrical characteristics curves Figure 12. High level input current Figure 11. Off state output current TBD Figure 13. Input clamp voltage Figure 14. Input low level Figure 15. Input high level Figure 16. Input hysteresis voltage 19/32 Electrical specifications VN5050AJ-E Figure 17. On state resistance vs. Tcase Figure 18. On state resistance vs. VCC Figure 19. Undervoltage shutdown Figure 20. Turn-on voltage slope Figure 21. ILIMH Vs. Tcase Figure 22. Turn-off voltage slope TBD 20/32 VN5050AJ-E Electrical specifications Figure 23. CS_DIS high level voltage Figure 24. CS_DIS clamp voltage Figure 25. CS_DIS low level voltage 21/32 Application information VN5050AJ-E 3 Application information Figure 26. Application schematic +5V VCC Rprot CS_DIS Dld C Rprot Rprot CURRENT SENSE GND RSENSE Cext VGND RGND DGND INPUT OUTPUT . 3.1 GND protection network against reverse battery This section provides two solutions for implementing a ground protection network against reverse battery. 3.1.1 Solution 1: resistor in the ground line (RGND only). This can be used with any type of load. The following show how to dimension the RGND resistor: 1. 2. RGND 600mV / (IS(on)max) RGND (- CC) / (-IGND) V where -IGND is the DC reverse ground pin current and can be found in the absolute maximum rating section of the device datasheet. Power dissipation in RGND (when VCC<0 during reverse battery situations) is: PD= (-VCC)2/RGND This resistor can be shared amongst several different HSDs. Please note that the value of this resistor should be calculated with formula (1) where IS(on)max becomes the sum of the maximum on-state currents of the different devices. Please note that, if the microprocessor ground is not shared by the device ground, then the RGND will produce a shift (IS(on)max * RGND) in the input thresholds and the status output values. This shift will vary depending on how many devices are ON in the case of several high side drivers sharing the same RGND. 22/32 VN5050AJ-E Application information If the calculated power dissipation requires the use of a large resistor, or several devices have to share the same resistor, then ST suggests using solution 2 below. 3.1.2 Solution 2: diode (DGND) in the ground line. Note that a resistor (RGND=1k) should be inserted in parallel to DGND if the device drives an inductive load. This small signal diode can be safely shared amongst several different HSDs. Also in this case, the presence of the ground network will produce a shift (j600mV) in the input threshold and in the status output values if the microprocessor ground is not common to the device ground. This shift will not vary if more than one HSD shares the same diode/resistor network. 3.2 Load dump protection Dld is necessary (voltage transient suppressor) if the load dump peak voltage exceeds the VCC maximum DC rating. The same applies if the device is subject to transients on the VCC line that are greater than those shown in the ISO T/R 7637/1 table. 3.3 MCU I/O protection If a ground protection network is used and negative transients are present on the VCC line, the control pins will be pulled negative. ST suggests to insert a resistor (Rprot) in line to prevent the C I/O pins from latching up. The value of these resistors is a compromise between the leakage current of C and the current required by the HSD I/Os (Input levels compatibility) with the latch-up limit of C I/Os: -VCCpeak/Ilatchup Rprot (VOHC-VIH-VGND) / IIHmax Equation 1: For the following conditions: VCCpeak= - 100V Ilatchup 20mA VOHC 4.5V 5k Rprot 65k . Recommended values are: Rprot =10k CEXT=10nF , 23/32 Application information VN5050AJ-E 3.4 Maximum demagnetization energy (VCC = 13.5V) Figure 27. Maximum turn off current versus inductance 100 A A C C 10 B B I (A) 1 0,1 1 L (mH) 10 100 A: Tjstart = 150C single pulse B: Tjstart = 100C repetitive pulse C: Tjstart = 125C repetitive pulse VIN, IL Demagnetization Demagnetization Demagnetization t Note: Values are generated with RL =0 .In case of repetitive pulses, Tjstart (at beginning of each demagnetization) of every pulse must not exceed the temperature specified above for curves A and B. 24/32 VN5050AJ-E Package and PCB thermal data 4 4.1 Package and PCB thermal data PowerSSO-12 thermal data Figure 28. PowerSSO-12 PC Board Note: Layout condition of Rth and Zth measurements (PCB: Double layer, Thermal Vias, FR4 area= 77mm x 86mm,PCB thickness=1.6mm, Cu thickness=70 m (front and back side), Copper areas: from minimum pad lay-out to 8cm2). Figure 29. Rthj-amb Vs. PCB copper area in open box free air condition RTHj_amb(C/ W) 70 65 60 55 50 45 40 0 2 4 6 8 10 PCB Cu heatsink area (cm^ 2) 25/32 Package and PCB thermal data VN5050AJ-E Figure 30. PowerSSO-12 thermal impedance junction ambient single pulse ZTH (C/W) 100 Footprint 2 cm2 8 cm2 10 1 0,1 0,0001 0,001 0,01 0,1 1 Time (s) 10 100 1000 Equation 2: pulse calculation formula Z TH =R TH +Z THtp ( 1 - ) where = tP/T Figure 31. Thermal fitting model of a single channel HSD in PowerSSO-12(a) a. The fitting model is a semplified thermal tool and is valid for transient evolutions where the embedded protections (power limitation or thermal cycling during thermal shutdown) are not triggered 26/32 VN5050AJ-E Table 13. Thermal parameter Footprint 0.6 2.8 6.5 10 22 26 0.001 0.0025 0.022 0.2 0.27 3 Package and PCB thermal data Area/island (cm2) R1 (C/W) R2 (C/W) R3 (C/W) R4 (C/W) R5 (C/W) R6 (C/W) C1 (W.s/C) C2 (W.s/C) C3 (W.s/C) C4 (W.s/C) C5 (W.s/C) C6 (W.s/C) 2 8 10 15 20 9 10 15 0.1 0.8 6 0.1 1 9 27/32 Package information VN5050AJ-E 5 5.1 Package information ECOPACK(R) packages In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second-level interconnect. The category of Second-Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com. 5.2 Package mechanical data Figure 32. PowerSSO-12TM package dimensions 28/32 VN5050AJ-E Table 14. PowerSSO-12TM mechanical data Millimeters Symbol Min A A1 A2 B C D E e H h L k X Y ddd 5.800 0.250 0.400 0 2.200 2.900 1.250 0.000 1.100 0.230 0.190 4.800 3.800 0.800 Typ Package information Max 1.620 0.100 1.650 0.410 0.250 5.000 4.000 6.200 0.500 1.270 8 2.800 3.500 0.100 29/32 Package information VN5050AJ-E 5.3 Packing information Figure 33. PowerSSO-12 tube shipment (no suffix) B C A Base Q.ty Bulk Q.ty Tube length ( 0.5) A B C ( 0.1) All dimensions are in mm. 100 2000 532 1.85 6.75 0.6 Figure 34. PowerSSO-12 tape and reel shipment (suffix "TR") REEL DIMENSIONS Base Q.ty Bulk Q.ty A (max) B (min) C ( 0.2) F G (+ 2 / -0) N (min) T (max) 2500 2500 330 1.5 13 20.2 12.4 60 18.4 TAPE DIMENSIONS According to Electronic Industries Association (EIA) Standard 481 rev. A, Feb. 1986 Tape width Tape Hole Spacing Component Spacing Hole Diameter Hole Diameter Hole Position Compartment Depth Hole Spacing All dimensions are in mm. W P0 ( 0.1) P D ( 0.05) D1 (min) F ( 0.1) K (max) P1 ( 0.1) 12 4 8 1.5 1.5 5.5 4.5 2 End Start Top cover tape No components 500mm min Empty components pockets saled with cover tape. User direction of feed 500mm min Components No components 30/32 VN5050AJ-E Revision history 6 Revision history Table 15. Date 24-Jan-2006 Jul-2006 Document revision history Revision 1 2 Initial release. Minor updates. Document reformatted. Table 14: PowerSSO-12TM mechanical data, X and Y values (slug dimensions) updated. Table 10: Current sense (8V 3 13-Sep-2007 4 31/32 VN5050AJ-E Please Read Carefully: Information in this document is provided solely in connection with ST products. STMicroelectronics NV and its subsidiaries ("ST") reserve the right to make changes, corrections, modifications or improvements, to this document, and the products and services described herein at any time, without notice. All ST products are sold pursuant to ST's terms and conditions of sale. Purchasers are solely responsible for the choice, selection and use of the ST products and services described herein, and ST assumes no liability whatsoever relating to the choice, selection or use of the ST products and services described herein. No license, express or implied, by estoppel or otherwise, to any intellectual property rights is granted under this document. If any part of this document refers to any third party products or services it shall not be deemed a license grant by ST for the use of such third party products or services, or any intellectual property contained therein or considered as a warranty covering the use in any manner whatsoever of such third party products or services or any intellectual property contained therein. UNLESS OTHERWISE SET FORTH IN ST'S TERMS AND CONDITIONS OF SALE ST DISCLAIMS ANY EXPRESS OR IMPLIED WARRANTY WITH RESPECT TO THE USE AND/OR SALE OF ST PRODUCTS INCLUDING WITHOUT LIMITATION IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE (AND THEIR EQUIVALENTS UNDER THE LAWS OF ANY JURISDICTION), OR INFRINGEMENT OF ANY PATENT, COPYRIGHT OR OTHER INTELLECTUAL PROPERTY RIGHT. UNLESS EXPRESSLY APPROVED IN WRITING BY AN AUTHORIZED ST REPRESENTATIVE, ST PRODUCTS ARE NOT RECOMMENDED, AUTHORIZED OR WARRANTED FOR USE IN MILITARY, AIR CRAFT, SPACE, LIFE SAVING, OR LIFE SUSTAINING APPLICATIONS, NOR IN PRODUCTS OR SYSTEMS WHERE FAILURE OR MALFUNCTION MAY RESULT IN PERSONAL INJURY, DEATH, OR SEVERE PROPERTY OR ENVIRONMENTAL DAMAGE. ST PRODUCTS WHICH ARE NOT SPECIFIED AS "AUTOMOTIVE GRADE" MAY ONLY BE USED IN AUTOMOTIVE APPLICATIONS AT USER'S OWN RISK. Resale of ST products with provisions different from the statements and/or technical features set forth in this document shall immediately void any warranty granted by ST for the ST product or service described herein and shall not create or extend in any manner whatsoever, any liability of ST. ST and the ST logo are trademarks or registered trademarks of ST in various countries. Information in this document supersedes and replaces all information previously supplied. The ST logo is a registered trademark of STMicroelectronics. All other names are the property of their respective owners. (c) 2007 STMicroelectronics - All rights reserved STMicroelectronics group of companies Australia - Belgium - Brazil - Canada - China - Czech Republic - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan Malaysia - Malta - Morocco - Singapore - Spain - Sweden - Switzerland - United Kingdom - United States of America www.st.com 32/32 |
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