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| MD1811 High Speed Quad MOSFET Driver Features 6ns rise and fall time 2 A peak output source/sink current 1.2V to 5V input CMOS compatible 5V to 12V total supply voltage Smart Logic threshold Low jitter design Quad matched channels Drives two P- and two N-channel MOSFETs Outputs can swing below ground Low inductance quad flat no-lead package High-performance thermally-enhanced General Description The Supertex MD1811 is a high speed, quad MOSFET driver designed to drive high voltage P and N-channel MOSFETs for medical ultrasound applications and other applications requiring a high output current for a capacitive load. The high-speed input stage of the MD1811 can operate from a 1.2 to 5.0 volt logic interface with an optimum operating input signal range of 1.8 to 3.3 volts. An adaptive threshold circuit is used to set the level translator switch threshold to the average of the input logic 0 and logic 1 levels. The input logic levels may be ground referenced, even though the driver is putting out bipolar signals. The level translator uses a proprietary circuit, which provides DC coupling together with high-speed operation. The output stage of the MD1811 has separate power connections enabling the output signal L and H levels to be chosen independently from the supply voltages used for the majority of the circuit. As an example, the input logic levels may be 0 and 1.8 volts, the control logic may be powered by +5 and -5 volts, and the output L and H levels may be varied anywhere over the range of -5 to +5 volts. The output stage is capable of peak currents of up to 2 amps, depending on the supply voltages used and load capacitance present. The OE pin serves a dual purpose. First, its logic H level is used to compute the threshold voltage level for the channel input level translators. Secondly, when OE is low, the outputs are disabled, with the A & C output high and the B & D output low. This assists in properly precharging the AC coupling capacitors that may be used in series in the gate drive circuit of an external PMOS and NMOS transistor pair. Applications Medical ultrasound imaging Piezoelectric transducer drivers Nondestructive evaluation PIN diode driver Clock driver/buffer High speed level translator Typical Application Circuit +10V 0.22 F +10V 0.47 F VDD VH OUTA 10nF INB OUTB Supertex TC6320 10nF +100V 1F ENAB +PLS1 #1 3.3V CMOS Logic Inputs -PLS1 OE INA To Piezoelectric Transducer #1 -100V 1F +PLS2 #2 -PLS2 INC OUTC +100V 1F IND GND VSS OUTD VL 10nF To Piezoelectric Transducer #2 Supertex MD1811 10nF -100V Supertex TC6320 1F MD1811 Ordering Information Package Options DEVICE MD1811 JA 16-Lead QFN 4x4mm body, 1.0mm height (max), 0.65mm pitch MD1811K6-G 45C/W (1oz. 4-layer 3x4inch PCB) -G indicates package is RoHS compliant (`Green') Absolute Maximum Ratings Parameter VDD-VSS, Logic supply voltage VH, Output high supply voltage VL, Output low supply voltage VSS, Low side supply voltage Logic Input levels Maximum junction temperature Storage temperature Soldering temperature Package power dissipation Value -0.5V to +13.5V VL-0.5V to VDD+0.5V VSS-0.5V to VH+0.5V -7V to +0.5V VSS-0.5V to VSS+7V +125C -65C to 150C 235C 2.2W Product Marking 1811 YWLL Y = Last Digit of Year Sealed W = Code for Week Sealed L = Lot Number = "Green" Packaging 16-Lead QFN Package Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. DC Electrical Characteristics (V Sym. VDD-VSS VSS VH VL IDDQ IHQ IDD IH VIH VIL IIH IIL VIH VIL RIN CIN Parameter Logic supply voltage Low side supply voltage Output high supply voltage Output low supply voltage VDD quiescent current VH quiescent current VDD average current VH average current Input logic voltage high Input logic voltage low Input logic current high Input logic current low OE Input logic voltage high OE Input logic voltage low Input logic impedance to GND Logic input capacitance H = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25C) Min. 4.5 -5.5 VSS+2 VSS VOE-0.3 0 1.2 0 12 - Typ. 0.8 Max. 13 0 VDD VDD-2 10 Units V V V V mA A mA mA V V A A V V K pF Conditions ----No input transitions, OE = 1 One channel on at 5.0Mhz, No load 8.0 26 20 5.0 5.0 0.3 1.0 1.0 5 0.3 30 10 For logic inputs INA, INB, INC, and IND For logic input OE -- 2 MD1811 Outputs (V Sym. RSINK RSOURCE ISINK ISOURCE H = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25C) Parameter Output sink resistance Output source resistance Peak output sink current Peak output source current Min. - Typ. 2.0 2.0 Max. 12.5 12.5 - Units A A Conditions ISINK = 50mA ISOURCE = 50mA --- AC Electrical Characteristics (V Sym tirf tPLH tPHL tPOE tr tf l tr - tf l l tPLHtPHL l tdm Parameter Input or OE rise & fall time Propagation delay when output is from low to high Propagation delay when output is from high to low Propagation delay OE to output Output rise time Output fall time Rise and fall time matching Propagation low to high and high to low matching Propagation delay matching H = VDD = 12V, VL = VSS = GND = 0V, VOE = 3.3V, TJ = 25C) Min - Typ 7.0 7.0 9.0 6.0 6.0 1.0 1.0 2.0 Max 10 - Units ns ns ns ns ns ns ns Conditions Logic input edge speed requirement CLOAD = 1000pF, see timing diagram Input signal rise/fall time 2ns for each channel ns ns Device to device delay match Logic Truth Table Logic Inputs OE H H H H L OE H H H H L INA L L H H X INC L L H H X INB L H L H X IND L H L H X OUTA VH VH VL VL VH OUTC VH VH VL VL VH Output OUTB VH VL VH VL VL OUTD VH VL VH VL VL 3 MD1811 Timing Diagram and VTH / VOE Curve 1.8V VTH vs VOE VTH VOE/2 2.0 IN 0V 50% 5 0% 1.5 t PLH 12V 90 % 10% tPHL 9 0% 1.0 0.6V 0.5 10% OUT 0V 0 tr tf 0 1.0 2.0 3.0 4.0 5.0 VOE Application Information For proper operation of the MD1811, low inductance bypass capacitors should be used on the various supply pins. The GND pin should be connected to the logic ground. The INA, INB INC, IND, and OE pins should be connected to a logic source with a swing of GND to VLL, where VLL is 1.2 to 5.0 volts. Good trace practices should be followed corresponding to the desired operating speed. The internal circuitry of the MD1811 is capable of operating up to 100MHz, with the primary speed limitation being the loading effects of the load capacitance. Because of this speed and the high transient currents that result with capacitive loads, the bypass capacitors should be as close to the chip pins as possible. Unless the load specifically requires bipolar drive, the VSS, and VL pins should have low inductance feed-through connections directly to a ground plane. If these voltages are not zero, then they need bypass capacitors in a manner similar to the positive power supplies. The power connection VDD should have a ceramic bypass capacitor to the ground plane with short leads and decoupling components to prevent resonance in the power leads. The voltages of VH and VL decide the output signal levels. These two pins can draw fast transient currents of up to 2A, so they should be provided with an appropriate bypass capacitor located next to the chip pins. A ceramic capacitor of up to 1.0F may be appropriate, with a series ferrite bead to prevent resonance in the power supply lead coming to the capacitor. Pay particular attention to minimizing trace lengths, current loop area and using sufficient trace width to reduce inductance. Surface mount components are highly recommended. Since the output impedance of this driver is very low, in some cases it may be desirable to add a small series resistance in series with the output signal to obtain better waveform transitions at the load terminals. This will of course reduce the output voltage slew rate at the terminals of a capacitive load. Pay particular attention that parasitic couplings are minimized from the output to the input signal terminals. The parasitic feedback may cause oscillations or spurious waveform shapes on the edges of signal transitions. Since the input operates with signals down to 1.2V even small coupled voltages may cause problems. Use of a solid ground plane and good power and signal layout practices will prevent this problem. Be careful that a circulating ground return current from a capacitive load cannot react with common inductance to cause noise voltages in the input logic circuitry. 4 MD1811 Simplified Block Diagram VDD VH OE INA MD1811 OUTA OUTB INB OUTC INC OUTD IND GND VSS VL Detailed Block Diagram OE Level Shifter Level Shifter V DD VH INA OUTA VSS VDD VL VH INB Level Shifter OUTB VSS VDD VL VH INC Level Shifter OUTC V SS VDD VL VH IND Level Shifter OUTD SUB GND VSS VL 5 MD1811 Pin Description Pin # 1 5 6 15 2 4 3 7 Function INB INC IND INA VL GND VSS Supply voltage for N-channel output stage. Logic input ground reference. Low side supply voltage. VSS is also connected to the IC substrate. It is required to connect to the most negative potential of voltage supplies and powered-up first. Output driver. Swings from VH to VL. Intended to drive the gate of an externel Nchannel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTD will swing to VL turning off the external N-channel MOSFET. Output driver. Swings from VH to VL. Intended to drive the gate of an externel P-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTC will swing to VH turning off the external P-channel MOSFET. Output driver. Swings from VH to VL. Intended to drive the gate of an externel Nchannel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTB will swing to VL turning off the external N-channel MOSFET. Output driver. Swings from VH to VL. Intended to drive the gate of an externel P-channel MOSFET via a series capacitor. When OE is low, the output is disabled. OUTA will swing to VH turning off the external P-channel MOSFET. Supply voltage for P-channel output stage. High side supply voltage. Output enable logic input. When OE is high, (VOE+VGND)/2 sets the threshold transition between logic level high and low. When OE is low, all outputs are at high impedance. Keep OE low until IC powered up. The IC substrate is internally connected to the thermal pad. Thermal Pad and VSS must be connected externally. Logic input. Input logic high will cause the output to swing to VH. Input logic low will cause the output to swing to VL. Keep all logic inputs low until IC powered up. Description 8 OUTD 9 OUTC 12 OUTB 13 10 11 14 16 OUTA VH VDD OE Substrate 6 MD1811 16-Lead QFN Package Outline (K6) 4x4mm body, 1.00mm height (max), 0.65mm pitch 16 D D2 16 Note 1 (Index Area D/2 x E/2) 1 Note 1 (Index Area D/2 x E/2) E e 1 E2 b View B Top View Bottom View Note 3 L A A3 A1 Seating Plane L1 Note 2 Side View View B Notes: 1. Details of Pin 1 identifier are optional, but must be located within the indicated area. The Pin 1 identifier may be either a mold, or an embedded metal or marked feature. 2. Depending on the method of manufacturing, a maximum of 0.15mm pullback (L1) may be present. 3. The inner tip of the lead may be either rounded or square. Symbol MIN Dimension (mm) NOM MAX A 0.80 0.90 1.00 A1 0.00 0.02 0.05 A3 0.20 REF b 0.25 0.30 0.35 D 3.85 4.00 4.15 D2 2.40 2.80 E 3.85 4.00 4.15 E2 2.40 2.80 e 0.65 BSC L 0.30 0.40 0.50 L1 0.15 0O 14O JEDEC Registration MO-220, Variation VGGC-3, Issue K, June 2006. Drawings not to scale. Doc.# DSFP - MD1811 NR40907 7 |
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