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8-Bit 12-Ch I/O DAC
PT8146
DESCRIPTION
The PT8146 is an 8-bit D/A converter with 12 built-in channels. Each of the 12 analog outputs have a built-in OP amplifier with large current drive capability. The data input/output format is chip select (/CS) with serial bus connection available while a built-in 12-bit I/O expander enables serial-parallel conversion (8 of the 12 bits can also be used for analog output).
FEATURES
* * * * * * * * * * * * Ultra compact package Ultra low power consumption (1.2mW/chl: typical) Built-in 12-channel R-2R type 8-bit D/A converter Built-in 12-bit I/O expander (8 bits also function as analog output) Built-in analog output amplifier (sink current 1.0mA maximum, source current 1.0mA maximum) Built-in power-on detection circuit (initialized at detection of VccD power-on) MCU interface compatible with 3V to 5V systems Power divided into MCU interface power supply (VccD) and OP amplifier power supply (VccA), D/A converter power supply (VccD) Analog output capability from 0 V to VccA Serial data I/O operates to maximum of 2.5MHz (in cascade connection, up to 2.5MHz when VccD=5V, up to 1.5Mhz when VccD=3V) CMOS process Available in 24 pin, SSOP Package
APPLICATIONS
* Microcontroller port expansion * Electronic level adjustment * Replacement of semi-fixed resistance for tuning
PT8146 V1.1
-1-
February, 2006
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8-Bit 12-Ch I/O DAC
PT8146
BLOCK DIAGRAM
/CS SI CLK VCCD DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 16-bit shift register and controller SO
D0 D1 DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 I/O Expander D2 D3
DF DE
D5 D4 12
DF
DF D8 D8
DF
DF D8 D8
8-bit latch DF D8 VDD
8-bit latch DF D8
8-bit latch DF D8
8-bit latch
GND
DF
D8
R-2R rudder circuit
R-2R rudder circuit
R-2R rudder circuit
R-2R rudder circuit
VCCA
-
+
-
+
-
+
-
+
8
AO1
AO4
D11/AO5
D4/AO12
PT8146 V1.1
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8-Bit 12-Ch I/O DAC
PT8146
PIN CONFIGURATION
AO1 AO2 AO3 AO4 D11/AO5 D10/AO6 D9/AO7 D8/AO8 D7/AO9 D6/AO10 D5/AO11 D4/AO12 1 2 3 4 5 6 PT8146 7 8 9 10 11 12 18 17 16 15 14 13 D0 D1 D2 D3 VCCD VDD 24 23 22 21 20 19 GND VCCA /CS SO SI CLK
PT8146 V1.1
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8-Bit 12-Ch I/O DAC
PT8146
PIN DESCRIPTION
Pin Name AO1 to AO4 Description Pin No. D/A converter analog output pins (VDD to GND output). 1 to 4 (Default: output #00 setting level) These pins may be used as either I/O expander parallel input/output 5 to 12 (VCCA/GND output 0.5 VCCA/0.2 VCCA input) or as D/A converter analog output (VDD to GND output). Pin status is controlled by input data. See "Data Configuration". (Default: Input mode, Hi-Z state) D/A converter reference power pin. 13 MCU interface power supply pin (power supply for I/O expander) 14 I/O expander parallel input/output pins. 15 to 18 (VCCD/GND output: When VCCD 4.0 V, 0.5 VCCD/0.2 VCCD input, When VCCD < 4.0 V, 2 V/0.2 VCCD input) Pin status is controlled by input data See "Data Configuration." (Default: Input mode, Hi-Z state) Shift clock signal input pin. 19 When CS = "L", SI data is loaded into the shift register at the rising edge of the shift clock. Data input pin (serial input pin). 20 Used for 16-bit serial data input. Data output pin (serial output pin). 21 The first bit (LSB) data of the 16-bit shift register is output simultaneously with the falling edge of the shift clock. When /CS output = "H", this pin goes to high impedance state. Chip select signal input pin. 22 Input to shift registers is enabled when the/ CS signal falling edges. Shift register contents can be executed when the /CS signal rising edges. Analog unit power supply pin (OP amplifier power supply). 23 Common GND pin 24
D11/AO5 to D4/AO12 VDD*1 VCCD*1
D3 to D0
CLK*2 SI*2
SO
/CS*2 VCCA*1 GND
*1: Be sure that VCCA VCCD, and that VCCA VDD. *2: Do not leave this pin in floating state.
PT8146 V1.1
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8-Bit 12-Ch I/O DAC
PT8146
DATA CONFIGURATION
1. DATA CONFIGURATION
MSB (last) DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 LSB (first) D0
Setting data
Channel select
2. CHANNEL SELECT
D3 0 0 0 to 1 1 1 1 1 D2 0 0 0 to 0 1 1 1 1 D1 0 0 1 to 1 0 0 1 1 D0 0 1 0 to 1 0 1 0 1 Function Don't care/special function AO1 selected AO2 selected to AO11 selected AO12 selected I/O expander (serial parallel) I/O expander (parallel serial) Expander Status Register (ESR)
PT8146 V1.1
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8-Bit 12-Ch I/O DAC
PT8146
3. SETTING DATA
DON'T CARE/SPECIAL FUNCTION (CHANNEL SELECT = "0000")
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 Function x x x x x x x x 0 0 0 0 Don't care to to to to to to to to to to to to Don't care x x x x x x x x 1 0 1 1 Don't care 0 0 0 0 0 0 0 0 1 1 0 0 GND (all channels) 0 0 0 0 0 0 0 1 1 1 0 0 VDD/256 x 1 (all channels) 0 0 0 0 0 0 1 0 1 1 0 0 VDD/256 x 2 (all channels) to to to to to to to to to to to to to 1 1 1 1 1 1 1 0 1 1 0 0 VDD/256 x 254 (all channels) 1 1 1 1 1 1 1 1 1 1 0 0 VDD/256 x 255 (all channels) x x x x x x x x 1 1 0 1 Hi-Z (I/O expander state)* x x x x x x x x 1 1 1 0 Reset (state when power is ON) x x x x x x x x 1 1 1 1 Don't care x: Don't care *: Hi-Z output on all channels of AO5 through AO12
D/A CONVERTER (CHANNEL SELECT = "0001" TO "1100")
DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 Function 0 0 0 0 0 0 0 0 0 0 0 0 GND 0 0 0 0 0 0 0 1 0 0 0 0 VDD/256 x 1 0 0 0 0 0 0 1 0 0 0 0 0 VDD/256 x 2 0 0 0 0 0 0 1 1 0 0 0 0 VDD/256 x 3 to to to to to to to to to to to to to 1 1 1 1 1 1 0 1 0 0 0 0 VDD/256 x 253 1 1 1 1 1 1 1 0 0 0 0 0 VDD/256 x 254 1 1 1 1 1 1 1 1 0 0 0 0 VDD/256 x 254 x x x x x x x x 0 0 0 1 Hi-Z (I/O expander state)* x x x x x x x x 0 0 1 0 Don't care to to to to to to to to to to to to Don't care x x x x x x x x 1 1 1 1 Don't care x: Don't care *: Only AO5 through AO12 output is valid
PT8146 V1.1 -6February, 2006
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8-Bit 12-Ch I/O DAC I/O EXPANDER (CHANNEL SELECT = "1101"): SERIAL PARALLEL CONVERSION
PT8146
Performs parallel conversion of data bits D4 to DF for output on pins D0 to D11. Note that only those pins designated for output in the ESR (expander status register) are output.
Shift register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Parallel I/O pins (output state) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
I/O EXPANDER (CHANNEL SELECT = "1110"): PARALLEL SERIAL CONVERSION
Writes data from D0 to D11 pins to bits D4 to DF in the shift register. Data is output to the SO pin on the shift clock (CLK) signal. (The first 4 bits output data D0 to D3, so the converted output should be read as data bits 5 through 16.) Note that the data value is "0" for pins designated for output in the ESR (expander status register) as well as analog output pins.
Shift register DF DE DD DC DB DA D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
Parallel I/O pins (output state) D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
PT8146 V1.1
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8-Bit 12-Ch I/O DAC EXPANDER STATUS REGISTER (CHANNEL SELECT = "1111")
S h ift re g is te r DF DE DD DC DB DA D9 D8 D7 D6 D5 D4
PT8146
ESR
D 11
D 10
D9
D8
D7
D6
D5
D4
D3
D2
D1
D0
T h is re g is te r s e ts th e s ta tu s o f e a c h p in .
Setting "0" "1"
Pin Status Input standby status (Hi-Z output) D11 to D4 pins for analog output should be set to "0". Output state
Note: After power VCCD is turned on, the state of pins and registers is as follows: Pin AO1 to AO4 D11/AO5 to D4/AO12 D3 to D0 Pin Shift register D/A register Parallel output register Expander Status Register (ESR) "L" output Hi-Z state (input state) Hi-Z state (input state) State Bits DF to D8 are "0", and D7 to D0 are not defined (retain prior status) All reset to "0" Not defined (retain prior state) All reset to "0" State
ESR settings have priority in determining pin states. Switching between input standby state and analog output state is enabled even when the ESR value is "1". When the ESR value returns to "0", the pin returns to its previously defined state. In input standby state with AO set for Hi-Z output, the AO output setting can be used for transitions to AO output state.
PT8146 V1.1
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February, 2006
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8-Bit 12-Ch I/O DAC
PT8146
SPECIFICATIONS
ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input voltage 1 Output voltage 1 Input voltage 2 Output voltage 2 Power consumption Operating temperature Storage temperature * : VCCA VCCD, VCCA VDD Symbol VCCA VCCD VDD VIN1 VOUT1 VIN2 VOUT2 PD Topr Tstg Conditions Based on GND (TA=+25) SI, CLK, /CS, SO, D1 to D3 D4 to D11 Min. -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -0.3 -40 -65 Ratings Max. +7.0 VCCA* VCCA* VCCD + 0.3 VCCD + 0.3 VCCA + 0.3 VCCA + 0.3 250 +85 +150 Unit V V V V V V V mW
RECOMMENDED OPERATING CONDITIONS
Parameter Symbol VCCA VCCD VDD GND IAL IAH COL Topr Conditions VCCA VCCD VCCA VCCD Source current Sink current Min. 4.5 2.7 2.0 -40 Ratings Typ. Max. 5.0 5.5 VCCA VCCA 0 1.0 1.0 1.0 +85 Unit V V V V mA mA F
Power supply voltage
Analog output current Oscillation limit output capacity Operation temperature
PT8146 V1.1
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8-Bit 12-Ch I/O DAC
PT8146
ELECTRICAL CHARACTERISTICS
DC CHARACTERISTICS
DIGITAL SECTION
(VCCD VCCA, Ta=-20 to +85) Parameter Power supply voltage Power supply current Standby current Input leak current "H" level input voltage "L" level input voltage High-impedance leak current "H" level output voltage "L" level output voltage Symbol Pin name VCCD ICCD ICCS IILK1 VIH1 VIL1 IOLK VOH1 VOL1 CLK, SI, /CS, D0 to D3 VCCD Conditions Ratings Min. Typ. 2.7 5.0 0.2 Max. 5.5 0.5 +10 +10 0.2 x VCCD +10 0.4 Unit V mA A A V V V A V V
CLK=1MHz, (Unloaded) CLK, SI, /CS Stop -10 Vin=VCCD or GND Vin=0 to VCCD -10 VCCD 4.0 V 0.5 x VCCD VCCD < 4.0 V 2.0 Vin=0 to VCCD IOH=-0.4mA IOL=2.5mA -10
SO SO, D0 to D3
VCCD - 0.4 -
D/A CONVERTER SECTION
(VCCA=5V10%, Ta=-20 to +85) Parameter Power supply voltage Power supply current Resolution Monotonic increase Nonlinearity error Differential linearity error Symbol VDD IDD Res Rem LE DLE Pin name VDD Conditions VDD VCCA VDD VCCA Ratings Unit Min. Typ. Max. 2.0 5.0 5.5 V 1.2 2.5 mA 8 bits 8 bits -1.5 +1.5 LSB -1.0 +1.0 LSB
Unload AO1 to AO12 VDD=VCCA - 0.1 V Digital value: #06 to #FF
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8-Bit 12-Ch I/O DAC
PT8146
Nonlinearity error:
Analog output
Differential linearity error:
Deviation (error) in input/output curves with respect to an ideal straight line connecting output voltage at "06" and output voltage at "FF". Deviation (error) in amplification with respect to theoretical increase in amplification per 1-bit increase in digital value.
Ideal straight line VAOH
Non-linearity error
VAOL
#06
Digital setting Note: The value of VAOH and VDD, and the value of VAOL and GND are not necessarily equivalent.
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8-Bit 12-Ch I/O DAC OPERATIONAL AMPLIFIER / ANALOG OUTPUT SECTION
(VDD=VCCA, Ta=-20 to +85) Parameter Power supply voltage Power supply current Input leak current "H" level digital input voltage "L" level digital input voltage "H" level digital output voltage "L" level digital output voltage Analog output minimum voltage 1 Analog output minimum voltage 2 Analog output minimum voltage 3 Analog output minimum voltage 4 Analog output minimum voltage 5 Analog output maximum voltage 1 Analog output maximum voltage 2 Analog output maximum voltage 3 Analog output maximum voltage 4 Analog output maximum voltage 5 Symbol Pin name VCCA ICCA IILK2 VIH2 VIL2 VOH2 VOL2 VAOL1 VAOL2 VAOL3 VAOL4 VAOL5 VAOH1 VAOH2 VAOH3 VAOH4 VAOH5 AO1 to AO12 AO1 to AO12 AO1 to AO12 D4 to D11 VCCA Conditions #80 setting (Unloaded) Vin = 0 to VCCA IOH = -0.4 mA IOL = 2.5 mA IAL = 0 mA #00 setting IAL = 0.5 mA #00 setting IAH = 0.5 mA #00 setting IAL = 1.0 mA #00 setting IAH = 1.0 mA #00 setting IAL = 0 mA #FF setting IAL = 0.5 mA #FF setting IAH = 0.5 mA #FF setting IAL = 1.0 mA #FF setting IAH = 1.0 mA #FF setting Min. 4.5 -10 0.5 x VCCA VCCA - 0.4 GND -0.2 GND -0.3 GND VCCA - 0.1 VCCA - 0.2 VCCA - 0.2 VCCA - 0.3 VCCA - 0.3 Value Typ. 5.0 1.0 GND GND VCCA VCCA
PT8146
Max. 5.5 3.7 +10 0.2 x VCCA 0.4 0.1 0.2 0.2 0.3 0.3 VCCA VCCA VCCA + 0.2 VCCA VCCA + 0.3
Unit V mA A V V V V V V V V V V V V V V
Note: IAH: Analog output sink current IAL: Analog output source current
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8-Bit 12-Ch I/O DAC
PT8146
AC CHARACTERISTICS
FOR OPERATION AT VCCD = 5.0 V
(VDD=VCCA=5.0V, Ta=-20 to +85) Parameter Clock "L" level pulse width Clock "H" level pulse width Clock rise time Clock fall time Serial input setup time Serial input hold time Serial output delay time CS input setup time CS hold time CS "H" level hold time Data ouput enable time Data ouput float time Parallel input setup time Parallel input hold time Parallel ouput delay time Analog output delay time Power supply rise time Power-on reset non-startup power supply variation Symbol tCKL tCKH tCr tCf tSSU tSHD tSOD tCSU tCCH tCSH tSO tSOZ tPSU tPHD tPOD tAOD tR VR Conditions -See "Load condition 1" See "Load condition 1" See "Load condition 2" Value
Min. Typ. Max.
Unit ns ns ns ns ns ns ns ns ns ns ns ns ns ns ns s ms V/s
200 200 30 60 0 100 200 100 30 60 -10
80 100 30 -
200 200 170 200 200 170 100 50 10
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8-Bit 12-Ch I/O DAC FOR OPERATION AT VCCD = 3.0 V *1
Parameter Serial output delay time Parallel output delay time Symbol tSOD tPOD Conditions See "Load condition 1" *2 See "Load condition 2" *3 Min. 0 -
PT8146
Value Typ. Max. 120 300 120 300
Unit ns ns
*1: Items not listed are identical to characteristics for VCCD = 5.0 V. *2: Cascade connection enable at 1.5 MHz. *3: Applied to D0 to D3 operation at VCCD Load Conditions:
PT8146 V1.1
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8-Bit 12-Ch I/O DAC INPUT/OUTPUT TIMING (/CS METHOD)
tCr CLK tCKH tCf
PT8146
tCKL
SI
tSSU
tSHD
tCSH
tCSU /CS tSO tSOD tSOD
tCCH tSOZ
tPSU
tPHD
D0 to D11 (For input)
tPOD
D0 to D11 (For output)
tAOD 90% AO1 to AO12 10%
The decision level for CLK, SI, /CS, SO, and D0 to D3 is 80% and 20% of VCCD. The decision level for D4 to D11 is 80% and 20% of VCCA, and for AO1 to AO12 is 90% and 10% of VCCA.
PT8146 V1.1 - 15 February, 2006
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8-Bit 12-Ch I/O DAC POWER SUPPLY TIMING
Power-On Timing
tR
PT8146
2.0 V
0.2 V VCCD
Power-On Reset Non-Startup Supply Variation
Upper limit, 5V
V
V
T 2.7V, lower limit
T
VR =
DV DT
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8-Bit 12-Ch I/O DAC
PT8146
ANALOG OUTPUT NOISE CHARACTERISTIC
(VDD=VCCD=VCCA=5.0V, Ta=+25) Parameter Digital supply noise reduction ratio Analog supply noise reduction ratio D/A supply noise reduction ratio Operating noise Symbol Conditions Value Measurement Unit Condition Min. Typ. Max. 1 1 1 20 20 0 dB dB dB
PSRD fNOISE=1KHz PSRA fNOISE=1KHz PSRDA fNOISE=1KHz During serial transfer During analog operation During Hi-Z commands See "Operating Noise VN1" Serial parallel conversion See "I/O Expander Operating Noise 1 VN2" During digital-only pin operations During parallel serial conversion ESR setting During digital input/digital output switching During serial -> parallel conversion See "I/O Expander Operating Noise 2 VN3" During digital/analog capable pin operation ESR setting During digital output/digital output switching
VN1
2
-30
-
30
mV
I/O expander operating noise 1
VN2
2
-30
-
30
mV
I/O expander operating noise 2
VN3
2
-0.1
-
0.1
V
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8-Bit 12-Ch I/O DAC MEASUREMENT CONDITION 1
PT8146
MEASUREMENT CONDITION 2
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8-Bit 12-Ch I/O DAC
PT8146
ANALOG OUTPUT NOISE DESCRIPTION
OUTPUT NOISE VN1
Noise to analog output during serial data transfer, analog operation, Hi-Z commands.
CLK
SI Analog operation commands, Hi-Z commands CS
AOX
Analog output
D11/AO5 to D0/AO12 AO1 to AO12 *: Hi-Z state = digital input state
Digital input* VN1 VN1
Analog output
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8-Bit 12-Ch I/O DAC I/O EXPANDER OPERATION NOISE 1 VN2
PT8146
Noise to analog during parallel serial conversion commands, serial parallel conversion command for digital-only pins, or ESR setting commands for switching between digital input and digital output.
CLK
SI Parallel -> serial conversion, serial -> parallel conversion, ESR setting commands CS
D3 to D0 D11 to D0 AO1 to AO12
Parallel output
Digital input VN2 VN2
Analog output
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8-Bit 12-Ch I/O DAC I/O EXPANDER OPERATION NOISE 2 VN3
PT8146
Noise to analog output during serial parallel switching commands for digital-only pins, or ESR setting commands for switching between digital output and analog output.
CLK
SI Parallel -> serial switching commands, ESR setting commands CS
D11 to D4 D11/AO5 D0/AO12 AO1 to AO12
Parallel output
Digital input VN3 VN3
Analog output
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8-Bit 12-Ch I/O DAC
PT8146
DATA INPUT/OUPUT TIMING
PT8146 DATA INPUT/OUTPUT TIMING (SERIAL BUS FORMAT)
D/A Converter operation, and I/O expander (serial parallel conversion) operation, and ESR writing operation
SI D0 D1 D2 DE DF
CLK
1
2
3
15
16
CS
AOX
DXX
SO
Data input is enabled at the falling edge of the /CS signal. 16-bit data is input, and the shift register command is executed at the rising edge of /CS. In D/A converter operations, the analog output selected at the rising edge of /CS is the conversion result. In serial parallel conversion, the digital output selected at the rising edge of /CS is the conversion result. In ESR write operation, ESR data is set and pin status determined at the rising edge of /CS.
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8-Bit 12-Ch I/O DAC
I/O expander (parallel -> serial conversion) operation
SI D0 DF
PT8146
CLK
1
16
1
2
16
CS
DXX Retrieved parallel data SO D0 DF
Parallel-to-serial -> Conversion result output
Data input is enabled at the falling edge of the /CS signal. 16-bit data (parallel serial conversion commands) is input and commands accepted at the rising edge of /CS. AT the falling edge of /CS, data from the parallel input is loaded into bits D4 to DF of the shift register, and output from the SO pin timed to the falling edge of the CLK signal.
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8-Bit 12-Ch I/O DAC
PT8146
USAGE PRECAUTIONS
PREVENTING LATCH-UP
A condition known as "latch-up" may occur when the input or output pins of a CMOS IC device are exposed to voltages higher than VDD or VCCA or lower than GND voltage, or when voltages are applied to the device in excess of rated values for VCCD, VCCA, or VDD to GND voltages. Latch-up produces a rapid increase in power supply current, and may result in thermal destruction of elements. Users should take sufficient precautions to ensure that absolute maximum ratings are not exceeded at any time during use.
POWER SUPPLY PINS
The power supply should be connected to the VCCD, VCCA, VDD and GND terminals of the PT8146 with as low impedance as possible. In addition, it is recommended that ceramic capacitors or approximately 0.1F be connected as bypass capacitors between the VCCD, VCCA, and VDD terminals and the GND terminals.
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8-Bit 12-Ch I/O DAC
PT8146
ORDER INFORMATION
Valid Part Number PT8146 PT8146 (L) Package Type 24 Pins, SSOP, 209mil 24 Pins, SSOP, 209mil Top Code PT8146 PT8146
Notes: 1. (L), (C) or (S) = Lead Free. 2. The Lead Free mark is put in front of the date code.
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8-Bit 12-Ch I/O DAC
PT8146
PACKAGE INFORMATION
24 PINS, SSOP, 209MIL
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8-Bit 12-Ch I/O DAC
Symbol A A1 A2 *b b1 c c1 D *E E1 e L L1 N R1 Min. 0.05 1.65 0.22 0.22 0.09 0.09 7.90 7.60 5.00 0.55 Nom. 1.75 0.30 0.15 8.20 7.80 5.30 0.65 BASIC 0.75 1.25 REF 24 4 Max 2.0 1.85 0.32 0.33 0.25 0.21 8.50 8.00 5.60 0.95
PT8146
0.09 0
8
Notes: 1. All dimensions are in millimeters. 2. Dimension and tolerancing per ANSI Y14.5M-1982. 3. D and E1 dimension do not include mold flash or protrusions, but do include mold mismatch and are measured at datum plane H, mold parting line. Mold flash or protrusion shall not exceed 0.20mm per side. 4. Dimension b does not include dambar protrusion/intrusion. Allowable dambar protrusion shall be 0.13mm total in excess of b dimension at maximum material condition. Dambar intrusion shall not reduce dimension b by more than 0.07mm at least material condition. 5. To be determined at the seating plane - datum "C". 6. "N" is the number of terminal positions. 7. A visual index feature must be located within the crosshatched area. 8. These dimensions apply to the flat section to the lead between 0.10 and 0.25mm from the lead tip. 9. Refer to JEDEC MO-150 variations AG 10. Dimensions marked with "*" are not complying with JEDEC product outlines. JEDEC is the registered trademark of JEDEC SOLID STATE TECHNOLOGY ASSOCIATION
PT8146 V1.1
- 27 -
February, 2006

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