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| 8 Bit Microcontroller TLCS-870/C Series TMP86FP24 The information contained herein is subject to change without notice. 021023_D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S (c) 2007 TOSHIBA CORPORATION All Rights Reserved TMP86FP24 CMOS 8-Bit Microcontroller TMP86FP24FG The TMP86FP24 is the high-speed, high-performance and low-power consumption 8-bit microcomputer, including ROM, RAM, LCD driver, multi-function timer/counter, serial interface (UART, HSIO), a 10-bit AD converter and two clock generators on chip. The TMP86FP24 has a 2 K bytes BOOT ROM (masked ROM) for programming to flash memory. Product No. TMP86FP24FG Flash Memory 48 K x 8 bits BOOT ROM 2 K x 8 bits RAM 2 K x 8 bits Package LQFP80-P-1212-0.50A Emulation Chip TMP86C948XB Feautures 8-bit single chip microcomputer TLCS-870/C series Instruction execution time: 0.25 s (at 16 MHz) 122 s (at 32.768 kHz) 132 types and 731 basic instructions 19 interrupt sources (External: 5, Internal: 14) Input/output ports (54 pins) (Out of which 16 pins are also used as SEG pins) 16-bit timer counter: 2 ch * Timer, event counter, pulse width measurement, external trigger timer, window, PPG output modes Timer, event counter, PWM output, programmable divider output, capture modes TMP86FP24FG LQFP80-P-1212-0.50A 8-bit timer counter: 2 ch * Time base timer Divider output function Watchdog timer * Interrupt source/internal reset generate (Programmable) * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S 86FP24-1 2007-08-24 TMP86FP24 Serial interface * * * * * * UART/SIO: 1ch SIO: 1ch ROM corrective function Four register bank 1 byte or 2 bytes replace mode Address replace mode Analog input: 8 ch 10-bit successive approximation type AD converter Five key-on wakeup pins LCD driver/controller * * * * Built-in voltage booster for LCD driver With display memory (12 bytes) LCD direct drive capability (Max 24 seg x 4 com) 1/4, 1/3, 1/2 duties or static drive are programmably selectable Single/dual clock mode STOP mode: Oscillation stops. Battery/capacitor backup. Port output hold/high impedance. Dual clock operation * * * * * * * * * Nine power saving operating modes SLOW1, 2 mode: Low power consumption operation using low-frequency clock (32.768 kHz). IDLE0 mode: IDLE1 mode: IDLE2 mode: SLEEP0 mode: SLEEP1 mode: SLEEP2 mode: CPU stops, and peripherals operate using high-frequency clock of time-base-timer. Release by falling edge of TBTCR Wide operating voltage: 1.8 to 3.6V at 8 MHz/32.768 kHz 2.7 to 3.6V at 16 MHz/32.768 kHz 86FP24-2 2007-08-24 TMP86FP24 Pin Assignments (Top view) LQFP80-P-1212-0.50A V3 V2 V1 C1 C0 WAKE (STOP/INT5) (BOOT) (INT0) (INT1) (INT2) (TC2) P20 P23 P00 P01 P02 P03 P04 (RXD/SI1) P05 (TXD/SO1) P06 (SCK1) P07 AVDD VAREF VSS XIN XOUT TEST VDD (XTIN) P21 (XTOUT) P22 RESET 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 (SO2) P10 (SI2) P11 ( SCK2 ) P12 ( PWM5 / PDO5 /TC5) P13 (INT3/TC3) P14 (TC1) P15 P30 P31 P32 P33 P34 P35 P36 P37 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41 COM0 COM1 COM2 COM3 SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 P97 (SEG8) P96 (SEG9) P95 (SEG10) P94 (SEG11) P93 (SEG12) P92 (SEG13) P91 (SEG14) P90 (SEG15) 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21 P47 (SEG16) P46 (SEG17) P45 (SEG18) P44 (SEG19) P43 (SEG20) P42 (SEG21) P41 (SEG22) P40 (SEG23/STOP4) P53 P52 P51 ( DVO ) P50 ( PPG ) P67 (AIN7/STOP3) P66 (AIN6/STOP2) P65 (AIN5/STOP1) P64 (AIN4/STOP0) P63 (AIN3) P62 (AIN2) P61 (AIN1) P60 (AIN0) 86FP24-3 2007-08-24 TMP86FP24 Block Diagram I/O Port (Segment output) Common outputs COM3 to COM0 Segment outputs SEG7 to SEG0 P97 (SEG8) P47 (SEG16) to to P90 (SEG15) P40 (SEG23) I/O port P37 to P30 Power supply VDD VSS LCD driver circuit C0 C1 V1 V2 V3 RESET TEST P9 P4 P3 LCD power supply Address/data bus LCD voltage booster circuit TLCS-870/C CPU System control circuit Standby control circuit (Key-on wakeup) Timing generator Data memory (RAM) Program memory (Flash) BOOT ROM (mask ROM) Reset input test pin Interrupt controller Resonator connecting pins Time-base-timer XIN XOUT High frequency Clock Low generator frequency 16-bit timer/counter TC1 TC2 8-bit timer/counter TC3 TC5 HSIO SIO2 SIO1 UART Watchdog timer Address/data bus P2 P6 P1 P0 P5 10-bit AD converter P23 to P20 AVDD VAREF Analog reference pins P67 (AIN7) P15 to P10 to P60 (AIN0) I/O ports P07 to P00 P53 to P50 I/O ports 86FP24-4 2007-08-24 TMP86FP24 Pin Funtions The TMP86FP24 has MCU mode and serial PROM mode. (1) MCU mode Make sure to fix the TEST pin to low level. (2) Serial PROM mode In the serial PROM mode, programming to flash memory is available by executing BOOT ROM. For details, refer to 2.16 "Serial PROM Mode". 86FP24-5 2007-08-24 TMP86FP24 Pin Functions (1/2) Pin Name P07 ( SCK1 ) P06 (TXD, SO1) P05 (RXD, SI1) P04 P03 (TC2) P02 (INT2) P01 (INT1) P00 ( INT0 ) P15 (TC1) P14 (TC3, INT3) P13 ( PWM5 , PDO5 , TC5) P12 ( SCK2 ) P11 (SI2) P10 (SO2) P23 P22 (XTOUT) P21 (XTIN) P20 ( INT5 , STOP ) Input/Output I/O (I/O) I/O (Output) I/O (Input) I/O I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (I/O) I/O (I/O) I/O (Input) I/O (Output) I/O I/O (Output) I/O (Input) I/O (Input) Functions 8-bit input/output port with latch. When used as a serial interface output or UART output, respective output latch (P0DR) should be set to "1". When used as an input port, an serial interface input, UART input, timer counter input or an external interrupt input, respective output control (P0OUTCR) should be cleared to "0" after setting P0DR to "1". 6-bit input/output port with latch. When used as a timer/counter output or serial interface output, respective output latch (P1DR) should be set to "1". When used as an input port, a timer counter input, an external interrupt input or serial interface input, respective output control (P1OUTCR) should be cleared to "0" after setting P1DR to "1". Serial clock input/output 1 UART data output, serial data output 1 UART data input, serial data input 1 Timer counter 2 input External interrupt 2 input External interrupt 1 input External interrupt 0 input Timer counter 1 input Timer counter 3 input, External interrupt 3 input PWM5 output, PDO5 output, Timer/counter 5 input Serial clock input/output 2 Serial data input 2 Serial data output 2 4-bit input/output port with latch. When used as an input port or an external interrupt input, respective output control (P2OUTCR) should be cleared to "0" after setting output latch (P2DR) to "1". 8-bit input/output port with latch (N-ch high current output). When used as an input port, respective output control (P3OUTCR) should be cleared to "0" after setting output latch (P3DR) to "1". 7-bit input/output port with latch. When used as an input port, respective output latch (P4DR) should be set to "1" after LCD output control (P4LCR) is cleared to "0". 1-bit input/output port with latch. When used as an input port, the output latch (P4DR) should be set to "1" after the LCD output control (P4LCR) is cleared to "0". When used as a LCD output, the P4LCR should be set to "1" after the STOPCR Resonator connecting pins (32.768 kHz) For inputting external clock, XTIN is used and XTOUT is opened. External interrupt input 5 or STOP mode release signal input P37 to P30 I/O P47 (SEG16) to P41 (SEG22) I/O (Output) LCD segment output P40 (SEG23, STOP4) I/O (I/O) LCD segment output STOP mode release input P53 P52 P51 ( DVO ) I/O I/O I/O (Output) Divider output P50 ( PPG ) I/O (Output) PPG output 86FP24-6 2007-08-24 TMP86FP24 Pin Functions (1/2) Pin Name P67 (AIN7, STOP3) P66 (AIN6, STOP2) P65 (AIN5, STOP1) P64 (AIN4, STOP0) P63 (AIN3) P62 (AIN2) P61 (AIN1) P60 (AIN0) Input/Output I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) I/O (Input) Functions 8-bit programmable input/output port (Tri-state). Each bit of this port can be individually configured as an input or an output under software control. When used as an input port, respective input/output control (P6CR1) should be cleared to "0" after setting input control (P6CR2) to "1". When used as an analog input or key-on wakeup input, respective P6CR1 should be cleared to "0" after clearing P6CR2 to "0". When used as a key-on wakeup input, STOPCR P97 (SEG8) to P90 (SEG15) I/O (Output) LCD segment output SEG7 to SEG0 COM3 to COM0 V3 to V1 C1 to C0 WAKE Output LCD voltage booster pin Output LCD voltage booster pin. Capacitors are required between C0 and C1 pin and V1/V2/V3 pin and GND. STOP mode monitor output. During CPU operation (including IDLE0/1/2, SLEEP0/1/2, warm-up period), it becomes "L" level state. In RESET and STOP mode, it becomes the high-impedance state. Resonator connecting pins for high-frequency clock. For inputting external clock, XIN is used and XOUT is opened. Reset signal input Test pin for out-going test. Be fixed to low. Power supply for operation XIN, XOUT RESET Input output Input Input TEST VDD, VSS VAREF AVDD Power supply Analog reference voltage for AD conversion AD circuit power supply 86FP24-7 2007-08-24 TMP86FP24 Operational Description 1. CPU Core Functions The CPU core consists of a CPU, a system clock controller, and an interrupt controller. This section provides a description of the CPU core, the program memory, the data memory, the external memory interface, and the reset circuit. 1.1 Memory Address Map The TMP86FP24 memory consists of 5 blocks: FLASH memory, BOOT ROM, RAM, DBR (Data buffer register) and SFR (Special function register). They are all mapped in 64-Kbyte address space. Figure 1.1.1 shows the TMP86FP24 memory address map. The general-purpose registers are not assigned to the RAM address space. 0000H SFR 003FH 0040H 64 bytes ROM: BOOT ROM: RAM: FLASH memory includes: Vector table FLASH writing program Random access memory includes: Data memory Stack Special function register includes: I/O ports Peripheral control registers Peripheral status registers System control registers Interrupt control registers Program status word Data buffer register includes: Peripheral control registers Peripheral status registers LCD display memory RAM 083FH 2048 bytes SFR: 1F80H DBR 1FFFH DBR: BOOT ROM 3800H 2048 bytes 3FFFH 4000H 128 bytes 49072 bytes FLASH memory FFB0H FFBFH FFC0H FFDFH FFE0H FFFFH 16 bytes 32 bytes 32 bytes TMP86FP24 Vector table for interrupts/reset (8 vectors) Vector table for vector call instructions (16 vectors) Vector table for interrupts/reset (16 vectors) Figure 1.1.1 Memory Address Maps 1.2 Program Memory (ROM) The TMP86FP24 has a 48 K x 8 bits (Address 4000H to FFFFH) of program memory (FLASH). 86FP24-8 2007-08-24 TMP86FP24 1.3 Data Memory (RAM) The TMP86FP24 has 2048 bytes of internal RAM. The first 192 bytes (0040H to 00FFH) of the internal RAM are located in the direct area; instructions with shorten operations are available against such an area. The data memory contents become unstable when the power supply is turned on; therefore, the data memory should be initialized by an initialization routine. Example: Clears RAM to "00H". LD HL, 0040H LD A, H LD BC, 07FFH SRAMCLR: LD (HL), A INC HL DEC BC JRS F, SRAMCLR ; ; Start address setup. Initial value (00H) setup. 86FP24-9 2007-08-24 TMP86FP24 1.4 System Clock Controller The system clock controller consists of a clock generator, a timing generator, and a standby controller. Timing generator control register TBTCR Clock generator XIN High-frequency clock oscillator XOUT XTIN Low-frequency clock oscillator fs System clocks 0038H SYSCR1 Clock generator control 0039H SYSCR2 fc Timing generator Standby controller 0036H XTOUT System control registers Figure 1.4.1 System Clock Control 1.4.1 Clock Generator The Clock generator generates the basic clock which provides the system clocks supplied to the CPU core and peripheral hardware. It contains two oscillation circuits: one for the high-frequency clock and one for the low-frequency clock. Power consumption can be reduced by switching of the standby controller to low-power operation based on the low-frequency clock. The high-frequency (fc) and low-frequency (fs) clocks can easily be obtained by connecting a resonator between the XIN/XOUT and XTIN/XTOUT pins respectively. Clock input from an external oscillator is also possible. In this case, external clock is applied to XIN/XTIN pin with XOUT/XTOUT pin not connected. High-frequency clock Low-frequency clock XOUT (Open) XTIN XTOUT XTIN XTOUT (Open) XIN XOUT XIN (a) Crystal/Ceramic resonator (b) External oscillator (c) Crystal (d) External oscillator Figure 1.4.2 Examples of Resonator Connection Note: The function to monitor the basic clock directly at external is not provided for hardware, however, with disabling all interrupts and watchdog timers, the oscillation frequency can be adjusted by monitoring the pulse which the fixed frequency is outputted to the port by the program. The system to require the adjustment of the oscillation frequency should create the program for the adjustment in advance. 86FP24-10 2007-08-24 TMP86FP24 (2) Dual-clock mode Both the high-frequency and low-frequency oscillation circuits are used in this mode. P21 (XTIN) and P22 (XTOUT) pins cannot be used as input/output ports. The main system clock is obtained from the high-frequency clock in NORMAL2 and IDLE2 modes, and is obtained from the low-frequency clock in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] in the NORMAL2 and IDLE2 modes, and 4/fs [s] (122 s at fs = 32.768 kHz) in the SLOW and SLEEP modes. The TLCS-870/C is placed in the single-clock mode during reset. To use the dual-clock mode, the low-frequency oscillator should be turned on at the start of a program. a. NORMAL2 mode In this mode, the CPU core operates with the high-frequency clock. On-chip peripherals operate using the high-frequency clock and/or low-frequency clock. b. SLOW2 mode In this mode, the CPU core operates with the low-frequency clock, while both the high-frequency clock and the low-frequency clock are operated. On-chip peripherals are triggered by the low-frequency clock. As the SYSCK on SYSCR2 becomes "0", the hardware changes into NORMAL2 mode. As the XEN on SYSCR2 becomes "0", the hardware changes into SLOW1 mode. Do not clear XTEN to "0" during SLOW2 mode. c. SLOW1 mode This mode can be used to reduce power consumption by turning off oscillation of the high-frequency clock. The CPU core and on-chip peripherals operate using the low-frequency clock. Switching back and forth between SLOW1 and SLOW2 modes are performed by XEN bit on the system control register 2 (SYSCR2). In SLOW1 and SLEEP mode, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. d. IDLE2 mode In this mode, the internal oscillation circuit remain active. The CPU and the watchdog timer are halted; however, on-chip peripherals remain active (Operate using the high-frequency clock and/or the low-frequency clock). Starting and releasing of IDLE2 mode are the same as for IDLE1 mode, except that operation returns to NORMAL2 mode. e. SLEEP1 mode In this mode, the internal oscillation circuit of the low-frequency clock remains active. The CPU, the watchdog timer, and the internal oscillation circuit of the high-frequency clock are halted; however, on-chip peripherals remain active (Operate using the low-frequency clock). Starting and releasing of SLEEP mode are the same as for IDLE1 mode, except that operation returns to SLOW mode. In SLOW and SLEEP mode, the input clock to the 1st stage of the divider is stopped; output from the 1st to 6th stages is also stopped. 86FP24-14 2007-08-24 TMP86FP24 f. SLEEP2 mode The SLEEP2 mode is the IDLE mode corresponding to the SLOW2 mode. The status under the SLEEP2 mode is same as that under the SLEEP1 mode, except for the oscillation circuit of the high-frequency clock. g. SLEEP0 mode In this mode, all the circuit, except oscillator and the Time-base-timer, stops operation. This mode is enabled by setting "1" on bit TGHALT on the system control register 2 (SYSCR2). When SLEEP0 mode starts, the CPU stops and the timing generator stops feeding the clock to the peripheral circuits other than TBT. Then, upon detecting the falling edge of the source clock selected with TBTCR Note 1: When the IDLE0/1/2 and SLEEP0/1/2 modes are started with the EEPCR 86FP24-15 2007-08-24 TMP86FP24 IDLE0 mode (Note 2) SYSCR1 STOP pin input STOP pin input Reset release RESET SYSCR2 SYSCR2 STOP pin input SYSCR2 SYSCR2 SYSCR2 Operating Mode RESET NORMAL1 Single IDLE1 clock IDLE0 STOP NORMAL2 IDLE2 Dual clock SLOW2 SLEEP2 SLOW1 SLEEP1 SLEEP0 STOP CPU Core Reset TBT Reset Operate Oscillation Operate Stop Halt Stop Operate with high frequency Oscillation Oscillation Halt Operate with low frequency Halt Operate with low frequency Stop Stop Halt Halt - 4/fc [s] Operate 4/fs [s] Operate Halt Halt - Figure 1.4.6 Operating Mode Transition Diagram 86FP24-16 2007-08-24 TMP86FP24 System Control Register 1 SYSCR1 7 6 (0038H) STOP RELM 5 RETM 4 OUTEN 3 WUT 2 1 0 (Initial value: 0000 00**) STOP RELM RETM OUTEN WUT 0: CPU core and peripherals remain active 1: CPU core and peripherals are halted (Start STOP mode) Release method for STOP pin 0: Edge-sensitive release (P20) 1: Level-sensitive release Operating mode after STOP 0: Return to NORMAL1/2 mode mode 1: Return to SLOW1 mode Port output during STOP 0: High impedance mode 1: Output kept Return to NORMAL mode Return to SLOW mode 16 10 13 3 3 x 2 /fs + (2 /fs) 00 3 x 2 /fc + (2 /fc) Warm-up time at releasing 16 10 13 3 2 /fc + (2 /fc) 2 /fs + (2 /fs) 01 STOP mode (Note 8) 14 10 6 3 3 x 2 /fc + (2 /fc) 3 x 2 /fs + (2 /fs) 10 14 10 6 3 2 /fc + (2 /fc) 2 /fs + (2 /fs) 11 STOP mode start R/W Note 1: Always set RETM to "0" when transiting from NORMAL mode to STOP mode. Always set RETM to "1" when transiting from SLOW mode to STOP mode. Note 2: When STOP mode is released with RESET pin input, a return is made to NORMAL1 regardless of the RETM contents. Note 3: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Note 4: Bits 1 and 0 in SYSCR1 are read as undefined data when a read instruction is executed. Note 5: As the hardware becomes STOP mode under OUTEN = "0", input value is fixed to "0"; therefore it may cause interrupt request on account of falling edge. Note 6: When the Key-on wakeup input (STOP0 to STOP4) is used, RELM should be set to "1". Note 7: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z mode. Note 8: When the STOP mode is started with the EEPCR 5 SYSCK 4 IDLE 3 2 TGHALT 1 0 (Initial value: 1000 *0**) XEN XTEN SYSCK High-frequency oscillator control Low-frequency oscillator control Main system clock select (Write)/main system clock monitor (Read) CPU and watchdog timer control (IDLE1/2, SLEEP1/2 mode) TG control (IDLE0, SLEEP0 mode) IDLE TGHALT 0: Turn off oscillation 1: Turn on oscillation 0: Turn off oscillation 1: Turn on oscillation 0: High-frequency clock 1: Low-frequency clock 0: CPU and watchdog timer remain active 1: CPU and watchdog timer are stopped (Start IDLE1/2, SLEEP1/2 mode) 0: Feeding clock to all peripherals from TG 1: Stop feeding clock to peripherals except TBT from TG. (Start IDLE0, SLEEP0 mode) R/W Note 1: A reset is applied if both XEN and XTEN are cleared to "0", XEN is cleared to "0" when SYSCK = "0", or XTEN is cleared to "0" when SYSCK = "1". Note 2: *: Don't care, TG: Timing generator Note 3: Bits 3, 1 and 0 in SYSCR2 are always read as undefined value. Note 4: Do not set IDLE and TGHALT to "1" simultaneously. Note 5: Because returning from IDLE0/SLEEP0 to NORMAL1/SLOW1 is executed by the asynchronous internal clock, the period of IDLE0/SLEEP0 mode might be shorter than the period setting by TBTCR Figure 1.4.7 System Control Registers 86FP24-17 2007-08-24 TMP86FP24 1.4.4 Operating Mode Control (1) STOP mode STOP mode is controlled by the system control register 1, the STOP pin input and key-on wakeup input (STOP0 to STOP4) which is controlled by the STOP mode release control register (STOPCR). The STOP pin is also used both as a port P20 and an INT5 (External interrupt input 5) pin. STOP mode is started by setting SYSCR1 d. The program counter holds the address 2 ahead of the instruction (e.g., [SET (SYSCR1).7]) which started STOP mode. STOP mode includes a level-sensitive mode and an edge-sensitive mode, either of which can be selected with the SYSCR1 86FP24-18 2007-08-24 TMP86FP24 Example 1: Starting STOP mode from NORMAL mode by testing a port P20. LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode. SSTOPH: TEST (P2PRD). 0 ; Wait until the STOP pin input goes low level. JRS SET F, SSTOPH (SYSCR1).7 ; Starts STOP mode. Example 2: Starting STOP mode from NORMAL mode with an INT5 interrupt. PINT5: TEST (P2PRD). 0 ; To reject noise, STOP mode does not start if port P20 is at high. JRS F, SINT5 LD (SYSCR1), 01010000B ; Sets up the level-sensitive release mode. SET (SYSCR1). 7 ; Starts STOP mode. SINT5: RETI Only when EEPCR STOP pin VIH XOUT pin NORMAL operation STOP operation Confirm by program that the STOP pin input is low and start STOP mode. NORMAL CPU operation wait STOP mode is released by the hardware. Always released if the STOP pin input is high. STOP Warm up Note: When the STOP mode is started with the EEPCR Figure 1.4.8 Level-sensitive Release Mode Note 1: Even if the STOP pin input is low after warm-up start, the STOP mode is not restarted. Note 2: In this case of changing to the level-sensitive mode from the edge-sensitive mode, the release mode is not switched until a rising edge of the STOP pin input is detected. b. Edge-sensitive release mode (RELM = "0") In this mode, STOP mode is released by a rising edge of the STOP pin input. This is used in applications where a relatively short program is executed repeatedly at periodic intervals. This periodic signal (for example, a clock from a low-power consumption oscillator) is input to the STOP pin. In the edge-sensitive release mode, STOP mode is started even when the STOP pin input is high level. Do not use any STOPx (x: 0 to 4) pin input for releasing STOP mode in edge-sensitive release mode. Example: Starting STOP mode from NORMAL mode. LD (SYSCR1), 10010000B ; Starts after specified to the edge-sensitive release mode. 86FP24-19 2007-08-24 TMP86FP24 Only when EEPCR STOP pin VIH XOUT pin NORMAL operation STOP mode started by the program. Note: STOP operation STOP Warm up NORMAL operation STOP operation CPU wait STOP mode is released by the hardware at the rising edge of STOP pin input. When the STOP mode is started with the EEPCR Figure 1.4.9 Edge-sensitive Release Mode STOP mode is released by the following sequence. a. In the dual-clock mode, when returning to NORMAL2, both the high-frequency and low-frequency clock oscillators are turned on; when returning to SLOW1 mode, only the low-frequency clock oscillator is turned on. In the single-clock mode, only the high-frequency clock oscillator is turned on. A STOP warm-up period is inserted to allow oscillation time to stabilize. During STOP warm up, all internal operations remain halted. Four different STOP warm-up times can be selected with the SYSCR1 b. c. d. Note 1: When the STOP mode is released, the start is made after the prescaler and the divider of the timing generator are cleared to "0". Note 2: STOP mode can also be released by inputting low level on the RESET pin, which immediately performs the normal reset operation. Note 3: When STOP mode is released with a low hold voltage, the following cautions must be observed. The power supply voltage must be at the operating voltage level before releasing STOP mode. The RESET pin input must also be "H" level, rising together with the power supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). 86FP24-20 2007-08-24 TMP86FP24 Table 1.4.1 Warm-up Time Example (at fc = 16.0 MHz, fs = 32.768 kHz) WUT 00 01 10 11 Warm-up Time [ms] (Note 2) Return to NORMAL Mode 12.288 4.096 3.072 1.024 + (0.064) + (0.064) + (0.064) + (0.064) Return to SLOW Mode 750 250 5.85 1.95 + (0.244) + (0.244) + (0.244) + (0.244) Note 1: The warm-up time is obtained by dividing the basic clock by the divider: Therefore, the warm-up time may include a certain amount of error if there is any fluctuation of the oscillation frequency when STOP mode is released. Thus, the warm-up time must be considered an approximate value. Note 2: The CPU wait period for FLASH is shown in parentheses. 86FP24-21 2007-08-24 Turn off Oscillator circuit Turn on Main system clock a+2 a+3 SET (SYSCR1).7 n+1 n+2 n+3 n+4 Halt Program counter Instruction execution Divider n 0 (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) Figure 1.4.10 STOP Mode Start/Release (when EEPCR STOP warm up Turn on a+3 a+4 Instruction address a + 2 Count up 0 1 (b) STOP mode release a+5 Instruction address a + 3 2 3 86FP24-22 STOP pin input Oscillator circuit Turn off Main system clock a+6 Instruction address a + 4 Program counter Halt Instruction execution Divider 0 TMP86FP24 2007-08-24 Turn off Oscillator circuit Turn on Main system clock a+2 a+3 SET (SYSCR1).7 n+1 n+2 n+3 n+4 Halt Program counter Instruction execution Divider n 0 (a) STOP mode start (Example: Start with SET (SYSCR1). 7 instruction located at address a) Figure 1.4.11 STOP Mode Start/Release (when EEPCR STOP warm up CPU wait Turn on a+3 a+4 Instruction address a + 2 Count up 0 1 m (b) STOP mode release m+1 The counting of divider is restarted. 86FP24-23 STOP pin input Oscillator circuit Turn off Main system clock a+5 Instruction address a + 3 m+2 Program counter Halt Instruction execution Divider 0 TMP86FP24 2007-08-24 TMP86FP24 (2) IDLE1/2 mode, SLEEP1/2 mode IDLE1/2 and SLEEP1/2 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following status is maintained during these modes. a. b. c. Operation of the CPU and watchdog timer (WDT) is halted. On-chip peripherals continue to operate. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before these modes were entered. The program counter holds the address 2 ahead of the instruction which starts these modes. Starting IDLE1/2 and SLEEP1/2 modes by instruction CPU, WDT are halted Reset input No No Interrupt request Yes "1" EEPCR Yes Reset "0" IMF (Normal release mode) "1" (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE1/2 and SLEEP1/2 modes start instruction Note 1: EEPCR Figure 1.4.12 IDLE1/2, SLEEP1/2 Modes 86FP24-24 2007-08-24 TMP86FP24 * Start the IDLE1/2 and SLEEP1/2 modes When IDLE1/2 and SLEEP1/2 modes start, set SYSCR2 RESET pin. After releasing reset, the operation mode is started from NORMAL1 mode. Note: During CPU wait, though CPU operations remain halted, but the peripheral function operation is resumed. Therefore in this time, though the interrupt latch might be set, interrupt operation is not executed until the CPU wait is finished. (a) Normal release mode (IMF = "0") IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled by the individual interrupt enable flag (EF). After the interrupt is generated, the program operation is resumed from the instruction following the IDLE1/2 and SLEEP1/2 modes start instruction. Normally, the interrupt latches (IL) of the interrupt source used for releasing must be cleared to "0" by load instructions. (b) Interrupt release mode (IMF = "1") IDLE1/2 and SLEEP1/2 modes are released by any interrupt source enabled with the individual interrupt enable flag (EF). After the interrupt is processed, the program operation is resumed from the instruction following the instruction, which starts IDLE1/2 and SLEEP1/2 modes. Note: When a watchdog timer interrupts is generated immediately before IDLE1/2 and SLEEP1/2 modes are started, the watchdog timer interrupt will be processed but IDLE1/2 and SLEEP1/2 modes will not be started. 86FP24-25 2007-08-24 Main system clock Interrupt request a+2 a+3 Halt SET (SYSCR2).4 Operate (a) IDLE1/2, SLEEP1/2 modes start (Example: Starting with the SET instruction located at address a) Program counter Instruction execution Wachdog timer Main system clock Interrupt request a+3 a+4 Instruction address a + 2 Operate (1) Normal release mode (EEPCR Program counter Instruction execution Halt Figure 1.4.13 IDLE1/2, SLEEP1/2 Modes Start/Release a+3 Acceptance of interrupt Operate (2) Interrupt release mode 86FP24-26 Wachdog timer Halt Main system clock Interrupt request Program counter Instruction execution Halt Wachdog timer Halt TMP86FP24 2007-08-24 (b) IDLE1/2, SLEEP1/2 modes release (EEPCR TMP86FP24 (3) IDLE0, SLEEP0 modes (IDLE0, SLEEP0) IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following status is maintained during IDLE0 and SLEEP0 modes. a. b. c. Timing generator stops feeding clock to peripherals except TBT. The data memory, CPU registers, program status word and port output latches are all held in the status in effect before IDLE0 and SLEEP0 modes were entered. The program counter holds the address 2 ahead of the instruction which starts IDLE0 and SLEEP0 modes. Before starting IDLE0 or SLEEP0 mode, be sure to stop (Disable) periperals. Note: Stopping Peripherals by instruction Starting IDLE0, SLEEP0 mode by instruction CPU, WDT are halted Reset input No No TBT Yes Reset source clock falling edge Yes "1" EEPCR "0" TBTCR No (Normal release mode) "0" TBT interrupt enable Yes IMF "1" (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE0, SLEEP0 mode start instruction Figure 1.4.14 IDLE0, SLEEP0 Modes 86FP24-27 2007-08-24 TMP86FP24 * Start the IDLE0 and SLEEP0 modes Stop (Disable) peripherals such as a timer counter. When IDLE0 and SLEEP0 modes start, set SYSCR2 RESET pin. After releasing reset, the operation mode is started from NORMAL1 mode. Note 1: IDLE0 and SLEEP0 modes TBTCR Note 2: During CPU wait, though CPU operations remain halted, but the peripheral function operation is resumed. Therefore in this time, though the interrupt latch might be set, interrupt operation is not executed until the CPU wait is finished. a. Normal release mode (IMF*EF7*TBTCR Note 1: Because returning from IDLE0, SLEEP0 to NORMAL1, SLOW1 is executed by the asynchronous internal clock, the period of IDLE0, SLEEP0 mode might be the shorter than the period setting by TBTCR 86FP24-28 2007-08-24 Main system clock Interrupt request a+2 a+3 Halt SET (SYSCR2).2 Operate (a) IDLE0, SLEEP0 modes start (Example: Starting with the SET instruction located at address a) Program counter Instruction execution Watchdog timer Main system clock TBT clock a+3 Instruction address a + 2 Operate (1) Normal release mode (EEPCR Program counter Figure 1.4.15 IDLE0, SLEEP0 Modes Start/Release a+3 Acceptance of interrupt Operate (2) Interrupt release mode (b) IDLE0, SLEEP0 modes release (EEPCR 86FP24-29 Instruction execution Halt Watchdog timer Halt Main system clock TBT clock Program counter Instruction execution Halt TMP86FP24 Watchdog timer Halt 2007-08-24 TMP86FP24 (4) SLOW mode SLOW mode is controlled by the system control register 2 (SYSCR2). The following is the methods to switch the mode with the warm-up counter (TC2). a. Switching from NORMAL2 mode to SLOW1 mode First, set SYSCR2 Example 1: Switching from NORMAL2 mode to SLOW1 mode. SET (SYSCR2). 5 ; SYSCR2 CLR RETI VINTTC2: DW (SYSCR2). 7 ; PINTTC2 ; INTTC2 vector table 86FP24-30 2007-08-24 TMP86FP24 b. Switching from SLOW1 mode to NORMAL2 mode First, set SYSCR2 Note 1: After SYSCK is cleared to "0", executing the instructions is continued by the low-frequency clock for the period synchronized with low-frequency and high-frequency clocks. High-frequency clock Low-frequency clock Main system clock SYSCK Note 2: SLOW mode can also be released by inputting low level on the RESET pin, which immediately performs the reset operation. After reset, the TMP86FP24 is placed in NORMAL1 mode. Example: Switching from the SLOW1 mode to the NORMAL2 mode. (fc = 16 MHz, warm-up time is = 4.0 ms.) SET (SYSCR2). 7 ; SYSCR2 RETI VINTTC2: DW PINTTC2 ; INTTC2 vector table 86FP24-31 2007-08-24 High-frequency clock Turn off Low-frequency clock Main system clock SYSCK XEN Instruction execution CLR (SYSCR2).7 SLOW2 mode SET (SYSCR2).5 NORMAL2 mode (a) Switching to the SLOW mode SLOW1 mode Figure 1.4.16 Switching between the NORMAL2 and SLOW Modes CLR (SYSCR2).5 Warm up during SLOW2 mode (b) Switching to the NORMAL2 mode 86FP24-32 High-frequency clock Low-frequency clock Main system clock SYSCK XEN Instruction execution SET (SYSCR2).7 TMP86FP24 SLOW1 mode NORMAL2 mode 2007-08-24 TMP86FP24 1.5 Interrupt Control Circuit The TMP86FP24 has a total (Reset is excluded) of 19 interrupt source: 5 externals and 14 internals. 4 of the internal sources are non-maskable interrupts, and the rest of them are maskable interrupts. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and independent vectors. The interrupt latch is set to "1" by the generation of its interrupt request which requests the CPU to accept its interrupts. Interrupts are enabled or disabled by software using the interrupt master enable flag (IMF) and interrupt enable flag (EF). If more than one interrupts are generated simultaneously, interrupts are accepted in order which is dominated by hardware. However, there are no prioritized interrupt factors among non-maskable interrupts. Table 1.5.1 Interrupt Sources Interrupt Factors Enable Interrupt Vector Priority Condition Latch Address Non maskable (Software interrupt) Non maskable Non maskable Non maskable Non maskable IMF*EF4 = 1 IMF*EF5 = 1 IMF*EF6 = 1 IMF*EF7 = 1 IMF*EF8 = 1 IMF*EF9 = 1 IMF*EF10 = 1 IMF*EF11 = 1 IMF*EF12 = 1 IMF*EF13 = 1 IMF*EF14 = 1 IMF*EF15 = 1 IMF*EF16 = 1 IMF*EF17 = 1 (UART received interrupt) (UART transmitted interrupt) (TC2 interrupt) (External interrupt 5) IMF*EF18 = 1 IMF*EF19 = 1 IMF*EF20 = 1 IMF*EF21 = 1 IMF*EF22 = 1 IMF*EF23 = 1 - - - IL2 IL3 IL4 IL5 IL6 IL7 IL8 IL9 IL10 IL11 IL12 IL13 IL14 IL15 IL16 IL17 IL18 IL19 IL20 IL21 IL22 IL23 FFFEH FFFCH FFFCH FFFAH FFF8H FFF6H FFF4H FFF2H FFF0H FFEEH FFECH FFEAH FFE8H FFE6H FFE4H FFE2H FFE0H FFBEH FFBCH FFBAH FFB8H FFB6H FFB4H FFB2H FFB0H Low High 1 2 2 2 2 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 Internal/External (Reset) Internal Internal Internal Internal External Internal External Internal External Internal Internal Internal Internal External Internal INTSWI INTUNDEF (Executed the undefined instruction interrupt) INTATRAP (Address trap interrupt) INTWDT INT0 (Watchdog timer interrupt) (External interrupt 0) (TC1 interrupt) (External interrupt 1) (Time-base-timer interrupt) (External interrupt 2) (TC3 interrupt) (Serial interface 1 interrupt) (Serial interface 2 interrupt) (TC5 interrupt) (External interrupt 3) (AD converter interrupt) INTTC1 INT1 INTTBT INT2 INTTC3 INTSIO1 INTSIO2 INTTC5 INT3 INTADC Reserved Reserved Reserved Internal Internal Internal External INTRXD INTTXD INTTC2 INT5 Reserved Reserved Note 1: To use the watchdog timer interrupt (INTWDT), clear WDTCR1 86FP24-33 2007-08-24 INTSWI INTUNDEF INTATRAP S R IL3 IL2 Q INTWDT S R IL5 IL6 IL7 IL8 IL9 IL10 IL11 IL12 IL13 IL14 IL15 IL16 IL17 IL18 IL19 IL20 IL21 IL22 IL23 IL4 Q INT0 Digital noise reject circuit INT0EN INTTC1 INT1 Priority encoder & Vector table address generator Edge selction, digital noise reject circuit INTTBT INT1NC, INT1ES INT2 Edge selction, digital noise reject circuit INTTC3 INT2ES INTSIO1 Vector table address INTSIO2 INTTC5 INT3 Edge selction, digital noise reject circuit Interrupt request IDLE1/2, SLEEP1/2 modes releease request INT3ES Figure 1.5.1 Interrupt Controller Block Diagram [DI] instruction 22 IL23 to IL2 write data Write strobe for IL 86FP24-34 20 EF23 to EF4 Internal reset INTADC INTRXD Interrupt acceptance INTTXD INTTC2 Q IMF RS INT5 Digital noise reject circuit [RETI] instruction during maskable interrupt service [RETN] instruction only when IMF was set before interrupt was accepted [EI] instruction 2 EINTCR TMP86FP24 2007-08-24 External interrupt control register Individual Interrupt enable flag Instruction which IMF to "0" Instruction which sets IMF to "1" TMP86FP24 (1) Interrupt latches (IL24 to IL2) An interrupt latch is provided for each interrupt source, except for a software interrupt. When interrupt request is generated, the latch is set to "1", and the CPU is requested to accept the interrupt if its interrupt is enabled. All interrupt latches are initialized to "0" during reset. The interrupt latches are located on address 002EH, 003CH and 003DH in SFR area. Except for IL3 and IL2, each latch can be cleared to "0" individually by instruction. (However, the read-modify-write instructions such as bit manipulation or operation instructions cannot be used. Interrupt request would be cleared inadequately if interrupt is requested while such instructions are executed.) Thus interrupt request can be canceled/initialized by software. Interrupt latches are not set to "1" by an instruction. Since interrupt latches can be read, the status for interrupt requests can be monitored by software. Note: When manipulating IL, clear IMF (to disable interrupts) beforehand. Example 1: Clears interrupt latches. DI LD (ILE), 11110011B LDW (ILL), 1110100000111111B EI Example 2: Reads interrupt latches. LD WA, (ILL) Example 3: Tests an interrupt latches. TEST (IL).7 JR F, SSET ; ; ; ; ; ; IMF 0 IL19, IL18 0 IL12, IL10 to IL6 0 IMF 1 W ILH, A ILL IL7 = 1 then jump. (2) Interrupt enable register (EIR) The interrupt enable register (EIR) enables and disables the acceptance of interrupts, except for the non-maskable interrupts (Software interrupt, undefined instruction interrupt, address trap interrupt and watchdog timer interrupt). Non-maskable interrupt is accepted regardless of the contents of the EIR. The EIR consists of an interrupt master enable flag (IMF) and the individual interrupt enable flags (EF). These registers are located on address 002CH, 003AH and 003BH in SFR area, and they can be read and written by an instructions (including read-modify-write instructions such as bit manipulation or operation instructions). a. Interrupt master enable flag (IMF) The interrupt enable register (IMF) enables and disables the acceptance of the whole maskable interrupt. While IMF = "0", all maskable interrupts are not accepted regardless of the status on each individual interrupt enable flag (EF). By setting IMF to "1", the interrupt becomes acceptable if the individuals are enabled. When an interrupt is accepted, IMF is cleared to "0" after the latest status on IMF is stacked. Thus the maskable interrupts which follow are disabled. By executing return interrupt instruction [RETI/RETN], the stacked data, which was the status before interrupt acceptance, is loaded on IMF again. The IMF is located on bit0 in EIRL (Address: 003AH in SFR), and can be read and written by an instruction. The IMF is normally set and cleared by [EI] and [DI] instruction respectively. During reset, the IMF is initialized to "0", and maskable interrupts are not accepted until it is set to "1". 86FP24-35 2007-08-24 TMP86FP24 b. Individual interrupt enable flags (EF23 to EF4) Each of these flags enables and disables the acceptance of its maskable interrupt. Setting the corresponding bit of an individual interrupt enable flag to "1" enables acceptance of its interrupt, and setting the bit to "0" disables acceptance. The individual interrupt enable flags (EF23 to EF4) are located on EIRE, EIRL to EIRH (Address: 002CH, 003AH to 003BH in SFR), and can be read and written by an instruction. During reset, all the individual interrupt enable flags (EF23 to EF4) are initialized to "0" and all maskable interrupts are not accepted until they are set to "1". Note: Before manipulating EF, be sure to clear IMF (Interrupt disabled). Then set IMF newly again after operating on the interrupt enables flag (EF). Normally, IMF is clear to "0" automatically on service routine. When IMF is set to "1" for using a multiple interrupt on service routine, be sure to process as is the case with EF. Example 1: Enables interrupts individually and sets IMF. DI LD (EIRE), 00001100B LDW (EIRL), 0110100010100000B ; ; ; ; ; IMF "0" EF19, EF18 "1" EF14, EF13, EF11, EF7, EF5 "1" Note: IMF is not set. IMF "1" /* 3AH shows EIRL address */ EI Example 2: C compiler description example. unsigned int _io (3AH) EIRL; _DI ( ); EIRL = 10100000B; _EI ( ); 86FP24-36 2007-08-24 TMP86FP24 Interrupt Latches ILH, ILL (003CH, 003DH) 15 IL15 14 IL14 13 IL13 12 IL12 11 IL11 10 IL10 9 IL9 8 IL8 7 IL7 6 IL6 5 IL5 4 IL4 3 IL3 2 IL2 1 0 ILH (003DH) 23 IL23 22 IL22 ILE (002EH) ILL (003CH) (Initial value: 00000000 000000**) 21 20 19 18 17 16 IL21 IL20 IL19 IL18 IL17 IL16 ILE (002EH) (Initial value: 00000000) at RD 0: No interrupt request 1: Interrupt request at WR Clears the interrupt request (Note 1) (Interrupt latch is not set.) IL23 to IL2 Interrupt Latches R/W Note 1: IL2 and IL3 are prohibited from clearing. Note 2: When manipulating IL, clear IMF (to disable interrupts) beforehand. Note 3: Do not clear IL with read-modify-write instructions such as bit operations. Interrupt Enable Registers 15 14 13 12 11 10 EIRH, EIRL EF15 EF14 EF13 EF12 EF11 EF10 (003AH, 003BH) EIRH (003BH) 9 EF9 8 EF8 7 EF7 6 EF6 5 EF5 4 EF4 3 2 1 0 IMF EIRE (002CH) 23 22 EIRL (003AH) (Initial value: 00000000 00000***0) 21 20 19 18 17 16 EF23 EF22 EF21 EF20 EF19 EF18 EF17 EF16 EIRE (002CH) (Initial value: 00000000) Individual-interrupt enable flag (Specified for each bit) Interrupt master enable flag EF23 to EF4 0: Disable the acceptance of each maskable interrupt. 1: Enable the acceptance of each maskable interrupt. 0: Disable the acceptance of all maskable interrupts. 1: Enable the acceptance of all maskable interrupts. R/W IMF Note 1: *: Don't care Note 2: When manipulating EF, clear IMF (to disable interrupts) beforehand. Note 3: Do not set IMF to "1" simultaneously with EF15 to EF4. Figure 1.5.2 Interrupt Latch (IL), Interrupt Enable Registers (EIR) 86FP24-37 2007-08-24 TMP86FP24 1.5.1 Interrupt Sequence An interrupt request, which raised interrupt latch, is held, until interrupt is accepted or interrupt latch is cleared to "0" by resetting or an instruction. Interrupt acceptance sequence requires 8 machine cycles (4 s at 8.0 MHz) after the completion of the current instruction. The interrupt service task terminates upon execution of an interrupt return instruction [RETI] (for maskable interrupts) or [RETN] (for non-maskable interrupts). Figure 1.5.3 shows the timing chart of interrupt acceptance processing. (1) Interrupt acceptance processing is packaged as follows. 1. 2. 3. The interrupt master enable flag (IMF) is cleared to "0" in order to disable the acceptance of any following interrupt. The interrupt latch (IL) for the interrupt source accepted is cleared to "0". The contents of the program counter (PC) and the program status word, including the interrupt master enable flag (IMF), are saved (Pushed) on the stack in sequence of PSW + IMF, PCH, PCL. Meanwhile, the stack pointer (SP) is decremented by 3. The entry address (Interrupt vector) of the corresponding interrupt service program, loaded on the vector table, is transferred to the program counter. The instruction stored at the entry address of the interrupt service program is executed. When the contents of PSW are saved on the stack, the contents of IMF are also saved. 4. 5. Note: Interrupt service task 1-machine cycle Interrupt request Interrupt latch (IL) IMF Execute instruction PC SP Execute instruction a-1 a+1 Interrupt acceptance a b Execute instruction b+1 b+2 b+3 c+1 Execute RETI instruction c+2 a a+1 a+2 a n n-1 n-2 n-3 n-2 n-1 n Note 1: a: Return address entry address, b: Entry address, c: Address which RETI instructrion is stored Note 2: On condition that interrupt is enabled, it takes 38/fc [s] or 38/fs [s] at maximum (If the interrupt latch is set at the first machine cycle on 10-cycle instruction) to start interrupt acceptance processing since its interrupt latch is set. Figure 1.5.3 Timing Chart of Interrupt Acceptance/Return Interrupt Instruction 86FP24-38 2007-08-24 TMP86FP24 Example: Correspondence between vector table address for INTTBT and the entry address of the interrupt service program Vector table address Entry address FFF0H FFF1H 03H Vector D2H D203H D204H 0FH 06H Interrupt service program A maskable interrupt is not accepted until the IMF is set to "1" even if the maskable interrupt higher than the level of current servicing interrupt is requested. In order to utilize nested interrupt service, the IMF is set to "1" in the interrupt service program. In this case, acceptable interrupt sources are selectively enabled by the individual interrupt enable flags. To avoid overloaded nesting, clear the individual interrupt enable flag whose interrupt is currently serviced, before setting IMF to "1". As for non-maskable interrupt, keep interrupt service shorter compared with length between interrupt requests; otherwise the status cannot be recovered as non-maskable interrupt would simply nested. (2) Saving/restoring general -purpose registers During interrupt acceptance processing, the program counter (PC) and the program status word (PSW, includes IMF) are automatically saved on the stack, but the accumulator and others are not. These registers are saved by software if necessary. When multiple interrupt services are nested, it is also necessary to avoid using the same data memory area for saving registers. The following methods are used to save/restore the general-purpose registers. a. Using PUSH and POP instructions To save only a specific register, PUSH and POP instructions are available. Example: Save/store register using PUSH and POP instructions. PINTxx: PUSH WA ; Save WA register. (Interrupt processing) POP WA ; Restore WA register. RETI ; RETURN Address (Example) SP A SP PCL PCH PSW W PCL PCH PSW SP PCL PCH PSW SP 023AH 023B 023C 023D 023E 023F At acceptance of an interrupt At execution of PUSH instruction At execution of POP instruction At execution of an RETI instruction 86FP24-39 2007-08-24 TMP86FP24 b. Using data transfer instructions To save only a specific register without nested interrupts, data transfer instructions are available. Example: Save/store register using data transfer instructions. PINTxx: LD (GSAVA), A ; Save A register. (Interrupt processing) LD A, (GSAVA) ; Restore A register. RETI ; RETURN Main task Interrupt acceptance Interrupt service task Saving registers Restoring registers Interrupt return Saving/restoring general-purpose registers using PUSH/POP instruction Figure 1.5.4 Saving/Restoring General-purpose Registers under Interrupt Processing (3) Interrupt return Interrupt return instructions [RETI]/[RETN] perform as follows. [RETI]/[RETN] Interrupt Return 1. Program counter (PC) and program status word (PSW, includes IMF) are restored from the stack. Stack pointer (SP) is incremented by 3. 2. As for address trap interrupt (INTARTAP), it is required to alter stacked data for program counter (PC) to restarting address, during interrupt service program. Otherwise returning interrupt causes INTATRAP again. When interrupt acceptance processing has completed, stacked data for PCL and PCH are located on address (SP + 1) and (SP + 2) respectively. Note: If [RETN] is executed with the above data unaltered, the program returns to the address trap area and INTATRAP occurs again. 86FP24-40 2007-08-24 TMP86FP24 Example 1: Returning from address trap interrupt (INTATRAP) service program. PINTxx: POP WA ; Recover SP by 2. LD WA, Return Address ; PUSH WA ; Alter stacked data. (Interrupt processing) ; RETURN RETN Example 2: Restarting without returning interrupt. (In this case, PSW (includes IMF) before interrupt acceptance is discarded.) PINTxx: INC SP ; Recover SP by 3. INC SP INC SP (Interrupt processing) LD EIRL, data ; Set IMF to "1" or clear it to "0". JP Restart Address ; Jump into restarting address. Note: It is recommended that stack pointer be return to rate before INTATRAP (Increment 3 times), if return interrupt instruction [RETN] is not utilized during interrupt service program under INTATRAP (Such as Example 2). Interrupt requests are sampled during the final cycle of the instruction being executed. Thus, the next interrupt can be accepted immediately after the interrupt return instruction is executed. Note: When the interrupt processing time is longer than the interrupt request generation time, the interrupt service task is performed but not the main task. 86FP24-41 2007-08-24 TMP86FP24 1.5.2 Software Interrupt (INTSW) Executing the [SWI] instruction generates a software interrupt and immediately starts interrupt processing (INTSW is highest prioritized interrupt). Use the [SWI] instruction only for detection of the address error or for debugging. (1) Address error detection FFH is read if for some cause such as noise the CPU attempts to fetch an instruction from a non-existent memory address during single chip mode. Code FFH is the SWI instruction, so a software interrupt is generated and an address error is detected. The address error detection range can be further expanded by writing FFH to unused areas of the program memory. Address-trap reset is generated in case that an instruction is fetched from RAM or SFR areas. (2) Debugging Debugging efficiency can be increased by placing the SWI instruction at the software break point setting address. 1.5.3 Undefined Instruction Interrupt (INTUNDEF) Taking code which is not defined as authorized instruction for instruction causes INTUNDEF. INTUNDEF is generated when the CPU fetches such a code and tries to execute it. INTUNDEF is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTUNDEF interrupt process starts, soon after it is requested. Note: The undefined instruction interrupt (INTUNDEF) forces CPU to jump into vector address, as software interrupt (SWI) does. 1.5.4 Address Trap Interrupt (INTATRAP) Fetching instruction from unauthorized area for instructions (Address trapped area) causes reset output or address trap interrupt (INTATRAP). INTATRAP is accepted even if non-maskable interrupt is in process. Contemporary process is broken and INTATRAP interrupt process starts, soon after it is requested. Note: The operating mode under address trapped, whether to be reset output or interrupt processing, is selected on watchdog timer control register (WDTCR). 1.5.5 External Interrupts The TMP86FP24 has five external interrupt inputs. These inputs are equipped with digital noise reject circuits (Pulse inputs of less than a certain time are eliminated as noise). Edge selection is also possible with INT1 to INT3. INT0 /P00 pin can be configured as either an external interrupt input pin or an input/output port, and is configured as an input port during reset. Edge selection, noise reject control and INT0 /P00 pin function selection are performed by the external interrupt control register (EINTCR). 86FP24-42 2007-08-24 TMP86FP24 Table 1.5.2 External Interrupts Source Pin Secondary Enable Conditions Function Pin Edge Digital Noise Reject Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 15/fc or 63/fc [s] are eliminated as noise. Pulses of 49/fc or 193/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 7/fc [s] are eliminated as noise. Pulses of 25/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. Pulses of less than 2/fc [s] are eliminated as noise. Pulses of 7/fc [s] or more are considered to be signals. In the SLOW or the SLEEP mode, pulses of less than 1/fs [s] are eliminated as noise. Pulses of 3.5/fs [s] or more are considered to be signals. INT0 INT0 P00 IMF = 1, EF4 = 1, INT0EN = 1 Falling edge INT1 INT1 P01 IMF*EF6 = 1 INT2 INT2 P02 IMF*EF8 = 1 Falling edge or Rising edge INT3 INT3 P14/TC3 IMF*EF13 = 1 INT5 INT5 P20/ STOP IMF*EF21 = 1 Falling edge Note 1: If a noiseless signal is input to the external interrupt pin in the NORMAL 1/2 or IDLE 1/2 mode, the maximum time from the edge of input signal until the IL is set is as follows: (1) INT1 pin 55/fc [s] (INT1NC = 1), 199/fc [s] (INT1NC = 0) (2) INT2, INT3 pin 31/fc [s] Note 2: Even if the falling edge of INT0 pin input is detected at INT0EN = 0, the interrupt latch IL4 is not set. Note 3: When data changed and did a change of I/O when used external interrupt ports as a normal ports, interrupt request signal occurs incorrectly. Handling of prohibition of interrupt enable register (EIR) is necessary. Note 4: The maximum time from modifying INT1NC until a noise reject time is changed is 26/fc External Interrupt Control Register 7 6 EINTCR (0037H) INT1NC INT0EN 5 4 3 2 1 0 (Initial value: 00** 000*) INT3ES INT2ES INT1ES INT1NC INT0EN INT3ES INT2ES INT1ES Noise reject time select P00/ INT0 pin configuration 0: Pulses of less than 63/fc [s] are eliminated as noise 1: Pulses of less than 15/fc [s] are eliminated as noise 0: P00 input/output port 1: INT0 pin (Port P00 should be set to an input mode) 0: Rising edge 1: Falling edge R/W INT3 to INT1 edge select Note 1: fc: High-frequency clock [Hz], *: Don't care Note 2: When the system clock frequency is switched between high and low or when the external interrupt control register (EINTCR) is overwritten, the noise canceller may not operate normally. It is recommended that external interrupts are disabled using the interrupt enable register (EIR). Figure 1.5.5 External Interrupt Control Register 86FP24-43 2007-08-24 TMP86FP24 1.6 Reset Circuit The TMP86FP24 has four types of reset generation procedures: An external reset input, an address trap reset, a watchdog timer reset and a system clock reset. Since the reset circuit has an 11-stage counter for generation of flash reset, which is the reset counter for stabilizing of the power supply for flash, the reset period is 210/fc [s] (64 s at 16.0 MHz). Because the malfunction reset circuit such as watchdog timer reset, address trap reset and system clock reset is not initialized when power is turned on, the reset operation occur for the maximum 24/fc [s] (1.5 s at 16.0 MHz). Therefore, the maximum reset period is 24/fc [s] + 210/fc [s] (65.5 s at 16.0 MHz). Table 1.6.1 shows on-chip hardware initialization by reset action. Table 1.6.1 Initializing Internal Status by Reset Action On-chip Hardware Initial Value (PC) (SP) (FFFEH) Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized Not initialized 0 0 0 Control registers RAM Refer to each of control register Not initialized Output latches of I/O ports Refer to I/O port circuitry Watchdog timer Enable Prescaler and Divider of timing generator 0 On-chip Hardware Initial Value Program counter Stack pointer General-purpose registers (W, A, B, C, D, E, H, L, IX, IY) Jump status flag Zero flag Carry flag Half carry flag Sign flag Overflow flag Interrupt master enable flag Interrupt individual enable flags Interrupt latches (JF) (ZF) (CF) (HF) (SF) (VF) (IMF) (EF) (IL) 1.6.1 External Reset Input The RESET pin contains a schmitt trigger (Hysteresis) with an internal pull-up resistor. When the RESET pin is held at "L" level for at least 3 machine cycles (12/fc [s]) with the power supply voltage within the operating voltage range and oscillation stable, a reset is applied and the internal state is initialized. When 210/fc (65.5 s at 16 MHz) period passes after the RESET pin input goes high, the reset operation is released and the program execution starts at the vector address stored at addresses FFFEH to FFFFH. VDD Flash reset counter RESET Reset input Watchdog timer reset Malfunction reset output circuit Sink open drain System clock reset Adddress trap reset Figure 1.6.1 Reset Circuit 86FP24-44 2007-08-24 TMP86FP24 1.6.2 Address-trap-reset If the CPU should start looping for some cause such as noise and an attempt be made to fetch an instruction from the on-chip RAM (when WDTCR1 Instruction execution Internal reset JP a Address trap is occurred Reset release Instruction at address r max 24/fc [s] 2 /fc [s] for Flash reset 10 4/fc to 12/fc [s] 16/fc [s] Note 1: Address "a" is in the SFR or on-chip RAM (WDTCR1 Figure 1.6.2 Address-trap-reset Note: The operating mode under address trapped is alternative of reset or interrupt. Address trap or no address trap can be selected by WDTCR1 1.6.3 Watchdog Timer Reset Refer to Section 2.4 "Watchdog Timer". 1.6.4 System-clock-reset If the condition as follows is detected, the system clock reset occurs automatically to prevent dead lock of the CPU (The oscillation is continued without stopping). * In case of clearing SYSCR2 When the system clock reset is generated, the flash reset is also generated. Therefore, the maximum reset period is 24/fc [s] + 210/fc [s] (65.5 s at 16.0 MHz). 86FP24-45 2007-08-24 TMP86FP24 2. 2.1 On-chip Peripherals Functions Special Function Register (SFR) The TMP86FP24 adopts the memory mapped I/O system, and all peripheral control and data transfers are performed through the special function register (SFR). The SFR is mapped on address 0000H to 003FH, DBR is mapped on address 1F80H to 1FFFH. Figure 2.1.1 to Figure 2.1.2 indicate the special function register (SFR) and data buffer register (DBR) for TMP86FP24. Address 0000H 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F Read Write Address 0020H 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F 30 31 32 33 34 35 36 37 Read Write P0DR (P0 port output latch) P1DR (P1 port output latch) P2DR (P2 port output latch) P3DR (P3 port output latch) P4DR (P4 port output latch) P5DR (P5 port output latch) P6DR (P6 port output latch) Reserved Reserved P9DR (P9 port output latch) P0OUTCR (P0 port output control) P1OUTCR (P1 port output control) P6CR1 (P6 port input/output control) P5OUTCR (P5 port output control) ADCCR1 (AD control register 1) ADCCR2 (AD control register 2) TC3DRA (Timer register 3A) TC3DRB (Timer register 3B) - TC3CR (Timer counter 3 control) TC2CR (Timer counter 2 control) TC5CR (Timer counter 5 control) TC5DR (Timer register 5) SIO1CR1 (SIO1 control 1) SIO1CR2 (SIO1 control 2) SIO1SR (SIO1 status) SIO1BUF (SIO1 data buffer) SIO2CR1 (SIO2 control 1) SIO2CR2 (SIO2 control 2) SIO2SR (SIO2 status) SIO2BUF (SIO2 data buffer) P4PDCR(P4 port pull-down control) TC1CR (Timer counter 1 control) - - TC1DRAL (Timer register 1A) TC1DRAH (Timer register 1A) TC1DRBL (Timer register 1B) TC1DRBH (Timer register 1B) TC2DRL (Timer register 2) TC2DRH (Timer register 2) ADCDR2 (AD result register 2) ADCDR1 (AD result register 1) - - P6CR2 (P6 port input control) TC3SEL (Timer counter 3 input control) P3OUTCR (P3 port output control) P4LCR (P4 segment output control) EIRE (Interrupt enable register) Reserved ILE (Interrupt latch) Reserved Reserved Reserved Reserved Reserved - - WDTCR1 (Watchdog timer control) WDTCR2 (Watchdog timer control) TBTCR (TBT/TG/DVO control) EINTCR (External interrupt control) SYSCR1 (System control 1) SYSCR2 (System control 2) EIRL (Interrupt enable register) EIRH (Interrupt enable register) ILL (Interrupt latch) ILH (Interrupt latch) Reserved PSW (Program status word) 38 39 3A 3B 3C 3D 3E 3F Note 1: Do not access reserved areas by the program. Note 2: -: Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Figure 2.1.1 The Special Function Register (SFR) for TMP86FP24 (1/2) 86FP24-46 2007-08-24 TMP86FP24 Address Bit7 1F80H 81 82 83 84 85 86 87 88 89 8A 8B Address Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 1FC0H C1 C2 C3 C4 C5 C6 C7 C8 C9 CA CB CC CD CE CF D0 D1 Read Write SEG1 SEG3 SEG5 SEG7 SEG9 SEG11 SEG13 SEG15 SEG17 SEG19 SEG21 SEG23 SEG0 SEG2 SEG4 SEG6 SEG8 SEG10 SEG12 SEG14 SEG16 SEG18 SEG20 SEG22 ROMCCR (ROM correction control register) RCAD0L (ROM correction BANK 0 address low) RCAD0H (ROM correction BANK 0 address high) RCDT0L (ROM correction BANK 0 data low) RCDT0H (ROM correction BANK 0 data high) RCAD1L (ROM correction BANK 1 address low) RCAD1H (ROM correction BANK 1 address high) RCDT1L (ROM correction BANK 1 data low) RCDT1H (ROM correction BANK 1 data high) RCAD2L (ROM correction BANK 2 address low) RCAD2H (ROM correction BANK 2 address high) RCDT2L (ROM correction BANK 2 data low) RCDT2H (ROM correction BANK 2 data high) RCAD3L (ROM correction BANK 3 address low) RCAD3H (ROM correction BANK 3 address high) RCDT3L (ROM correction BANK 3 data low) RCDT3H (ROM correction BANK 3 data high) Reserved Reserved UARTSR (UART status) - RDBUF (UART received data buffer) EEPSR (FLASH status) LCDCR (LCD control) P2OUTCR (P2 port output control) Reserved Reserved Reserved P9PDCR (P9 port pull down control) P9LCR (P9 segment output control) Reserved Reserved Reserved P0PRD (P0 terminal input) P1PRD (P1 terminal input) P2PRD (P2 terminal input) P3PRD (P3 terminal input) P4PRD (P4 terminal input) P5PRD (P5 terminal input) P9PRD (P9 terminal input) Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved Reserved STOPCR (Key-on wakeup control) Reserved - - - - - - - UARTCR1 (UART control 1) UARTCR2 (UART control 2) TDBUF (UART transmit data buffer) - DC DD DE DF E0 E1 E2 E3 E4 E5 E6 E7 E8 E9 EA EB EC ED EE EF F0 F1 F2 F3 F4 F5 F6 F7 F8 F9 FA FB FC FD FE FF EEPCR (FLASH control) EEPEVA (FLASH write emulation time control) Note 1: Do not access reserved areas by the program. Note 2: -: Cannot be accessed. Note 3: Write-only registers and interrupt latches cannot use the read-modify-write instructions (Bit manipulation instructions such as SET, CLR, etc. and logical operation instructions such as AND, OR, etc.). Figure 2.1.2 The Special Function Register (SFR) for TMP86FP24 (2/2) 86FP24-47 2007-08-24 TMP86FP24 2.2 I/O Ports The TMP86FP24 has 8 parallel input/output ports (54 pins) as follows. Primary Function Secondary Functions External interrupt input, serial interface input/output, UART input/output and timer/counter input . External interrupt input, serial interface input/output and timer/counter input/output. Low-frequency resonator connections, external interrupt input, STOP mode release signal input. Segment output and STOP mode release signal input. Divider output and timer/counter output. Analog input and STOP mode release signal input. Segment output. Port P0 Port P1 Port P2 Port P3 Port P4 Port P5 Port P6 Port P9 8-bit I/O port 6-bit I/O port 4-bit I/O port 8-bit I/O port 8-bit I/O port 4-bit I/O port 8-bit I/O port 8-bit I/O port Each output port contains a latch, which holds the output data. All input ports do not have latches, so the external input data should be externally held until the input data is read from outside or reading should be performed several times before processing. Figure 2.2.1 shows input/output timing examples. External data is read from an I/O port in the S1 state of the read cycle during execution of the read instruction. This timing cannot be recognized from outside, so that transient input such as chattering must be processed by the program. Output data changes in the S2 state of the write cycle during execution of the instruction which writes to an I/O port. Fetch cycle Fetch cycle Read cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Instruction execution cycle Ex: LD A, (x) Input strobe Data input (a) Input timing Fetch cycle Fetch cycle Read cycle S0 S1 S2 S3 S0 S1 S2 S3 S0 S1 S2 S3 Instruction execution cycle Ex: LD (x), A Output strobe Data output Old (b) Output timing New Note: The positions of the read and write cycles may vary, depending on the instruction. Figure 2.2.1 Input/Output Timing (Example) 86FP24-48 2007-08-24 TMP86FP24 2.2.1 Port P0 (P07 to P00) Port P0 is an 8-bit input/output port which is also used as an external interrupt input, serial interface input/output, timer/counter input and UART input/output. It can be selected whether output circuit of P0 port is CMOS output or a sink open drain individually, by setting the output circuit control (P0OUTCR). When a corresponding bit of P0OUTCR is cleared to "0", the output circuit is selected to a sink open drain and when a corresponding bit of P0OUTCR is set to "1", the output circuit is selected to a CMOS output. When used as an input port or a secondary function input (External interrupt input, serial interface input, timer/counter input or UART input), the respective output latch (P0DR) should be set to "1" and its corresponding P0OUTCR bit should be cleared to "0". When used as a secondary function output (Serial interface output or UART output), the respective P0DR should be set to "1". During reset, the P0DR is initialized to "1" and P0OUTCR is initialized to "0". P0 port output latch (P0DR) and P0 port terminal input (P0PRD) are located on their respective address. When read the output latch data, the P0DR should be read and when read the terminal input data, the P0PRD register should be read. STOP OUTEN P0OUTCRi P0OUTCRi input Data input (P0PRD) Data input (P0DR) Data output (P0DR) Control output Control input 7 P0DR (0000H) R/W P0OUTCR (000AH) Port P0 output circuit control (set for each bit individually) 0: Sink open-drain output 1: CMOS output P07 SCK1 D Q D Q P0i Note: i = 7 to 0 Output latch 6 P06 TXD SO1 5 P05 RXD SI1 4 P04 3 P03 TC2 2 P02 INT2 1 P01 INT1 0 P00 INT0 (Initial value: 1111 1111) (Initial value: 0000 0000) P0OUTCR R/W P0PRD (1FEDH) Read only P07 P06 P05 P04 P03 P02 P01 P00 Figure 2.2.2 Port 0 86FP24-49 2007-08-24 TMP86FP24 2.2.2 Port P1 (P15 to P10) Port P1 is a 6-bit input/output port which is also used as an external interrupt input, serial interface input/output and timer/counter input/output. It can be selected whether output circuit of P1 port is CMOS output or a sink open drain individually, by setting the output circuit control (P1OUTCR). When a corresponding bit of P1OUTCR is cleared to "0", the output circuit is selected to a sink open drain and when a corresponding bit of P1OUTCR is set to "1", the output circuit is selected to a CMOS output. When used as an input port or a secondary function input (External interrupt input, serial interface input, timer/counter input), the respective output latch (P1DR) should be set to "1" and its corresponding P1OUTCR bit should be cleared to "0". When used as a secondary function output (Serial interface output or timer/counter output), the respective P1DR should be set to "1". During reset, the P1DR is initialized to "1" and P1OUTCR is initialized to "0". P1 port output latch (P1DR) and P1 port terminal input (P1PRD) are located on their respective address. When read the output latch data, the P1DR should be read and when read the terminal input data, the P1PRD register should be read. If a read instruction is executed for P1DR, P1OUTCR and P1PRD, read data of bits 7 and 6 are unstable. STOP OUTEN P1OUTCRi P1OUTCRi input Data input (P1PRD) Data input (P1DR) Data output (P1DR) Control output TC3SEL TC3SEL input Control input (TC3) Control input (except TC3) 7 P1DR (0001H) R/W 6 5 P15 TC1 4 P14 TC3 INT3 3 P13 TC5 PWM5 PDO5 D Q D Q P14 only P1i Note: i = 5 to 0 Output latch D Q 2 P12 SCK2 1 P11 SI2 0 P10 SO2 (Initial value: **11 1111) *: Don't care P1OUTCR (000BH) Port P1 output circuit control P1OUTCR (Set for each bit individually) P1PRD (1FEEH) Read only 0: Sink open-drain output 1: CMOS output (Initial value: **00 0000) *: Don't care R/W P15 P14 P13 P12 P11 P10 Figure 2.2.3 Port 1 86FP24-50 2007-08-24 TMP86FP24 The TC3 input can have its input waveform phase-inverted by using the TC3SEL register. For details, refer to 2.8 "8-Bit Timer/Counter 3". If a read instruction is executed for TC3SEL, read data of bits 7 to 1 are unstable. TC3SEL (0029H) 0: Normal input 1: Inverted input TC3INV (Initial value: **** ***0) *: Don't care TC3INV TC3 input control R/W Figure 2.2.4 TC3 Input Control 86FP24-51 2007-08-24 TMP86FP24 2.2.3 Port P2 (P23 to P20) Port P2 is a 4-bit input/output port. It is also used as an external interrupt, a STOP mode release signal input, and low-frequency crystal oscillator connection pins. It can be selected whether output circuit of P2 port is CMOS (P21 and P22 have a pull-up resistor) output or a sink open drain individually, by setting the output circuit control (P2OUTCR). When a corresponding bit of P2OUTCR is cleared to "0", the output circuit is selected to a sink open drain and when a corresponding bit of P2OUTCR is set to "1", the output circuit is selected to a CMOS output. (In case of P21 and P22, the pull-up resistor is connected.) When used as an input port or an external interrupt input, the respective output latch (P2DR) should be set to "1". During reset, the P2DR is initialized to "1" and P2OUTCR is initialized to "0". A low-frequency crystal oscillator (32.768 kHz) is connected to pins P21 (XTIN) and P22 (XTOUT) in the dual-clock mode. In the single-clock mode, pins P21 and P22 can be used as normal input/output ports. It is recommended that pin P20 should be used as an external interrupt input, a STOP mode release signal input, or an input port. If it is used as an output port, the interrupt latch is set on the falling edge of the output pulse. P2 port output latch (P2DR) and P2 port terminal input (P2PRD) are located on their respective address. When read the output latch data, the P2DR should be read and when read the terminal input data, the P2PRD register should be read. If a read instruction is executed for port P2DR, P2OUTCR and P2PRD, read data of bits 7 to 4 are unstable. Data input (P21PRD) Data input (P21) Output latch Data output (P21) P2OUTCR P2OUTCR input Data input (P22PRD) Data input (P22) Data output (P22) D Q D D Q Q Osc.enable VDD P21 (XTIN) VDD P22 (XTOUT) Output latch P2OUTCR P2OUTCR input fs STOP OUTEN XTEN D Q Note: When XTEN Figure 2.2.5 Port 2 (P21 and P22) 86FP24-52 2007-08-24 TMP86FP24 Data input (P20PRD) INT5 , STOP input STOP P2OUTCR P2OUTCR input Data input (P20) Data output (P20) D Q P20 ( INT5 , STOP ) D Q Output latch Note: Port P20 is used as STOP pin. Therefore, when stop mode is started, OUTEN does not affect to P20, and P20 becomes High-Z state. Data input (P23PRD) STOP OUTEN P2OUTCR P2OUTCR input Data input (P23) Data output (P23) D Q P23 D Q Output latch 7 P2DR (0002H) R/W 6 5 4 3 P23 2 P22 XTOUT 1 P21 XTIN 0 P20 INT5 STOP (Initial value: **** 1111) *: Don't care P2OUTCR (1FE4H) (Initial value: **** 0000) *: Don't care P2OUTCR Port P2 output circuit control (Set for each bit individually) 0: Sink open-drain output 1: CMOS output (P20, P23 ports) CMOS output with pull-up resistor (P21, P22 ports) R/W P2PRD (1FEFH) Read only P23 P22 P21 P20 Figure 2.2.6 Port 2 (P20 and P23) 86FP24-53 2007-08-24 TMP86FP24 2.2.4 Port P3 (P37 to P30) Port P3 is an 8-bit input/output port. It can be selected whether output circuit of P3 port is CMOS output or a sink open drain individually, by setting P3OUTCR. (N-ch high current output) When a corresponding bit of P3OUTCR is cleared to "0", the output circuit is selected to a sink open drain and when a corresponding bit of P3OUTCR is set to "1", the output circuit is selected to a CMOS output. When used as an input port, the respective output latch (P3DR) should be set to "1" and its corresponding P3OUTCR bit should be cleared to "0". During reset, the P3DR is initialized to "1", and the P3OUTCR is initialized to "0". P3 port output latch (P3DR) and P3 port terminal input (P3PRD) are located on their respective address. When read the output latch data, the P3DR should be read and when read the terminal input data, the P3PRD register should be read. STOP OUTEN P3OUTCRi P3OUTCRi input Data input (P3PRD) Data input (P3DR) Data output (P3DR) D Q P3i Note: i = 7 to 0 2 P32 1 P31 0 P30 (Initial value: 1111 1111) D Q Output latch 7 P3DR (0003H) R/W P3OUTCR (002AH) Port P3 output circuit control (Set for each bit individually) 0: Sink open-drain output 1: CMOS output P37 6 P36 5 P35 4 P34 3 P33 (Initial value: 0000 0000) P3OUTCR R/W P3PRD (1FF0H) Read only P37 P36 P35 P34 P33 P32 P31 P30 Figure 2.2.7 Port 3 86FP24-54 2007-08-24 TMP86FP24 2.2.5 Port P4 (P47 to P40) Port P4 is an 8-bit input/output port which is also used as a segment pins of LCD or key-on wakeup input. P4 port has pull-down resistors that programming control is possible. Pull-down control is specified by control register (P4PDCR). To connect pull-down resistor, P4PDCR should be set to "1". When used as an input port, the respective output latch (P4DR) should be set to "1" and the respective P4LCR bit should be cleared to "0". When used as an output port, the respective P4LCR bit should be cleared to "0". When used as a segment pins of LCD, the respective bit of P4LCR should be set to "1". When P40 is used as a key-on wakeup port, STOP4EN STOP4EN 0 0 0 0 0 0 1 Note 1: Note 2: Note 3: P4LCR 0 0 0 0 1 1 * *: Don't care STOP4EN is bit3 in STOPCR. EDSP is bit7 in LCDCR. EDSP * * * * 0 1 * P4PDCR 0 0 1 1 * * * P4DR 0 1 0 1 * * * P4PRD read Terminal input Terminal input Terminal input Terminal input "0" "0" Terminal input Output Low High-Z Low Low Low Segment High-Z Remark I/O I/O I/O (Pull down) I/O (Pull down) LCD Blanking LCD Key-on wakeup Table 2.2.2 P47 to P41 State P4LCR 0 0 0 0 1 1 Note 1: Note 2: *: Don't care EDSP is bit7 in LCDCR. EDSP * * * * 0 1 P4PDCR 0 0 1 1 * * P4DR 0 1 0 1 * * P4PRD read Terminal input Terminal input Terminal input Terminal input "0" "0" Output Low High-Z Low Low Low Segment Remark I/O I/O I/O (Pull down) I/O (Pull down) LCD Blanking LCD 86FP24-55 2007-08-24 TMP86FP24 STOP4EN STOP OUTEN P4LCR P4LCR input Data input (P4PRD) STOP4 input Data input (P4DR) Data output (P4DR) LCD data output P4PDCR P4PDCR input D Q D Q P40 Note: STOP4EN is bit4 in STOPCR. D Q Output latch STOP OUTEN P4LCR P4LCR input Data input (P4PRD) Data input (P4DR) Data output (P4DR) LCD data output P4PDCR P4PDCR input D Q D Q P4i Note: i = 7 to 1 D Q Output latch P4DR (0004H) R/W 7 P47 SEG16 6 P46 SEG17 5 P45 SEG18 4 P44 SEG19 3 P43 SEG20 2 P42 SEG21 1 P41 SEG22 0 P40 SEG23 STOP4 (Initial value: 1111 1111) P4LCR (002BH) Port P4/segment output control (Set for each bit individually) 0: P4 input/output port 1: LCD segment output (Initial value: 0000 0000) P4LCR R/W P4PDCR (001EH) Port P4 pull-down control (Set for each bit individually) 0: Pull-down disable 1: Pull-down enable (Initial value: 0000 0000) P4PDCR R/W P4PRD (1FF1H) Read only P47 P46 P45 P44 P43 P42 P41 P40 Figure 2.2.8 Port 4 86FP24-56 2007-08-24 TMP86FP24 2.2.6 Port P5 (P53 to P50) Port P5 is an 4-bit input/output port which is also used as a timer/counter output and divider output. (N-ch high current output) It can be selected whether output circuit of P5 port is CMOS output or a sink open drain individually, by setting the output circuit control (P5OUTCR). When a corresponding bit of P5OUTCR is cleared to "0", the output circuit is selected to a sink open drain and when a corresponding bit of P5OUTCR is set to "1", the output circuit is selected to a CMOS output. When used as an input port, the respective output latch (P5DR) should be set to "1" and its corresponding P5OUTCR bit should be cleared to "0". When used as a secondary function output (Timer/counter output or divider output), the respective P5DR should be set to "1". During reset, the P5DR is initialized to "1" and P5OUTCR is initialized to "0". P5 port output latch (P5DR) and P5 port terminal input (P5PRD) are located on their respective address. When read the output latch data, the P5DR should be read and when read the terminal input data, the P5PRD register should be read. If a read instruction is executed for P5DR, P5OUTCR and P5PRD, read data of bits 7 to 4 are unstable. STOP OUTEN P5OUTCRi P5OUTCRi input Data input (P5PRD) Data input (P5DR) Data output (P5DR) Control output D Q P5i Note: i = 3 to 0 D Q Output latch 7 P5DR (0005H) R/W 6 5 4 3 P53 2 P52 1 P51 DVO 0 P50 PPG (Initial value: **** 1111) *: Don't care Figure 2.2.9 Port 5 86FP24-57 2007-08-24 TMP86FP24 P5OUTCR (000DH) Port P5 output circuit control (Set for each bit individually) 0: Sink open-drain output 1: CMOS output (Initial value: **** 0000) *: Don't care P5OUTCR R/W P5PRD (1FF2H) Read only P53 P52 P51 P50 Figure 2.2.10 P5OUTCR and P5PRD 86FP24-58 2007-08-24 TMP86FP24 2.2.7 Port P6 (P67 to P60) Port P6 is an 8-bit input/output port which can be configured as an input or an output in one-bit unit. Port P6 is also used as an analog input and key-on wakeup input. Input/output mode is specified by the P6 control register (P6CR1). P6 port input is controlled by the input control register (P6CR2). When used as an output port, respective P6CR1 should be set to "1". When used as an input port, respective P6CR1 should be cleared to "0" and respective P6CR2 should be set to "1". When used as an analog input, respective P6CR2 should be cleared to "0" after respective P6CR1 is cleared to "0". When used as a key-on wakeup input, respective STOPkEN P6CR1 0 0 1 1 *: Don't care P6CR2 0 1 * * P6DR * * 0 1 P6DR read "0" Terminal input "0" (Output latch) "1" (Output latch) Output High-Z High-Z Low High Remark - Input mode Output mode Output mode Table 2.2.4 P67 to P64 State STOPkEN 0 0 0 0 1 Note 1: Note 2: P6CR1 0 0 1 1 * *: Don't care STOPkEN is bit7 to bit4 in STOPCR. P6CR2 0 1 * * * P6DR * * 0 1 * P6DR read "0" Terminal input "0" (Output latch) "1" (Output latch) Terminal input Output High-Z High-Z Low High High-Z Remark - Input mode Output mode Output mode Key-on wakeup Analog input AINDS SAIN STOP OUTEN P6CR2i P6CR2i input P6CR1i P6CR1i input Data input (P6DR) P6i Note 1: i = 3 to 0 Note 2: SAIN is bit0 to bit3 in ADCCR1 D Q D Q Data output (P6DR) D Q Figure 2.2.11 Port 6 (P63 to P60) 86FP24-59 2007-08-24 TMP86FP24 Analog input AINDS SAIN STOPkEN STOP OUTEN P6CR2j P6CR2j input P6CR1j P6CR1j input STOPk input Data input (P6DR) P6j Note 1: j = 7 to 4, k = 3 to 0 Note 2: SAIN is bit0 to bit3 in ADCCR1 Note 3: STOPkEN is bit7 to bit4 in STOPCR. D Q D Q Data output (P6DR) D Q P6DR (0006H) R/W 7 6 5 4 P67 P66 P65 P64 AIN7 AIN6 AIN5 AIN4 STOP3 STOP2 STOP1 STOP0 3 P63 AIN3 2 P62 AIN2 1 P61 AIN1 0 P60 AIN0 (Initial value: 0000 0000) P6CR1 (000CH) Port P6 I/O control (Set for each bit individually) 0: Input mode or analog input 1: Output mode (Initial value: 0000 0000) P6CR1 R/W P6CR2 (0028H) Port P6 input control (Set for each bit individually) 0: Input disable 1: Input enable (Initial value: 1111 1111) P6CR2 R/W Note 1: Note 2: Do not set output mode to pin which is used for an analog input. If both P6CR1 and P6CR2 are cleared to "0", the read value of P6DR is always "0". Figure 2.2.12 Port 6 (P67 to P64), P6DR, P6CR1 and P6CR2 86FP24-60 2007-08-24 TMP86FP24 2.2.8 Port P9 (P97 to P90) Port P9 is an 8-bit input/output port which is also used as a segment pins of LCD. P9 port has pull-down resistors that programming control is possible. Pull-down control is specified by control register (P9PDCR). To connect pull-down resistor, P9PDCR should be set to "1". When used as an input port, the respective output latch (P9DR) should be set to "1" and the respective P9LCR bit should be cleared to "0". When used as an output port, the respective P9LCR bit should be cleared to "0". When used as a segment pins of LCD, the respective bit of P9LCR should be set to "1". During reset, the P9DR is initialized to "1" and the P9LCR and the P9PDCR are initialized to "0". P9 port output latch (P9DR) and P9 port terminal input (P9PRD) are located on their respective address. When read the output latch data, the P9DR should be read and when read the terminal input data, the P9PRD register should be read. Table 2.2.5 shows a P9 state. Table 2.2.5 P97 to P90 State P9LCR 0 0 0 0 1 1 Note 1: Note 2: *: Don't care EDSP is bit7 in LCDCR. EDSP * * * * 0 1 P9PDCR 0 0 1 1 * * P9DR 0 1 0 1 * * P9PRD read Terminal input Terminal input Terminal input Terminal input "0" "0" Output Low High-Z Low Low Low Segment Remark I/O I/O I/O (Pull down) I/O (Pull down) LCD Blanking LCD STOP OUTEN P9LCR P9LCR input Data input (P9PRD) Data input (P9DR) Data output (P9DR) LCD data output P9PDCR P9PDCR input D Q D Q P9i Note: i = 7 to 0 D Q Output latch Figure 2.2.13 Port 9 86FP24-61 2007-08-24 TMP86FP24 P9DR (0009H) R/W P9LCR (1FE9H) 7 P97 SEG8 6 P96 SEG9 5 P95 SEG10 4 P94 SEG11 3 P93 SEG12 2 P92 SEG13 1 P91 SEG14 0 P90 SEG15 (Initial value: 1111 1111) (Initial value: 0000 0000) Port P9/segment output control (Set for each bit individually) 0: P9 input/output port 1: LCD segment output P9LCR R/W P9PDCR (1FE8H) Port P9 pull-down control (Set for each bit individually) 0: Pull-down disable 1: Pull-down enable (Initial value: 0000 0000) P9PDCR R/W P9PRD (1FF3H) Read only P97 P96 P95 P94 P93 P92 P91 P90 Figure 2.2.14 P9DR, P9LCR, P9PDCR and P9PRD 86FP24-62 2007-08-24 TMP86FP24 2.2.9 WAKE Pin The TMP86FP24 has the function of outputting a monitor signal to the outside upon release of STOP mode by an external interrupt signal input. This pin is assigned as the dedicated output pin and it has N-ch open-drain form. This function enables the real time notification of the start/release of STOP mode timing to the outside. Therefore, it is effective for the system which requires the stop control against a peripheral device connected to the microcontroller. VDD WAKE pin STOP (STOP mode start signal) RESET (Internal reset signal) Figure 2.2.15 WAKE Pin While the microcontroller is operating, "L" level is output from the WAKE pin. When STOP mode is initiated and the operation of CPU is stopped, the WAKE pin becomes the high impedance state. When STOP mode is released by an external interrupt signal input, the WAKE pin becomes "L" level. Therefore, during warm-up, the WAKE pin is "L" level. During reset, the WAKE pin is in the high impedance state. Table 2.2.6 shows the WAKE pin state and Figure 2.2.16 shows the WAKE pin output timing. Table 2.2.6 WAKE Pin State State During reset During operation (except in STOP mode) During STOP mode During warm-up WAKE pin output High impedance "L" High impedance "L" Clock input Internal reset Start Release Warm-up end STOP instruction WAKE pin High-Z "L" Output High-Z "L" Output Figure 2.2.16 WAKE Pin Output Timing 86FP24-63 2007-08-24 TMP86FP24 2.3 Time-base-timer (TBT) The time-base-timer generates time base for key scanning, dynamic displaying, etc. It also provides a time base timer interrupt (INTTBT). An INTTBT is generated on the first falling edge of source clock (the divider output of the timing generator) after the time base timer has been enabled. The divider is not cleared by the program; therefore, only the first interrupt may be generated ahead of the set interrupt period (Figure 2.3.1 (b)). The interrupt frequency (TBTCK) must be selected with the time base timer disabled (the interrupt frequency must not be changed with the disable from the enable state). Both frequency selection and enabling can be performed simultaneously. MPX fc/2 21 fc/2 16 fc/2 14 fc/2 13 fc/2 12 fc/2 11 fc/2 9 fc/2 23 or or or or or or or or fs/2 13 fs/2 8 fs/2 6 fs/2 5 fs/2 4 fs/2 3 fs/2 fs/2 15 A B C D E F G H 3 TBTCK Source clock Y Falling edge detector IDLE0/SLEEP0 release request INTTBT interrupt request S TBTEN TBTCR Time-base-timer control register (a) Configuration Source clock TBTEN INTTBT Interrupt period Enable TBT (b) Time-base-timer interrupt MPX: Multiplexer Figure 2.3.1 Time-base-timer Example: Sets the time-base-timer frequency to fc/2 [Hz] and enables an INTTBT interrupt. LD (TBTCR), 00000010B ; TBTCK 010 LD (TBTCR), 00001010B ; TBTEN 1 DI ; IMF 0 SET (EIRL), 6 16 86FP24-64 2007-08-24 TMP86FP24 TBTCR (0036H) 7 (DVOEN) 6 5 4 (DV7CK) 3 TBTEN 2 1 TBTCK 0 (Initial value: 0000 0000) (DVOCK) TBTEN Time-base-timer enable/disable 0: Disable 1: Enable NORMAL1/2, IDLE1/2 Mode 000 001 010 011 100 101 110 111 DV7CK = 0 23 fc/2 21 fc/2 16 fc/2 14 fc/2 13 fc/2 12 fc/2 11 fc/2 9 fc/2 DV7CK = 1 15 fs/2 13 fs/2 8 fs/2 6 fs/2 5 fs/2 4 fs/2 3 fs/2 fs/2 SLOW, SLEEP Mode fs/2 13 fs/2 - - - - - - 15 TBTCK Time-base-timer interrupt frequency select [Hz] R/W Note: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Figure 2.3.2 Time-base-timer Control Register Table 2.3.1 Time-base-timer Interrupt Frequency (Example: fc = 16 MHz, fs = 32.768 kHz) Time-base-timer Interrupt Frequency [Hz] TBTCK 000 001 010 011 100 101 110 111 NORMAL1/2, IDLE1/2 Modes DV7CK = 0 1.91 7.63 244.14 976.56 1953.13 3906.25 7812.5 31250 DV7CK = 1 1 4 128 512 1024 2048 4096 16384 SLOW, SLEEP Modes 1 4 - - - - - - 86FP24-65 2007-08-24 TMP86FP24 2.4 Watchdog Timer (WDT) The watchdog timer is a fail-safe system to rapidly detect the CPU malfunctions such as endless looping caused by noise or the like, or deadlock and resume the CPU to the normal state. The watchdog timer signal for detecting malfunction can be selected either a "reset request" or a non-maskable "interrupt request". However, selection is possible only once after reset. At first the "reset request" is selected. When the watchdog timer is not being used for malfunction detection, it can be used as a timer to generate an interrupt at fixed intervals. Note: Care must be given in system design so as to protect the Watchdog timer from disturbing noise. Otherwise the watchdog timer may not fully exhibit its functionality. 2.4.1 Watchdog Timer Configuration Reset release signal from TG Binary counters Clock 1 2 R Overflow WDT output SQ Interrupt request 2 INTWDT Reset request fc/2 or fs/2 21 13 fc/2 or fs/2 19 11 fc/2 or fs/2 17 9 fc/2 or fs/2 Clear 23 15 MPX A B Y C DS Internal reset Q S R WDTT WDTEN Writing disable code Writing clear code WDTOUT Controller 0034H WDTCR1 0035H WDTCR2 MPX: Multiplexer Watchdog timer control registers Figure 2.4.1 Watchdog Timer Configuration 86FP24-66 2007-08-24 TMP86FP24 2.4.2 Watchdog Timer Control Figure 2.4.2 shows the watchdog timer control registers (WDTCR1, WDTCR2). The watchdog timer is automatically enabled after reset. (1) Malfunction detection methods using the watchdog timer The CPU malfunction is detected as follows. 1. 2. Setting the detection time, selecting output, and clearing the binary counter. Repeatedly clearing the binary counter within the setting detection time If the CPU malfunctions such as endless looping or deadlock occur for any cause, the watchdog timer output will become active at the rising of an overflow from the binary counters unless the binary counters are cleared. At this time, when WDTCR1 21 Example: Sets the watchdog timer detection time to 2 /fc [s] and resets the CPU malfunction. LD (WDTCR2), 4EH ; Clears the binary counters. LD (WDTCR1), 00001101B ; WDTT 10, WDTOUT 1 LD (WDTCR2), 4EH ; Clears the binary counters. Within 3/4 of (Always clear immediately before and WDT after changing WDTT.) detection time LD (WDTCR2), 4EH ; Clears the binary counters. Within 3/4 of WDT detection time LD (WDTCR2), 4EH ; Clears the binary counters. 86FP24-67 2007-08-24 TMP86FP24 Watchdog Timer Register 1 WDTCR1 7 6 (0034H) 5 4 3 2 WDTT 1 0 WDTOUT (ATAS) (ATOUT) WDTEN (Initial value: **11 1001) WDTEN Watchdog timer enable/disable 0: Disable (It is necessary to write the disable code to WDTCR2) 1: Enable NORMAL1/2 mode DV7CK = 0 DV7CK = 1 2 /fs 15 2 /fs 13 2 /fs 11 2 /fs 17 SLOW mode 2 /fs 15 2 /fs 13 2 /fs 11 2 /fs 17 WDTT Watchdog timer detection time [s] 00 01 10 11 0: Interrupt request 1: Reset request 2 /fc 23 2 /fc 21 2 /fc 19 2 /fc 25 Write only WDTOUT Note 1: Note 2: Note 3: Note 4: Watchdog timer output select WDTOUT cannot be set to "1" by program after clearing WDTOUT to "0". fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care WDTCR1 is a write-only register and must not be used with any of read-modify-write instructions. The watchdog timer must be disabled or the counter must be cleared immediately before entering to the STOP mode. When the counter is cleared, the counter must be cleared again immediately after releasing the STOP mode. Note 5: To disable the watchdog timer, always write "4EH" (Clear code) to WDTCR2 for clearing the binary counter before writing "0" to WDTEN, and then write "B1H" (Disable code) to WDTCR2. Also, immediately before these procedure, disable the interrupt mater flag (IMF) by DI instruction. Watchdog Timer Register 2 WDTCR2 7 6 (0035H) 5 4 3 2 1 0 (Initial value: **** ****) 4EH: WDTCR2 Watchdog timer control code write register B1H: D2H: Watchdog timer binary counter clear (Clear code) Watchdog timer disable (Disable code) Enable assigning address trap area Write only Others: Invalid Note 1: Note 2: Note 3: Note 4: The disable code is invalid unless written when WDTCR1 Figure 2.4.2 Watchdog Timer Control Registers (2) Watchdog timer enable The watchdog timer is enabled by setting WDTCR1 86FP24-68 2007-08-24 TMP86FP24 Example: Disables watchdog timer. DI LD (WDTCR2), 4EH LDW (WDTCR1), 0B101H ; ; ; IMF 0 Clear the binary counter. WDTEN 0, WDTCR2 Disable code. Table 2.4.1 Watchdog Timer Detection Time (Example: fc = 16 MHz, fs = 32.768 kHz) Watchdog Timer Detection Time [s] WDTT 00 01 10 11 NORMAL1/2 Mode DV7CK = 0 2.097 524.288 m 131.072 m 32.768 m DV7CK = 1 4 1 250 m 62.5 m SLOW Mode 4 1 250 m 62.5 m 2.4.3 Watchdog Timer Interrupt (INTWDT) This is a non-maskable interrupt which can be accepted regardless of the contents of the EIR. If a watchdog timer interrupt or a software interrupt is already accepted, however, the new watchdog timer interrupt waits until the previous interrupt processing is completed (the end of the [RETN] instruction execution). The stack pointer (SP) should be initialized before using the watchdog timer output as an interrupt source with WDTOUT. Example: Watchdog timer interrupt setting up. LD SP, 023FH LD (WDTCR1), 00001000B ; ; Sets the stack pointer. WDTOUT 0 2.4.4 Watchdog Timer Reset If the watchdog timer reset request occur, a reset is generated and the internal hardware is reseted. When the Watchdog timer reset is generated, the EEPROM reset is also generated. Therefore, the maximum reset period is 24/fc [s] + 210/fc [s] (65.5 s at 16.0 MHz). Note: The high-frequency clock oscillator also immediately turns on when a watchdog timer reset is generated in SLOW mode. In this case, the reset time may include a certain amount of error if there is any fluctuation of the oscillation frequency at starting the high-frequency clock oscillation. Therefore, the reset time must be considered an approximated value. 2 /fc [s] 2 /fc 17 19 Clock Binary counter Overflow INTWDT interrupt (WDTCR1 (WDTT = 11B) 1 2 3 0 1 2 3 0 Internal reset (WDTCR1 Reset generate Write 4EH to WDTCR2 Figure 2.4.3 Watchdog Timer Interrupt/Reset 86FP24-69 2007-08-24 TMP86FP24 2.4.5 Address Trap The watchdog timer control register 1, 2 shares its addresses with the control registers in case of address trap. These control registers for address trap are shown on Figure 2.4.4. Watchdog Timer Control Register 1 WDTCR1 7 6 5 (0034H) ATAS - - 4 3 2 (WDTT) 1 0 (WDTOUT) ATOUT (WDTEN) (Initial value: **11 1001) ATAS Selection of address trap in internal RAM Selection of operation at address trap 0: No address trap 1: Address trap (After setting ATAS to "1", it is necessary to write the control code D2H to WDTCR2) 0: Interrupt request 1: Reset request Write only ATOUT Watchdog Timer Control Register 2 WDTCR2 7 6 5 (0035H) 4 3 2 1 0 (Initial value: **** ****) Watchdog timer control code WDTCR2 and address trapped area control code D2H: Address trapped area valid to set (ATRAP control code) 4EH: Watchdog timer binary counter clear (WDT clear code) B1H: Watchdog timer disable(WDT disable code) Others: Invalid Write only Figure 2.4.4 Watchdog Timer Control Registers (1) Selection of address trap in internal RAM (ATAS) Using WDTCR1 86FP24-70 2007-08-24 TMP86FP24 2.5 Divider Output (DVO) Approximately 50% duty pulse can be output using the divider output circuit, which is useful for piezoelectric buzzer drive. Divider output is from pin P51 ( DVO ). The P51 output latch should be set to "1". Note: Selection of divider output frequency must be made while divider output is disabled. Also, in other words, when changing the state of the divider output frequency from enabled to disable, do not change the setting of the divider output frequency. 7 DVOEN 6 DVOCK 5 4 3 2 1 (TBTCK) 0 (Initial value: 0000 0000) TBTCR (0036H) (DV7CK) (TBTEN) 0: Disable 1: Enable DVOEN Divider output enable/disable NORMAL1/2 Mode DV7CK = 0 DVOCK Divider output ( DVO ) frequency selection [Hz] 00 01 10 11 Note: fc/2 12 fc/2 11 fc/2 10 fc/2 13 DV7CK = 1 fs/2 4 fs/2 3 fs/2 2 fs/2 5 SLOW, SLEEP Mode fs/2 fs/2 fs/2 fs/2 5 4 3 2 R/W fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Figure 2.5.1 Divider Output Control Register Example: 1.95 kHz pulse output (at fc = 16.0 MHz). SET (P5DR).1 LD (TBTCR), 00000000B LD (TBTCR), 10000000B ; ; ; P51 output latch "1" DVOCK "00" DVOEN "1" Table 2.5.1 Divider Output Frequency (Example: at fc = 16.0 MHz, fs = 32.768 kHz) Divider Output Frequency [Hz] DVOCK 00 01 10 11 NORMAL1/2, IDLE1/2 Mode DV7CK = 0 1.953 k 3.906 k 7.813 k 15.625 k DV7CK = 1 1.024 k 2.048 k 4.096 k 8.192 k SLOW, SLEEP Mode 1.024 k 2.048 k 4.096 k 8.192 k Output latch Data output D Q P51 ( DVO ) MPX: Multiplexer MPX fc/2 or fs/2 12 4 fc/2 or fs/2 11 3 fc/210 or fs/22 fc/2 or fs/2 DVOCK TBTCR Divider output control register (a) Configuration DVO pin output 13 5 A B C D 2 Y S P51 output latch DVOEN DVOEN (b) Timing Chart Figure 2.5.2 Divider Output 86FP24-71 2007-08-24 MCAP1 2.6 2.6.1 S TC1S 2 Command start INTTC1 interrupt Start Set Q MPPG1 TC1S clear PPG output mode Clear METT1 A Y B MPX External trigger start Decoder Configuration Pulse width measurement mode External trigger Falling Rising 16-Bit Timer/Counter 1 Edge detector TC1 pin MPX B Y A S Window mode Capture Match CMP Clear Source clock Clear MPX Port (Note 2) 16-bit up counter Pulse width measurement mode D Figure 2.6.1 Timer/Counter 1 (TC1) PPG output mode Q Set Toggle Internal reset 86FP24-72 B ACAP1 fc/2 or fs/2 7 fc/2 3 fc/2 11 3 A BY C S 2 Toggle Q Set Clear Y TC1DRA A S Port (Note 2) PPG pin TC1CK TC1CR TC1DRB TC1 control register 16-bit timer register 1A, B TC1CR write strobe TFF1 Note 1: MPX: Multiplexer CMP: Comparator TMP86FP24 2007-08-24 Note 2: When control input/output is used, I/O port setting should be set correctly. For details, refer to 2.2 "I/O Ports". TMP86FP24 2.6.2 Control The timer/counter 1 is controlled by a timer/counter 1 control register (TC1CR) and two 16-bit timer registers (TC1DRA and TC1DRB). 15 TC1DRA (0021,0020H) R/W TC1DRB (0023,0022H) R/W Note: 7 TC1CR (001FH) 14 13 12 11 10 TC1DRAH (0021H) 9 8 7 6 5 4 3 2 TC1DRAL (0020H) 1 0 (Initial value: 1111 1111 1111 1111) TC1DRBH (0023H) TC1DRB should not be written except PPG mode. 6 5 TC1S 4 3 2 1 0 (Initial value: 0000 0000) TC1DRBL (0022H) (Initial value: 1111 1111 1111 1111) ACAP1 MCAP1 TFF1 METT1 MPPG1 TC1CK TC1M TC1M TC1 operating mode select 00: 01: 10: 11: TC1CK TC1 source clock select [Hz] 00 01 10 11 00: 01: 10: 11: Timer/external trigger timer/event counter mode Window mode Pulse width measurement mode PPG (Programmable pulse generate) output mode NORMAL1/2, IDLE1/2 mode SLOW1/2, SLEEP1/2 mode DV7CK=0 DV7CK=1 3 11 3 fs/2 fs/2 fc/2 7 7 fc/2 fc/2 - 3 3 fc/2 fc/2 - External clock (TC1 pin input) Timer Extend Event Window Pulse PPG TC1S TC1 start control Stop and counter clear Command start External trigger start at the rising edge External trigger start at the falling edge x x x x x x R/W ACAP1 MCAP METT1 MPPG1 TFF1 Auto capture control 0: Auto-capture disable Pulse width measurement 0: Double edge capture mode control External trigger timer mode 0: Trigger start control PPG output control Time F/F1 control Note 1: Note 2: 0: Clear 1: Auto-capture enable 1: Single edge capture 1: Trigger start and stop 0: Continuous pulse generation 1: One shot 1: Set fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz] The timer register consists of two shift registers. A value set in the timer register is put in effect at the rising edge of the first source clock pulse that occurs after the upper data (TC1DRAH and TC1DRBH) are written. Therefore, the lower byte must be written before the upper byte (It is recommended that a 16-bit access instruction be used in writing). Writing only the lower data (TC1DRAL and TC1DRBL) does not put the setting of the timer register in effect. Set the mode, source clock, PPG control and timer F/F control when TC1 stops (TC1S = 00). Auto capture can be used in only timer, event counter, and window modes. Values to be loaded to timer registers must satisfy the following condition. TC1DRA > TC1DRB > 1 (PPG output mode), TC1DRA > 1 (others) Note 3: Note 4: Note 5: Note 6: Note 7: Note 8: Always write "0" to TFF1 except PPG output mode. Writing to the TC1DRB is not possible unless TC1 is set to the PPG output mode. On entering STOP mode, the TC1 start control (TC1S) is cleared to "00" automatically. So, the timer stops. Once the STOP mode has been released, to start using the timer counter, set TC1S again. Note 9: Use the auto-capture function in the operative condition of TC1. A captured value may not be fixed if it's read after the execution of the timer stop or auto-capture disable. Read the capture value in a capture enabled condition. 86FP24-73 2007-08-24 TMP86FP24 Note 10: Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR Figure 2.6.2 Timer Registers and TC1 Control Register 2.6.3 Function Timer/counter 1 has six operating modes: Timer, external trigger timer, event counter, window, pulse width measurement, programmable pulse generator output mode. (1) Timer mode In this mode, counting up is performed using the internal clock. The contents of TC1DRA are compared with the contents of up counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to "0". Counting up resumes after the counter is cleared. The current contents of up counter can be transferred to TC1DRB by setting TC1CR Table 2.6.1 Source Clock (Internal clock) for Timer/Counter 1 (Example: at fc = 16 MHz, fs = 32.768kHz) NORMAL1/2, IDLE1/2 Modes DV7CK = 0 TC1CK Resolution [s] 00 01 10 128 8.0 0.5 SLOW1/2, SLEEP1/2 Modes Maximum Time Setting [s] 16.0 0.524 32.77 m 11 DV7CK = 1 Resolution [s] 244.14 8.0 0.5 Maximum Time Setting [s] 8.39 0.524 32.77 m Resolution [s] 244.14 - - Maximum Time Setting [s] 16.0 - - Example 1: Sets the timer mode with source clock fc/2 [Hz] and generates an interrupt 1 second later (at fc = 16 MHz, DV7CK = 0). LDW DI SET EI LD LD Example 2: Auto capture. LD LD Note : (TC1CR), 01010000B WA, (TC1DRB) ACAP1 "1" (Capture) Reads the capture value. (TC1CR), 00000000B (TC1CR), 00010000B (EIRL). 5 (TC1DRA), 1E84H ; Sets the timer register. (1 s / 2 /fc = 1E84H) 11 IMF = "0" Enable INTTC1. IMF = "1" TFF1 "0", TC1CK "00", TC1M "00" Starts TC1. Since the up-counter value is captured into TC1DRB by the source clock of up-counter after setting TC1CR 86FP24-74 2007-08-24 TMP86FP24 Command start Source clock Up counter TC1DRA INTTC1 interrupt Source clock Up counter TC1DRB ACAP1 (b) Auto capture ? m-2 m-1 m-1 m m+1 Capture m m+1 m+2 m+2 n-1 n-1 n n+1 Capture n n+1 ? 0 n Match detect (a) Timer mode Counter clear 1 2 3 4 n-1 n 0 1 2 3 4 5 6 7 Figure 2.6.3 Timer Mode Timing Chart 86FP24-75 2007-08-24 TMP86FP24 (2) External trigger timer mode In this mode, counting up is started by an external trigger. This trigger is the edge of the TC1 pin input. Either the rising or falling edge can be selected with TC1S. Source clock is an internal clock. The contents of TC1DRA is compared with the contents of up counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared to "0" and halted. The counter is restarted by the selected edge of the TC1 pin input. When TC1CR Example 1: Detects rising edge in TC1 pin input and generates an interrupt 100 s later (at fc = 16 MHz, DV7CK = 0). DI LDW SET EI LD LD (at fc = 16 MHz). DI LDW SET EI LD LD (TC1CR), 01001000B (TC1CR), 01111000B (TC1DRA), 1F40H (EIRL). 5 ; ; ; ; ; ; IMF = "0" 4 ms / 2 /fc = 1F40H 3 ; (TC1DRA), 00C8H (EIRL). 5 (TC1CR), 00001000B (TC1CR), 00101000B ; ; ; ; ; IMF = "0" 100 s / 2 /fc = C8H 3 INTTC1 interrupt enable. IMF = "1" TFF1 = "0", TC1CK = "10", TC1M = "00" TC1 external trigger start, METT1 = "0" Example 2: Generates an interrupt, inputting "L" level pulse (Pulse width: 4 ms or more) to the TC1 pin INTTC1 interrupt enable. IMF = "1" TFF1 = "0", TC1CK = "10", TC1M = "00" TC1 external trigger start, METT1 = 1 86FP24-76 2007-08-24 TMP86FP24 Count start TC1 pin input Internal clock Up counter TC1DRA INTTC1 interrupt ? n Match detect (a) Trigger start (METT1 = 0) Count start TC1 pin input Internal clock Up counter TC1DRA INTTC1 interrupt n Match detect (b) Trigger start and Stop (METT1 = 1) Counter clear 0 1 2 3 m 0 1 n-2 n-1 n Count start Trigger Trigger TC1S = 10 at the rising edge 0 1 2 3 n-1 n 0 1 2 3 Counter clear Count clear Count start Trigger Trigger Trigger TC1S = 10 at the rising edge 0 Note: m < n Figure 2.6.4 External Trigger Timer Mode Timing Chart (3) Event counter mode In this mode, events are counted at the edge of the TC1 pin input (Either the rising or falling edge can be selected with the external trigger TC1CR1 Count start TC1 pin input Up counter TC1DRA INTTC1 interrupt ? 0 n Match detect Counter clear 1 2 n-1 n 0 1 2 TC1S = 10 at the rising edge Figure 2.6.5 Event Counter Mode Timing Chart 86FP24-77 2007-08-24 TMP86FP24 Table 2.6.2 Timer/Counter 1 External Clock Source Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 Modes "H" Width "L" Width 2 /fc 2 /fc 3 3 SLOW1/2, SLEEP1/2 Modes 2 /fs 2 /fs 3 3 (4) Window mode In this mode, counting up is performed on the rising edge of the pulse that is the logical AND-ed product of the TC1 pin input (Window pulse) and an internal clock. The contents of TC1DRA are compared with the contents of up counter. If a match is found, an INTTC1 interrupt is generated, and the counter is cleared. It is possible to select either positive logic or negative logic for the TC1 pin input (by using the TC1 start control TC1CR Count start Command start TC1 pin input Internal clock Up counter TC1DRA INTTC1 interrupt Command start TC1 pin input Internal clock Up counter TC1DRA INTTC1 interrupt (b) Negative logic (at TC1S = 11) ? 9 Match detect Counter clear 0 1 2 3 4 5 6 7 8 901 Count start ? 7 Match detect (a) Positive logic (at TC1S = 10) Count stop Counter clear 0 1 2 3 4 5 6 70 1 2 3 Count stop Count start Count start Figure 2.6.6 Window Mode Timing Chart 86FP24-78 2007-08-24 TMP86FP24 (5) Pulse width measurement mode In this mode, counting is started by the external trigger (Set to external trigger start by TC1CR Example: Duty measurement (resolution fc/2 [Hz]). CLR LD DI SET EI LD PINTTC1: CPL JRS LD LD RETI SINTTC1: LD LD RETI VINTTC1: DW PINTTC1 L, (TC1DRBL) H, (TC1DRBH) ; Duty calculation. ; Reads TC1DRB (Period). (TC1CR), 00100110B (INTTC1SW). 0 F, SINTTC1 A, (TC1DRBL) W, (TC1DRBH) ; Reads TC1DRB ("H" level pulse width). (EIRL). 5 (INTTC1SW). 0 (TC1CR), 00000110B ; ; ; ; ; ; ; INTTC1 service switch initial setting. Sets the TC1 mode and source clock. IMF = "0" Enables INTTC1. IMF = "1" Starts TC1 with an external trigger at MCAP1 = 0. Inverts INTTC1 service switch. 7 WIDTH HPULSE TC1 pin INTTC1SW 86FP24-79 2007-08-24 TMP86FP24 Count start Trigger Count start (TC1S = "10") TC1 pin input Internal clock Up counter TC1DRB INTTC1 interrupt 0 1 2 3 4 n-1 n 0 Capture n 1 2 3 TC1 pin input Internal clock Up counter TC1DRB INTTC1 interrupt Count start [Application] "H" or "L" level pulse width measurement (a) Single edge capture (MCAP1 = "1") Count start (TC1S = "10") 0 1 2 3 4 n-1 n n+1 n+2 n+3 Capture n m-2 m-1 m 0 1 Capture m 2 [Application] (1) Period/frequency measurement (2) Duty measurement (b) Double edge capture (MCAP1 = "0") Figure 2.6.7 Pulse Measurement Mode Timing Chart 86FP24-80 2007-08-24 TMP86FP24 (6) Programmable pulse generate (PPG) output mode The PPG output mode is intended to output pulses having an arbitrary duty cycle selected using two timer registers. The timer starts at an edge (Rising or falling edge), that is, the same edge type as selected with the external trigger edge select bits (TC1CR Example: Pulse output "H" level 800 s, "L" level 200 s (at fc = 16 MHz, DV7CK = 0). SET LD LDW LDW LD (P5DR). 0 (TC1CR), 10001011B (TC1DRA), 07D0H (TC1DRB), 0190H (TC1CR), 10011011B ; ; ; ; ; P50 output latch 1 Sets the PPG output mode. Sets the period (1 ms / 2 /fc = 07D0H). 3 Sets "L" level pulse width (200 s / 2 /fc = 0190H). 3 Starts. 86FP24-81 2007-08-24 TMP86FP24 P50 output latch Data output D R Q TFF1 TC1CR write strobe Internal reset Match with TC1DRB Match with TC1DRA INTTC1 interrupt MPPG1 Set Clear Q P50 ( PPG ) pin Toggle Timer F/F1 TC1S clear MPX: Multiplexer Figure 2.6.8 PPG Output Command start Internal clock Up counter TC1DRB TC1DRA PPG pin output 0 n 1 2 n n+1 m0 1 2 n n+1 m0 1 2 Match m INTTC1 interrupt (a) Continuous pulse generation (with TC1S = 01) Count start TC1 pin input Internal clock Up counter TC1DRB TC1DRA PPG pin output Note: m > n Trigger 0 n 1 n n+1 m 0 Match m INTTC1 interrupt [Application] One shot pulse output (b) One shot (with TC1S = 10) Note: m > n Figure 2.6.9 PPG Output Mode Timing Chart 86FP24-82 2007-08-24 TMP86FP24 2.7 16-Bit Timer/Counter 2 Configuration 2.7.1 (Note 2) TC2 pin 23 TC2S MPX H Source clock Y A S TC2M S 3 TC2CK TC2S CMP Match Enable Match detect control TC2DR 16-bit timer register 2 TC2DRL write strobe INTTC2 interrupt Port fc/2 or fs/2 13 5 fc/2 or fs/2 8 fc/2 3 fc/2 fc fs 15 Window A B C D E F B Timer/event counter Y Clear 16-bit up counter TC2CR TC2 control register TC2DRH write strobe Note 1: MPX: Multiplexer CMP: Comparator Note 2: When control input/output is used, I/O port setting should be set correctly. For details, refer to 2.2 "I/O ports". Figure 2.7.1 Timer/Counter 2 (TC2A) 86FP24-83 2007-08-24 TMP86FP24 2.7.2 Control The timer/counter 2 is controlled by a timer/counter 2 control register (TC2CR) and a 16-bit timer register 2 (TC2DR). Reset does not affect TC2DR. 15 TC2DR (0025, 0024H) R/W TC2CR (0013H) 14 13 12 11 10 TC2DRH (0025H) 9 8 7 6 5 4 3 2 TC2DRL (0024H) 1 0 7 6 5 TC2S 4 3 TC2CK 2 1 0 TC2M (Initial value: **00 00*0) TC2M TC2 operating mode select 0: 1: Timer/event counter mode Window mode NORMAL1/2, IDLE1/2 mode DV7CK=0 DV7CK=1 15 23 fs/2 fc/2 5 13 fs/2 fc/2 8 8 fc/2 fc/2 3 3 fc/2 fc/2 - - fs fs SLOW1/2 mode fs/2 5 fs/2 - - fc (Note 7) - 15 SLEEP1/2 mode fs/2 5 fs/2 - - - - 15 TC2CK TC2 source clock select [Hz] 000 001 010 011 100 101 110 111 0: 1: R/W Reserved External clock (TC2 pin input) Stop and counter clear Start TC2S Note 1: Note 2: TC2 start control fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care When writing to the timer register 2 (TC2DR), always write to the lower side (TC2DRL) and then the upper side (TC2DRH) in that order. Writing to only the lower side (TC2DRL) or the upper side (TC2DRH) has no effect. Note 3: The timer register 2 (TC2DR) uses the value previously set in it for coincidence detection until data is written to the upper side (TC2DRH) after writing data to the lower side (TC2DRL). Set the mode and source clock when the TC2 stops (TC2S = 0). Values to be loaded to the timer register must satisfy the following condition. TC2DR > 1 (TC2DR15 to 11 > 1 at warm up) Note 4: Note 5: Note 6: Note 7: Note 8: If a read instruction is executed for TC2CR, read data of bit7, bit6 and bit1 are unstable. The high-frequency clock (fc) can be selected only when the timer mode at SLOW2 mode is selected. On entering STOP mode, the TC2 start control (TC2S) is cleared to "0" automatically. So, the timer stops. Once the STOP mode has been released, to start using the timer counter, set TC2S again. Figure 2.7.2 Timer Register 2 and TC2 Control Register 86FP24-84 2007-08-24 TMP86FP24 2.7.3 Function The timer/counter 2 has three operating modes: timer, event counter and window modes. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TC2DR are compared with the contents of up counter. If a match is found, a timer/counter 2 interrupt (INTTC2) is generated, and the counter is cleared. Counting up is resumed after the counter is cleared. When fc is selected for source clock at SLOW2 mode, lower 11 bits of TC2DR are ignored and generated a interrupt by matching upper 5 bits. Though, in this situation, it is necessary to set TC2DRH only. Table 2.7.1 Source Clock (Internal clock) for Timer/Counter 2 (at fc = 16 MHz) NORMAL1/2, IDLE1/2 Modes TC2CK DV7CK = 0 Resolution 000 001 010 011 100 101 524.29 ms 512.00 s 16.00 s 0.50 s - 30.52 s Maximum Time Setting 9.54 h 33.55 s 1.05 s 32.77 ms - 2.00 s DV7CK = 1 Resolution 1.00 s 0.98 ms 16.00 s 0.50 s - 30.52 s Maximum Time Setting 18.20 h 1.07 min 1.05 s 32.77 ms - 2.00 s 1.00 s 0.98 ms - - 62.5 ns (Note) - 18.20 h 1.07 min - - - - 1.00 s 0.98 ms - - - - 18.20 h 1.07 min - - - - Resolution Maximum Time Setting Resolution Maximum Time Setting SLOW1/2 Mode SLEEP1/2 Mode Note: When fc is selected as the source clock in timer mode, it is used at warm up for switching from SLOW2 mode to NORMAL2 mode. Example: Sets the timer mode with source clock fc/2 [Hz] and generates an interrupt every 25 ms (at fc = 3 16 MHz). LDW DI SET EI LD LD (TC2CR), 00001100B (TC2CR), 00101100B (EIRE). 4 ; ; ; ; (TC2DR), 0C350H ; Sets TC2DR (25 ms / 2 /fc = C350H). 3 IMF = "0" Enables INTTC2 interrupt. IMF = "1" TC2CK "011", TC2M "0" Starts TC2. 86FP24-85 2007-08-24 TMP86FP24 (2) Event counter mode In this mode, events are counted on the rising edge of the TC2 pin input. The contents of TC2DR are compared with the contents of the up counter. If a match is found, an INTTC2 interrupt is generated, and the counter is cleared. The minimum input pulse width of the TC2 pin is shown in Table 2.7.2. Two or more machine cycles are required for both the "H" and "L" levels of the pulse width. Match detect is executed on the falling edge of the TC2 pin. A match can not be detected and INTTC2 is not generated when the pulse is still in a falling state. Example: Sets the event counter mode and generates an INTTC2 interrupt 640 counts later. LDW DI SET EI LD LD (TC2CR), 00011100B (TC2CR), 00111100B (EIRE). 4 (TC2DR), 640 ; ; ; ; ; ; Sets TC2DR. IMF = "0" Enables INTTC2 interrupt. IMF = "1" TC2CK "111", TC2M "0" Starts TC2. Table 2.7.2 Timer/Counter 2 External Clock Source Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 Modes "H" Width "L" Width 2 /fc 2 /fc 3 3 SLOW1/2, SLEEP1/2 Modes 2 /fs 2 /fs 3 3 86FP24-86 2007-08-24 TMP86FP24 (3) Window mode In this mode, counting up performed on the rising edge of an internal clock during TC2 external pin input (window pulse) is "H" level. The contents of TC2DR are compared with the contents of up counter. If a match found, an INTTC2 interrupt is generated, and the up counter is cleared. The maximum applied frequency (TC2 input) must be considerably slower than the selected internal clock. Note: In the window mode, before the SLOW/SLEEP mode is entered, the timer should be halted by setting TC2CR Example: Generates an interrupt, inputting "H" level pulse width of 120 ms or more (at fc = 16 MHz, DV7CK = 0). LDW DI SET EI LD LD (TC2CR), 00000101B (TC2CR), 00100101B (EIRE). 4 (TC2DR), 00EAH ; ; ; ; ; ; Sets TC2DR (120 ms / 2 /fc = 00EAH). 13 IMF = "0" Enables INTTC2 interrupt. IMF = "1" TC2CK "001", TC1M "1" Starts TC2. TC2 pin input Internal clock Up counter TC2DR INTTC2 interrupt n Match detect Counter clear 0 1 2 n-3 n-2 n-1 n 0 1 2 3 Figure 2.7.3 Window Mode Timing Chart 86FP24-87 2007-08-24 TMP86FP24 2.8 8-Bit Timer/Counter 3 Configuration TC3 input control register 2.8.1 TC3SEL TC3INV TC3 pin S TC3S Edge detector Falling MPX Y H A B C D E F G S 3 TC3CK TC3S TC3M ACAP Y Source clock Rising Clear Port (Note 2) 0 1 fc/2 or fs/2 12 4 fc/211 or fs/23 fc/210 or fs/22 fc/2 or fs/2 9 fc/28 or fs/2 fc/27 fc/2 13 5 8-bit up counter Overflow CMP Capture TC3DRB TC3DRA Capture Match 1 0 S Y INTTC3 interrupt TC3S 8-bit timer register 3A, B TC3CR TC3 control register Note 1: MPX: Multiplexer CMP: Comparator Note 2: When control input/output is used, I/O port setting should be set correctly. For details, refer to 2.2 "I/O ports". Figure 2.8.1 Timer/Counter 3 (TC3) 86FP24-88 2007-08-24 TMP86FP24 2.8.2 Control The timer/counter 3 is controlled by a timer/counter 3 control register (TC3CR) and two 8-bit timer registers (TC3DRA and TC3DRB). TC3DRA (0010H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) 7 TC3DRB (0011H) Read only 7 TC3CR (0012H) 6 5 4 3 2 1 0 (Initial value: 1111 1111) 6 ACAP 5 4 TC3S 3 2 TC3CK 1 0 TC3M (Initial value: *0*0 0000) TC3M TC3 operation mode set 0: Timer/event counter 1: Capture NORMAL1/2, IDLE1/2 Mode DV7CK = 0 DV7CK = 1 13 5 fs/2 fc/2 12 4 fc/2 fs/2 11 3 fc/2 fs/2 10 2 fc/2 fs/2 9 fc/2 fs/2 8 8 fc/2 fc/2 7 7 fc/2 fc/2 SLOW1/2, SLEEP1/2 Mode 5 fs/2 4 fs/2 3 fs/2 2 fs/2 fs/2 - - TC3CK TC3 source clock select [Hz] 000 001 010 011 100 101 110 111 R/W External clock (TC3 pin input) TC3S ACAP Note 1: Note 2: Note 3: TC3 start select Auto-capture control 0: Stop and clear 1: Start 0: - 1: Auto-capture enable fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Set the mode and the source clock when the TC3 stops (TC3S = 0). Values to be loaded into timer register 3A must satisfy the following condition. TC3DRA > 1 (in the timer and event counter mode) Note 4: Note 5: Note 6: Note 7: Auto capture can be used only in the timer and event counter mode. If a read instruction is executed for TC3CR, read data for bits 7 and 5 are unstable. During TC3 operation, do not change TC3DRA. On entering STOP mode, TC3 start control (TC3S) is cleared to "0" automatically, so the timer stops. Once the STOP mode has been released, to start using the timer counter, set TC3S again. TC3 input control (normal/invert) TC3SEL (0029H) 0: Normal 1: Invert 7 6 5 4 3 2 1 0 TC3INV (Initial value: **** ***0) TC3INV Note: TC3 input control R/W If a read instruction is executed for TC3SEL, read data for bits 7 to 1 are unstable. Figure 2.8.2 Timer Register 3 and TC3 Control Register 86FP24-89 2007-08-24 TMP86FP24 2.8.3 TC3 Input Control Register This microcomputer has the function to invert or not to invert the waveform entered from the TC3 pin. This selection is made by using TC3SEL 2.8.4 Function The timer/counter 3 has three operating modes: Timer, event counter, and capture mode. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TC3DRA are compared with the contents of up counter. If a match is found, a timer/counter 3 interrupt (INTTC3) is generated, and the up counter is cleared. The current contents of up counter are loaded into TC3DRB by setting TC3CR Clock Counter TC3DRB FE FE FF 00 FF 01 01 Table 2.8.1 Source Clock (Internal clock) for Timer/counter 3 (Example: at fc = 16 MHz) NORMAL1/2, IDLE1/2 Modes DV7CK = 0 TC3CK Resolution [s] 000 001 010 011 100 101 110 512.0 256.0 128.0 64.0 32.0 16.0 8.0 Maximum Time Setting [ms] 130.6 65.3 32.6 16.3 8.2 4.1 2.0 DV7CK = 1 Resolution [s] 976.6 488.3 244.1 122.0 61.0 16.0 8.0 Maximum Time Setting [ms] 249.0 124.5 62.3 31.1 15.6 4.1 2.0 976.6 488.3 244.1 122.0 61.0 - - 249.0 124.5 62.3 31.1 15.6 - - Resolution [s] SLOW1/2 Modes Maximum Time Setting [ms] 86FP24-90 2007-08-24 TMP86FP24 (2) Event counter mode In this mode, events are counted on the edge of the TC3 pin input. The input pulse at the TC3 pin can have its polarity inverted using the TC3SEL register TC3INV bit. When TC3SEL "H" Width "L" Width 2 /fc 2 /fc 2 2 SLOW1/2, SLEEP1/2 Modes 2 /fs 2 /fs 2 2 86FP24-91 2007-08-24 TMP86FP24 (3) Capture mode In this mode, the pulse width, period and duty of the TC3 pin input are measured in this mode, which can be used in decoding the remote control signals or distinguishing AC 50/60 Hz, etc. The TC3 pin input can have its polarity changed between normal and inverse by using the TC3SEL Register. a. If TC3SEL "0" (Non-inverting input) "1" (Inverting input) Capture into TC3DRB Falling edge Rising edge Capture into TC3DRA INTTC3 Interrupt Rising edge Falling edge When the overflow occurs before detecting the edge, the INTTC3 interrupt is generated, setting "FFH" to TC3DRA and clearing the counter. It is possible to confirm whether the overflow has occurred or not by reading TC3DRA in interrupt routine. After generating of interrupt, the capture function and overflow detection stop until the TC3DRA is read, but the counting is continued. Because the capture function and overflow detection are restarted by reading TC3DRA, read the TC3DRB before the reading TC3DRA. 86FP24-92 2007-08-24 Command start TC3S Source clock 1 1 2 3 FE FF 1 i-1 i 1 m-1 n-1 n 0 m m+1 i+1 k-1 k 0 2 3 Up counter 0 TC3 pin input Internal waveform (Normal) k n m Capture Capture FE Overflow i FF (Overflow) TC3DRA TC3DRB INTTC3 interrupt Reading TC3DRA a) In case of TC3INV = "0" (Normal) Command start Figure 2.8.3 Capture Mode Timing Chart 86FP24-93 1 i-1 i 0 1 k k-1 k+1 m-1 m 0 1 i k Capture Capture m b) In case of TC3INV = "1" (Invert) TC3S Source clock n-3 n-2 n-1 n 0 1 FE FF 1 2 3 Up counter 0 TC3 pin input Internal waveform (Invert) n n-2 Capture 2 When TC3DRA is not read, capture and overflow detection are stopped. TC3DRA TC3DRB INTTC3 interrupt TMP86FP24 2007-08-24 Reading TC3DRA TMP86FP24 2.9 8-Bit Timer/Counter 5 Configuration TC5S MPX 2.9.1 fc/2 or fs/2 7 fc/25 fc/23 fc/2 fc/2 fc/2 fc 2 11 3 A B C D Y E F G H Source clock Clear 8-bit up counter Overflow AY B S Match Timer F/F5 Toggle TC5 pin (Note 2) Port S 3 TC5CK TC5M TC5S 2 CMP Port A B YS PDO mode TC5S Clear PWM5 / (Note 2) PDO5 pin TC5CR TC5 control register TC5DR 8-bit timer register 5 INTTC5 interrupt PWM output mode Note 1: Note 2: MPX: Multiplexer CMP: Comparator When control input/output is used, I/O port setting should be set correctly. For details, refer to 2.2 "I/O ports". Figure 2.9.1 Timer/Counter 5 (TC5) 86FP24-94 2007-08-24 TMP86FP24 2.9.2 Control The timer/counter 5 is controlled by a timer/counter 5 control register (TC5CR) and an 8-bit timer register 5 (TC5DR). Reset does not affect TC5DR. TC5DR (0015H) R/W 7 6 5 4 3 2 1 0 (Initial value: 1111 1111) 7 TC5CR (0014H) 6 5 TC5S 4 3 TC5CK 2 1 0 (Initial value: **00 0000) TC5M TC5S TC5 start control 0: 1: Stop and counter clear Start NORMAL1/2, IDLE1/2 Modes DV7CK = 0 DV7CK = 1 11 3 fc/2 fs/2 7 7 fc/2 fc/2 5 5 fc/2 fc/2 3 3 fc/2 fc/2 2 2 fc/2 fc/2 fc/2 fc/2 fc fc Timer/event counter mode Reserved Programmable divider output (PDO) mode Pulse width modulation (PWM) output mode SLOW1/2, SLEEP1/2 Modes 3 fs/2 - - - - - - TC5CK TC5 source clock select [Hz] 000 001 010 011 100 101 110 111 00: 01: 10: 11: R/W External clock (TC5 pin input) TC5M TC5 operating mode select Note 1: Note 2: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz], *: Don't care Values to be loaded to the timer register must satisfy the following condition. 1 TC5DR 255 When TC5 operation is started (TC5S = "0" "1") or TC5 operation is stopped (TC5S = "1" "0"), do not change TC5CR Note 3: Note 4: Available source clocks for each operation mode is referred to the following table. Timer Mode 000 001 010 Event Counter Mode x x x x x x x PDO Mode PWM Mode x x x TC5CK 011 100 101 110 111 x x x x x x x x x x Note 5: Note 6: Note 7: The TC5S is automatically cleared to "0" after starting STOP mode. If a read instruction is executed for TC5CR, read data of bits 7 and 6 are unstable. During TC5 operation except PWM mode, do not change TC5DR. Figure 2.9.2 Timer Register 5 and TC5 Control Register 86FP24-95 2007-08-24 TMP86FP24 2.9.3 Function The timer/counter 5 has four operating modes: Timer, event counter, programmable divider output, and PWM output mode. (1) Timer mode In this mode, the internal clock is used for counting up. The contents of TC5DR is compared with the contents of up counter. If a match is found, an INTTC5 interrupt is generated and the up counter is cleared to "0". Counting up resumes after the up counter is cleared. Table 2.9.1 Source Clock (internal clock) for Timer/Counter 5 (Example: at fc = 16 MHz) NORMAL1/2, IDLE1/2 Modes DV7CK = 0 TC5CK Resolution [s] 000 001 010 011 128.0 8.0 2.0 0.5 Maximum Time Setting [ms] 32.6 2.0 0.510 0.128 DV7CK = 1 Resolution [s] 244.14 8.0 2.0 0.5 Maximum Time Setting [ms] 62.3 2.0 0.510 0.128 244.14 - - - 62.3 - - - Resolution [s] SLOW1/2 Modes Maximum Time Setting [ms] (2) Event counter mode In this mode, events are counted on the rising edge of the TC5 pin input (External clock). The contents of the TC5DR is compared with the contents of the up counter. If a match is found, an INTTC5 interrupt is generated and the counter is cleared. Counting up resumes after the up counter is cleared. The minimum input pulse width of the TC5 pin is shown in Table 2.9.2. Two or more machine cycles are required for both the "H" and "L" levels of the pulse width. Match detect is executed on the falling edge of the TC5 pin. A match can not be detected and INTTC5 interrupt is not generated when the pulse is still in a falling state. Note: In SLOW1/2 and SLEEP1/2 modes, because external clock is not received, can not use the event counter mode. Table 2.9.2 Timer/Counter 5 External Clock Source Minimum Input Pulse Width [s] NORMAL1/2, IDLE1/2 Modes "H" Width "L" Width 2 /fc 2 /fc 3 3 86FP24-96 2007-08-24 TMP86FP24 (3) Programmable divider output (PDO) mode The programmable divider output (PDO) mode is intended to output a pulse having a duty cycle of about 50%. The counter counts up on an internal source clock. If the timer value matches TC5DR, the timer F/F5 is inverted, and the counter is cleared, generating an INTTC5 interrupt. The counter keeps counting up, and the timer F/F5 is inverted each time the timer value matches TC5DR. The P13 ( PDO5 ) pin outputs an inversion of the timer F/F5 output level. At a reset or when the timer stops, the timer F/F5 is cleared to "0". So, stopping the timer when the PDO output is low may cause the duty cycle to become smaller than the set value. To use the programmable divider output mode, set the output latch of the P13 port to "1". Example: Output a 1024 Hz pulse (at fc = 16 MHz). LD SET LD LD (TC5CR), 00000110B (P1DR). 3 (TC5DR), 3DH (TC5CR), 00100110B ; ; ; ; Sets PDO mode. (TC5M = 10, TC5CK = 001) P13 output latch 1 1/1024 / 2 /fc / 2 = 3DH 7 Starts TC5. Internal clock Up counter TC5DR Timer F/F5 PDO5 pin output 0 1 n 2 n0 1 2 n0 1 2 n0 1 2 n0 1 Match detect INTTC5 interrupt Figure 2.9.3 PDO Mode Timing Chart 86FP24-97 2007-08-24 TMP86FP24 (4) Pulse width modulation (PWM) output mode The pulse width modulation (PWM) output mode is intended to output pulses at constant intervals with a resolution of 8 bits. The counter counts up on the internal source clock. If the timer value matches TC5DR, the timer F/F5 is inverted, and the counter keeps up counting. If an overflow is detected, the timer F/F5 is inverted again, generating an INTTC5 interrupt. The P13 ( PWM5 ) pin outputs an inversion of the timer F/F5 output level. At a reset or when the timer stops, the timer F/F5 is cleared to "0". So, stopping the timer when the PWM output is low may cause one cycle to become smaller than the set value. To use the pulse width modulation (PWM) output mode, set the output latch of the P13 port to "1". TC5DR is configured a 2-stage shift register and, during pulse width, will not switch until one output cycle is completed even if TC5DR is overwritten; therefore, pulse width can be altered continuously. Also, the first time, TC5DR is shifted by setting TC5CR Internal clock Up counter TC5DR Timer F/F5 PWM pin output 0 1 n/n Match n n+1 FF 0 1 n/m Overwrite n n+1 FF 0 1 m/m Shift m-1 m INTTC5 interrupt 1 cycle Figure 2.9.4 PWM Output Mode Timing Chart Table 2.9.3 PWM Output Mode (Example: at fc = 16 MHz) TC5CK 000 001 010 011 100 101 110 NORMAL1/2, IDLE1/2 Modes Resolution [ns] - - - 500 250 125 62.5 Repeat Cycle [s] - - - 128 64 32 16 86FP24-98 2007-08-24 TMP86FP24 2.10 UART (Asynchronous serial interface) The TMP86FP24 has 1 channel of UART (Asynchronous serial interface). The UART is connected to external devices via RXD and TXD. RXD is also used as P05; TXD, as P06. To use P05 or P06 as the RXD or TXD pin, set P0 port output latches to "1". 2.10.1 Configuration UART control register 1 Transmit data buffer UARTCR1 TDBUF Receive data buffer RDBUF 32 2 Shift register Parity bit Stop bit Shift register Receive control circuit Noise rejection circuit RXD Transmit control circuit INTTXD INTRXD Y Transmit/receive clock MPX fc/13 fc/26 fc/52 fc/104 fc/208 fc/416 INTTC5 fc/96 S A B CM DPY EX F G H M P X S 2 Counter UARTSR UART status register Baud rate generator 4 2 UARTCR2 UART control register 2 A B C fc/2 fc/2 fc/2 6 7 8 TXD MPX: Multiplexer Figure 2.10.1 UART 86FP24-99 2007-08-24 TMP86FP24 2.10.2 Control UART is controlled by the UART control registers (UARTCR1, UARTCR2). The operating status can be monitored using the UART status register (UARTSR). UART control register UARTCR1 (1FDDH) 7 TXE 6 RXE 5 STBT 4 EVEN 3 PE 2 1 BRG 000: fc/13 [Hz] 001: fc/26 010: fc/52 011: fc/104 100: fc/208 101: fc/416 110: TC5 (INTTC5) 111: fc/96 0: No parity 1: Parity 0: Odd-numbered parity 1: Even-numbered parity 0: 1 bit 1: 2 bits 0: Disable 1: Enable 0: Disable 1: Enable Write only 0 (Initial value: 0000 0000) BRG Transmit clock select PE EVEN STBT RXE TXE Note 1: Parity addition Even-numbered parity Transmit stop bit length Receive operation Transfer operation When operations are disabled by setting TXE and RXE bit to "0", the setting becomes valid when data transmit or receive complete. When the transmit data is stored in the transmit data buffer, the data are not transmitted. Even if data transmit is enabled, until new data are written to the transmit data buffer, the current data are not transmitted. Note 2: Note 3: The transmit clock and the parity are common to transmit and receive. UARTCR1 UARTCR2 (1FDEH) 7 6 5 4 3 2 1 0 STOPBR (Initial value: **** *000) RXDNC 0: 1 bit 1: 2 bits STOPBR Receive stop bit length RXDNC Selection of RXD input noise rejection time 00: No noise rejection (Hysteresis input) 01: Rejects pulses shorter than 31/fc [s] as noise 10: Rejects pulses shorter than 63/fc [s] as noise 11: Rejects pulses shorter than 127/fc [s] as noise Write only Note: When UARTCR2 Figure 2.10.2 UART Control Register 86FP24-100 2007-08-24 TMP86FP24 UARTSR (1FDDH) 7 PERR 6 FERR 5 OERR 4 RBFL 3 TEND 2 TBEP 1 0 (Initial value: 0000 11**) TBEP TEND RBFL OERR FERR PERR Note: Transmit data buffer empty flag Transmit end flag Receive data buffer full flag Overrun error flag Framing error flag Parity error flag 0: Transmit data buffer full 1: Transmit data buffer empty 0: Transmitting 1: Transmit end 0: Receive data buffer empty 1: Receive data buffer full 0: No overrun error 1: Overrun error 0: No framing error 1: Framing error 0: No parity error 1: Parity error Read only When an INTTXD is generated TBEP is set to "1" automatically. UART receive data buffer 7 6 RDBUF (1FDFH) UART transmit data buffer 7 6 TDBUF (1FDFH) 5 4 3 2 1 0 Read only (Initial value: 0000 0000) 5 4 3 2 1 0 Write only (Initial value: 0000 0000) Figure 2.10.3 UART Status Register and Data Buffer Registers 86FP24-101 2007-08-24 TMP86FP24 2.10.3 Transfer Data Format In UART, a one-bit start bit (low level), stop bit (bit length selectable at high level, by UARTCR1 Frame length PE STBT 1 2 3 8 9 10 11 12 0 0 Start Bit0 Bit1 Bit6 Bit7 Stop 1 0 1 Start Bit0 Bit1 Bit6 Bit7 Stop 1 Stop 2 1 0 Start Bit0 Bit1 Bit6 Bit7 Parity Stop 1 1 1 Start Bit0 Bit1 Bit6 Bit7 Parity Stop 1 Stop 2 Note: In order to switch the transmit data format, perform transmit operations in the following sequence except for the initial setting. Without parity/1 STOP bit With parity/1 STOP bit Without parity/2 STOP bit With parity/2 STOP bit 86FP24-102 2007-08-24 TMP86FP24 2.10.4 Transfer Rate The baud rate of UART is set of UARTCR1 BRG 000 001 010 011 100 101 Source Clock 16 MHz 76800 [baud] 38400 19200 9600 4800 2400 8 MHz 38400 [baud] 19200 9600 4800 2400 1200 4 MHz 19200 [baud] 9600 4800 2400 1200 600 When TC5 is used as the UART transfer rate (when UARTCR1 2.10.5 Data Sampling The UART receiver keeps sampling input using the clock selected by UARTCR1 RXD pin RT0 RT clock Internal receive data Start bit Bit0 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 Start bit Bit0 a) Without noise rejection circuit RXD pin RT0 RT clock Internal receive data Start bit Bit0 2 3 4 5 6 7 8 9 10 11 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 0 1 Start bit Bit0 b) With noise rejection circuit Figure 2.10.4 Data Sampling 86FP24-103 2007-08-24 TMP86FP24 2.10.6 STOP Bit Length Select a transmit stop bit length (1 bit or 2 bits) by UARTCR1 2.10.7 Parity Set parity/no parity by UARTCR1 2.10.8 Transmit/Receive (1) Data transmit Set UARTCR1 86FP24-104 2007-08-24 TMP86FP24 2.10.9 Status Flag/Interrupt Signal (1) Parity error When parity determined using the receive data bits differs from the received parity bit, the parity error flag UARTSR RXD pin xxxx0** Parity Stop Shift register pxxxx0* 1pxxxx0 UARTSR INTRXD Figure 2.10.5 Generation of Parity Error (2) Framing error When "0" is sampled as the stop bit in the receive data, framing error flag UARTSR RXD pin Final bit Stop Shift register xxx0** xxxx0* 1xxxx0 UARTSR Reading UARTSR then RDBUF clears FERR. INTRXD Figure 2.10.6 Generation of Framing Error 86FP24-105 2007-08-24 TMP86FP24 (3) Overrun error When all bits in the next data are received while unread data are still in RDBUF, overrun error flag UARTSR RBFL = "H" RXD pin Final bit Stop Shift register xxx0** xxxx0* 1xxxx0 RDBUF yyyy UARTSR Reading UARTSR then RDBUF clears OERR. INTRXD Figure 2.10.7 Generation of Overrun Error (4) Receive data buffer full Loading the received data in RDBUF sets receive data buffer full flag UARTSR RXD pin Final bit Stop Shift register xxx0** xxxx0* 1xxxx0 RDBUF yyyy xxxx UARTSR Reading UARTSR then RDBUF clears RBFL. INTRXD Figure 2.10.8 Generation of Receive Buffer Full 86FP24-106 2007-08-24 TMP86FP24 (5) Transmit data buffer empty When no data is in the transmit buffer TDBUF, UARTSR Data write TDBUF xxxx y Data write zzzz Shift register *****1 1xxxx0 *1xxxx ****1x *****1 1yyyy0 TXD pin Start Bit0 Final bit Stop Start UARTSR INTTXD Figure 2.10.9 Generation of Transmit Buffer Empty (6) Transmit end flag When data are transmitted and no data is in TDBUF (UARTSR Transmit clock Shift register ***1xx ****1x *****1 1yyyy0 *1yyyy TXD pin Stop Data writing to TDBUF Start Bit0 UARTSR UARTSR INTTXD Figure 2.10.10 Generation of Transmit Buffer Empty 86FP24-107 2007-08-24 TMP86FP24 2.11 Key-on wakeup (KWU) In the TMP86FP24, the STOP mode must be released by not only P20 ( INT5 / STOP ) pin but also P64 to P67 and P40 pins. When the STOP mode is released by P40, P64 to P67 pins, the P20 ( INT5 / STOP ) pin needs to be used. 2.11.1 Configuration Stop Mode Control INT5 Stop mode release signal (1: release) P20 ( INT5 / STOP ) Edge detector Edge Edge Edge Edge Edge P64 (AIN4/STOP0) P65 (AIN5/STOP1) P66 (AIN6/STOP2) P67 (AIN7/STOP3) P40 (STOP4) STOPCR Figure 2.11.1 Key-on wakeup Circuit Table 2.11.1 Input Edge (Level) of STOP Mode Release Terminal Name STOP STOP0 STOP1 STOP2 STOP3 STOP4 As Both Terminal P20/ INT5 P64/AIN4 P65/AIN5 P66/AIN6 P67/AIN7 P40 SYSCR1 Note: When the SYSCR1 86FP24-108 2007-08-24 TMP86FP24 2.11.2 Control P64 to P67 (STOP0 to STOP3) and P40(STOP4) pins can controlled by key-on wakeup control register (STOPCR). It can be configured as enable/disable in one-bit unit. The STOP mode is started by SYSCR1 Key-on Wakeup Control Register STOPCR (1FFEH) 7 STOP0 6 5 4 3 2 - 1 - 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable 0: Disable 1: Enable R/W 0 - (Initial value: 0000 0***) STOP1 STOP2 STOP3 STOP4 STOP0 STOP1 STOP2 STOP3 STOP4 Stop mode released by P64 port Stop mode released by P65 port Stop mode released by P66 port Stop mode released by P67 port Stop mode released by P40 port Figure 2.11.2 Key-on Wakeup Control Register 86FP24-109 2007-08-24 TMP86FP24 2.12 10-Bit AD Converter (ADC) The TMP86FP24 has a 10-bit successive approximation type AD converter. 2.12.1 Configuration The circuit configuration of the 10-bit AD converter is shown in Figure 2.12.1. It consists of control registers ADCCR1 and ADCCR2, conversion result registers ADCDR1 and ADCDR2, a DA converter, a sample-and-hold circuit, a comparator, and a successive comparison circuit. DA converter VAREF VSS AVDD R/2 R Reference voltage R/2 Analog input multiplexer AIN0 AIN1 A B Y Sample hold circuit 10 Analog comparator AIN6 AIN7 G H 4 S EN SAIN AINDS Shift clock Successive approximate circuit Control circuit INTADC ADRS 2 AMD IREFON ACK 8 2 EOCF ADBF 3 ADCCR2 ADCDR1 ADCDR2 ADCCR1 AD converter control register 1, 2 AD conversion result register Figure 2.12.1 AD Converter (ADC) 86FP24-110 2007-08-24 TMP86FP24 2.12.2 Register Configuration The AD converter consists of the following four registers: * * * AD converter control register 1 (ADCCR1) AD converter control register 2 (ADCCR2) AD conversion result register 1/2 (ADCDR1/ADCDR2) (1) AD converter control register 1 (ADCCR1) This register selects the analog channels and operation mode (Software start or repeat) in which to perform AD conversion and controls the AD converter as it starts operating. (2) AD converter control register 2 (ADCCR2) This register selects the AD conversion time and controls the connection of the DA converter (Ladder resistor network). (3) AD conversion result register (ADCDR1) This register is used to store the digital value (Bit9 to bit2) after being converted by the AD converter. (4) AD conversion result register (ADCDR2) This register is used to store the digital value (Bit1 and bit0) after being converted by the AD converter, and then this register is also used to monitor the operating status of the AD converter. The AD converter control register configurations are shown in Figure 2.12.2 and Figure 2.12.3. 86FP24-111 2007-08-24 TMP86FP24 AD Converter Control Register 1 ADCCR1 7 6 5 (000EH) ADRS AMD 4 AINDS 3 2 SAIN 1 0 (Initial value: 0001 0000) ADRS AD conversion start AMD AD Operating mode AINDS Analog input control SAIN Analog input channel select 0: - 1: Start 00: AD operation disable 01: Software start mode 10: Reserved 11: Repeat mode 0: Analog input enable 1: Analog input disable 0000: Selects AIN0 0001: Selects AIN1 0010: Selects AIN2 0011: Selects AIN3 0100: Selects AIN4 0101: Selects AIN5 0110: Selects AIN6 0111: Selects AIN7 1***: Reserved R/W Note 1: Select analog input when AD converter stops (ADCDR2 4 "1" 3 2 ACK 1 0 "0" (Initial value: **00 0000) IREFON DA converter (Ladder resistor) connection control ACK AD conversion time select Inputting current to the ladder resistor 0: Connected only during AD conversion 1: Always connected Conversion fc = fc = ACK time 16 MHz 8 MHz 000 39/fc - - 001 Reserved 010 78/fc - - 011 156/fc - - 39.0 s 100 312/fc - 101 624/fc 39.0 s 78.0 s 110 1248/fc 78.0 s 156.0 s 111 Reserved fc = 4 MHz - fc = 1 MHz 39.0 s R/W 78.0 s - 39.0 s 156.0 s 78.0 s - 156.0 s - - - Note 1: Settings for "-" in the above table are inhibited. Note 2: Set conversion time by analog reference voltage (VAREF) as follows. VAREF = 2.7 to 3.6 V (31.2 s or more) VAREF = 1.8 to 3.6 V (124.8 s or more) Note 3: Always set bit0 in ADCCR2 to "0" and set bit4 in ADCCR2 to "1". Note 4: When a read instruction for ADCCR2, bit6 to bit7 in ADCCR2 read in as undefined data. Note 5: fc; High-frequency clock [Hz] Note 6: After STOP or SLOW mode are started, AD converter control register 2 (ADCCR2) is all initialized. Therefore, set the ADCCR2 newly again after exiting these modes. Figure 2.12.2 AD Converter Control Register 86FP24-112 2007-08-24 TMP86FP24 AD Conversion Result Register ADCDR1 7 6 (0027H) AD09 AD08 ADCDR2 (0026H) 7 AD01 6 AD00 5 AD07 5 EOCF 4 AD06 4 ADBF 3 AD05 3 2 AD04 2 1 AD03 1 0 AD02 0 (Initial value: 0000 ****) (Initial value: 0000 0000) EOCF ADBF AD conversion end flag AD conversion busy flag 0: Before or during conversion 1: Conversion completed 0: During stop of AD conversion 1: During AD conversion Read only Note 1: The EOCF is cleared to "0" when reading the ADCDR1. Therefore, the AD conversion result should be read to ADCDR2 more first than ADCDR1. Note 2: ADBF is set to "1" when AD conversion starts and cleared to "0" when the AD conversion is finished. It also is cleared upon entering STOP or SLOW mode. Note 3: If a read instruction is executed for ADCDR2, read data of bit3 to bit0 are unstable. Figure 2.12.3 AD Converter Result Register 2.12.3 AD Converter Operation (1) Set up the AD converter control register 1 (ADCCR1) as follows: * * * Choose the channel to AD convert using AD input channel select (SAIN). Specify analog input enable for analog input control (AINDS). Specify AMD for the AD converter control operation mode (Software or repeat mode). (2) Setup the AD converter control register 2 (ADCCR2) as follows: * * Set the AD conversion time using AD conversion time (ACK). For details on how to set the conversion time, refer to Note 2 for AD converter control register 2. Choose IREFON for DA converter control. (3) After setting up (1) and (2) above, set AD conversion start (ADRS) of AD converter control register 1 (ADCCR1) to "1". (4) After an elapse of the specified AD conversion time, the AD converted value is stored in AD conversion result register 1 (ADCDR1), AD conversion result register 2 (ADCDR2) and then the AD conversion end flag (EOCF) of AD conversion result register 2 (ADCDR2) is set to "1", upon which time AD conversion interrupt INTADC is generated. (5) EOCF is cleared to "0" by a read of the conversion result. However, if reconverted before a register read, although EOCF is cleared the previous conversion result is retained until the next conversion is completed. 86FP24-113 2007-08-24 TMP86FP24 2.12.4 AD Converter Operation Modes There are following two AD converter operation modes: * * Software start: AD conversion is performed once by setting AMD to "01B" and ADRS to "1". Repeat mode: AD conversion is performed repeatedly by setting AMD to "11B" and ADRS to "1". (1) Software start mode After setting ADCCR1 ADCCR1 ADCDR2 Figure 2.12.4 Operation in Software Start Mode 86FP24-114 2007-08-24 TMP86FP24 Example: After selecting the conversion time of 39.0 s at 16 MHz and the analog input channel AIN3 pin, perform AD conversion once. After checking EOCF, read the converted value, store the lower 2 bits in address 009EH and store the upper 8 bits in address 009FH on RAM. The operation mode is software start mode. ; AIN SELECT LD (P6CR1), 00000000B ; P6CR1 bit3 = 0 LD (P6CR2), 00000000B ; P6CR2 bit3 = 0 LD (ADCCR1), 00100011B ; Select AIN3. LD (ADCCR2), 11011010B ; Select conversion time (624/fc) and operation mode. ; AD CONVERT START SET (ADCCR1). 7 ; ADRS = 1 SLOOP: TEST (ADCDR2). 5 ; EOCF = 1 ? JRS T, SLOOP ; RESULT DATA READ LD A, (ADCDR2) LD (9EH), A LD A, (ADCDR1) LD (9FH), A (2) Repeat mode AD conversion of the voltage at the analog input pin specified by ADCCR1 ADCCR1 "11" "00" AD conversion finished AD convert operation suspended. Conversion result is not stored. Third conversion result ADCCR1 First conversion Indeterminate Second conversion Third conversion First conversion result Second conversion result ADCDR2 Figure 2.12.5 Operation in Repeat Mode 86FP24-115 2007-08-24 TMP86FP24 2.12.5 STOP and SLOW Modes during AD Conversion When the STOP or SLOW mode is entered forcibly during AD conversion, the AD convert operation is suspended and the AD converter is initialized (ADCCR1 and ADCCR2 are initialized to initial value). Also, the conversion result is indeterminate. (Conversion results up to the previous operation are cleared, so be sure to read the conversion results before entering STOP or SLOW mode.) When released from STOP or SLOW mode, AD conversion is not automatically restarted. Therefore, when the AD converter is used again, it is necessary to restart AD conversion (Set ADCCR1 2.12.6 Analog Input Voltage and AD Conversion Result The analog input voltage is corresponded to the 10-bit digital value converted by the AD as shown in Figure 2.12.6. 3FFH 3FEH AD conversion result 3FDH 003H 002H 001H VAREF - VASS 1024 0 x 1 2 3 1021 1022 1023 1024 Analog input voltage Figure 2.12.6 Analog Input Voltage and AD Conversion Result (typ.) 86FP24-116 2007-08-24 TMP86FP24 2.12.7 Precautions about AD Converter (1) Analog input pin voltage range Make sure the analog input pins (AIN0 to AIN7) are used at voltages within VSS below VAREF. If any voltage outside this range is applied to one of the analog input pins, the converted value on that pin becomes uncertain. The other analog input pins also are affected by that. (2) Analog input shared pins The analog input pins (AIN0 to AIN7) are shared with input/output ports. When using any of the analog inputs to execute AD conversion, do not execute input/output instructions for all other ports. This is necessary to prevent the accuracy of AD conversion from degrading. Not only these analog input shared pins, some other pins may also be affected by noise arising from input/output to and from adjacent pins. (3) Noise countermeasure The internal equivalent circuit of the analog input pins is shown in Figure 2.12.7. The higher the output impedance of the analog input source, more easily they are susceptible to noise. Therefore, make sure the output impedance of the signal source in your design is 5 k or less. Toshiba also recommends attaching a capacitor external to the chip. AINi Allowable signal source impedance 5 k (max) Internal resistance R = 5 k (typ.) Internal capacitance C = 22 pF (typ.) Analog comparator DA converter Note: i = 0 to 7 Figure 2.12.7 Analog Input Equivalent Circuit and Example of Input Pin Processing 86FP24-117 2007-08-24 TMP86FP24 2.13 LCD Driver The TMP86FP24 has a driver and control circuit to directly drive the liquid crystal device (LCD). The pins to be connected to LCD are as follows: a. b. c. Segment output port Segment output or P4, P9 input/output port Common output port 8 pins (SEG7 to SEG0) 16 pins (SEG23 to SEG8) 4 pins (COM3 to COM0) In addition, C0, C1, V1, V2, V3 pin are provided for the LCD driver's booster circuit. The devices that can be directly driven is selectable from LCD of the following drive methods: a. b. c. d. 1/4 Duty (1/3 Bias) LCD Max 96 Segments (8 segments x 12 digits) 1/3 Duty (1/3 Bias) LCD Max 72 Segments (8 segments x 9 digits) 1/2 Duty (1/2 Bias) LCD Max 48 Segments (8 segments x 6 digits) Static LCD Max 24 Segments (8 segments x 3 digits) 2.13.1 Configuration LCDCR fs fc 7 6 EDSP BRES 5 4 VFSEL 3 2 DUTY 17 1 SLF 9 0 DBR display data area Dedicated Divider fc/2 , fs/2 16 8 fc/2 , fs/2 15 fc/2 13 fc/2 Duty control Timing control 2 fc/2 , fs/2 13 5 fc/2 , fs/2 fc/2 , fs/2 10 11 9 3 Display data select control Blanking control Common driver fc/2 Display data buffer register Constant voltage booster circuit Segment driver C0 C1 V1 V2 V3 COM0 to COM3 SEG0 to SEG7 SEG8 to SEG23 Figure 2.13.1 LDC Driver Note: The LCD driver circuit has a built-in dedicated divider circuit. Thus, during use of the tool, LCD outputting is not stopped by debugger break processing. 86FP24-118 2007-08-24 TMP86FP24 2.13.2 Control The LCD driver is controlled using the LCD control register (LCDCR). The LCD driver's display is enabled using the EDSP. LCDCR (1FE3H) 7 EDSP 6 BRES 5 VFSEL 4 3 DUTY 2 1 SLF 0 (Initial value: 0000 0000) EDSP BRES LCD display control Booster circuit control 0: Blanking 1: Enables LCD display (Blanking is released) 0: Disable (Use divider resistance) 1: Enable NORMAL1/2,IDLE0/1/2 Modes SLOW1/2, SLEEP01/2 DV7CK = 0 DV7CK = 1 fs/2 fs/2 fs/2 fc/2 5 3 2 9 Modes fs/2 fs/2 fs/2 5 3 2 VFSEL Selection of boost frequency 00: 01: 10: 11: 00: 01: 10: 11: fc/2 fc/2 fc/2 13 11 10 9 fc/2 Reserved DUTY Selection of driving methods 1/4 Duty (1/3 Bias) 1/3 Duty (1/3 Bias) 1/2 Duty (1/2 Bias) Static NORMAL1/2,IDLE0/1/2 Modes SLOW1/2, SLEEP01/2 DV7CK = 0 DV7CK = 1 fs/2 fs/2 fc/2 fc/2 9 8 R/W Modes fs/2 fs/2 9 8 SLF Selection of LCD frame frequency 00: 01: 10: 11: fc/2 fc/2 fc/2 fc/2 17 16 15 13 15 13 Reserved Reserved Note 1: When Figure 2.13.2 LCD Driver Control Register 86FP24-119 2007-08-24 TMP86FP24 (1) LCD driving methods As for LCD driving method, 4 types can be selected by DUTY (Bit3 to bit2 of LCDCR). The driving method is initialized in the initial program according to the LCD used. VLCD3 1/fF VLCD3 1/fF 0 0 -VLCD3 Data "1" (a) 1/4 Duty (1/3 Bias) VLCD3 0 -VLCD3 Data "1" Data "0" Data "0" -VLCD3 Data "1" Data "0" (b) 1/3 Duty (1/3 Bias) VLCD3 0 -VLCD3 Data "1" (d) Static Data "0" 1/fF 1/fF (c) 1/2 Duty (1/2 Bias) fF: Frame frequency VLCD3: LCD drive voltage Figure 2.13.3 LCD Drive Waveform (COM-SEG pins) 86FP24-120 2007-08-24 TMP86FP24 (2) Frame frequency Frame frequency (fF) is set according to driving method and base frequency as shown in the following Table 2.13.1. The base frequency is selected by SLF (Bit1 and bit0 of LCDCR) according to the frequency fc and fs of the basic clock to be used. Table 2.13.1 Setting of LCD Frame Frequency a. SLF At the single clock mode. At the dual clock mode (DV7CK = 0). Base Frequency [Hz] fc 17 2 (fc = 16 MHz) (fc = 8 MHz) fc 16 2 (fc = 8 MHz) (fc = 4 MHz) fc 15 2 (fc = 4 MHz) (fc = 2 MHz) fc 13 2 (fc = 1 MHz) Note: fc: High-frequency clock [Hz] Frame Frequency [Hz] 1/4 duty fc 17 2 122 61 fc 16 2 122 61 fc 15 2 122 61 fc 13 2 122 4 3 4 3 4 3 1/3 duty 4 3 * 163 81 * 163 81 * 163 81 * 163 fc 13 2 fc 15 2 fc 16 2 fc 17 2 1/2 duty 4 2 * 244 122 4 2 * 244 122 4 2 * 244 122 4 2 * 244 fc 13 2 fc 15 2 fc 16 2 fc 17 2 Static fc 17 2 122 61 fc 16 2 122 61 fc 15 2 122 61 fc 13 2 122 00 01 10 11 b. SLF At the dual clock mode (DV7CK = 1 or SYSCK = 1) Base Frequency [Hz] fs 9 2 (fs = 32.768 kHz) fc 8 2 (fs = 32.768 kHz) Frame Frequency [Hz] 1/4 duty fs 9 2 64 fs 8 2 128 4 3 1/3 duty 4 3 * 85 * 171 fs 8 2 fs 9 2 1/2 duty 4 2 * 128 4 2 * 256 fs 8 2 fs 9 2 Static fs 9 2 64 fs 8 2 128 00 01 Note: fs: Low-frequency clock [Hz] 86FP24-121 2007-08-24 TMP86FP24 (3) Booster circuit for LCD driver The LCD voltage booster pin can select the booster circuit or the divider resistance. The booster circuit control is selected by LCDCR Keep the following condition. (a) V1 pin reference V3 VDD V1 = 0.8 to 1.2 V C = 0.1 to 0.47 F (b) V2 pin reference V3 VDD V2 = 1.6 to 2.4 V C = 0.1 to 0.47 F VSS VDD V3 V2 V1 C C Reference voltage (1V) C0 C C1 VDD V3 V2 V1 C C C C0 C C1 VSS Reference voltage (2V) Note: If the reference pin is the V2 pin, a capacitor is needed also across the V1 pin and a ground. Figure 2.13.4 Example of a Booster Circuit (LCDCR Adjustment of contrast VDD V3 R1 V2 C0 C1 V1 R3 VSS VSS Open Open R2 VDD Adjustment of contrast VDD V3 R1 V2 C0 C1 V1 R2 VSS Open Open Adjustment of contrast V3 V2 C0 C1 V1 R1 Open Open 1/3 Bias (R1 = R2 = R3) Keep the following condition. VDD V3 V2 V1 VSS 1/2 Bias (R1 = R2) Static Figure 2.13.5 Example of Divider Resistance (LCDCR 86FP24-122 2007-08-24 TMP86FP24 2.13.3 LCD Display Operation (1) Display data setting Display data is stored to the display data area (Assigned to address 1F80H to 1F8BH) in the DBR. The display data which are stored in the display data area is automatically read out and sent to the LCD driver by the hardware. The LCD driver generates the segment signal and common signal according to the display data and driving method. Therefore, display patterns can be changed by only over writing the contents of display data area by the program. Figure 2.13.6 shows the correspondence between the display data area and SEG/COM pins. LCD light when display data is "1" and turn off when "0". According to the driving method of LCD, the number of pixels which can be driven becomes different, and the number of bits in the display data area which is used to store display data also becomes different. Therefore, the bits which are not used to store display data as well as the data buffer which corresponds to the addresses not connected to LCD can be used to store general user process data (See Table 2.13.2). Note: The display data memory contents become unstable when the power supply is turned on; therefore, the display data memory should be initialized by an initiation routine. Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0 Address 1F80H 81 82 83 84 85 86 87 88 89 8A 8B SEG1 SEG0 SEG3 SEG2 SEG5 SEG4 SEG7 SEG6 SEG9 SEG8 SEG11 SEG10 SEG13 SEG12 SEG15 SEG14 SEG17 SEG16 SEG19 SEG18 SEG21 SEG20 SEG23 SEG22 COM3 COM2 COM1 COM0 COM3 COM2 COM1 COM0 Figure 2.13.6 LCD Display Data Area (DBR) Table 2.13.2 Driving Method and Bit for Display Data Driving Methods 1/4 Duty 1/3 Duty 1/2 Duty Static Bit7/3 COM3 - - - Bit6/2 COM2 COM2 - - Bit5/1 COM1 COM1 COM1 - Bit4/0 COM0 COM0 COM0 COM0 -: This bit is not used for display data (2) Blanking Blanking is enabled when EDSP is cleared to "0". Blanking turns off LCD through outputting a GND level to SEG/COM pin. When in STOP mode, EDSP is cleared to "0" and automatically blanked. To redisplay LCD after exiting STOP mode, it is necessary to set EDSP back to "1". Note: During reset, the LCD segment outputs (SEG0 to SEG7) and LCD common outputs are fixed "0" level. But the multiplex terminal (P4 and P9 ports) of input/output port and LCD segment output becomes high impedance. Therefore, when the reset input is long remarkably, ghost problem may appear in LCD display. 86FP24-123 2007-08-24 TMP86FP24 2.13 2.13.4 Control Method of LCD Driver (1) Initial setting shows the flowchart of initialization. Example: To operate a 1/4 duty LCD of 24 segments x 4 commons at frame fc/2 [Hz]. LD (LCDCR), 01000001B ; Sets LCD driving method, frame frequency and Boost frequency. LD (P4LCR), 0FFH ; Sets P4 port as segment output . LD (P9LCR), 0FFH ; Sets P9 port as segment output . ; Sets the initial value of display data. LD (LCDCR), 11000001B ; Display enable 16 Sets Booster circuit control (BRES) Sets LCD driving method (DUTY) Sets Boost frequency (VFSEL) Sets frame frquency (SLF) Sets P4, P9 port. Initialization of display data area. Display enable (EDSP) (Releases from blanking.) Figure 2.13.7 Initial Setting of LCD Driver (2) Store of display data Generally, display data are prepared as fixed data in program memory and stored in display data area by load command. Example 1: To display using 1/4 duty LCD a numerical value which corresponds to the LCD data stored in data memory at address 80H (when pins COM and SEG are connected to LCD as in Figure 2.13.8), display data become as shown in Table 2.12.2. LD A, (80H) ADD A, TABLE - $ - 7 LD HL, 1F80H LD W, (PC + A) LD (HL), W RET TABLE: DB 11011111B, 00000110B, 11100011B, 10100111B, 00110110B, 10110101B, 11110101B, 00010111B, 11110111B, 10110111B SNEXT: Note: DB is a byte data difinition instruction. 86FP24-124 2007-08-24 TMP86FP24 COM0 COM1 COM2 SEG0 SEG1 COM3 Figure 2.13.8 Example of COM, SEG Pin Connection (1/4 duty) Table 2.13.4 Example of Display Data (1/4 duty) Number 0. Display Display Data 11011111 Number 5 Display Display Data 10110101 1 00000110 6 11110101 2 11100011 7 00000111 3 10100111 8 11110111 4 00110110 9 10110111 Example 2: Table 2.13.4 shows an example of display data which are displayed using 1/2 duty LCD in the same way as Table 2.13.5. The connection between pins COM and SEG are the same as shown in Figure 2.13.9. COM0 SEG3 SEG0 SEG2 SEG1 COM1 Figure 2.13.9 Example of COM, SEG Pin Connection Table 2.13.5 Example of Display Data (1/2 duty) Display Data Display Data Number High Order Address Low Order Address Number High Order Address Low Order Address (1F81H) (1F80H) (1F81H) (1F80H) 0 1 2 3 4 *: Don't care **01**11 **00**10 **10**01 **10**10 **11**10 **01**11 **00**10 **01**11 **01**11 **00**10 5 6 7 8 9 **11**10 **11**11 **01**10 **11**11 **11**10 **01**01 **01**01 **00**11 **01**11 **01**11 86FP24-125 2007-08-24 TMP86FP24 (3) Example of LCD drive output COM0 COM1 COM2 SEG0 SEG1 EDSP SEG0 SEG1 Display data area Address 1F80H 1011 0101 COM1 COM2 COM3 COM0 VLCD3 0 VLCD3 0 VLCD3 0 VLCD3 0 VLCD3 0 VLCD3 0 VLCD3 0 -VLCD3 VLCD3 0 -VLCD3 COM3 COM0 to SEG 0 (Selected) COM2 to SEG1 (Non-selected) Figure 2.13.10 1/4 Duty (1/3 bias) Drive SEG1 SEG2 SEG0 COM0 COM1 COM2 EDSP SEG0 VLCD3 0 SEG1 Display data area Address VLCD3 0 VLCD3 0 VLCD3 0 VLCD3 0 VLCD3 0 VLCD3 0 -VLCD3 VLCD3 0 -VLCD3 SEG2 COM0 1F80H 1F81H *111 *010 **** *001 COM1 COM2 COM0 to SEG1 (Selected) *: Don't care COM1 to SEG2 (Non-selected) Figure 2.13.11 1/3 Duty (1/3 bias) Drive 86FP24-126 2007-08-24 TMP86FP24 COM0 SEG3 SEG0 SEG2 SEG1 EDSP SEG0 SEG1 Display data area Address 1F80H 1F81H **01 **01 **11 **10 COM0 COM1 COM0 to SEG1 (Selected) SEG2 SEG3 VLCD3 0 VLCD3 0 VLCD3 0 VLCD3 0 VLCD3 0 VLCD3 0 VLCD3 0 -VLCD3 VLCD3 0 -VLCD3 COM1 *: Don't care COM0 to SEG2 (Non-selected) Figure 2.13.12 1/2 Duty (1/3 bias) Drive SEG0 SEG1 SEG6 SEG2 SEG7 EDSP SEG0 Display data area Address 1F80H 1F81H 1F82H 1F83H ***0 ***1 ***1 ***1 ***1 ***0 ***0 ***1 COM0 to SEG0 (Selected) VLCD3 0 -VLCD3 VLCD3 0 -VLCD3 COM0 SEG7 SEG4 VLCD3 0 VLCD3 0 VLCD3 0 VLCD3 0 SEG5 SEG4 SEG3 COM0 *: Don't care COM0 to SEG4 (Non-selected) Figure 2.13.13 Static Drive 86FP24-127 2007-08-24 TMP86FP24 2.14 SIO (Synchronous serial interface) The TMP86FP24 contains two SIO (Synchronous serial interface) channel. They are connected to external devices via the SI1, SI2, SO1, SI2, SCK2 and SCK1 pins. The SI1 (SI2) pin is used also as the P05 (P11) pin, the SO1 (SO2) pin is used also as the P06(P10) pin, and the SCK1 ( SCK2 ) pin is used also as the P07 (P12) pin. Using these pins for serial interfacing requires setting the output latches of the port P0 and P1 to "1". Because SIO1 and SIO2 are the same except that the register for each SIO are located at different addresses, explanation here is made of only SIO1. The registers for SIO1 and SIO2 are listed in Table 2.14.1 below. Table 2.14.1 Control Registers SIO1 Register Name SIO control register 1 SIO control register 2 SIO status register SIO data buffer SIO1CR1 SIO1CR2 SIO1SR SIO1BUF SIO2 Address 0016H 0017H 0018H 0019H Register Name SIO2CR1 SIO2CR2 SIO2SR SIO2BUF Address 001AH 001BH 001CH 001DH 2.14.1 Configuration SCK 13 5 SIO buffer SIO1CR1 SIO1SR SIO1CR2 Buffer control fc/2 , fs/2 8 fc/2 6 fc/2 5 fc/2 4 fc/2 3 fc/2 2 fc/2 External clock A B C D E F G H Transmit shift register Shift clock Y SO1 pin Serial data output SI1 pin Serial data input Receive shift register MSB/LSB selection SCK1 pin Serial clock input/output Control circuit INTSIO1 interrupt Figure 2.14.1 Configuration of the Serial Interface 86FP24-128 2007-08-24 TMP86FP24 2.14.2 Control SIO is controlled using serial interface control register 1 (SIO1CR1) and serial interface control register 2 (SIO1CR2). The operating status of the serial interface can be determined by reading the serial interface status register (SIO1SR). Serial Interface Control Register 1 SIO1CR1 7 6 SIOS SIOINH 5 SIOM 4 3 SIODIR 2 1 SCK 0 (Initial value: 0000 0000) SIOS SIOINH Start/stop a transfer. Continue/abort a transfer (Note 1). 0: Stop 1: Start 0: Continue transfer. 1: Abort transfer (automatically cleared to "0" after abort). 00: Transmit mode 01: Receive mode 10: Transmit/receive mode 11: Reserved 0: MSB (Transfer beginning with bit7) 1: LSB (Transfer beginning with bit0) NORMAL1/2, IDLE1/2 Mode DV7CK = 0 000 001 010 011 100 101 110 111 R/W SLOW1/2, SLEEP1/2 Mode 5 13 5 fs/2 fs/2 fc/2 8 8 - fc/2 fc/2 6 6 - fc/2 fc/2 5 5 - fc/2 fc/2 4 4 - fc/2 fc/2 3 3 - fc/2 fc/2 2 2 - fc/2 fc/2 External clock (Supplied via the SCK1 pin) DV7CK = 1 SIOM Select transfer mode. SIODIR Select direction of transfer. SCK Select a serial clock. (Note 2) Note 1: If SIO1CR1 Note 2: Note 3: When selecting a serial clock, do not make such a setting that the serial clock rate will exceed 1 Mbps. Before setting SIO1CR1 Note 4: Reserved: Setting prohibited Figure 2.14.2 Serial Interface Control Register 1 86FP24-129 2007-08-24 TMP86FP24 Serial Interface Control Register 2 7 SIO1CR2 6 5 4 3 2 1 SIORXD 0 (Initial value: **** *000) SIORXD 000: 1-byte transfer 001: 2-byte transfer 010: 3-byte transfer Set the number of data bytes 011: 4-byte transfer 100: 5-byte transfer to transmit/receive. 101: 6-byte transfer 110: 7-byte transfer 111: 8-byte transfer R/W Note 1: Note 2: Note 3: Before setting the number of data bytes to transfer, make sure the SIO is idle (SIO1SR Serial Interface Status Register SIO1SR 7 SIOF 6 SEF 5 TXF 4 3 2 RXF TXERR RXERR 1 0 (Initial value: 0010 00**) SIOF SEF TXF Monitor the operating status of 0: Transfer ended (Note 1) serial transfer. Number of clocks monitor. Transmit buffer flag. 1: Transfer in process 0: 8 clocks 1: 1 to 7 clocks 0: The transmit buffer contains data. 1: The transmit buffer contains no data. 0: The receive buffer contains no data. 1: As many data bytes specified in SIO1CR2 RXF Receive buffer flag. been received. (The flag is reset to "0" when as many data bytes as specified in SIO1CR2 TXERR RXERR Note 1: Transmit error flag (Note 2) Receive error flag (Note 2) The SIO1SR |