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STHDMI002A
Wide bandwidth, 2 to 1 HDMI switch with single enable
Features

Compatible with HDMI v1.2, DVI v1.0 digital interfaces 165MHz speed operation supports all video formats up to 1080p and SXGA (1280 x 1024 at 75Hz) Data rate per channel for UXGA: 1.65Gbps Low RON: 5.5 (typ) VCC operating range: 3.135V to 3.465V Low current consumption: 20A ESD human body model HBM Voltage: - 2KV for all I/Os Channel ON capacitance: 6pF (typ) Switching speed: 9ns Near-zero propagation delay: 250ps Low crosstalk: -32dB at 825MHz Bit-to-bit skew: 200ps Very low ground bounce in flow through mode Data and control inputs provide an undershoot clamp diode Wide bandwidth minimizes skew and jitter Hot insertion capable Isolated Digital Display Control (DDC) bus for unused ports 5V tolerance to all DDC and HPD_SINK inputs Supports bi-directional operation Available in the TQFP48 package -40C to 85C operating temperature range
TQFP48

Description
The STHDMI002A is a differential Single Pole Double Throw (SPDT) 2 to 1, low Ron, bi-directional HDMI switch designed for advanced TV applications supporting HDMI/DVI which demand high definition superior image quality. The differential signal from the 2 ports of HDMI is multiplexed through the switch to form a single output HDMI channel going to the HDMI receiver while the unselected output goes to the high-Z state. It is designed for very low cross-talk, low bit-to-bit skew, high channel-to-channel noise isolation and low I/O capacitance. The switch offers very little or practically no attenuation of the high-speed signals at the outputs, thus preserving the signal integrity to pass stringent requirements. The STHDMI002A also includes the DDC as well as the HPD line switching. The pin layout is optimized for easy PCB routing to the HDMI connector and HDMI receivers. The maximum DVI/HDMI data rate of 1.65Gbps provides the resolution required by the advanced HDTV and PC graphics.
Applications

Advantages
STHDMI002A provides the ability to switch a single source output to various display devices or switch video display devices between multiple sources. It reduces the overall BOM costs by eliminating the need for more costly multi inputoutput controllers.
Advanced TVs Front projectors LCD TVs PDPs LCD monitors Notebook PCs STB and DVD players
October 2006
Rev 1
1/26
www.st.com 26
Contents
STHDMI002A
Contents
1 2 Functional diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
2.1 2.2 HPD pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 DDC channels . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
3 4
Application diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7
4.1 Function table ................................................ 9
5 6
Maximum rating . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 DC electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11
6.1 6.2 6.3 6.4 6.5 Capacitance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Power supply characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Dynamic electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Dynamic switching characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 ESD performance . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
7 8 9
Test circuit for electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Timing waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
9.1 Power supply sequencing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
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STHDMI002A 9.2 9.3
Contents
Supply bypassing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 Differential traces . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20
10 11 12
Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
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Functional diagram
STHDMI002A
1
Functional diagram
Figure 1. Functional diagram
4/26
STHDMI002A
Functional description
2
Functional description
The STHDMI002A routes physical layer signals for high bandwidth digital video and is compatible with low voltage differential signaling standards like TMDS. The device multiplexes differential outputs from a video source to one of the two corresponding outputs to a common display. The low on-resistance and low I/O capacitance of STHDMI002A result in a very small propagation delay. The device integrates SPDT-type switches for 3 differential data TMDS channels and 1 differential clock channel. Additionally it integrates the switches for DDC and HPD lines switching.
The IC interface of the selected input port is linked to the IC interface of the output port, and the hot plug detector (HPD) of the selected input port is output to HPD_SINK. For the unused ports, the IC interfaces are isolated, and the HPD pins are also isolated.
2.1
HPD pins
The input of the Y_HPD is 5V tolerant, allowing direct connection to 5V signals. The switch is able to pass both 0V and 5V signal levels. The HPD switch resistance depends on the input voltage level. At low (near to 0V) input voltage levels, the resistance is 20 typically and at high (near to 5V) input voltage levels, the resistance is 150 typically.
2.2
DDC channels
The DDC channels are designed with a bi-directional NMOS gate, providing 5V signal tolerance. The 5V tolerance allows direct connection to a standard IC bus, thus eliminating the need for a level shifter. When the input is a 5V, the NMOS switch is turned off and the pull up resistor on either side of the switch determines the high voltage potential.
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Application diagram
STHDMI002A
3
Application diagram
Figure 2. Application diagram
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STHDMI002A
Pin configuration
4
Pin configuration
Figure 3. Pin connections
TQFP48 (pitch = 0.5mm)
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Pin configuration
STHDMI002A
Table 1.
Pin description
Pin Name VCC ACLKACLK+ GND A0A0+ GND A1A1+ GND A2A2+ VCC B_HPD GND B_DDC_SDA B_DDC_SCL VCC BCLKBCLK+ GND B0B0+ GND B1B1+ GND B2B2+ SEL Y2+ Y2GND Y1+ Type Power Input Input Power Input Input Power Input Input Power Input Input Power Output Power I/O I/O Power Input Input Power Input Input Power Input Input Power Input Input Input Output Output Power Output Function Supply voltage (3.3V 5%) TMDS Clock- for port A TMDS Clock+ for port A Ground TMDS Data 0- for port A TMDS Data 0+ for port A Ground TMDS Data 1- for port A TMDS Data 1+ for port A Ground TMDS Data 2- for port A TMDS Data 2+ for port A Supply voltage (3.3V 5%) Hot Plug Detect (HPD) output for port B Ground DDC SDA input for port B DDC SCL input for port B Supply voltage (3.3V 5%) TMDS Clock- for port B TMDS Clock+ for port B Ground TMDS Data 0- for port B TMDS Data 0+ for port B Ground TMDS Data 1- for port B TMDS Data 1+ for port B Ground TMDS Data 2- for port B TMDS Data 2+ for port B Select control input to select port A or port B TMDS Data2+ output TMDS Data2- output Ground TMDS Data1+ output
Pin number 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34
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STHDMI002A
Table 1. Pin description
Pin name Y1GND Y0+ Y0GND YCLK+ YCLKY_DDC_SCL Y_DDC_SDA Type Output Power Output Output Power Output Output I/O I/O TMDS Data1- output Ground TMDS Data0+ output TMDS Data0- output Ground TMDS Clock+ output TMDS Clock- output DDC SCL output DDC SDA output Function
Pin configuration
Pin number 35 36 37 38 39 40 41 42 43
44
Y_HPD
Input
Sink side hot plug detector input High : 5V power signal asserted from source to sink and EDID is ready Low : No 5V power signal is asserted from source to sink or EDID is not ready Hot Plug Detect (HPD) output for port A Supply voltage (3.3V 5%) DDC SDA input for port A DDC SCL input for port A
45 46 47 48
A_HPD VCC A_DDC_SDA A_DDC_SCL
Output Power I/O I/O
4.1
Function table
Table 2.
SEL L H
Function table
Signal status Y= TMDS Data, Clock for port A Port B is in `Z' state Y=TMDS Data, Clock for port B Port A is in `Z' state DDC Status Y = DDC for port A DDC for port B is `Z' Y = DDC for port B DDC for port A is `Z' HPD Status Y= HPD for port A HPD for port B is `Z' Y= HPD for port B HPD for port A is `Z'
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Maximum rating
STHDMI002A
5
Maximum rating
Stressing the device above the rating listed in the "absolute maximum ratings" table may cause permanent damage to the device. these are stress ratings only and operation of the device at these or any other conditions above those indicated in the operating sections of this specification is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. Refer also to the STMicroelectronics sure program and other relevant quality documents. Table 3.
Symbol VCC Supply voltage to Ground DC Input Voltage (TMDS A,B ports) VI SEL A_DDC_SDA, A_DDC_SCL, B_DDC_SDA, B_DDC_SCL, Y_DDC_SDA, Y_DDC_SCL, Y_HPD, A_HPD, B_HPD VIC IO TSTG TL VESD DC control input voltage DC output current Storage temperature Lead temperature (10 sec) Electrostatic discharge voltage on IOs(1)1 Human body model Contact discharge
Absolute maximum ratings
Parameter Value -0.5 to +4.0 1.7 to +4.0 -0.5 to +4.0 -0.5 to +6.0 -0.5 to +4.0 120 -65 to +150 300 -2 to +2 -2 to +2 Unit V V V V V mA C C kV kV
1. In accordance with the MIL STD 883 method 3015
Table 4.
Symbol RthJA
Thermal data
Description Thermal Resistance Junction-ambient Value TBA Unit C/W
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STHDMI002A
DC electrical characteristics
6
DC electrical characteristics
TA = -40 to +85 C, VCC = 3.3V 5%
Table 5.
Symbol VIH VIL VIK IIH IIL
DC electrical characteristics
Parameter HIGH level input voltage (SEL pin) LOW level input voltage (SEL pin) Clamp Diode voltage (All IOs) Input high current (SEL pin, A, B data ports) Input low current (SEL pin, A, B data ports) Test conditions High level guaranteed Low level guaranteed VCC = 3.465V, IIN = -18mA VCC = 3.465V, VIN = VCC VCC = 3.465V, VIN = GND VCC = 0V; Min 2.0 -0.5 -0.8 0.8 -1.2 5 5 Typ Max Unit V V V A A
IOFF
Power down leakage current
Outputs (Y-port) = 0V; Inputs (A-port) = 3.465V; Inputs (B-port) = 3.465V VCC = 3.135 V,
5
A
RON
Switch ON resistance (1)
VIN = 1.5 to VCC IIN = -40mA VCC = 3.135 V,
5.5
7.5
RFLAT
ON resistance flatness (1) (2)
VIN = 1.5 to VCC IIN = -40mA
0.8
RON
ON resistance match between channels RON = RONMAX - RONMIN (1) (3)
VCC = 3.135 V, VIN = 1.5 to VCC IIN = -40mA 1.0 1.3
DDC I/O Pins VCC = 3.465V II(leak) Input leakage current VI (max) = 5.3V on isolated DDC ports Y= 0.0V VCC = 0V; IOFF Power down leakage current Outputs (Y-port) = 0V; Inputs (A-port) = 5.3V; Inputs (B-port) = 5.3V VI=0V, VCC=3.3V, T= 25C F = 1 MHz 5 9 5 A 0.1 +2 A
CI/O
Switch off capacitance Switch on capacitance
pF pF
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DC electrical characteristics
STHDMI002A
Table 5.
Symbol
DC electrical characteristics
Parameter Test conditions VCC = 3.3V IO=3mA; VO=0.0V VCC = 3.3V Min Typ 32 Max Unit
RON
Switch resistance
IO=3mA; VO=0.4V VCC = 3.3V IO=3mA; VO=0.8V VCC = 3.3V IO=3mA; VO=1.5V
36
42
62
Status pins (Y_HPD) VCC = 3.465V II(leak) Input leakage current VI (max) = 5.3V on isolated HPD port Y= 0.0V VCC = 0V; IOFF Power down leakage current (Y-port) = 0V; (A-port) = 5.3V; (B-port) = 5.3V 5 A 0.1 +2 A
Status pins (A_HPD, B_HPD) CI/O Switch off capacitance Switch on capacitance VI=0V, VCC=3.3V, T= 25C F = 1 MHz VCC = 3.3V RON Switch resistance IO=3mA; VO=0.0V VCC = 3.3V IO=3mA; VO=5.0V 5 9 24 pF pF
150
1. Measured by voltage drop between channels at the indicated current through the switch. On-resistance is determined by the lower of the two voltages. 2. Flatness is defined as the difference between the RONMAX and the RONMIN of the on resistance over the specified range. 3. RON measured at the same VCC, temperature and voltage level.
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STHDMI002A
DC electrical characteristics
6.1
Table 6.
Symbol CIN COFF CON
1.
Capacitance
TA = 25C, f = 1MHz Capacitance
Parameter Input capacitance Port x0 to Port x1, Switch off (Note 4) Capacitance switch on (x to x0 or x to x1) (1) Test conditions VIN = 0V VIN = 0V VIN = 0V Min Typ 2 4 6 Max 3 6 12 Unit pF pF pF
x = Port Y; x0 = Port A; x1 = Port B
6.2
Table 7.
Symbol ICC
Power supply characteristics
TA = -40 to +85 C Power supply characteristics
Parameter Quiescent power supply current Test conditions VCC = 3.465 V, VIN = VCC or GND Min Typ 50 Max 500 Unit A
6.3
Table 8.
Symbol XTALK
Dynamic electrical characteristics
TA = -40 to +85 C, VCC = 3.3V 5% Dynamic electrical characteristics
Parameter Non-adjacent channel Cross-talk Test conditions , RL = 100 f = 370MHz RL = 100 f = 825MHz , Min Typ -32 -31 -36 -30 850 1.65 Max Unit dB dB dB dB MHz Gbps
OIRR
Off Isolation
, RL = 100 f = 370MHz RL = 100 f = 825MHz ,
BW DR
-3dB bandwidth Data rate per channel
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DC electrical characteristics
STHDMI002A
6.4
Table 9.
Symbol tPD
Dynamic switching characteristics
TA = -40 to +85 C, VCC = 3.3V 5% Dynamic switching characteristics
Parameter Propagation delay Test conditions VCC = 3.135V to 3.465V VCC = 3.135V to 3.465V VCC = 3.135V to 3.465V VCC = 3.135V to 3.465V VCC = 3.135V to 3.465V 0.5 0.5 Min Typ 0.30 6.5 6.5 0.1 0.1 9 8.5 0.2 0.2 Max Unit ns ns ns ns ns
tPZH, tPZL Line Enable Time, SEL to x to x0 or x to x1 tPHZ, tPLZ Line Disable Time, SEL to x to x0 or x to x1 tSK(O) tSK(P) Output skew between center port to any other port Skew between opposite transition of the same output (tPHL - tPLH)
DDC I/O pins Propagation delay from A_DDC_SDA/ B_DDC_SDA to Y_DDC_SDA or A_DDC_SCL/B_DDC_SCL to tPD(DDC) Y_DDC_SCL or Y_DDC_SDA to A_DDC_SDA/ B_DDC_SDA tPZH, tPZL Line Enable Time, SEL to x to x0 or x to x1 tPHZ, tPLZ Line Disable Time, SEL to x to x0 or x to x1 Status pins (Y_HPD, A_HPD, B_HPD) tPD(HPD) Propagation delay (from Y_HPD to the active port of HPD) CL = 10pF VCC = 3.135V to 3.465V VCC = 3.135V to 3.465V 6.5 6.5 2.5 9 8.5 ns ns ns
CL = 10pF
2.5
ns
VCC = 3.135V to 3.465V VCC = 3.135V to 3.465V
6.5 6.5
9 8.5
ns ns
tPZH, tPZL Line Enable Time, SEL to x to x0 or x to x1 tPHZ, tPLZ Line Disable Time, SEL to x to x0 or x to x1
Note:
x = Port Y; x0 = Port A; x1 = Port B
6.5
Table 10.
Symbol ESD
ESD performance
ESD performance
Parameter MIL STD 883 method 3015 (all pins) Test conditions Human Body Model (HBM) Min Typ 2 Max Unit kV
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STHDMI002A
Test circuit for electrical characteristics
7
Test circuit for electrical characteristics
Figure 4. Timing measurement test circuit
Note: 1 CL = Load capacitance: includes jig and probe capacitance. 2 RT = Termination resistance: should be equal to ZOUT of the Pulse Generator. Figure 5. Bandwidth measurement test circuit
Note:
CL includes probe and jig capacitance Frequency response is measured at the output of the ON channel. For example, when VSEL = 0 and Y0+ is the input, the output is measured at A0+. All unused analog I/O ports are left open. HP8753ES set up: Average = 4 RBW = 3kHz VBIAS = 0.35V ST = 2s P1 = 0dBm
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Test circuit for electrical characteristics
STHDMI002A
Figure 6.
Crosstalk measurement test circuit
Note: 1 CL includes probe and jig capacitance 2 A 50 termination resistor is needed to match the loading network analyzer Crosstalk is measured at the output of the non-adjacent ON channel. For example, when VSEL = 0, and Y0- is the input, the output is measured at Y1-. All unused analog input ports (Y) are connected to GND and output ports (A,B) are left open. HP8753ES set up: Average = 4 RBW = 3kHz VBIAS = 0.35V ST = 2s P1 = 0dBm
16/26
STHDMI002A
Figure 7. Off-isolation measurement test circuit
Test circuit for electrical characteristics
Note: 1 CL includes probe and jig capacitance 2 A 50 termination resistor is needed to match the loading network analyzer Off-isolation is measured at the output of the OFF channel. For example, when VSEL=0, and Y0- is the input, the output is measured at B0-. All unused analog input ports (Y) are connected to GND and output ports (A,B) are left open. HP8753ES set up: Average = 4 RBW = 3kHz VBIAS = 0.35V ST = 2s P1 = 0dBm
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Timing waveforms
STHDMI002A
8
Figure 8.
Timing waveforms
Propagation delay times
Figure 9.
Enable and disable times
18/26
STHDMI002A
Figure 10. Output skew
Timing waveforms
Figure 11. Pulse skew
19/26
Application information
STHDMI002A
9
9.1
Application information
Power supply sequencing
Proper power-supply sequencing is advised for all CMOS devices. It is recommended to always apply VCC before applying any signals to the input/output or control pins.
9.2
Supply bypassing
Bypass each of the VCC pins with 0.1F and 1nF capacitors in parallel as close to the device as possible, with the smaller-valued capacitor as close to the VCC pin of the device as possible.
9.3
Differential traces
The high-speed TMDS inputs are the most critical parts for the device. There are several considerations to minimize discontinuities on these transmission lines between the connectors and the device. a) b) c) d) Maintain 100- differential transmission line impedance into and out of the STHDMI002A. Keep an uninterrupted ground plane below the high-speed I/Os. Keep the ground-path vias to the device as close as possible to allow the shortest return current path. Layout of the TMDS differential inputs should be with the shortest stubs from the connectors.
Output trace characteristics affect the performance of the STHDMI002A. Use controlled impedance traces to match trace impedance to both the transmission medium impedance and termination resistor. Run the differential traces close together to minimize the effects of the noise. Reduce skew by matching the electrical length of the traces. Avoid discontinuities in the differential trace layout. Avoid 90 degree turns and minimize the number of vias to further prevent impedance discontinuities.
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STHDMI002A
Package mechanical data
10
Package mechanical data
In order to meet environmental requirements, ST offers these devices in ECOPACK(R) packages. These packages have a Lead-free second level interconnect . The category of second Level Interconnect is marked on the package and on the inner box label, in compliance with JEDEC Standard JESD97. The maximum ratings related to soldering conditions are also marked on the inner box label. ECOPACK is an ST trademark. ECOPACK specifications are available at: www.st.com.
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Package mechanical data
STHDMI002A
Figure 12. TQFP48 package dimensions
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STHDMI002A
Figure 13. TQFP48 Tape and reel dimensions
Package mechanical data
Tape & Reel TQFP48 MECHANICAL DATA
mm. DIM. MIN. A C D N T Ao Bo Ko Po P 9.5 9.5 2.1 3.9 11.9 12.8 20.2 60 22.4 9.7 9.7 2.3 4.1 12.1 0.374 0.374 0.083 0.153 0.468 TYP MAX. 330 13.2 0.504 0.795 2.362 0.882 0.382 0.382 0.091 0.161 0.476 MIN. TYP. MAX. 12.992 0.519 inch
23/26
Order codes
STHDMI002A
11
Table 11.
Order codes
Order codes
Temperature range -65 C to +150 C Package TQFP48 Packing Tape and reel
Part number STHDMI002ABTR
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STHDMI002A
Revision history
12
Revision history
Table 12.
Date 10-Oct-2006
Revision history
Revision 1 First release Change
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STHDMI002A
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