 |
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
|
| If you can't view the Datasheet, Please click here to try to view without PDF Reader . |
|
|
| Datasheet File OCR Text: |
| 8 Bit Microcontroller TLCS-870/C1 Series TMP89FM42 The information contained herein is subject to change without notice. 021023_D TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S (c) 2007 TOSHIBA CORPORATION All Rights Reserved Revision History Date 2007/10/25 2007/11/3 Revision 1 2 First Release Contents Revised Table of Contents TMP89FM42 1.1 1.2 1.3 1.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Assignment . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Pin Names and Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 3 4 5 2. CPU Core 2.1 2.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Memory space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Code area ................................................................................................................................................. 9 RAM BOOTROM Flash SFR RAM BOOTROM Flash 2.2.1.1 2.2.1.2 2.2.1.3 2.2.2.1 2.2.2.2 2.2.2.3 2.2.2.4 2.2.1 2.2.2 Data area ................................................................................................................................................ 12 2.3 System clock controller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Configuration .......................................................................................................................................... 15 Control .................................................................................................................................................... 15 Functions ................................................................................................................................................ 17 Clock generator Clock gear Timing generator 2.3.1 2.3.2 2.3.3 2.3.4 2.3.5 2.3.3.1 2.3.3.2 2.3.3.3 2.3.4.1 2.3.4.2 2.3.5.1 2.3.5.2 2.3.5.3 2.3.5.4 2.3.6.1 2.3.6.2 2.3.6.3 2.3.6.4 Warm-up counter .................................................................................................................................... 20 Operation mode control circuit ................................................................................................................ 22 Single-clock mode Dual-clock mode STOP mode Transition of operation modes STOP mode IDLE1/2 and SLEEP1 modes IDLE0 and SLEEP0 modes SLOW mode Warm-up counter operation when the oscillation is enabled by the hardware Warm-up counter operation when the oscillation is enabled by the software 2.3.6 Operation Mode Control ......................................................................................................................... 27 2.4 Reset Control Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Configuration .......................................................................................................................................... Control .................................................................................................................................................... Functions ................................................................................................................................................ Reset Signal Generating Factors............................................................................................................ External reset input (RESET pin input) Power-on reset Voltage detection reset Watchdog timer reset System clock reset Trimming data reset Flash standby reset Internal factor reset detection status register How to use the external reset input pin as a port 2.4.1 2.4.2 2.4.3 2.4.4 38 38 40 41 2.5 2.4.4.1 2.4.4.2 2.4.4.3 2.4.4.4 2.4.4.5 2.4.4.6 2.4.4.7 2.4.4.8 2.4.4.9 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 i 3. Interrupt Control Circuit 3.1 3.2 3.3 3.4 3.5 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Interrupt Latches (IL25 to IL3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 Interrupt Enable Register (EIR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 51 Maskable Interrupt Priority Change Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . 54 Interrupt Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 56 Initial Setting ........................................................................................................................................... 56 Interrupt acceptance processing............................................................................................................. 56 Saving/restoring general-purpose registers ............................................................................................ 57 Using PUSH and POP instructions Using data transfer instructions Using a register bank to save/restore general-purpose registers 3.3.1 3.3.2 Interrupt master enable flag (IMF) .......................................................................................................... 51 Individual interrupt enable flags (EF25 to EF4) ...................................................................................... 51 3.5.1 3.5.2 3.5.3 3.6 3.5.4 3.6.1 3.6.2 3.5.3.1 3.5.3.2 3.5.3.3 Software Interrupt (INTSW) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Undefined Instruction Interrupt (INTUNDEF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 61 Address error detection .......................................................................................................................... 60 Debugging .............................................................................................................................................. 60 Interrupt return ........................................................................................................................................ 59 3.7 3.8 4. External Interrupt control circuit 4.1 4.2 4.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 63 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 64 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67 Low power consumption function ........................................................................................................... 67 External interrupt 0 ................................................................................................................................. 68 External interrupts 1/2/3.......................................................................................................................... 68 Interrupt request signal generating condition detection function A noise canceller pass signal monitoring function when interrupt request signals are generated Noise cancel time selection function Interrupt request signal generating condition detection function A noise canceller pass signal monitoring function when interrupt request signals are generated Noise cancel time selection function 4.3.1 4.3.2 4.3.3 4.3.4 4.3.3.1 4.3.3.2 4.3.3.3 4.3.4.1 4.3.4.2 4.3.4.3 External interrupt 4 ................................................................................................................................. 69 4.3.5 External interrupt 5 ................................................................................................................................. 71 5. Watchdog Timer (WDT) 5.1 5.2 5.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 73 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 75 Setting of enabling/disabling the watchdog timer operation ................................................................... Setting the clear time of the 8-bit up counter .......................................................................................... Setting the overflow time of the 8-bit up counter .................................................................................... Setting an overflow detection signal of the 8-bit up counter ................................................................... Writing the watchdog timer control codes ............................................................................................... Reading the 8-bit up counter .................................................................................................................. Reading the watchdog timer status ........................................................................................................ 75 76 76 77 77 78 78 5.3.1 5.3.2 5.3.3 5.3.4 5.3.5 5.3.6 5.3.7 6. Power-on Reset Circuit 6.1 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 ii 6.2 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79 7. Voltage Detection Circuit 7.1 7.2 7.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 81 Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 82 Enabling/disabling the voltage detection operation ................................................................................ Selecting the voltage detection operation mode ..................................................................................... Selecting the detection voltage level ...................................................................................................... Voltage detection flag and voltage detection status flag......................................................................... Selecting the STOP mode release signal ............................................................................................... 83 83 83 83 84 7.4 7.5 7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.4.1 7.4.2 Register Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 85 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87 Setting procedure when the operation mode is set to generate voltage detection interrupt request signals 85 Setting procedure when the operation mode is set to generate voltage detection reset signals ............ 85 8. I/O Ports 8.1 8.2 8.3 I/O Port Control Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 90 List of I/O Port Settings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 91 I/O Port Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 94 Port P0 (P03 to P00)............................................................................................................................... 94 Port P1 (P13 to P10)............................................................................................................................... 98 Port P2 (P27 to P20)............................................................................................................................. 101 Port P4 (P47 to P40)............................................................................................................................. 105 Port P7 (P77 to P70)............................................................................................................................. 108 Port P8 (P81 to P80)............................................................................................................................. 110 Port P9 (P91 to P90)............................................................................................................................. 113 Port PB (PB7 to PB4) ........................................................................................................................... 116 8.4 8.5 8.3.1 8.3.2 8.3.3 8.3.4 8.3.5 8.3.6 8.3.7 8.3.8 Serial Interface Selecting Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 119 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 121 9. Special Function Registers 9.1 9.2 9.3 SFR1 (0x0000 to 0x003F) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123 SFR2 (0x0F00 to 0x0FFF). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 124 SFR3 (0x0E40 to 0x0EFF) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 126 10. Low Power Consumption Function for Peripherals 10.1 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130 11. Divider Output (DVO) 11.1 11.2 11.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 135 Function .............................................................................................................................................. 133 11.2.1 iii 12. Time Base Timer (TBT) 12.1 Time Base Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 137 Configuration ...................................................................................................................................... 137 Control ................................................................................................................................................ 137 Functions ............................................................................................................................................ 138 12.1.1 12.1.2 12.1.3 12.2 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 140 13. 16-bit Timer Counter (TCA) 13.1 13.2 13.3 13.4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Consumption Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer Function. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Timer mode......................................................................................................................................... 148 Setting Operation Auto capture Register buffer configuration Setting Operation Auto capture Register buffer configuration Setting Operation Auto capture Register buffer configuration Setting Operation Auto capture Register buffer configuration Setting Operation 13.4.1.1 13.4.1.2 13.4.1.3 13.4.1.4 13.4.2.1 13.4.2.2 13.4.2.3 13.4.2.4 13.4.3.1 13.4.3.2 13.4.3.3 13.4.3.4 13.4.4.1 13.4.4.2 13.4.4.3 13.4.4.4 13.4.5.1 13.4.5.2 13.4.6.1 13.4.6.2 13.4.6.3 142 143 147 148 13.4.1 13.4.2 External trigger timer mode ................................................................................................................ 152 13.4.3 Event counter mode............................................................................................................................ 154 13.4.4 Window mode ..................................................................................................................................... 156 13.4.5 13.4.6 Pulse width measurement mode ........................................................................................................ 158 Programmable pulse generate (PPG) mode ...................................................................................... 160 Setting Operation Register buffer configuration 13.5 13.6 Noise Canceller . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 163 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 164 Setting................................................................................................................................................. 163 13.5.1 14. 8-bit Timer Counter (TC0) 14.1 14.2 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 166 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 167 Timer counter 00................................................................................................................................. Timer counter 01................................................................................................................................. Common to timer counters 00 and 01 ................................................................................................ Operation modes and usable source clocks ....................................................................................... 167 169 171 173 14.3 14.4 14.2.1 14.2.2 14.2.3 14.2.4 Low Power Consumption Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 174 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 175 8-bit timer mode .................................................................................................................................. 175 Setting Operation Double buffer Setting 14.4.1 14.4.2 14.4.1.1 14.4.1.2 14.4.1.3 14.4.2.1 8-bit event counter mode .................................................................................................................... 178 iv 14.4.3 14.4.2.2 14.4.2.3 14.4.3.1 14.4.3.2 14.4.3.3 14.4.4.1 14.4.4.2 14.4.4.3 14.4.5.1 14.4.5.2 14.4.5.3 14.4.6.1 14.4.6.2 14.4.6.3 14.4.7.1 14.4.7.2 14.4.7.3 14.4.8.1 14.4.8.2 14.4.8.3 8-bit pulse width modulation (PWM) output mode .............................................................................. 180 Setting Operations Double buffer Setting Operation Double buffer Setting Operations Double buffer Setting Operations Double buffer Setting Operations Double buffer Setting Operations Double buffer Operation Double buffer 14.4.4 8-bit programmable pulse generate (PPG) output mode .................................................................... 185 14.4.5 16-bit timer mode ................................................................................................................................ 188 14.4.6 16-bit event counter mode .................................................................................................................. 192 14.4.7 12-bit pulse width modulation (PWM) output mode ............................................................................ 194 14.4.8 16-bit programmable pulse generate (PPG) output mode .................................................................. 200 15. Real Time Clock (RTC) 15.1 15.2 15.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 203 Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 204 Low Power Consumption Function ..................................................................................................... 204 Enabling/disabling the real time clock operation................................................................................. 204 Selecting the interrupt generation interval .......................................................................................... 204 15.4 15.3.1 15.3.2 15.3.3 15.4.1 15.4.2 Real Time Clock Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205 Enabling the real time clock operation ................................................................................................ 205 Disabling the real time clock operation ............................................................................................... 205 16. Asynchronous Serial Interface (UART) 16.1 16.2 16.3 16.4 16.5 16.6 16.7 16.8 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 208 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 209 Low Power Consumption Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 213 Protection to Prevent UART0CR1 and UART0CR2 Registers from Being Changed 214 Activation of STOP, IDLE0 or SLEEP0 Mode . . . . . . . . . . . . . . . . . . . . . . . . . . 215 Transfer Data Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Infrared Data Format Transfer Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 216 Transfer Baud Rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 217 Transfer baud rate calculation method ............................................................................................... 218 Bit width adjustment using UART0CR2 16.5.1 16.5.2 Transition of register status ................................................................................................................ 215 Transition of TXD pin status ............................................................................................................... 215 16.8.1 16.9 Data Sampling Method . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 221 16.10 Received Data Noise Rejection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 223 16.11 Transmit/Receive Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 224 16.12 16.11.1 16.11.2 16.8.1.1 16.8.1.2 Status Flag . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 225 Data transmit operation .................................................................................................................... 224 Data receive operation...................................................................................................................... 224 v 16.13 16.14 16.15 16.12.1 16.12.2 16.12.3 16.12.4 16.12.5 16.12.6 Receiving Process . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 232 AC Properties . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 234 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 235 IrDA properties.................................................................................................................................. 234 Parity error ........................................................................................................................................ Framing Error.................................................................................................................................... Overrun error .................................................................................................................................... Receive Data Buffer Full................................................................................................................... Transmit busy flag ........................................................................................................................... Transmit Buffer Full .......................................................................................................................... 225 226 227 230 231 231 16.14.1 17. Synchronous Serial Interface (SIO) 17.1 17.2 17.3 17.4 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Low Power Consumption Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Transfer format ................................................................................................................................... 243 Serial clock ......................................................................................................................................... 243 Transfer edge selection ...................................................................................................................... 243 8-bit transmit mode ............................................................................................................................. 245 Setting Starting the transmit operation Transmit buffer and shift operation Operation on completion of transmission Stopping the transmit operation Setting Starting the receive operation Operation on completion of reception Stopping the receive operation 238 239 242 243 17.5 17.4.1 17.4.2 17.4.3 17.5.1 Transfer Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 245 17.5.2 17.5.1.1 17.5.1.2 17.5.1.3 17.5.1.4 17.5.1.5 17.5.2.1 17.5.2.2 17.5.2.3 17.5.2.4 17.5.3.1 17.5.3.2 17.5.3.3 17.5.3.4 17.5.3.5 8-bit Receive Mode ............................................................................................................................. 250 17.5.3 8-bit transmit/receive mode ................................................................................................................ 254 Setting Starting the transmit/receive operation Transmit buffer and shift operation Operation on completion of transmission/reception Stopping the transmit/receive operation 17.6 17.7 AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260 18. Serial Bus Interface (SBI) 18.1 18.2 18.3 18.4 Communication Format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 261 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 264 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 267 I2C bus ............................................................................................................................................... 261 Free data format ................................................................................................................................. 262 18.1.1 18.1.2 18.4.1 Low Power Consumption Function ..................................................................................................... 267 18.4.2 Selecting the slave address match detection and the GENERAL CALL detection............................. 268 18.4.3 Selecting the number of clocks for data transfer and selecting the acknowledgement or non-acknowledgment mode ........................................................................................................................................................... 268 18.4.4 18.4.5 18.4.6 18.4.7 18.4.3.1 18.4.3.2 18.4.4.1 18.4.4.2 Serial clock ......................................................................................................................................... 270 Clock source Clock synchronization Number of clocks for data transfer Output of an acknowledge signal Master/slave selection ........................................................................................................................ 272 Transmitter/receiver selection............................................................................................................. 272 Start/stop condition generation ........................................................................................................... 273 vi 18.5 18.4.8 Interrupt service request and release ................................................................................................. 18.4.9 Setting of serial bus interface mode ................................................................................................... 18.4.10 Software reset................................................................................................................................... 18.4.11 Arbitration lost detection monitor ...................................................................................................... 18.4.12 Slave address match detection monitor............................................................................................ 18.4.13 GENERAL CALL detection monitor .................................................................................................. 18.4.14 Last received bit monitor................................................................................................................... 18.4.15 Slave address and address recognition mode specification ............................................................. 18.5.1 18.5.2 18.5.3 18.5.4 18.5.5 Data Transfer of I2C Bus . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 278 Device initialization ............................................................................................................................. 278 Start condition and slave address generation..................................................................................... 278 1-word data transfer............................................................................................................................ 279 Stop condition generation ................................................................................................................... 283 Restart ................................................................................................................................................ 283 When SBI0SR2 274 274 274 275 276 277 277 277 18.5.3.1 18.5.3.2 18.6 18.7 AC Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 285 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 287 19. Key-on Wakeup (KWU) 19.1 19.2 19.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 289 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 290 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 291 20. 10-bit AD Converter (ADC) 20.1 20.2 20.3 Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 293 Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 294 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 298 Single mode........................................................................................................................................ 298 Repeat mode ...................................................................................................................................... 298 AD operation disable and forced stop of AD operation....................................................................... 299 20.4 20.5 20.6 20.7 20.3.1 20.3.2 20.3.3 Register Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Starting STOP/IDLE0/SLOW Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog Input Voltage and AD Conversion Result . . . . . . . . . . . . . . . . . . . . . . . Precautions about the AD Converter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Analog input pin voltage range ........................................................................................................... 302 Analog input pins used as input/output ports ...................................................................................... 302 Noise countermeasure........................................................................................................................ 302 300 300 301 302 20.7.1 20.7.2 20.7.3 21. Flash Memory 21.1 21.2 Flash Memory Control . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 304 Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 307 Flash memory command sequence execution and toggle control (FLSCR1 21.3 21.2.1 21.2.2 21.2.3 21.2.4 21.2.5 21.2.6 21.3.1 21.3.2 21.3.3 Command Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 312 Byte program ...................................................................................................................................... 312 Sector erase (4-kbyte partial erase) ................................................................................................... 313 Chip erase (all erase) ......................................................................................................................... 313 vii 21.4 21.5 21.3.4 21.3.5 21.3.6 Toggle Bit (D6) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314 Access to the Flash Memory Area. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 315 Flash memory control in serial PROM mode ...................................................................................... 315 Flash memory control in MCU mode .................................................................................................. 318 How to write to the flash memory by transferring a control program to the RAM area How to write to the flash memory by using a support program (API) of BOOTROM How to transfer and write a control program to the RAM area in RAM loader mode of the serial PROM mode Product ID entry .................................................................................................................................. 314 Product ID exit .................................................................................................................................... 314 Security program ................................................................................................................................ 314 21.5.1 21.5.2 21.5.1.1 21.5.2.1 21.5.2.2 21.6 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 323 22. Serial PROM Mode 22.1 22.2 22.3 22.4 22.5 22.6 22.7 22.8 Outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 325 Serial PROM Mode Setting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 326 Example Connection for On-board Writing . . . . . . . . . . . . . . . . . . . . . . . . . . . . 328 Activating the Serial PROM Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 329 Interface Specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 330 Memory Mapping . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Operation Commands . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 332 Flash memory erase command (0xF0) ............................................................................................... 335 Specifying the erase area 22.3.1 Serial PROM mode control pins ......................................................................................................... 326 22.6.1 22.6.2 SIO communication ............................................................................................................................ 330 UART communication ......................................................................................................................... 330 22.8.1 22.8.2 22.8.3 22.8.4 22.8.5 22.8.6 22.8.7 22.8.8 22.8.9 22.8.1.1 Flash memory write command (operation command: 0x30)............................................................... Flash memory read command (operation command: 0x40) ............................................................... RAM loader command (operation command: 0x60) ........................................................................... Flash memory SUM output command (operation command: 0x90) ................................................... Product ID code output command (operation command: 0xC0)......................................................... Flash memory status output command (0xC3) ................................................................................... Flash memory status code 338 340 342 344 345 347 22.8.7.1 22.9 Error Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 352 22.10 Checksum (SUM) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 353 22.11 22.12 22.10.1 22.10.2 Mask ROM emulation setting command (0xD0) ................................................................................. 350 Flash memory security setting command (0xFA)................................................................................ 351 Intel Hex Format (Binary) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 354 Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 355 Passwords ........................................................................................................................................ 355 How a password can be specified Password structure Password setting, cancellation and authentication Password values and setting range How the security program functions Enabling or disabling the security program Calculation method ........................................................................................................................... 353 Calculation data ................................................................................................................................ 353 22.12.1 22.12.2 22.12.1.1 22.12.1.2 22.12.1.3 22.12.1.4 22.12.2.1 22.12.2.2 Security program .............................................................................................................................. 359 22.13 22.14 22.12.3 22.12.4 Flowchart . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 363 AC Characteristics (UART) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 364 Reset timing ...................................................................................................................................... Flash memory erase command (0xF0) ............................................................................................. Flash memory write command (0x30)............................................................................................... Flash memory read command (0x40) ............................................................................................... RAM loader command (0x60) ........................................................................................................... Flash memory SUM output command (0x90) ................................................................................... 365 365 366 366 367 367 Option codes..................................................................................................................................... 360 Recommended settings .................................................................................................................... 362 22.14.1 22.14.2 22.14.3 22.14.4 22.14.5 22.14.6 viii 22.15 22.14.7 Product ID code output command (0xC0) ........................................................................................ 22.14.8 Flash memory status output command (0xC3) ................................................................................. 22.14.9 Mask ROM emulation setting command (0xD0) ............................................................................... 22.14.10 Flash memory security setting command (0xFA)............................................................................ Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 369 367 368 368 368 23. On-chip Debug Function (OCD) 23.1 23.2 23.3 23.4 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . How to Connect the On-chip Debug Emulator to a Target System . . . . . . . . . . Security . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 371 371 372 372 24. Input/Output Circuit 24.1 Control Pins . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 373 25. Electrical Characteristics 25.1 25.2 Absolute Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 375 Operating Conditions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 376 MCU mode (Flash Programming or erasing) ...................................................................................... 376 MCU mode (Except Flash Programming or erasing) .......................................................................... 377 Serial PROM mode ............................................................................................................................. 378 25.3 25.4 25.5 25.6 25.7 25.2.1 25.2.2 25.2.3 DC Characteristics. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AD Conversion Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Power-on Reset Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Voltage Detecting Circuit Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . AC Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . MCU mode (Flash programming or erasing) ...................................................................................... 385 MCU mode (Except Flash Programming or erasing) .......................................................................... 385 Serial PROM mode ............................................................................................................................. 386 379 382 383 384 385 25.8 25.7.1 25.7.2 25.7.3 25.8.1 Flash Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 386 Write characteristics ........................................................................................................................... 386 25.9 Recommended Oscillating Condition- 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 387 25.10 Handling Precaution . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 388 25.11 Revision History. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 389 26. Package Dimensions ix x TMP89FM42 CMOS 8-Bit Microcontroller TMP89FM42 The TMP89FM42 is a single-chip 8-bit high-speed and high-functionality microcomputer incorporating 32768 bytes of Flash Memory. It is pin-compatible with the TMP89CM42 (Mask ROM version). The TMP89FM42 can realize operations equivalent to those of the TMP89CM42 by programming the on-chip Flash Memory. Product No. TMP89FM42UG Note : ROM (Flash) 32768 bytes RAM 2048 bytes Package LQFP44-P-1010-0.80B Flash MCU * TMP89CM42UG Emulation Chip * TMP89C900XBG * ; Under development 1.1 Features 1. 8-bit single chip microcomputer TLCS-870/C1 series - Instruction execution time : 100 ns (at 10 MHz) 122 s (at 32.768 kHz) - 133 types & 732 basic instructions 2. 25 interrupt sources (External : 6 Internal : 19 , Except reset) 3. Input / Output ports (40 pins) Note : Two of above pins can not be used for the I/O port, because they should be connected with the high frequency OSC input. Large current output: 8 pins (Typ. 20mA) 4. Watchdog timer - Interrupt or reset can be selected by the program. 5. Power-on reset circuit 6. Voltage detection circuit 7. Divider output function 8. Time base timer 9. 16-bit timer counter : 2 ch - Timer, External trigger, Event Counter, Window, Pulse width measurement, PPG OUTPUT modes This product uses the Super Flash(R) technology under the licence of Silicon Storage Technology, Inc. Super Flash(R) is registered trademark of Silicon Storage Technology, Inc. * The information contained herein is subject to change without notice. 021023_D * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. 021023_A * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. 021023_B * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. 060106_Q * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. 070122_C * The products described in this document are subject to foreign exchange and foreign trade control laws. 060925_E * For a discussion of how the reliability of microcontrollers can be predicted, please refer to Section 1.3 of the chapter entitled Quality and Reliability Assurance/Handling Precautions. 030619_S RA000 Page 1 1.1 Features TMP89FM42 10. 8-bit timer counter: 4 ch - Timer, Event Counter, PWM, PPG OUTPUT modes - Usable as a 16-bit timer, 12-bit PWM output and 16-bit PPG output by the cascade connection of two channels. 11. Real time clock 12. UART : 1ch 13. UART/SIO : 1ch Note : One SIO channel can be used at the same time. 14. I2C/SIO : 1ch 15. Key-on wake-up : 8 ch 16. 10-bit successive approximation type AD converter - Analog input : 8ch 17. On-chip debug function - Break/Event - Trace - RAM monitor - Flash memory writing 18. Clock operation mode control circuit : 2 circuit Single clock mode / Dual clock mode 19. Low power consumption operation (8 mode) - STOP mode: Oscillation stops. (Battery/Capacitor back-up.) - SLOW1 mode: Low power consumption operation using low-frequency clock.(High-frequency clock stop.) - SLOW2 mode: Low power consumption operation using low-frequency clock.(High-frequency clock oscillate.) - IDLE0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using high frequency clock. Released when the reference time set to TBT has elapsed. - IDLE1 mode: The CPU stops, and peripherals operate using high frequency clock. Release by interruputs(CPU restarts). - IDLE2 mode: CPU stops and peripherals operate using high and low frequency clock. Release by interruputs. (CPU restarts). - SLEEP0 mode: CPU stops, and only the Time-Based-Timer(TBT) on peripherals operate using low frequency clock. Released when the reference time set to TBT has elapsed. - SLEEP1 mode: CPU stops, and peripherals operate using low frequency clock. Release by interruput.(CPU restarts). 20. Wide operation voltage: 4.3 V to 5.5 V at 10MHz /32.768 kHz 2.7 V to 5.5 V at 4.2 MHz /32.768 kHz 2.2 V to 5.5 V at 2MHz /32.768 kHz RA000 Page 2 TMP89FM42 1.2 Pin Assignment Figure 1-1 Pin Assignment RA000 VSS (XIN) P00 (XOUT) P01 MODE VDD (XTIN) P02 (XTOUT) P03 (RESET) P10 (STOP/INT5) P11 (INT0) P12 (INT1) P13 1 2 3 4 5 6 7 8 9 10 11 (TXD1/RXD1) P91 (PWM02/PPG02/TC02) P80 (PWM03/PPG03/TC03) P81 (PWM00/PPG00/TC00) P70 (PWM01/PPG01/TC01) P71 (PPGA0/TCA0) P72 (PPGA1/TCA1) P73 (SO0/RXD0/TXD0) PB4 (SI0/TXD0/RXD0) PB5 (SCLK0) PB6 PB7 33 32 31 30 29 28 27 26 25 24 23 P90 (TXD1/RXD1) P77 (INT4) P76 (INT3) P75 (INT2) P74 (DVO) P47 (AIN7/KWI7) P46 (AIN6/KWI6) P45 (AIN5/KWI5) P44 (AIN4/KWI4) P43 (AIN3/KWI3) P42 (AIN2/KWI2) 22 21 20 19 18 17 16 15 14 13 12 34 35 36 37 38 39 40 41 42 43 44 P41(AIN1/KWI1) P40(AIN0/KWI0) VAREF/AVDD P27 P26 P25(SCLK0) P24(SCL0/SI0) P23(SDA0/SO0) P22(SCLK0) P21(RXD0/TXD0/SI0/OCDIO) P20(TXD0/RXD0/SO0/OCDCK) Page 3 1.3 Block Diagram TMP89FM42 1.3 Block Diagram Figure 1-2 Block Diagram RA000 Page 4 TMP89FM42 1.4 Pin Names and Functions The TMP89FM42 has MCU mode, parallel PROM mode, and serial PROM mode. Table 1-1 shows the pin functions in MCU mode. The serial PROM mode is explained later in a separate chapter. Table 1-1 Pin Names and Functions(1/3) Pin Name P03 XTOUT P02 XTIN P01 XOUT P00 XIN P13 INT1 P12 INT0 Input/Output IO O IO I IO O IO I IO I IO I IO I I IO I IO IO IO IO IO IO I IO IO O IO IO IO I O I IO IO O I O I IO I I IO I I Functions PORT03 Low frequency OSC output PORT02 Low frequency OSC input PORT01 High frequency OSC output PORT00 High frequency OSC input PORT13 External interrupt 1 input PORT12 External interrupt 0 input PORT11 External interrupt 5 input STOP mode release input PORT10 Reset signal input PORT27 PORT26 PORT25 Serial clock input/output 0 PORT24 I2C bus clock input/output 0 Serial data input 0 PORT23 I2C bus data input/output 0 Serial data output 0 PORT22 Serial clock input/output 0 PORT21 UART data input 0 UART data output 0 Serial data input 0 OCD data input/output PORT20 UART data output 0 UART data input 0 Serial data output 0 OCD clock input PORT47 Analog input 7 Key-on wake-up input 7 PORT46 Analog input 6 Key-on wake-up input 6 P11 INT5 STOP P10 RESET P27 P26 P25 SCLK0 P24 SCL0 SI0 P23 SDA0 SO0 P22 SCLK0 P21 RXD0 TXD0 SI0 OCDIO P20 TXD0 RXD0 SO0 OCDCK P47 AIN7 KWI7 P46 AIN6 KWI6 RA000 Page 5 1.4 Pin Names and Functions TMP89FM42 Table 1-1 Pin Names and Functions(2/3) Pin Name P45 AIN5 KWI5 P44 AIN4 KWI4 P43 AIN3 KWI3 P42 AIN2 KWI2 P41 AIN1 KWI1 P40 AIN0 KWI0 P77 INT4 P76 INT3 P75 INT2 P74 DVO Input/Output IO I I IO I I IO I I IO I I IO I I IO I I IO I IO I IO I IO O IO I O IO I O IO I O O IO I O O IO I O O IO I O O IO I O PORT45 Analog input 5 Key-on wake-up input 5 PORT44 Analog input 4 Key-on wake-up input 4 PORT43 Analog input 3 Key-on wake-up input 3 PORT42 Analog input 2 Key-on wake-up input 2 PORT41 Analog input 1 Key-on wake-up input 1 PORT40 Analog input 0 Key-on wake-up input 0 PORT77 External interrupt 4 input PORT76 External interrupt 3 input PORT75 External interrupt 2 input PORT74 Divider output PORT73 TCA1 input PPGA1 output PORT72 TCA0 input PPGA0 output PORT71 TC01 input PPG01 output PWM01 output PORT70 TC00 input PPG00 output PWM00 output PORT81 TC03 input PPG03 output PWM03 output PORT80 TC02 input PPG02 output PWM02 output PORT91 UART data input 1 UART data output 1 Functions P73 TCA1 PPGA1 P72 TCA0 PPGA0 P71 TC01 PPG01 PWM01 P70 TC00 PPG00 PWM00 P81 TC03 PPG03 PWM03 P80 TC02 PPG02 PWM02 P91 RXD1 TXD1 RA000 Page 6 TMP89FM42 Table 1-1 Pin Names and Functions(3/3) Pin Name P90 TXD1 RXD1 PB7 PB6 SCLK0 PB5 RXD0 TXD0 SI0 PB4 TXD0 RXD0 SO0 MODE Input/Output IO O I IO IO IO IO I O I IO O I O I PORT90 UART data output 1 UART data input 1 PORTB7 PORTB6 Serial clock input/output 0 PORTB5 UART data input 0 UART data output 0 Serial data input 0 PORTB4 UART data output 0 UART data input 0 Serial data output 0 Test pin for out-going test (fix to Low level). Analog reference voltage input pin for A/D conversion. / Analog power supply pin. VDD pin GND pin Functions VAREF / AVDD I VDD VSS I I RA000 Page 7 1.4 Pin Names and Functions TMP89FM42 RA000 Page 8 TMP89FM42 2. CPU Core 2.1 Configuration The CPU core consists of a CPU, a system clock controller and a reset circuit. This chapter describes the CPU core address space, the system clock controller and the reset circuit. 2.2 Memory space The 870/C1 CPU memory space consists of a code area to be accessed as instruction operation codes and operands and a data area to be accessed as sources and destinations of transfer and calculation instructions. Both the code and data areas have independent 64-Kbyte address spaces. 2.2.1 Code area The code area stores operation codes, operands, vector tables for vector call instructions and interrupt vector tables. The RAM, the BOOTROM and the Flash are mapped in the code area. 0x0000 0x003F 0x0040 0x083F SWI instruction (0xFF) is fetched. 0x1000 0x17FF 0x1800 SWI instruction (0xFF) is fetched. RAM (2048 bytes) SWI instruction (0xFF) is fetched. RAM (2048 bytes) SWI instruction (0xFF) is fetched. SWI instruction (0xFF) is fetched. SWI instruction (0xFF) is fetched. BOOTROM (2048 bytes) BOOTROM (2048 bytes) 0x7FFF 0x8000 Flash (32768 bytes) Flash (32768 bytes) Flash (32768 bytes) Flash (32768 bytes) 0xFFA0 0xFFBF Vector table for vector call instructions (32 bytes) Vector table for vector call instructions (32 bytes) Vector table for vector call instructions (32 bytes) Vector table for vector call instructions (32 bytes) 0xFFCC 0xFFFF Interrupt vector table (52 bytes) Immediately after reset release Interrupt vector table (52 bytes) When the RAM is mapped in the code area Interrupt vector table (52 bytes) When the BOOTROM is mapped in the code area Interrupt vector table (52 bytes) When the RAM and the BOOTROM are mapped in the code area Note: Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM mode. Figure 2-1 Memory Map in the Code Area RA001 Page 9 2. CPU Core 2.2 Memory space TMP89FM42 2.2.1.1 RAM The RAM is mapped in the data area immediately after reset release. By setting SYSCR3 Note 1: When the RAM is not mapped in the code area, the SWI instruction is fetched from 0x0040 to 0x083F. Note2: The contents of the RAM become unstable when the power is turned on and immediately after a reset is released. To execute the program by using the RAM, transfer the program to be executed in the initialization routine. System control register 3 SYSCR3 (0x0FDE) 7 Bit Symbol Read/Write After reset R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 RVCTR R/W 0 1 RAREA R/W 0 0 (RSTDIS) R/W 0 RAREA Specifies mapping of the RAM in the code area 0: 1: The RAM is not mapped from 0x0040 to 0x083F in the code area. The RAM is mapped from 0x0040 to 0x083F in the code area. Vector table for vector call instructions Vector table for interrupt 0xFFC8 to 0xFFFF in the code area 0x01C8 to 0x01FD in the code area RVCTR Specifies mapping of the vector table for vector call instructions and interrupts 0: 0xFFA0 to 0xFFBF in the code area 0x01A0 to 0x01BF in the code area 1: Note 1: The value of SYSCR3 System control register 4 SYSCR4 (0x0FDF) 7 Bit Symbol Read/Write After reset 0 0 0 0 6 5 4 SYSCR4 W 0 0 0 0 3 2 1 0 SYSCR4 Writes the SYSCR3 data control code. 0xB2 : 0xD4 : 0x71 : Enables the contents of SYSCR3 Note 1: SYSCR4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit operation. Note 2: After SYSCR3 RA001 Page 10 TMP89FM42 System control status register 4 SYSSR4 (0x0FDF) 7 Bit Symbol Read/Write After reset R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 RVCTRS R 0 1 RAREAS R 0 0 (RSTDIS) R 0 RAREAS Status of mapping of the RAM in the code area Status of mapping of the vector address in the area 0: 1: 0: 1: The enabled SYSCR3 RVCTRS Note: Bits 7 to 3 of SYSSR4 are read as "0". Example: Program transfer (Transfer the program saved in the data area to the RAM.) LD LD LD TRANS_RAM: LD LD INC INC DEC JRS HL, TRANSFER_START_ADDRESS DE, PROGRAM_START_ADDRESS BC, BYTE_OF_PROGRAM A, (DE) (HL), A HL DE BC F, TRANS_RAM ; Destination RAM address ; Source ROM address ; Number of bytes of the program to be executed -1 ; Reading the program to be transferred ; Writing the program to be transferred ; Destination address increment ; Source address increment ; Have all the programs been transferred? 2.2.1.2 BOOTROM The BOOTROM is not mapped in the code area or the data area after reset release. Setting FLSMD Note 1: When the BOOTROM is not mapped in the code area, an instruction is fetched from the Flash or an SWI instruction is fetched, depending on the capacity of the internal Flash. Note 2: Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM mode. Flash memory control register 1 FLSCR1 (0x0FD0) 7 Bit Symbol Read/Write After reset 0 6 (FLSMD) R/W 1 0 5 4 BAREA R/W 0 0 3 (FAREA) R/W 0 0 2 1 (ROMSEL) R/W 0 0 BAREA Specifies mapping of the BOOTROM in the code and data areas 0: 1: The BOOTROM is not mapped to 0x1000 to 0x17FF in the code area and to 0x1000 to 0x17FF in the data area. The BOOTROM is mapped to 0x1000 to 0x17FF in the code area and to 0x1000 to 0x17FF in the data area. Note: The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift register. Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift register. This means that a register setting value does not take effect until "0xD5" is written to the register FLSCR2. The value of the shift register can be checked by reading the register FLSCRM. RA001 Page 11 2. CPU Core 2.2 Memory space TMP89FM42 Flash memory control register 2 FLSCR2 (0x0FD1) Bit Symbol Read/Write After reset * * * * 7 6 5 4 CR1EN W * * * * 3 2 1 0 CR1EN FLSCR1 register enable/disable control 0xD5 Others Enable a change in the FLSCR1 setting Reserved 2.2.1.3 Flash The Flash is mapped to 0x8000 to 0xFFFF in the code area after reset release. 2.2.2 Data area The data area stores the data to be accessed as sources and destinations of transfer and calculation instructions. The SFR, the RAM, the BOOTROM and the FLASH are mapped in the data area. 0x0000 0x003F 0x0040 0x083F SFR1 (64 bytes) RAM (2048 bytes) 0xFF is read SFR1 (64 bytes) RAM (2048 bytes) 0xFF is read SFR3 (192 bytes) SFR2 (256 bytes) BOOTROM (2048 bytes) 0x0E40 0x0EFF 0x0F00 0x0FFF 0x1000 0x17FF 0x1800 SFR3 (192 bytes) SFR2 (256 bytes) 0xFF is read 0x7FFF 0x8000 0xFF is read Flash (32768 bytes) Flash (32768 bytes) 0xFFFF Immediately after reset release When the BOOTROM is mapped in the data area Note: Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM mode. Figure 2-2 Memory Map in the Data Area RA001 Page 12 TMP89FM42 2.2.2.1 SFR The SFR is mapped to 0x0000 to 0x003F (SFR1), 0x0F00 to 0x0FFF (SFR2) and 0x0E40 to 0x0EFF (SFR3) in the data area after reset release. Note: Don't access the reserved SFR. 2.2.2.2 RAM The RAM is mapped to 0x0040 to 0x083F in the data area after reset release. Note: The contents of the RAM become unstable when the power is turned on and immediately after a reset is released. To execute the program by using the RAM, transfer the program to be executed in the initialization routine. Example: RAM initialization program LD LD LD HL, RAM_TOP_ADDRESS A, 0x00 BC, BYTE_OF_CLEAR_BYTES (HL), A HL BC F, CLR_RAM ; Head of address of the RAM to be initialized ; Initialization data ; Number of bytes of RAM to be initialized -1 ; Initialization of the RAM ; Initialization address increment ; Have all the RAMs been initialized? CLR_RAM: LD INC DEC JRS 2.2.2.3 BOOTROM The BOOTROM is not mapped in the code area or the data area after reset release. Setting FLSMD Note 1: When the BOOTROM is not mapped in the data area, 0xFF is read from 0x1000 to 0x17FF. Note2: Only the first 2 Kbytes of the BOOTROM are mapped in the memory map, except in the serial PROM mode. Flash memory control register 1 FLSCR1 (0x0FD0) 7 Bit Symbol Read/Write After reset 0 6 (FLSMD) R/W 1 0 5 4 BAREA R/W 0 0 3 (FAREA) R/W 0 0 2 1 (ROMSEL) R/W 0 0 BAREA Specifies mapping of the BOOTROM in the code and data areas 0: 1: The BOOTROM is not mapped to 0x1000 to 0x17FF in the code area and to 0x1000 to 0x17FF in the data area. The BOOTROM is mapped to 0x1000 to 0x17FF in the code area and to 0x1000 to 0x17FF in the data area. Note: The flash memory control register 1 has a double-buffer structure comprised of the register FLSCR1 and a shift register. Writing "0xD5" to the register FLSCR2 allows a register setting to be reflected and take effect in the shift register. This means that a register setting value does not take effect until "0xD5" is written to the register FLSCR2. The value of the shift register can be checked by reading the register FLSCRM. Flash memory control register 2 FLSCR2 (0x0FD1) Bit Symbol Read/Write After reset * * * * 7 6 5 4 CR1EN W * * * * 3 2 1 0 RA001 Page 13 2. CPU Core 2.2 Memory space TMP89FM42 CR1EN FLSCR1 register enable/disable control 0xD5 Others Enable a change in the FLSCR1 setting Reserved 2.2.2.4 Flash The Flash is mapped to 0x8000 to 0xFFFF in the data area after reset release. RA001 Page 14 TMP89FM42 2.3 System clock controller 2.3.1 Configuration The system clock controller consists of a clock generator, a clock gear, a timing generator, a warm-up counter and an operation mode control circuit. WUCCR WUCDR Warm-up counter INTWUC interrupt XEN/XTEN STOP Clock generator XIN TBTCR DV9CK SYSCR1 SYSCR2 High-frequency clock oscillation circuit XOUT fc Clock gear (x1/4,x1/2,x1) FCGCKSEL Clock gear control register fcgck Timing generator Operation mode control circuit System control register System clock 1/4 XTIN Low-frequency clock oscillation circuit XTOUT fs Oscillation/stop control Figure 2-3 System Clock Controller 2.3.2 Control The system clock controller is controlled by system control register 1 (SYSCR1), system control register 2 (SYSCR2), the warm-up counter control register (WUCCR), the warm-up counter data register (WUCDR) and the clock gear control register (CGCR). System control register 1 SYSCR1 (0x0FDC) 7 Bit Symbol Read/Write After reset STOP R/W 0 6 RELM R/W 0 5 OUTEN R/W 0 4 DV9CK R/W 0 3 R 1 2 R 0 1 R 0 0 R 0 STOP Activates the STOP mode 0: 1: 0: Operate the CPU and the peripheral circuits Stop the CPU and the peripheral circuits (activate the STOP mode) Edge-sensitive release mode (Release the STOP mode at the rising edge of the STOP mode release signal) Level-sensitive release mode (Release the STOP mode at the "H" level of the STOP mode release signal) High impedance Output hold fcgck/29 fs/4 RELM Selects the STOP mode release method 1: OUTEN Selects the port output state in the STOP mode Selects the input clock to stage 9 of the divider 0: 1: 0: 1: DV9CK Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz] Note 2: Bits 2, 1 and 0 of SYSCR1 are read as "0". Bit 3 is read as "1". RA001 Page 15 2. CPU Core 2.3 System clock controller TMP89FM42 Note 3: If the STOP mode is activated with SYSCR1 System control register 2 SYSCR2 (0x0FDD) 7 Bit Symbol Read/Write After reset R 0 6 XEN R/W 1 5 XTEN R/W 0 4 SYSCK R/W 0 3 IDLE R/W 0 2 TGHALT R/W 0 1 R 0 0 R 0 XEN Controls the high-frequency clock oscillation circuit Controls the low-frequency clock oscillation circuit Selects a system clock CPU and WDT control (IDLE1/2 or SLEEP1 mode) TG control (IDLE0 or SLEEP0 mode) 0: 1: 0: 1: 0: 1: 0: 1: 0: 1: Stop oscillation Continue or start oscillation Stop oscillation Continue or start oscillation Gear clock (fcgck) (NORMAL1/2 or IDLE1/2 mode) Low-frequency clock (fs/4) (SLOW1/2 or SLEEP1 mode) Operate the CPU and the WDT Stop the CPU and the WDT (Activate IDLE1/2 or SLEEP1 mode) Enable the clock supply from the TG to all the peripheral circuits Disable the clock supply from the TG to the peripheral circuits except the TBT (Activate IDLE0 or SLEEP0 mode) XTEN SYSCK IDLE TGHALT Note 1: fcgck: Gear clock [Hz], fs: Low-frequency clock [Hz] Note 2: WDT: Watchdog timer, TG: Timing generator Note 3: Don't set both SYSCR2 Warm-up counter control register WUCCR (0x0FCD) 7 Bit Symbol Read/Write After reset WUCRST W 0 6 R 0 5 R 0 4 R 0 1 3 WUCDIV R/W 1 2 1 WUCSEL R/W 0 0 R 1 WUCRST Resets and stops the warm-up counter 0: 1: 00 : 01 : 10 : 11 : 0: 1: Clear and stop the counter Source clock Source clock / 2 Source clock / 22 Source clock / 23 Select the high-frequency clock (fc) Select the low-frequency clock (fs) WUCDIV Selects the frequency division of the warm-up counter source clock WUCSEL Selects the warm-up counter source clock Note 1: fc: High-frequency clock [Hz], fs: Low-frequency clock [Hz] Note 2: WUCCR RA001 Page 16 TMP89FM42 Warm-up counter data register WUCDR (0x0FCE) 7 Bit Symbol Read/Write After reset 0 1 1 0 6 5 4 WUCDR R/W 0 1 1 0 3 2 1 0 WUCDR Warm-up time setting Note 1: Don't start the warm-up counter operation with WUCDR set at "0x00". Clock gear control register CGCR (0x0FCF) 7 Bit Symbol Read/Write After reset R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 R 0 0 1 FCGCKSEL R/W 0 0 FCGCKSEL Clock gear setting 00 : 01 : 10 : 11 : fcgck = fc / 4 fcgck = fc / 2 fcgck = fc Reserved Note 1: fcgck: Gear clock [Hz], fc: High-frequency clock [Hz] Note 2: Don't change CGCR 2.3.3 Functions Clock generator The clock generator generates the basic clock for the system clocks to be supplied to the CPU core and peripheral circuits. It contains two oscillation circuits: one for the high-frequency clock and the other for the low-frequency clock. The oscillation circuit pins are also used as ports P0. For the setting to use them as ports, refer to the chapter of I/O Ports. To use ports P00 and P01 as the high-frequency clock oscillation circuits (the XIN and XOUT pins), set P0FC0 to "1" and then set SYSCR2 2.3.3.1 RA001 Page 17 2. CPU Core 2.3 System clock controller TMP89FM42 The hardware control is executed by reset release and the operation mode control circuit when the operation is switched to the STOP mode as described in "2.3.5 Operation mode control circuit". Note: No hardware function is available for external direct monitoring of the basic clock. The oscillation frequency can be adjusted by programming the system to output pulses at a certain frequency to a port (for example, a clock output) with interrupts disabled and the watchdog timer disabled and monitoring the output. An adjustment program must be created in advance for a system that requires adjustment of the oscillation frequency. To prevent the dead lock of the CPU core due to the software-controlled enabling/disabling of the oscillation, an internal factor reset is generated depending on the combination of values of the clock selected as the main system clock, SYSCR2 P0FC0 Don't Care SYSCR2 Don't Care Don't Care 0 1 Don't Care 0 Don't Care 0 0 1 Don't Care Don't Care Note: It takes a certain period of time after SYSCR2 High-frequency clock XIN XOUT XIN XOUT XTIN Low-frequency clock XTOUT XTIN XTOUT (Open) (Open) (a) Crystal or ceramic oscillator (b) External oscillator (c) Crystal oscillator (d) External oscillator Figure 2-4 Examples of Oscillator Connection 2.3.3.2 Clock gear The clock gear is a circuit that selects a gear clock (fcgck) obtained by dividing the high-frequency clock (fc) and inputs it to the timing generator. Selects a divided clock at CGCR RA001 Page 18 TMP89FM42 Immediately after reset release, the gear clock (fcgck) becomes the clock that is a quarter of the highfrequency clock (fc). Table 2-2 Gear Clock (fcgck) CGCR Note: Don't change CGCR 2.3.3.3 Timing generator The timing generator is a circuit that generates system clocks to be supplied to the CPU core and the peripheral circuits, from the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). The timing generator has the following functions: 1. Generation of the main system clock (fm) 2. Generation of clocks for the timer counter, the time base timer and other peripheral circuits Main system clock fm Main system clock generator Machine cycle counter SYSCR2 Timer counter, time base timer and other peripheral circuits Figure 2-5 Configuration of Timing Generator (1) Configuration of timing generator The timing generator consists of a main system clock generator, a prescaler, a 21-stage divider and a machine cycle counter. 1. Main system clock generator This circuit selects the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs) for the main system clock (fm) to operate the CPU core. Clearing SYSCR2 RA001 Page 19 2. CPU Core 2.3 System clock controller TMP89FM42 2. Prescaler and divider These circuits divide fcgck. The divided clocks are supplied to the timer counter, the time base timer and other peripheral circuits. When both SYSCR1 2.3.4 Warm-up counter The warm-up counter is a circuit that counts the high-frequency clock (fc) and the low-frequency clock (fs), and it consists of a source clock selection circuit, a 3-stage frequency division circuit and a 14-stage counter. The warm-up counter is used to secure the time after a power-on reset is released before the supply voltage becomes stable and secure the time after the STOP mode is released or the operation mode is changed before the oscillation by the oscillation circuit becomes stable. WUCCR WUCSEL WUCDIV WUCRST SYSCR2 XEN XTEN STOP SYSCR1 INTWUC interrupt Warm-up counter controller S Clock for high-frequency clock oscillation circuit (fc) Clock for low-frequency clock oscillation circuit (fs) Enable/disable counting up Enable CPU operation AZ B 123 S D CZ B A 1 2 3 4 5 6 7 8 9 10 11 12 13 14 Comparator 01234567 WUCDR Figure 2-6 Warm-up Counter Circuit RA001 Page 20 TMP89FM42 2.3.4.1 Warm-up counter operation when the oscillation is enabled by the hardware (1) When a power-on reset is released or a reset is released The warm-up counter serves to secure the time after a power-on reset is released before the supply voltage becomes stable and the time after a reset is released before the oscillation by the high-frequency clock oscillation circuit becomes stable. When the power is turned on and the supply voltage exceeds the power-on reset release voltage, the warm-up counter reset signal is released. At this time, the CPU and the peripheral circuits are held in the reset state. A reset signal initializes WUCCR Note: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. (2) When the STOP mode is released The warm-up counter serves to secure the time after the oscillation is enabled by the hardware before the oscillation becomes stable at the release of the STOP mode. The high-frequency clock (fc) or the low-frequency clock (fs), which generates the main system clock when the STOP mode is activated, is selected as the input clock for frequency division circuit, regardless of WUCCR Clock that generates the main system clock when the STOP mode is activated WUCCR WUCCR Counter input clock Warm-up time 00 01 fc Don't Care 10 11 00 01 fs Don't Care 10 11 fc fc / 2 fc / 22 fc / 23 26 / fc to 255 x 26 / fc 27 / fc to 255 x 27 / fc 28 / fc to 255 x 28 / fc 29 / fc to 255 x 29 / fc 26 / fs to 255 x 26 / fs 27 / fs to 255 x 27 / fs 28 / fs to 255 x 28 / fs 29 / fs to 255 x 29 / fs fs fs / 2 fs / 22 fs / 23 Note 1: When the operation is switched to the STOP mode during the warm-up for the oscillation enabled by the software, the warm-up counter holds the value at the time, and restarts counting after the STOP mode is released. In this case, the warm-up time at the release of the STOP mode becomes insufficient. Don't switch the operation to the STOP mode during the warm-up for the oscillation enabled by the software. RA001 Page 21 2. CPU Core 2.3 System clock controller TMP89FM42 Note 2: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. Set the sufficient time for the oscillation start property of the oscillator. 2.3.4.2 Warm-up counter operation when the oscillation is enabled by the software The warm-up counter serves to secure the time after the oscillation is enabled by the software before the oscillation becomes stable, at a mode change from NORMAL1 to NORMAL2 or from SLOW1 to SLOW2. Select the input clock to the frequency division circuit at WUCCR Note: The warm-up counter starts counting when SYSCR2 WUCCR WUCCR Counter input clock fc fc / 2 fc / 22 fc / 23 fs fs / 2 fs / 22 fs / 23 26 Warm-up time / fc to 255 x 26 / fc 27 / fc to 255 x 27 / fc 28 / fc to 255 x 28 / fc 29 / fc to 255 x 29 / fc 26 / fs to 255 x 26 / fs 27 / fs to 255 x 27 / fs 28 / fs to 255 x 28 / fs 29 / fs to 255 x 29 / fs 0 10 11 00 01 1 10 11 Note: The clock output from the oscillation circuit is used as the input clock to the warm-up counter. The warm-up time contains errors because the oscillation frequency is unstable until the oscillation circuit becomes stable. Set the sufficient time for the oscillation start property of the oscillator. 2.3.5 Operation mode control circuit The operation mode control circuit starts and stops the oscillation circuits for the high-frequency and lowfrequency clocks, and switches the main system clock (fm). There are three operating modes: the single-clock mode, the dual-clock mode and the STOP mode. These modes are controlled by the system control registers (SYSCR1 and SYSCR2). Figure 2-7 shows the operating mode transition diagram. 2.3.5.1 Single-clock mode Only the gear clock (fcgck) is used for the operation in the single-clock mode. RA001 Page 22 TMP89FM42 The main system clock (fm) is generated from the gear clock (fcgck). Therefore, the machine cycle time is 1/fcgck [s]. The gear clock (fcgck) is generated from the high-frequency clock (fc). In the single-clock mode, the low-frequency clock generation circuit pins P03 (XTIN) and P04 (XTOUT) can be used as the I/O ports. (1) NORMAL1 mode In this mode, the CPU core and the peripheral circuits operate using the gear clock (fcgck). The NORMAL1 mode becomes active after reset release. (2) IDLE1 mode In this mode, the CPU and the watchdog timer stop and the peripheral circuits operate using the gear clock (fcgck). The IDLE1 mode is activated by setting SYSCR2 (3) IDLE0 mode In this mode, the CPU and the peripheral circuits stop, except the oscillation circuits and the time base timer. In the IDLE0 mode, the peripheral circuits stop in the states when the IDLE0 mode is activated or become the same as the states when a reset is released. For operations of the peripheral circuits in the IDLE0 mode, refer to the section of each peripheral circuit. The IDLE0 mode is activated by setting SYSCR2 RA001 Page 23 2. CPU Core 2.3 System clock controller TMP89FM42 2.3.5.2 Dual-clock mode The gear clock (fcgck) and the low-frequency clock (fs) are used for the operation in the dual-clock mode. The main system clock (fm) is generated from the gear clock (fcgck) in the NORMAL2 or IDLE2 mode, and generated from the clock that is a quarter of the low-frequency clock (fs) in the SLOW1/2 or SLEEP0/1 mode. Therefore, the machine cycle time is 1/fcgck [s] in the NORMAL2 or IDLE2 mode and is 4/fs [s] in the SLOW1/2 or SLEEP0/1 mode. P03 (XTIN) and P04 (XTOUT) are used as the low-frequency clock oscillation circuit pins. (These pins cannot be used as I/O ports in the dual-clock mode.) The operation of the TLCS-870/C1 Series becomes the single-clock mode after reset release. To operate it in the dual-clock mode, allow the low-frequency clock to oscillate at the beginning of the program. (1) NORMAL2 mode In this mode, the CPU core operates using the gear clock (fcgck), and the peripheral circuits operate using the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). (2) SLOW2 mode In this mode, the CPU core and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). In the SLOW mode, some peripheral circuits become the same as the states when a reset is released. For operations of the peripheral circuits in the SLOW mode, refer to the section of each peripheral circuit. Set SYSCR2 (3) SLOW1 mode In this mode, the high-frequency clock oscillation circuit stops operation and the CPU core and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). This mode requires less power to operate the high-frequency clock oscillation circuit than in the SLOW2 mode. In the SLOW mode, some peripheral circuits become the same as the states when a reset is released. For operations of the peripheral circuits in the SLOW mode, refer to the section of each peripheral circuit. Set SYSCR2 (4) IDLE2 mode In this mode, the CPU and the watchdog timer stop and the peripheral circuits operate using the gear clock (fcgck) or the clock that is a quarter of the low-frequency clock (fs). The IDLE2 mode can be activated and released in the same way as for the IDLE1 mode. The operation returns to the NORMAL2 mode after this mode is released. RA001 Page 24 TMP89FM42 (5) SLEEP1 mode In this mode, the high-frequency clock oscillation circuit stops operation, the CPU and the watchdog timer stop, and the peripheral circuits operate using the clock that is a quarter of the low-frequency clock (fs). In the SLEEP1 mode, some peripheral circuits become the same as the states when a reset is released. For operations of the peripheral circuits in the SLEEP1 mode, refer to the section of each peripheral circuit. The SLEEP1 mode can be activated and released in the same way as for the IDLE1 mode. The operation returns to the SLOW1 mode after this mode is released. In the SLOW1 or SLEEP1 mode, outputs of the prescaler and stages 1 to 8 of the divider stop. (6) SLEEP0 mode In this mode, the high-frequency clock oscillation circuit stops operation, the time base timer operates using the clock that is a quarter of the low-frequency clock (fs), and the core and the peripheral circuits stop. In the SLEEP0 mode, the peripheral circuits stop in the states when the SLEEP0 mode is activated or become the same as the states when a reset is released. For operations of the peripheral circuits in the SLEEP0 mode, refer to the section of each peripheral circuit. The SLEEP0 mode can be activated and released in the same way as for the IDLE0 mode. The operation returns to the SLOW1 mode after this mode is released. In the SLEEP0 mode, the CPU stops and the timing generator stops the clock supply to the peripheral circuits except the time base timer. 2.3.5.3 STOP mode In this mode, all the operations in the system, including the oscillation circuits, are stopped and the internal states in effect before the system was stopped are held with low power consumption. In the STOP mode, the peripheral circuits stop in the states when the STOP mode is activated or become the same as the states when a reset is released. For operations of the peripheral circuits in the STOP mode, refer to the section of each peripheral circuit. The STOP mode is activated by setting SYSCR1 RA001 Page 25 2. CPU Core 2.3 System clock controller TMP89FM42 2.3.5.4 Transition of operation modes RESET Reset release IDLE0 mode Warm-up that follows reset release Warm-up completed SYSCR2 IDLE2 mode SLOW2 mode SYSCR2 Note 1: The NORMAL1 and NORMAL2 modes are generically called the NORMAL mode; the SLOW1 and SLOW2 modes are called the SLOW mode; the IDLE0, IDLE1 and IDLE2 modes are called the IDLE mode; and the SLEEP0 and SLEEP1 are called the SLEEP mode. Note 2: The mode is released by the falling edge of the source clock selected at TBTCR Figure 2-7 Operation Mode Transition Diagram RA001 Page 26 TMP89FM42 Table 2-3 Operation Modes and Conditions Oscillation circuit Operation mode High-frequency Low-frequency CPU core Watchdog timer Time base timer Other peripheral circuits Machine cycle time RESET NORMAL1 Oscillation Single clock IDLE1 IDLE0 STOP Stop Stop Reset Operate Reset Operate Reset Reset Operate Operate Stop Stop Stop Stop Operate with the high frequency Operate with the high/low frequency Stop Operate with the low frequency Operate with the low frequency 1 / fcgck [s] A| NORMAL2 1 / fcgck [s] IDLE2 Oscillation Stop Operate with the low frequency Operate with the low frequency SLOW2 Oscillation Dual clock SLOW1 Operate Operate 4/ fs [s] SLEEP1 SLEEP0 STOP Stop Stop Stop Stop Stop Stop A| 2.3.6 Operation Mode Control STOP mode The STOP mode is controlled by system control register 1 (SYSCR1) and the STOP mode release signals. 2.3.6.1 (1) Start the STOP mode The STOP mode is started by setting SYSCR1 (2) Release the STOP mode The STOP mode is released by the following STOP mode release signals. It is also released by a reset by the RESET pin, a power-on reset and a reset by the voltage detection circuits. When a reset is released, the warm-up starts. After the warm-up is completed, the NORMAL1 mode becomes active. 1. Release by the STOP pin RA001 Page 27 2. CPU Core 2.3 System clock controller TMP89FM42 2. Release by key-on wakeup 3. Release by the voltage detection circuits Note: During the STOP period (from the start of the STOP mode to the end of the warm-up), due to changes in the external interrupt pin signal, interrupt latches may be set to "1" and interrupts may be accepted immediately after the STOP mode is released. Before starting the STOP mode, therefore, disable interrupts. Also, before enabling interrupts after STOP mode is released, clear unnecessary interrupt latches. 1. Release by the STOP pin Release the STOP mode by using the STOP pin. To release the STOP mode by using the STOP pin, set VDCR2 Note: When the STOP mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the STOP mode was started, regardless of WUCCR Example: Starting the STOP mode from the SLOW mode with an INT5 interrupt (Warm-up time at release of the STOP mode is about 450ms at fs=32.768 KHz.) PINT5: TEST JRS LD LD LD DI SET SINT5: RETI (SYSCR1).7 (P0PRD).5 F, SINT5 (SYSCR1), 0x40 (WUCCR), 0x03 (WUCDR),0xE8 ; To reject noise, the STOP mode does not start ; if the STOP pin input is high. ; Sets up the level-sensitive release mode ; WUCCR Note: When the STOP mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the STOP mode was started, regardless of WUCCR STOP pin VIH XOUT pin NORMAL mode STOP mode Confirm by program that the STOP pin input is low and start the STOP mode. Warm-up NORMAL mode The STOP mode is released by the hardware. Always released if the STOP pin input is high. RA001 Page 28 TMP89FM42 Even if the STOP pin input returns to low after the warm-up starts, the STOP mode is not restarted. Figure 2-8 Level-sensitive Release Mode (Example when the high-frequency clock oscillation circuit is selected) - Edge-sensitive release mode In this mode, the STOP mode is released at the rising edge of the STOP pin input. Setting SYSCR1 Example: Starting the STOP mode from the NORMAL mode (Warm-up time at release of the STOP mode is about 200ms at fc=10 MHz.) LD LD DI LD (SYSCR1) , 0x80 (WUCCR),0x01 (WUCDR),0x20 ; WUCCR Note: When the STOP mode is released, the warm-up counter source clock automatically changes to the clock that generated the main system clock when the STOP mode was started, regardless of WUCCR STOP pin VIH XOUT pin NORMAL mode The STOP mode is started by the program. STOP mode Warm-up NORMAL mode STOP mode The STOP mode is released by the hardware at the rising edge of the STOP pin input. Note: If the rising edge is input to the STOP pin within 1 machine cycle after SYSCR1 Figure 2-9 Edge-sensitive Release Mode (Example when the high-frequency clock oscillation circuit is selected) RA001 Page 29 2. CPU Core 2.3 System clock controller TMP89FM42 2. Release by the key-on wakeup The STOP mode is released by inputting the prescribed level to the key-on wakeup pin. The level to release the STOP mode can be selected from "H" and "L". For release by the key-on wakeup, refer to section "Key-on Wakeup". Note: If the key-on wakeup pin input becomes the opposite level to the release level after the warm-up starts, the STOP mode is not restarted. 3. Release by the voltage detection circuits The STOP mode is released by the supply voltage detection by the voltage detection circuits. To release the STOP mode by using the voltage detection circuits, set VDCR2 Note: If the supply voltage becomes equal to or higher than the detection voltage within 1 machine cycle after SYSCR1 (3) STOP mode release operation The STOP mode is released in the following sequence: 1. Oscillation starts. For the oscillation start operation in each mode, refer to "Table 2-4 Oscillation Start Operation at Release of the STOP Mode". 2. Warm-up is executed to secure the time required to stabilize oscillation. The internal operations remain stopped during warm-up. The warm-up time is set by the warm-up counter, depending on the oscillator characteristics. 3. After the warm-up time has elapsed, the normal operation is restarted by the instruction that follows the STOP mode start instruction. At this time, the prescaler and the divider of the timing generator are cleared to "0". Note: When the STOP mode is released with a low hold voltage, the following cautions must be observed. The supply voltage must be at the operating voltage level before releasing the STOP mode. The RESET pin input must also be "H" level, rising together with the supply voltage. In this case, if an external time constant circuit has been connected, the RESET pin input voltage will increase at a slower pace than the power supply voltage. At this time, there is a danger that a reset may occur if the input voltage level of the RESET pin drops below the non-inverting high-level input voltage (Hysteresis input). RA001 Page 30 TMP89FM42 Table 2-4 Oscillation Start Operation at Release of the STOP Mode Operation mode before the STOP mode is started High-frequency clock High-frequency clock oscillation circuit Low-frequency clock Oscillation start operation after release The high-frequency clock oscillation circuit starts oscillation. The low-frequency clock oscillation circuit stops oscillation. The high-frequency clock oscillation circuit starts oscillation. The low-frequency clock oscillation circuit starts oscillation. The high-frequency clock oscillation circuit stops oscillation. The low-frequency clock oscillation circuit starts oscillation. Single-clock mode NORMAL1 - NORMAL2 Dual-clock mode SLOW1 High-frequency clock oscillation circuit Low-frequency clock oscillation circuit - Low-frequency clock oscillation circuit Note: When the operation returns to the NORMAL2 mode, fc is input to the frequency division circuit of the warm-up counter. 2.3.6.2 IDLE1/2 and SLEEP1 modes The IDLE1/2 and SLEEP1 modes are controlled by the system control register 2 (SYSCR2) and maskable interrupts. The following states are maintained during these modes. 1. The CPU and the watchdog timer stop their operations. The peripheral circuits continue to operate. 2. The data memory, the registers, the program status word and the port output latches are all held in the status in effect before IDLE1/2 or SLEEP1 mode was started. 3. The program counter holds the address of the instruction 2 ahead of the instruction which starts the IDLE1/2 or SLEEP1 mode. RA001 Page 31 2. CPU Core 2.3 System clock controller TMP89FM42 Starting IDLE1/2 mode or SLEEP1 mode by an instruction CPU and WDT stop Reset input No No Interrupt request Yes No (Normal release mode) Yes Reset IMF = "1" Yes (Interrupt release mode) Interrupt processing Execution of the instruction which follows the IDLE1/2 mode or SLEEP1 mode start instruction Figure 2-10 IDLE1/2 and SLEEP 1 Modes RA001 Page 32 TMP89FM42 (1) Start the IDLE1/2 and SLEEP1 modes After the interrupt master enable flag (IMF) is set to "0", set the individual interrupt enable flag (EF) to "1", which releases IDLE1/2 and SLEEP1 modes. To start the IDLE1/2 or SLEEP1 mode, set SYSCR2 Note 1: When a watchdog timer interrupt is generated immediately before the IDLE1/2 or SLEEP1 mode is started, the watchdog timer interrupt will be processed but the IDLE1/2 or SLEEP1 mode will not be started. Note 2: Before starting the IDLE1/2 or SLEEP1 mode, enable the interrupt request signals to be generated to release the IDLE1/2 or SLEEP1 mode and set the individual interrupt enable flag. (2) Release the IDLE1/2 and SLEEP1 modes The IDLE1/2 and SLEEP1 modes include a normal release mode and an interrupt release mode. These modes are selected at the interrupt master enable flag (IMF). After releasing IDLE1/2 or SLEEP1 mode, SYSCR2 2.3.6.3 IDLE0 and SLEEP0 modes The IDLE0 and SLEEP0 modes are controlled by the system control register 2 (SYSCR2) and the time base timer control register (TBTCR). The following states are maintained during the IDLE0 and SLEEP0 modes: * The timing generator stops the clock supply to the peripheral circuits except the time base timer. * The data memory, the registers, the program status word and the port output latches are all held in the states in effect before the IDLE0 or SLEEP0 mode was started. * The program counter holds the address of the instruction 2 ahead of the instruction which starts the IDLE0 or SLEEP0 mode. RA001 Page 33 2. CPU Core 2.3 System clock controller TMP89FM42 Stopping peripherals by instructions Starting IDLE0 or SLEEP0 mode by an instruction CPU and WDT stop Reset input No No TBT source clock falling edge Yes Reset Yes "0" TBTCR (Normal release mode) Interrupt processing Execution of the instruction which follows the IDLE0 or SLEEP0 mode start instruction Figure 2-11 IDLE0 and SLEEP0 Modes * Start the IDLE0 and SLEEP0 modes Stop (disable) the peripherals such as a timer counter. To start the IDLE0 or SLEEP0 mode, set SYSCR2 RA001 Page 34 TMP89FM42 (1) Normal release mode (IMF, EF5, TBTCR (2) Interrupt release mode (IMF, EF5, TBTCR Note 1: The IDLE0 or SLEEP0 mode is released to the NORMAL1 or SLOW1 mode by the asynchronous internal clock selected at TBTCR 2.3.6.4 SLOW mode The SLOW mode is controlled by system control register 2 (SYSCR2). (1) Switching from the NORMAL2 mode to the SLOW1 mode Set SYSCR2 Note 1: Be sure to follow this procedure to switch the operation from the NORMAL2 mode to the SLOW1 mode. Note 2: It is also possible to allow the basic clock for the high-frequency clock to oscillate continuously to return to NORMAL2 mode. However, be sure to turn off the oscillation of the basic clock for the high-frequency clock when the STOP mode is started from the SLOW mode. Note 3: After switching SYSCR2 Quarter of the low-frequency clock (fs/4) Gear clock (fcgck) SYSCR2 Main system clock 10/fs (max.) When the rising edge of fcgck is When the rising edge of fs/4 is detected detected twice after SYSCR2 Figure 2-12 Switching of the Main System Clock (fm) (Switching from fcgck to fs/4) RA001 Page 35 2. CPU Core 2.3 System clock controller TMP89FM42 Example 1: Switching from the NORMAL2 mode to the SLOW1 mode (when fc is used as the basic clock for the high-frequency clock) SET (SYSCR2).4 ; SYSCR2 Example 2: Switching to the SLOW1 mode after the stable oscillation of the low-frequency clock oscillation circuit is confirmed at the warm-up counter (fs=32.768KHz, warm-up time = about 100 ms) ; #### Initialize routine #### SET | | LD LD (WUCCR), 0x02 (WUCDR), 0x33 ; WUCCR SET SET (EIRL).4 (SYSCR2).5 | ; #### Interrupt service routine of warm-up counter interrupts #### PINTWUC: SET NOP NOP CLR RETI | VINTWUC: DW PINTWUC ; INTWUC vector table (SYSCR2).6 ; SYSCR2 (2) Switching from the SLOW1 mode to the NORMAL1 mode Set SYSCR2 Note 1: Be sure to follow this procedure to switch the operation from the SLOW1 mode to the NORMAL1 mode. Note 2: After switching SYSCR2 RA001 Page 36 TMP89FM42 Quarter of the low-frequency clock (fs/4) Gear clock (fcgck) SYSCR2 2.5/fcgck(max.) Main system clock When the rising edge of fs/4 is When the rising edge of fcgck is detected detected twice after SYSCR2 Figure 2-13 Switching the Main System Clock (fm) (Switching from fs/4 to fcgck) Example : Switching from the SLOW1 mode to the NORMAL1 mode after the stability of the high-frequency clock oscillation circuit is confirmed at the warm-up counter (fc = 10 MHz, warm-up time = 4.0 ms) ; #### Initialize routine #### SET | | LD LD (WUCCR), 0x09 (WUCDR), 0x9D ; WUCCR SET SET | (EIRL). 4 (SYSCR2) .6 ; #### Interrupt service routine of warm-up counter interrupts #### PINTWUC: CLR NOP NOP CLR RETI | VINTWUC: DW PINTWUC ; INTWUC vector table (SYSCR2). 5 ; SYSCR2 RA001 Page 37 2. CPU Core 2.4 Reset Control Circuit TMP89FM42 2.4 Reset Control Circuit The reset circuit controls the external and internal factor resets and initializes the system. 2.4.1 Configuration The reset control circuit consists of the following reset signal generation circuits: 1. External reset input (external factor) 2. Power-on reset (internal factor) 3. Voltage detection reset 1 (internal factor) 4. Voltage detection reset 2 (internal factor) 5. Watchdog timer reset (internal factor) 6. System clock reset (internal factor) 7. Trimming data reset (internal factor) 8. Flash standby reset (internal factor) P10(RESET) Power-on reset signal P10 port Internal factor reset detection status register, Voltage detection circuit reset signal External reset input enable reset signal Voltage detection reset 1 signal Voltage detection reset 2 signal Watchdog timer reset signal System clock reset signal Trimming data reset signal Flash standby reset signal Warm-up counter Warm-up counter reset signal CPU/peripheral circuits reset signal System clock control circuit Figure 2-14 Reset Control Circuit 2.4.2 Control The reset control circuit is controlled by system control register 3 (SYSCR3), system control register 4 (SYSCR4), system control status register (SYSSR4) and the internal factor reset detection status register (IRSTSR). System control register 3 SYSCR3 (0x0FDE) 7 Bit Symbol Read/Write After reset R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 (RVCTR) R/W 0 1 (RAREA) R/W 0 0 RSTDIS R/W 0 RSTDIS External reset input enable register 0 : Enables the external reset input. 1 : Disables the external reset input. Note 1: The enabled SYSCR3 RA001 Page 38 TMP89FM42 Note 3: After SYSCR3 System control register 4 SYSCR4 (0x0FDF) 7 Bit Symbol Read/Write After reset 0 0 0 0 6 5 4 SYSCR4 W 0 0 0 0 3 2 1 0 SYSCR4 Writes the SYSCR3 data control code. 0xB2 : Enables the contents of SYSCR3 Note 1: SYSCR4 is a write-only register, and must not be accessed by using a read-modify-write instruction, such as a bit operation. Note 2: After SYSCR3 System control status register 4 SYSSR4 (0x0FDF) 7 Bit Symbol Read/Write After reset R 0 6 R 0 5 R 0 4 R 0 3 R 0 2 (RVCTRS) R 0 1 (RAREAS) R 0 0 RSTDISS R 0 RSTDISS External reset input enable status 0 : The enabled SYSCR3 Note 1: The enabled SYSCR3 Internal factor reset detection status register IRSTSR (0x0FCC) 7 Bit Symbol Read/Write After reset FCLR W 0 6 FLSRF R 0 5 TRMDS R 0 4 TRMRF R 0 3 LVD2RF R 0 2 LVD1RF R 0 1 SYSRF R 0 0 WDTRF R 0 RA001 Page 39 2. CPU Core 2.4 Reset Control Circuit TMP89FM42 FCLR Flag initialization control 0 :1 : Clears the internal factor reset flag to "0". 0 :1 : Detects the flash standby reset. 0 :1 : Detect state of abnormal trimming data 0 :1 : Detects the trimming data reset. 0 :1 : Detects the voltage detection 2 reset. 0 :1 : Detects the voltage detection 1 reset. 0 :1 : Detects the system clock reset. 0 :1 : Detects the watchdog timer reset. FLSRF Flash standby reset detection flag TRMDS Trimming data status TRMRF Trimming data reset detection flag LVD2RF Voltage detection reset 2 detection flag LVD1RF Voltage detection reset 1 detection flag SYSRF System clock reset detection flag WDTRF Watchdog timer reset detection flag Note 1: IRSTSR is initialized by an external reset input or power-on reset. Note 2: Care must be taken in system designing since the IRSTSR may not fulfill its functions due to disturbing noise and other effects. Note 3: IRSTSR 2.4.3 Functions The power-on reset, external reset input and internal factor reset signals are input to the warm-up circuit of the clock generator. During reset, the warm-up counter circuit is reset, and the CPU and the peripheral circuits are reset. After reset is released, the warm-up counter starts counting the high frequency clock (fc), and executes the warm-up operation that follows reset release. During the warm-up operation that follows reset release, the trimming data is loaded from the non-volatile exclusive use memory for adjustment of the ladder resistor that generates the comparison voltage for the power-on reset and the voltage detection circuits. When the warm-up operation that follows reset release is finished, the CPU starts execution of the program from the reset vector address stored in addresses 0xFFFE to 0xFFFF. When a reset signal is input during the warm-up operation that follows reset release, the warm-up counter circuit is reset. The reset operation is common to the power-on reset, external reset input and internal factor resets, except for the initialization of some special function registers and the initialization of the voltage detection circuits. When a reset is applied, the peripheral circuits become the states as shown in Table 2-5. RA001 Page 40 TMP89FM42 Table 2-5 Initialization of Built-in Hardware by Reset Operation and Its Status after Release Built-in hardware During reset During the warm-up operation that follows reset release MCU mode: 0xFFFE Serial PROM mode:0x01FF 0x00FF Indeterminate Indeterminate 0 Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate 0 0 0 Oscillation enabled Oscillation disabled Start 0 Disabled Disabled or enabled HiZ Refer to the SFR map. Immediately after the warm-up operation that follows reset release MCU mode: 0xFFFE Serial PROM mode:0x01FF 0x00FF Indeterminate Indeterminate 0 Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate 0 0 0 Oscillation enabled Oscillation disabled Stop 0 Enabled Disabled or enabled HiZ Refer to the SFR map. Program counter (PC) MCU mode: 0xFFFE Serial PROM mode:0x01FF 0x00FF Indeterminate Indeterminate 0 Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate Indeterminate 0 0 0 Oscillation enabled Oscillation disabled Reset 0 Disabled Disabled or enabled HiZ Refer to the SFR map. Stack pointer (SP) RAM General-purpose registers (W, A, B, C, D, E, H, L, IX and IY) Register bank selector (RBS) Jump status flag (JF) Zero flag (ZF) Carry flag (CF) Half carry flag (HF) Sign flag (SF) Overflow flag (VF) Interrupt master enable flag (IMF) Individual interrupt enable flag (EF) Interrupt latch (IL) High-frequency clock oscillation circuit Low-frequency clock oscillation circuit Warm-up counter Timing generator prescaler and divider Watchdog timer Voltage detection circuit I/O port pin status Special function register Note: The voltage detection circuits are disabled by an external reset input or power-on reset only. 2.4.4 Reset Signal Generating Factors Reset signals are generated by each factor as follows: 2.4.4.1 External reset input (RESET pin input) Port P10 is also used as the RESET pin, and it serves as the RESET pin after the power is turned on. If the supply voltage is lower than the recommended operating voltage range, for example, when the power is turned on, the supply voltage is raised to the operating voltage range with the RESET pin kept at the "L" level, and a reset is applied 5 s after the oscillation is stabilized. If the supply voltage is within the recommended operating voltage range, the RESET pin is kept at the "L" level for 5 s with the stabilized oscillation, and then a reset is applied. In each case, after a reset is applied, it is released by turning the RESET pin to "H" and the warm-up operation that follows reset release gets started. RA001 Page 41 2. CPU Core 2.4 Reset Control Circuit TMP89FM42 Note: When the supply voltage is equal to or lower than the detection voltage of the power-on reset circuit, the power-on reset remains active, even if the RESET pin is turned to "H". Operating voltage Reset time RESET pin CPU/peripheral circuits reset During reset Warm-up operation CPU and peripheral circuits start operation Figure 2-15 External Reset Input (when the power is turned on) Operating voltage Reset time RESET pin During reset Reset signal Warm-up operation CPU and peripheral circuits start operation Figure 2-16 External Reset Input (when the power is stabilized) RA001 Page 42 TMP89FM42 2.4.4.2 Power-on reset The power-on reset is an internal factor reset that occurs when the power is turned on. When power supply voltage goes on, if the supply voltage is equal to or lower than the releasing voltage of the power-on reset circuit, a reset signal is generated and if it is higher than the releasing voltage of the power-on reset circuit, a reset signal is released. When power supply voltage goes down, if the supply voltage is equal to or lower than the detecting voltage of the power-on reset circuit, a reset signal is generated. Refer to "Power-on Reset circuit". 2.4.4.3 Voltage detection reset The voltage detection reset is an internal factor reset that occurs when it is detected that the supply voltage has reached a predetermined detection voltage. Refer to "Voltage Detection Circuit". 2.4.4.4 Watchdog timer reset The watchdog timer reset is an internal factor reset that occurs when an overflow of the watchdog timer is detected. Refer to "Watchdog Timer". 2.4.4.5 System clock reset The system clock reset is an internal factor reset that occurs when it is detected that the oscillation enable register is set to a combination that puts the CPU into deadlock. Refer to "Clock Control Circuit". 2.4.4.6 Trimming data reset The trimming data reset is an internal factor reset that occurs when the trimming data latched in the internal circuit is broken down during operation due to noise or other factors. The trimming data is a data bit provided for adjustment of the ladder resistor that generates the comparison voltage for the power-on reset and the voltage detection circuits. This bit is loaded from the non-volatile exclusive use memory during the warm-up time that follows reset release (tPWUP) and latched into the internal circuit. If the trimming data loaded from the non-volatile exclusive use memory during the warm-up operation that follows reset release is abnormal, IRSTSR 2.4.4.7 Flash standby reset The flash standby reset is an internal factor reset generated by the reading or writing of data of the flash memory while it is on standby. Refer to "Flash Memory". RA001 Page 43 2. CPU Core 2.4 Reset Control Circuit TMP89FM42 2.4.4.8 Internal factor reset detection status register By reading the internal factor reset detection status register IRSTSR after the release of an internal factor reset, except the power-on reset, the factor which causes a reset can be detected. The internal factor reset detection status register is initialized by an external reset input or power-on reset. Set IRSTSR Note 1: Care must be taken in system designing since the IRSTSR may not fulfill its functions due to disturbing noise and other effects. Note 2: After IRSTSR 2.4.4.9 How to use the external reset input pin as a port To use the external reset input pin as a port, keep the external reset input pin at the "H" level until the power is turned on and the warm-up operation that follows reset release is finished. After the warm-up operation that follows reset release is finished, set P1PU0 to "1" and P1CR0 to "0", and connect a pull-up resistor for a port. Then set SYSCR3 Note 1: If you switch the external reset input pin to a port or switch the pin used as a port to the external reset input pin, do it when the pin is stabilized at the "H" level. Switching the pin function when the "L" level is input may cause a reset. Note 2: If the external reset input is used as a port, the statement which clears SYSCR3 RA001 Page 44 TMP89FM42 2.5 Revision History Rev Description "2.3.4.1 Warm-up counter operation when the oscillation is enabled by the hardware" Fixed specification from T.B.D. to 0x66. RA001 "Figure 2-15 External Reset Input (when the power is turned on)" and "Figure 2-16 External Reset Input (when the power is stabilized)" Deleted "Recommended". RA001 Page 45 2. CPU Core 2.5 Revision History TMP89FM42 RA001 Page 46 TMP89FM42 3. Interrupt Control Circuit The TMP89FM42 has a total of 25 interrupt sources excluding reset. Interrupts can be nested with priorities. Three of the internal interrupt sources are non-maskable while the rest are maskable. Interrupt sources are provided with interrupt latches (IL), which hold interrupt requests, and have independent vector addresses. When a request for an interrupt is generated, its interrupt latch is set to "1", which requests the CPU to accept the interrupt. Acceptance of interrupts is enabled or disabled by software using the interrupt master enable flag (IMF) and individual enable flag (EF) for each interrupt source. If multiple maskable interrupts are generated simultaneously, the interrupts are accepted in order of descending priority. The priorities are determined by the interrupt priority change control register (ILPRS1-ILPRS6) as Levels and determined by the hardware as the basic priorities. However, there are no prioritized interrupt sources among non-maskable interrupts. Interrupt sources Enable condition Interrupt latch Vector Address (MCU mode) RVCTR=0 enabled 0xFFFE 0xFFFC 0xFFFC 0xFFF8 0xFFF6 0xFFF4 0xFFF2 0xFFF0 0xFFEE 0xFFEC 0xFFEA 0xFFE8 0xFFE6 0xFFE4 0xFFE2 0xFFE0 0xFFDE 0xFFDC 0xFFDA 0xFFD8 0xFFD6 0xFFD4 0xFFD2 0xFFD0 0xFFCE 0xFFCC RVCTR=1 enabled 0x01FC 0x01FC 0x01F8 0x01F6 0x01F4 0x01F2 0x01F0 0x01EE 0x01EC 0x01EA 0x01E8 0x01E6 0x01E4 0x01E2 0x01E0 0x01DE 0x01DC 0x01DA 0x01D8 0x01D6 0x01D4 0x01D2 0x01D0 0x01CE 0x01CC - Basic priority Internal/ External Internal Internal Internal Internal Internal Internal Internal External Internal Internal Internal Internal Internal Internal Internal External External External External External Internal Internal Internal Internal Internal - (Reset) INTSWI INTUNDEF INTWDT INTWUC INTTBT INTRXD0 / INTSIO0 INTTXD0 INT5 INTVLTD INTADC INTRTC INTTC00 INTTC01 INTTCA0 INTSBI0/INTSIO0 INT0 INT1 INT2 INT3 INT4 INTTCA1 INTRXD1 INTTXD1 INTTC02 INTTC03 - Non-maskable Non-maskable Non-maskable Non-maskable IMF AND EIRL ILL |