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| 16 Bit Microcontroller TLCS-900/L1 Series TMP91FU62FG TMP91FU62DFG Revision 1.1 TOSHIBA CORPORATION The information contained herein is subject to change without notice. TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunction or failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of TOSHIBA or others. Please contact your sales representative for product-by-product details in this document regarding RoHS comaptibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate ths inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occurring as a result of noncompliance with applicable laws and regulations. (c) 2007 TOSHIBA CORPORATION All Rights Reserved TMP91FU62 Revision History Date 2007/01/18 Revision 0.2 TENTATIVE Table 1-1 Pin Names and Functions WAIT pin deletion. HV-monitor EMU0 P00-P07 large-current port 2.1 RESET 10 system clocks 16us 1us 2.3.4 Prescaler Clock Controller Table 4-1 Port Functions Table 4-2 I/O Port Setting List 4.3 Port3 (P30 to P33) Deleted The input function of wait control(WAIT) Deleted Note2. P40 to P43 function Table. 4.9.1 Port 90 (TXD0/RXD0), 93 (TXD1/RXD0) 4.9.2 Port91(RXD0/TXD0), 94 (RXD1/TXD1) PB0 to PB2 function Table. 4.12 Open-drain Control 4.13 Serial channel pin change Control 14.1 Absolute Maximum Ratings Table 2-7 Source of Halt State Clearance and Halt Clearance Operation Table 4-2 I/O Port Setting List (Port B) 4.1 Port 0 (P00 to P07) 4.2 Port 1 (P10 to P17) 4.4 Port 4 (P40 to P43) Figure 4-12 Port72 4.13 Serial channel pin change/ Open-drain output Control Table 6-1 Registers and Pins for TMRB 9. 10-bit AD Converter (ADC) VREFH AVCC 2007/04/27 0.4 Figure 9-4 Analog Input Voltage and AD Conversion Result (Typ.) 13.6.10 Programming the Flash Memory by the Internal CPU Read Values in Product ID Mode Example: Program to be loaded and executed in RAM 14.2 DC Electrical Characteristics Low-level output current 14.3 AD Conversion Characteristics Deleted Analog current for analog reference voltage 15.Table of SFR's Deleted P4FC register TMP91FU62 Date 2007/06/07 Revision 0.5 14.1 Absolute Maximum Ratings IOL, IOH is corrected 14.2 DC Electrical Characteristics ICC, IDDP-P is corrected 2007/8/27 1.0 DMAR register (89H) is corrected by RWM prohibition. 17.2 Points of note j. Releasing the HALT mode by requesting an interruption is deleted. 2.3.2 Note3 is added 7.2.1 Plescaler is corrected, and Table 7-2 is corrected 7.3 Note2 and Note3 are added 17.2 Points of note j.Clocks for serial channels (SIO)is added 6.3 SFR 15. Table of SFR's TB0FFCR, TB1FFCR, TB2FFCR and TB3FFCR register is corrected. 2007/10/10 1.1 TMP91FU62 CMOS 16 Bit Microcontroller TMP91FU62FG/DFG Product No. TMP91FU62FG 96K bytes TMP91FU62DFG 4K bytes QFP80-P-1420-0.80B ROM (Flash ROM) RAM Package LQFP80-P-1212-0.50E 1.1 Features * High-speed 16-bit CPU (900/L1 CPU) - Instruction mnemonics are upward-compatible with TLCS-900,900/H,900/L - 16 Mbytes of linear address space - General-purpose registers and register banks - 16-bit multiplication and division instructions; bit transfer and arithmetic instructions - Micro DMA: 4 channels (800ns/2 bytes at 20MHz) * Minimum instruction execution time:200ns (at 20MHz) * Built-in memory - ROM: 96K bytes (Flash ROM) - RAM: 4K bytes * 8-bit timers: 4 channels * 16-bit timers: 4 channels * General-purpose serial interface: 4 channels - UART/Synchronous mode: 3 channels - I2C bus mode: 1 channels * 10-bit AD converter (Built-in Sample hold circuit): 16 channels * Special timer for CLOCK * Watchdog timer * Program patch logic: 6 banks This product uses the Super Flash(R) technology under the licence of Silicon Storage Technology, Inc. Super Flash(R) is registered trademark of Silicon Storage Technology, Inc. 20070701-EN * The information contained herein is subject to change without notice. * TOSHIBA is continually working to improve the quality and reliability of its products. Nevertheless, semiconductor devices in general can malfunction or fail due to their inherent electrical sensitivity and vulnerability to physical stress. It is the responsibility of the buyer, when utilizing TOSHIBA products, to comply with the standards of safety in making a safe design for the entire system, and to avoid situations in which a malfunction or failure of such TOSHIBA products could cause loss of human life, bodily injury or damage to property. In developing your designs, please ensure that TOSHIBA products are used within specified operating ranges as set forth in the most recent TOSHIBA products specifications. Also, please keep in mind the precautions and conditions set forth in the "Handling Guide for Semiconductor Devices," or "TOSHIBA Semiconductor Reliability Handbook" etc. * The TOSHIBA products listed in this document are intended for usage in general electronics applications (computer, personal equipment, office equipment, measuring equipment, industrial robotics, domestic appliances, etc.). These TOSHIBA products are neither intended nor warranted for usage in equipment that requires extraordinarily high quality and/or reliability or a malfunctionor failure of which may cause loss of human life or bodily injury ("Unintended Usage"). Unintended Usage include atomic energy control instruments, airplane or spaceship instruments, transportation instruments, traffic signal instruments, combustion control instruments, medical instruments, all types of safety devices, etc. Unintended Usage of TOSHIBA products listed in this document shall be made at the customer's own risk. * The products described in this document shall not be used or embedded to any downstream products of which manufacture, use and/or sale are prohibited under any applicable laws and regulations. * The information contained herein is presented only as a guide for the applications of our products. No responsibility is assumed by TOSHIBA for any infringements of patents or other rights of the third parties which may result from its use. No license is granted by implication or otherwise under any patents or other rights of TOSHIBA or the third parties. * Please contact your sales representative for product-by-product details in this document regarding RoHS compatibility. Please use these products in this document in compliance with all applicable laws and regulations that regulate the inclusion or use of controlled substances. Toshiba assumes no liability for damage or losses occuuring as a result of noncompliance with applicable laws and regulations. Page 1 2007-10-10 TMP91FU62 * Interrupts: 48 interrupts - 9 CPU interrupts: Software interrupt instruction and illegal instruction - 30 internal interrupts: 7 priority levels are selectable - 9 external interrupts: 7 priority levels are selectable (among 1 interrupts are selectable edge mode) * Input/output ports: 69 pins * Standby function: Three HALT modes: IDLE2 (Programmable), IDLE1 and STOP * Clock controller - Clock gear function: Select a High-frequency clock fc/1 to fc/16 - Oscillator for CLOCK (fs = 32.768 kHz) * Operating voltage Flash read operation > Vcc=4.5 V - 5.5 V (fc max = 20MHz) Flash write/erase operation > Vcc=4.75 V - 5.25 V (fc max = 20MHz) * Package - LQFP80-P-1212-0.50E (TMP91FU62FG) - QFP80-P-1420-0.80B (TMP91FU62DFG) Page 2 2007-10-10 TMP91FU62 1.2 Pin Assignment Diagram P67/AN15 P66/AN14 P65/AN13 P64/AN12 P63/AN11 P62/AN10 P61/AN9 P60/AN8 P57/AN7 P56/AN6 P55/AN5 P54/AN4 P53/AN3 P52/AN2 P51/AN1 P50/AN0 PB2 PB1 PB0 P33/TB3OUT1 75 80 70 30 Figure 1-1 Pin Assignment(TMP91FU62FG) AM0 DVCC X2 DVSS X1 AM1 RESET P94/RXD1/TXD1 P95/SCLK1/CTS1 P96/XT1 P97/XT2 PA0/TB2IN0/INT1 PA1/TB2IN1/INT2 PA2/TB2OUT0 PA3/TB2OUT1 P40/SCOUT P41/TXD2/RXD2 P42/RXD2/TXD2 P43/SCLK2/CTS2 EMU0 25 35 40 AVSS AVCC P70/TA0IN P71/TA1OUT P72 P73/TA4IN P74/TA5OUT P75/INT0 P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0/RXD0 P91/RXD0/TXD0 P92/SCLK0/CTS0 P93/TXD1/RXD1 1 65 60 5 55 TMP91FU62FG 10 LQFP80 TOPVIEW 15 50 45 20 P32/TB3OUT0 P31/TB3IN1/INT4/SCL0 P30/TB3IN0/INT3/SDA0 P17 P16 P15 P14 P13 P12 P11 P10 DVSS P07 P06 P05 P04 P03 P02 P01 P00 Page 3 2007-10-10 PB1 PB2 P50/AN0 P51/AN1 P52/AN2 P53/AN3 P54/AN4 P55/AN5 P56/AN6 P57/AN7 P60/AN8 P61/AN9 P62/AN10 P63/AN11 P64/AN12 P65/AN13 65 75 80 70 1 5 60 10 55 QFP80 TOPVIEW TMP91FU62DFG Figure 1-2 Pin Assignment(TMP91FU62DFG) 15 Page 4 20 50 P66/AN14 P67/AN15 AVSS AVCC P70/TA0IN P71/TA1OUT P72 P73/TA4IN P74/TA5OUT P75/INT0 P80/TB0IN0/INT5 P81/TB0IN1/INT6 P82/TB0OUT0 P83/TB0OUT1 P84/TB1IN0/INT7 P85/TB1IN1/INT8 P86/TB1OUT0 P87/TB1OUT1 P90/TXD0/RXD0 P91/RXD0/TXD0 P92/SCLK0/CTS0 P93/TXD1/RXD1 AM0 DVCC 45 40 PB0 P33/TB3OUT1 P32/TB3OUT0 P31/TB3IN1/INT4/SCL0 P30/TB3IN0/INT3/SDA0 P17 P16 P15 P14 P13 P12 P11 P10 DVSS P07 P06 P05 P04 P03 P02 P01 P00 EMU0 P43/SCLK2/CTS2 30 35 25 P42/RXD2/TXD2 P41/TXD2/RXD2 P40/SCOUT PA3/TB2OUT1 PA2/TB2OUT0 PA1/TB2IN1/INT2 PA0/TB2IN0/INT1 P97/XT2 P96/XT1 P95/SCLK1/CTS1 P94/RXD1/TXD1 RESET AM1 X1 DVSS X2 TMP91FU62 2007-10-10 TMP91FU62 1.3 Block Diagram Figure 1-3 Block Diagram Page 5 2007-10-10 TMP91FU62 1.4 Pin Names and Functions Table 1-1 Pin Names and Functions(1/3) Input / Output IO IO IO I I IO IO I I IO IO O IO O IO O IO O I IO I O IO IO I IO I IO I IO I IO O IO IO I IO O IO I IO I I Pin Name Pin Number Functions P00-P07 P10-P17 P30 TB3IN0 INT3 SDA0 P31 TB3IN1 INT4 SCL0 P32 TB3OUT0 P33 TB3OUT1 P40 SCOUT P41 TXD2 RXD2 P42 RXD2 TXD2 P43 SCLK2 CTS2 P50-57 AN0-AN7 P60-67 AN8-AN15 P70 TA0IN P71 TA1OUT P72 P73 TA4IN P74 TA5OUT P75 INT0 P80 TB0IN0 INT5 8 8 Port 0: I/O port that allows I/O to be selected at the bit level (large-current port) Port 1: I/O port that allows I/O to be selected at the bit level Port 30: I/O port 16-bit timer 3 input 0:Timer B3 count/capture trigger Input 0 Interrupt Request Pin 3: Interrupt request pin with programmable rising edge / falling edge. Serial bus interface data 0 in I2C bus Mode. Port 31: I/O port 16-bit timer 3 input 1:Timer B3 count/capture trigger Input 1 Interrupt Request Pin 4: Interrupt request on rising edge Serial bus interface clock 0 in I2C bus Mode. Port 32: I/O port 16-bit timer 3 output 0: Timer B3 Output 0 Port 33: I/O port 16-bit timer 3 output 1: Timer B3 Output 1 Port 40: I/O port (with pull-up resistor) System Clock Output: Outputs fSYS or fs clock. Port 41: I/O port (with pull-up resistor) Serial Send Data 2 Serial Receive Data 2 Port 42: I/O port (with pull-up resistor) Serial Receive Data 2 Serial Send Data 2 Port 43: I/O port (with pull-up resistor) Serial Clock I/O 2 Serial Data Send Enable 2 (Clear to Send) Port 5: I/O port Analog input: Pin used to input to AD converter Port 6: I/O port Analog input: Pin used to input to AD converter Port 70: I/O port 8-bit timer 0 input: Timer A0 Input Port 71: I/O port 8-bit timer 1 output:Timer A1 Output Port 72: I/O port Port 73: I/O port 8-bit timer 4 input: Timer A4 Input Port 74: I/O port 8-bit timer 5 output:Timer A5 Output Port 75: I/O port Interrupt Request Pin 0: Interrupt request pin with programmable level / rising edge / falling edge. Port 80: I/O port 16-bit timer 0 input 0:Timer B0 count/capture trigger Input 0 Interrupt Request Pin 5: Interrupt request pin with programmable rising edge / falling edge. 1 1 1 1 1 1 1 1 8 8 1 1 1 1 1 1 1 Page 6 2007-10-10 TMP91FU62 Table 1-1 Pin Names and Functions(2/3) Input / Output IO I I IO O IO O IO I I IO I I IO O IO O IO O I IO I O IO IO I IO O I IO I O IO IO I IO I IO O IO I I IO I I IO O IO O Pin Name Pin Number Functions P81 TB0IN1 INT6 P82 TB0OUT0 P83 TB0OUT1 P84 TB1IN0 INT7 P85 TB1IN1 INT8 P86 TB1OUT0 P87 TB1OUT1 P90 TXD0 RXD0 P91 RXD0 TXD0 P92 SCLK0 CTS0 P93 TXD1 RXD1 P94 RXD1 TXD1 P95 SCLK1 CTS1 P96 XT1 P97 XT2 PA0 TB2IN0 INT1 PA1 TB2IN1 INT2 PA2 TB2OUT0 PA3 TB2OUT1 1 Port 81: I/O port 16-bit timer 0 input 1:Timer B0 count/capture trigger Input 1 Interrupt Request Pin 6: Interrupt request on rising edge Port 82: I/O port 16-bit timer 0 output 0: Timer B0 Output 0 Port 83: I/O port 16-bit timer 0 output 1: Timer B0 Output 1 Port 84: I/O port 16-bit timer 1 input 0:Timer B1 count/capture trigger Input 0 Interrupt Request Pin 7: Interrupt request pin with programmable rising edge / falling edge. Port 85: I/O port 16-bit timer 1 input 1:Timer B1 count/capture trigger Input 1 Interrupt Request Pin 8: Interrupt request on rising edge Port 86: I/O port 16-bit timer 1 output 0: Timer B1 Output 0 Port 87: I/O port 16-bit timer 1 output 1: Timer B1 Output 1 Port 90: I/O port Serial Send Data 0 Serial Receive Data 0 Port 91: I/O port Serial Receive Data 0 Serial Send Data 0 Port 92: I/O port Serial Clock I/O 0 Serial Data Send Enable 0 (Clear to Send) Port 93: I/O port Serial Send Data 1 Serial Receive Data 1 Port 94: I/O port Serial Receive Data 1 Serial Send Data 1 Port 95: I/O port Serial Clock I/O 1 Serial Data Send Enable 1 (Clear to Send) Port 96: I/O port Low-frequency oscillator connection pin Port 97: I/O port Low-frequency oscillator connection pin Port A0: I/O port 16-bit timer 2 input 0:Timer B2 count/capture trigger Input 0 Interrupt Request Pin 1: Interrupt request pin with programmable rising edge / falling edge. Port A1: I/O port 16-bit timer 2 input 1:Timer B2 count/capture trigger Input 1 Interrupt Request Pin 2: Interrupt request on rising edge Port A2: I/O port 16-bit timer 2 output 0: Timer B2 Output 0 Port A3: I/O port 16-bit timer 2 output 1: Timer B2 Output 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 1 Page 7 2007-10-10 TMP91FU62 Table 1-1 Pin Names and Functions(3/3) Input / Output IO Pin Name Pin Number Functions PB0-PB2 3 Port B: I/O port that allows I/O to be selected at the bit level Operation mode:Fixed to AM1 "1", AM0 "1". Single Boot mode:Fixed to AM1 "0", AM0 "1". Programmer mode:Fixed to AM1 "1", AM0 "0". Open pin Reset: initializes TMP91FU62. (with pull-up resistor) Power supply pin for AD converter GND pin for AD converter (0 V) AM0-1 2 I EMU0 RESET AVCC AVSS X1/X2 DVCC DVSS 1 1 1 1 2 3 3 O I IO High frequency oscillator connection pins Power supply pins (All DVCC pins should be connected with the power supply pin.) GND pins (0 V) (All DVSS pins should be connected with the GND (0V) pin.) Note: All pins that have built-in pull-up resistors (other than the RESET pin) can be disconnected from the built-in pull-up resistor by software. Page 8 2007-10-10 TMP91FU62 2. CPU The TMP91FU62 incorporates a high-performance 16-bit CPU (The 900/L1-CPU). For CPU operation, see the "TLCS-900/L1 CPU". The following describe the unique function of the CPU used in the TMP91FU62; these functions are not covered in the TLCS-900/L1 CPU section. 2.1 RESET When resetting the TMP91FU62 microcontroller, ensure that the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to low level at least for 10 system clocks (1us at 20 MHz). Thus, when turn on the switch, be set to the power supply voltage is within the operating voltage range, and that the internal high-frequency oscillator has stabilized. Then hold the RESET input to Low level at least for 10 system clocks. It means that the system clock mode fSYS is set to fc/2. When the reset is accept, the CPU: 1. Sets as follows the program counter (PC) in accordance with the reset vector stored at address FFFF00H to FFFF02H: - PC (7:0) - PC (15:8) <- Value at FFFF00H address <- Value at FFFF01H address - PC (23:16) <- Value at FFFF02H address 2. Sets the stack pointer (XSP) to 100H. 3. Sets bits Note 1: The CPU internal register (except to PC, SR, XSP in CPU) and internal RAM data do not change by resetting. Note 2: It is necessary to re-set up a stack pointer XSP by the user program. Figure 2-1 is a reset timing chart of the TMP91FU62. Page 9 2007-10-10 fFPH Sampling Sampling RESET Figure 2-1 TMP91FU62 Reset Timing Chart Page 10 (input mode) (input mode) P40~P43 P00 P30 P60 P80 PA0 P07, P10 P33, P50 P67, P70 P87, P90 PA3, PB0 P17 P57 P75 P97 PB2 TMP91FU62 2007-10-10 TMP91FU62 2.2 Memory Map Figure 2-2 is a memory map of the TMP91FU62. 000000H Internal I/O (4 Kbytes) (n) 000100H 001000H Internal RAM (4 Kbytes) 64 Kbyte area (nn) 002000H 010000H FE8000H 96 Kbyte 16-Mbyte area (R) (-R) (R+) (R + R8/16) (R + d8/16) (nnn) FFFF00H FFFFFFH Figure 2-2 TMP91FU62 Memory Map Page 11 2007-10-10 TMP91FU62 2.3 System Clock Function and Standby Control TMP91FU62 contains a clock gear, stand-by controller and noise-reduction circuit. It is used for low-noise systems. The clock operating modes are as follows: (a) Single clock mode (X1 and X2 pins only), (b) Dual clock mode (X1,X2,XT1 and XT2 pins). Figure 2-3 shows a transition figure. (fOSCH/2) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) NORMAL mode (fOSCH /gear value/2) STOP mode (Stops All circuits) (a) Single clock mode transition figure (fOSCH/2) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) NORMAL mode (fOSCH /gear value/2) STOP mode (Stops All circuits) IDLE2 mode (I/O operate) IDLE1 mode (Operate only oscillator) SLOW mode (fs/2) (b) Dual clock mode transition figure Figure 2-3 TMP91FU62 Clock Operating Mode Note: The clock frequency input from the X1 and X2 pins is called fOSCH and the clock frequency input from the XT1 and XT2 pins is called fs. The clock frequency selected by SYSCR1 Page 12 2007-10-10 TMP91FU62 2.3.1 Block Diagram of System Clock SYSCR0 /4 SYSCR0 Lowfrequency oscillator fs fFPH fs fc fc/2 2 fc/4 fc/8 fc/16 / / / / fSYS SYSCR0 Highfrequency oscillator SYSCR1 SYSCR1 fOSCH fSYS TMRA01 and TMRA45 T0 Prescaler CPU ROM RAM TMRB0 toTMRB3 Prescaler WDT I/O port SIO0 to SIO2 ADC Prescaler SBI0 Prescaler fs Binary counter SYSCR2 f Figure 2-4 Block Diagram of System Clock Page 13 2007-10-10 TMP91FU62 2.3.2 Table 2-1 SFR SFR for System Clock 7 Bit Symbol Read/Write After reset 1 0 1 XEN 6 XTEN 5 RXEN 4 RXTEN R/W 0 0 0 Warm-up timer control 0 Write: Don't care 1 Write: Start warmup 0 Read: End warmup 1 Read: Do not end warm-up GEAR2 R/W 0 0 0 0 0 3 RSYSCK 2 WUEF 1 PRCK1 0 - - - SYSCR0 (00E0H) Function Highfrequency oscillator 0:Stop 1:Oscillation Lowfrequency oscillator 0:Stop 1:Oscillation Highfrequency oscillator (fc) after release of STOP mode 0:Stop 1:Oscillation Lowfrequency oscillator (fs) after release of STOP mode 0:Stop 1:Oscillation Selects clock after release of STOP mode 0:fc 1:fs Select prescaler clock 0:fFPH 1:fc/16 Bit Symbol Read/Write After reset - - - - - - - - - - - - SYSCK GEAR1 GEAR0 SYSCR1 (00E1H) Function - - - - Select system clock 0: fc 1: fs Select gear value of high frequency (fc) 000:fc 001:fc/2 010:fc/4 011:fc/8 100:fc/16 101:reserved 110:reserved 111:reserved HALTM0 Bit Symbol Read/Write After reset SYSCR2 (00E2H) Function - - - SCOSEL WUPTM1 WUPTM0 R/W HALTM1 - - DRVE R/W 0 Pin state control in STOP mode 0: I/O off 1: Remains the state before HALT 0 1 0 1 1 - - Select SCOUT 0:fs 1:fSYS Select warm-up time for oscillator 00:218/inputted frequency 01:28/inputted frequency 10:214/inputted frequency 11:216/inputted frequency HALT mode 00:reserved 01:STOP mode 10:IDLE1 mode 11:IDLE2 mode - Note 1: "-" = Don't care Note 2: SYSCR0 Page 14 2007-10-10 TMP91FU62 2.3.3 System Clock Controller The system clock controller generates the system clock signal (fSYS) for the CPU core and internal I/O.It contains two oscillation circuits and a clock gear circuit for high-frequency (fc) operation. The register SYSCR1 Note 1: When using an oscillator (other than a resonator) with stable oscillation, a warm-up timer is not needed. Note 2: The warm-up timer is operated by an oscillation clock. Hence, there may be some variation in warm-up time. Note 3: Note of using low-frequency oscillator When connect low-frequency oscillator to ports 96 and 97, need below setting for cut consumption power. (Case of resonators) Set P9CR Table 2-2 Warm-up Times (when changing clock) Select Warm-up Time SYSCR2 Note: At fOSCH=20MHzfs=32.768kHz Page 15 2007-10-10 TMP91FU62 Example 1: Changing from high frequency (fc) to low frequency (fs). SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET WUP: BIT JR SET RES 00E0H 00E1H 00E2H (SYSCR2),X-11--X-B 6,(SYSCR0) 2,(SYSCR0) 2,(SYSCR0) NZ,WUP 3,(SYSCR1) 7,(SYSCR0) ; ; ; ; Detects stopping of warm-up timer. Sets warm-up time to 216/fs. Enables low-frequency oscillation. Clears and starts warm-up timer. ; ; ; Changes fSYS from fc to fs. Disables high-frequency oscillation. Note: X: Don't care, -:No change Counts up by fSYS Counts up by fs Figure 2-5 Changing from high frequency (fc) to low frequency (fs) Page 16 2007-10-10 TMP91FU62 Example 2: Changing from low frequency (fs) to high frequency (fc). SYSCR0 SYSCR1 SYSCR2 EQU EQU EQU LD SET SET WUP: BIT JR RES RES 00E0H 00E1H 00E2H (SYSCR2),X-10--X-B 7,(SYSCR0) 2,(SYSCR0) 2,(SYSCR0) NZ,WUP 3,(SYSCR1) 6,(SYSCR0) ; ; ; ; Detects stopping of warm-up timer. ; ; ; Changes fSYS from fs to fc Disables low-frequency oscillation. Sets warm-up time to 214/fc. Enables high-frequency oscillation. Clears and starts warm-up timer. Note: X: Don't care, -:No change Counts up by fc Figure 2-6 Changing from low frequency (fs) to high frequency (fc) (2) Clock gear controller When the high-frequency clock fc is selected by setting SYSCR1 Page 17 2007-10-10 TMP91FU62 Example 3: Changing to a clock gear SYSCR1 EQU LD X:Don't care (Clock gear changing) To change the clock gear, write the register value to the SYSCR1 ; Changes fSYS to fc/2. SYSCR1 EQU LD LD 00E1H (SYSCR1),XXXX0000B (DUMMY),00H ; ; Changes fSYS to fc/2. Dummy instruction Instruction to be executed after clock gear has changed. (3)Internal clock output The fSYS or fs internal clock can be driven out from the P40/SCOUT pin. The P40/SCOUT pin is configured as SCOUT (System clock output) by programming the port 4 registers as follows: P4CR HALT mode NORMAL SLOW IDLE2 2.3.4 Prescaler Clock Controller For the internal I/O (TMRA01 and TMRA45, TMRB0 to TMRB3, SIO0 to SIO2, SBI0) there is a prescaler which can divide the clock. The T0 clock input to the prescaler is either the clock fFPH divided by 2 or the clock fc/16 divided by 4. The setting of the SYSCR0 Page 18 2007-10-10 TMP91FU62 2.3.5 Runaway provision with SFR protection register (Purpose) Provision in runaway of program by noise mixing. Write operation to specified SFR is prohibited so that provision program in runaway prevents that it is it in the state which is fetch impossibility by stopping of clock, memory control register (CS/WAIT controller) is changed. Specified SFR list 1. Clock gear (write enable only EMCCR1) SYSCR0, SYSCR1, SYSCR2 (Block diagram) EMCCR0 S R Q Write signal to SFR (Setting method) If writing except "1FH" code to EMCCR1 register, it become protect ON. By this operation, write operation to specified SFR is disabling. If writing "1FH" to EMCCR1 register, it become protect OFF. State of protect can to confirm by reading EMCCR0 7 Bit Symbol Read/Write EMCCR0 (00E3H) After reset PROTECT R 0 Protect flag 0: OFF 1: ON 0 1 0 6 5 4 3 2 1 0 - - - - R/W 0 - - - 0 1 1 Function Write "0". Write "1". Write "0". Write "0". Write "0". Write "1". Write "1". Bit Symbol EMCCR1 (00E4H) Read/Write After reset Function Protect OFF by writing "1FH". Protect ON by writing except "1FH". Page 19 2007-10-10 TMP91FU62 2.3.6 Standby Controller (1)HALT modes When the HALT instruction is executed, the operating mode switches to IDLE2, IDLE1 or STOP mode, depending on the contents of the SYSCR2 Internal I/O TMRA01 TMRA45 TMRB0 TMRB1 TMRB2 TMRB3 SFR TA01RUN 2. IDLE1: Only the oscillator and the RTC (Real time clock) continue to operate. 3. STOP: All internal circuits stop operating. The operation of each of the different HALT modes is described in Table 2-6. Table 2-6 I/O Operation during HALT Modes HALT mode SYSCR2 11 10 Stop 01 Keep the state when the HALT instruction was executed. See Table 2-9 Stop WDT Interrupt controller Operate Page 20 2007-10-10 TMP91FU62 (2)How to release the HALT mode These halt states can be released by resetting or requesting an interrupt. The halt release sources are determined by the combination between the states of interrupt mask register Note:Usually, interrupts can release all halts status. However, the interrupts (INT0, INTRTC) which can release the HALT mode may not be able to do so if they are input during the period CPU is shifting to the HALT mode (for about 5 clocks of fFPH) with IDLE1 or STOP mode (IDLE2 is not applicable to this case). (In this case, an interrupt request is kept on hold internally.) If another interrupt is generated after it has shifted to HALT mode completely, halt status can be released without difficulty. The priority of this interrupt is compared with that of the interrupt kept on hold internally, and the interrupt with higher priority is handled first followed by the other interrupt. Releasing by resetting Releasing all halt status is executed by resetting. When the STOP mode is released by RESET, it is necessary enough resetting time (See Table 2-6)to set the operation of the oscillator to be stable. When releasing the HALT mode by resetting, the internal RAM data keeps the state before the "HALT" instruction is executed. However the other settings contents are initialized. (Releasing due to interrupts keeps the state before the "HALT" instruction is executed.) Page 21 2007-10-10 TMP91FU62 Table 2-7 Source of Halt State Clearance and Halt Clearance Operation Status of Received Interrupt Interrupt Enable (Interrupt level) IDLE2 (Interrupt mask) STOP Interrupt Disable (Interrupt level) < (Interrupt mask) IDLE2 IDLE1 STOP - HALT mode INTWDT INT0(Note 1) IDLE1 (Note 2) x x x x x x x x x *1 x x x x x x x x x x x x x x x x x x x x x x *1 x x x x x x x x Source of Halt state clearance INTRTC INT1-INT8 Interrupt INTTA0, INTTA1, INTTA4, INTTA5 INTTB00-30, INTTB01-31 INTTB0F0-3 INTRX0-INTRX2, INTTX0-INTTX2 INTSBI0 INTAD RESET Initialize LSI :After clearing the HALT mode, CPU starts interrupt processing. :After clearing the HALT mode, CPU resumes executing starting from instruction following the HALT instruction. (Interrupt routine don't execute.) x:It can not be used to release the HALT mode. - :The priority level (Interrupt request level) of non-maskable interrupts is fixed to 7, the highest priority level. There is not this combination type. *1:Releasing the HALT mode is executed after passing the warm-up time. Note 1: When the HALT mode is cleared by an INT0 interrupt of the level mode in the interrupt enabled status, hold high level until starting interrupt process. If low level was set before interrupt process is stared, interrupt process is not started correctly. Note 2: If using external interrupt INT1 to INT8 in IDLE2 mode, set 16-bit timer RUN register TB0RUN Page 22 2007-10-10 TMP91FU62 Example:Clearing halt state An INT0 interrupt clears the halt state when the device is in IDLE1 mode. 8203H 8206H 8209H 820BH 820EH INT0 LD LD EI LD HALT (IIMC), 00H (INTE0AD), 06H 5 (SYSCR2), 28H ; Selects INT0 interrupt rising edge. ; Sets INT0 interrupt level to 6. ; Sets CPU interrupt level to 5. ; Sets HALT mode to IDLE1 mode. ; Halts CPU. INT0 interrupt routine RETI 820FH LD XX, XX (3)Operation 1. IDLE2 mode In IDLE2 mode only specific internal I/O operations, as designated by the IDLE2 setting register, can take place. Instruction execution by the CPU stops. Figure 2-7 illustrates an example of the timing for clearance of the IDLE2 mode halt state by an interrupt. X1 A0~A23 RD IDLE2 Figure 2-7 Timing Chart for IDLE2 Mode Halt State Cleared by Interrupt Page 23 2007-10-10 TMP91FU62 2. IDLE1 mode In IDLE1 mode, only the internal oscillator and the RTC continue to operate. The system clock in the MCU stops. In the halt state, the interrupt request is sampled asynchronously with the system clock; however, clearance of the Halt state (e.g., restart of operation) is synchronous with it. Figure 2-8 illustrates the timing for clearance of the IDLE1 mode halt state by an interrupt. X1 A0A23 RD IDLE1 mode Figure 2-8 Timing Chart for IDLE1 Mode Halt State Cleared by Interrupt Page 24 2007-10-10 TMP91FU62 3. STOP mode When STOP mode is selected, all internal circuits stop, including the internal oscillator. Pin status in STOP mode depends on the settings in the SYSCR2 X1 A0A23 RD STOP Figure 2-9 Timing Chart for STOP Mode Halt State Cleared by Interrupt Table 2-8 Sample Warm-up Times after Clearance of STOP Mode SYSCR0 Note: fOSCH=20MHz, fs=32.768kHz Page 25 2007-10-10 TMP91FU62 Example: "The STOP mode is entered when the low-frequency operates, and high-frequency operates after releasing due to INT0. SYSCR0 SYSCR1 SYSCR2 8FFDH 9000H 9002H 9005H INT0 EQU EQU EQU LD LD LD HALT 00E0H 00E1H 00E2H (SYSCR1), 08H (SYSCR2), X-1001X1B (SYSCR0), 011000 - -B ; ; ; fSYS = fs/2 214/fOSCH INT0 9006H LD -: No change XX, XX RETI Note:When different modes are used before and after STOP mode as the above mentioned, there is possible to release the HALT mode without changing the operation mode by acceptance of the halt release interrupt request during execution of "HALT" instruction (during 6 state). In the system which accepts the interrupts during execution "HALT" instruction, set the same operation mode before and after the STOP mode. Page 26 2007-10-10 TMP91FU62 Table 2-9 Input/output Buffer State Table Port Name P00-07 Input / Output input mode output mode input mode output mode input mode output mode input mode output mode input mode output mode analog input input mode output mode analog input input mode output mode input mode output mode input mode output mode input mode output mode input mode output mode input mode output mode input input input output PU* PU* input input input "H" level output output output output PU* output output output input output input output output output output output input input "H" level output P10-17 P30-33 P40-43 P50-57 P60-67 P70-74 P75 P80-87 P90-97 PA0-A3 PB0-B2 RESET AM0,AM1 X1 X2 -: Input for input mode / input pins is invalid; output mode / output pin is at high impedance. input: Input gate in operation. Fix input voltage to "L" or "H" so that input pin stays constant. output: Output state PU*: Programmable pull-up pin. Input gate disable state. No through current even if the pin is set high impedance. Page 27 2007-10-10 TMP91FU62 3. Interrupts Interrupts are controlled by the CPU interrupt mask register SR * Interrupts generated by CPU: 9 sources (Software interrupts, illegal instruction interrupt) * Interrupts on external pins ( INT0 to INT8): 9 sources * Internal interrupts: 30 sources A (fixed) individual interrupt vector number is assigned to each interrupt. One of six (Variable) priority level can be assigned to each maskable interrupt. The priority level of non-maskable interrupts are fixed at 7 as the highest level. When an interrupt is generated, the interrupt controller sends the priority of that interrupt to the CPU. If multiple interrupts are generated simultaneously, the interrupt controller sends the interrupt with the highest priority to the CPU. (The highest priority is level 7 using for non-maskable interrupts.) The CPU compares the priority level of the interrupt with the value of the CPU interrupt mask register Page 28 2007-10-10 TMP91FU62 Interrupt processing Interrupt specified by micro DMA start vector? Yes Micro DMA soft start request Clear interrupt request flag No Interrupt vector value "V" read Interrupt request F/F clear General-purpose interrupt processing Data transfer by micro DMA PUSH PUSH SR PC SR Level of accepted interrupt + 1 INTNEST + 1 Count Count - 1 Micro DMA processing PC (FFFF00H + V) Yes Count = 0 No Clear vector register generating micro DMA transfer and interrupt (INTTC0 to INTTC3) Interrupt processing program RETI instruction POP SR POP PC INTNEST - 1 INTNEST End Figure 3-1 Overall Interrupt Processing Flow Page 29 2007-10-10 TMP91FU62 3.1 General-purpose Interrupt Processing When the CPU accepts an interrupt, it usually performs the following sequence of operations. That is also the same as TLCS-900/L and TLCS-900/H. 1. The CPU reads the interrupt vector from the interrupt controller. If the same level interrupts occur simultaneously, the interrupt controller generates an interrupt vector in accordance with the default priority and clears the interrupt request. (The default priority is already fixed for each interrupt. The smaller vector value has the higher priority level.) 2. The CPU pushes the value of program counter (PC) and status register (SR) onto the stack area (Indicated by XSP). 3. The CPU sets the value which is the priority level of the accepted interrupt plus 1 (+1) to the interrupt mask register Page 30 2007-10-10 TMP91FU62 Table 3-1 TMP91FU62 Interrupt Vectors Table(1/2) Default Priority 1 2 3 4 5 6 7 8 9 10 - 11 12 13 14 15 16 17 18 19 20 21 22 23 Maskable 24 25 26 27 28 29 30 31 32 33 34 35 36 37 (Reserved) (Reserved) INTTA4: 8-bit timer 4 INTTA5: 8-bit timer 5 INTTB00: 16-bit timer 0 (TB0RG0) INTTB01: 16-bit timer 0 (TB0RG1) INTTB10: 16-bit timer 1 (TB1RG0) INTTB11: 16-bit timer 1 (TB1RG1) INTTB20: 16-bit timer 2 (TB2RG0) INTTB21: 16-bit timer 2 (TB2RG1) INTTB30: 16-bit timer 3 (TB3RG0) INTTB31: 16-bit timer 3 (TB3RG1) (Reserved) (Reserved) 005CH 0060H 0064H 0068H 006CH 0070H 0074H 0078H 007CH 0080H 0084H 0088H 008CH 0090H FFFF5CH FFFF60H FFFF64H FFFF68H FFFF6CH FFFF70H FFFF74H FFFF78H FFFF7CH FFFF80H FFFF84H FFFF88H FFFF8CH FFFF90H 17H 18H 19H 1AH 1BH 1CH 1DH 1EH 1FH 20H 21H 22H 23H 24H Nonmaskable Type Interrupt Source and Source of Micro DMA Request "Reset" or "SWI 0" instruction "SWI 1" instruction INTUNDEF: Illegal instruction or "SWI 2" instruction "SWI 3" instruction "SWI 4" instruction "SWI 5" instruction "SWI 6" instruction "SWI 7" instruction (Reserved) INTWD: Watchdog timer Micro DMA (MDMA) INT0: INT0 pin INT1: INT1 pin INT2: INT2 pin INT3: INT3 pin INT4: INT4 pin INT5: INT5 pin INT6: INT6 pin INT7: INT7 pin INT8: INT8 pin (Reserved) (Reserved) INTTA0: 8-bit timer 0 INTTA1: 8-bit timer 1 Vector Value (V) 0000H 0004H 0008H 000CH 0010H 0014H 0018H 001CH 0020H 0024H - 0028H 002CH 0030H 0034H 0038H 003CH 0040H 0044H 0048H 004CH 0050H 0054H 0058H Vector Reference Address FFFF00H FFFF04H FFFF08H FFFF0CH FFFF10H FFFF14H FFFF18H FFFF1CH FFFF20H FFFF24H - FFFF28H FFFF2CH FFFF30H FFFF34H FFFF38H FFFF3CH FFFF40H FFFF44H FFFF48H FFFF4CH FFFF50H FFFF54H FFFF58H Micro DMA Start Vector - - - - - - - - - - - 0AH 0BH 0CH 0DH 0EH 0FH 10H 11H 12H 13H 14H 15H 16H Page 31 2007-10-10 TMP91FU62 Table 3-1 TMP91FU62 Interrupt Vectors Table(2/2) Default Priority 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 Maskable Type Interrupt Source and Source of Micro DMA Request INTTBOF0: 16-bit timer 0 (Over flow) INTTBOF1: 16-bit timer 1 (Over flow) INTTBOF2: 16-bit timer 2 (Over flow) INTTBOF3: 16-bit timer 3 (Over flow) (Reserved) INTRX0:Serial reception (Channel 0) INTTX0:Serial transmission (Channel 0) INTRX1:Serial reception (Channel 1) INTTX1:Serial transmission (Channel 1) INTRX2:Serial reception (Channel 2) INTTX2:Serial transmission (Channel 2) INTSBI0:Serial bus interface interrupt (Channel 0) (Reserved) INTRTC: Interrupt for special timer for CLOCK INTAD: AD conversion end INTTC0 Micro DMA end (Channel 0) INTTC1: Micro DMA end (Channel 1) INTTC2: Micro DMA end (Channel 2) INTTC3: Micro DMA end (Channel 3) (Reserved) : (Reserved) Vector Value (V) 0094H 0098H 009CH 00A0H 00A4H 00A8H 00ACH 00B0H 00B4H 00B8H 00BCH 00C0H 00C4H 00C8H 00CCH 00D0H 00D4H 00D8H 00DCH 00E0H : 00FCH Vector Reference Address FFFF94H FFFF98H FFFF9CH FFFFA0H FFFFA4H FFFFA8H FFFFACH FFFFB0H FFFFB4H FFFFB8H FFFFBCH FFFFC0H FFFFC4H FFFFC8H FFFFCCH FFFFD0H FFFFD4H FFFFD8H FFFFDCH FFFFE0H : FFFFFCH Micro DMA Start Vector 25H 26H 27H 28H 29H 2AH 2BH 2CH 2DH 2EH 2FH 30H 31H 32H 33H - - - - - : - Note: Micro DMA default priority: Micro DMA stands up prior to other maskable interrupt. Page 32 2007-10-10 TMP91FU62 3.2 Micro DMA Processing In addition to general-purpose interrupt processing, the TMP91FU62 supports a micro DMA function. Interrupt requests set by micro DMA perform micro DMA processing at the highest priority level (Level 6) among maskable interrupts, regardless of the priority level of the particular interrupt source. The micro DMA has 4 channels and is possible continuous transmission by specifying the described later burst mode. The micro DMA has 4 channels and is possible continuous transmission by specifying the described later burst mode. Because the micro DMA function has been implemented with the cooperative operation of CPU, when CPU goes to a standby mode (STOP, IDLE1 and IDLE2) by HALT instruction, the requirement of micro DMA will be ignored (Pending) and DMA transfer is started after release HALT. 3.2.1 Micro DMA Operation When an interrupt request specified by the micro DMA start vector register is generated, the micro DMA triggers a micro DMA request to the CPU at interrupt priority level 6 and starts processing the request in spite of any interrupt source's level. The micro DMA is ignored on Note:If the priority level of micro DMA is set higher than that of other interrupts, CPU operates as follows. In case INTxxx interrupt is generated first and then INTyyy interrupt is generated between checking "Interrupt specified by micro DMA start vector" (in the Figure 3-1) and reading interrupt vector with setting below, the vector shifts to that of INTyyy at the time. This is because the priority level of INTyyy is higher than that of INTxxx. In the interrupt routine, CPU reads the vector of INTyyy because checking of micro DMA has been finished. And INTyyy is generated regardless of transfer counter of micro DMA. INTxxx: level 1 without micro DMA INTyyy: level 6 with micro DMA Page 33 2007-10-10 TMP91FU62 Three micro DMA transfer modes are supported: 1-byte transfer, 2-byte (One-word) transfer, and 4-byte transfer. After a transfer in any mode, the transfer source/destination addresses are increased, decreased, or remain unchanged. This simplifies the transfer of data from I/O to memory, from memory to I/O, and from I/O to I/O. For details of the transfer modes, see" 3.2.4 Detailed Description of the Transfer Mode Register ". As the transfer counter is a 16-bit counter, micro DMA processing can be set for up to 65536 times per interrupt source. (The micro DMA processing count is maximized when the transfer counter initial value is set to 0000H.) Micro DMA processing can be started by the 42 interrupts shown in the micro DMA start vectors of Table 31 and by the micro DMA soft start, making a total of 43 interrupts. Figure 3-2 shows the word transfer micro DMA cycle in transfer destination address INC mode (except for counter mode, the same as for other modes). (The conditions for this cycle are based on an external 16-bit bus, 0 waits, transfer source/transfer destination addresses both even-numberd values). 1 state DM1 DM2 DM3 DM4 (Note 1) DM5 DM6 (Note 2) DM7 DM8 X1 Transfer destination address A0 to A23 Transfer source address RD WR, HWR D0 to D15 Input Output Figure 3-2 Timing for Micro DMA Cycle States 1 to 3: Instruction fetch cycle (Gets next address code). If 3 bytes and more instruction codes are inserted in the instruction queue buffer, this cycle becomes a dummy cycle. States 4 to 5: Micro DMA read cycle State 6: Dummy cycle (The address bus remains unchanged from state 5.) States 7 to 8: Micro DMA write cycle Note 1: If the source address area is an 8-bit bus, it is increased by two states. If the source address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. Note 2: If the destination address area is an 8-bit bus, it is increased by two states. If the destination address area is a 16-bit bus and the address starts from an odd number, it is increased by two states. Page 34 2007-10-10 TMP91FU62 3.2.2 Soft Start Function In addition to starting the micro DMA function by interrupts, TMP91FU62 includes a micro DMA software start function that starts micro DMA on the generation of the write cycle to the DMAR register. Writing "1" to each bit of DMAR register causes micro DMA once (If write "0" to each bit, micro DMA doesn't operate) At the end of transfer, the corresponding bit of the DMAR register is automatically cleared to "0". Only one-channel can be set once for micro DMA. (Do not write "1" to plural bits.) When writing again "1" to the DMAR register, check whether the bit is "0" before writing "1". If read "1", micro DMA transfer isn't started yet. When a burst is specified by DMAB register, data is continuously transferred until the value in the micro DMA transfer counter is "0" after start up of the micro DMA. If execute soft start during micro DMA transfer by interrupt source, micro DMA transfer counter doesn't change. Don't use Read-modify-write instruction to avoid writing to other bits by mistake. Symbol Name Address 89H 7 - - - 6 - - - 5 - - - 4 - - - 3 DMAR3 2 DMAR2 R/W 1 DMAR1 0 DMAR0 DMAR DMA Request Register RMW instructions are prohibited. 0 0 0 0 DMA request 3.2.3 Transfer Control Registers The transfer source address and the transfer destination address are set in the following registers in CPU. Data setting for these registers is done by an "LDC cr, r" instruction. Channel 0 DMAS0 DMAD0 DMAC0 DMAM0 DMA source address register 0: Only use LSB 24 bits DMA destination address register 0: Only use LSB 24 bits DMA counter register 0: 1 to 65536 DMA mode register 0 Channel 3 DMAS3 DMAD3 DMAC3 DMAM3 DMA source address register 3 DMA destination address register 3 DMA counter register 3 DMA mode register 3 8 bits 16 bits 32 bits Page 35 2007-10-10 TMP91FU62 3.2.4 Detailed Description of the Transfer Mode Register (DMAM0 to DMAM3) 0 0 0 Mode Note: The upper three bit of data programmed to these registers must always be 0. Execution time ZZ: 0 = Byte transfer, 1 = Word transfer, 2 = 4-byte transfer, 3 = Reserved Transfer destination address INC modeI/O to memory (DMADn+) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Transfer destination address DEC mode I/O to memory (DMADn-) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Transfer source address INT modememory to I/O (DMADn) (DMASn+) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Transfer source address DEC mode memory to I/O (DMADn) (DMASn-) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Address fixed modeI/O to I/O (DMADn) (DMASn) DMACn DMACn - 1 if DMACn = 0 then INTTC is generated Counter mode for counting number of times interrupt is generated DMASn DMASn + 1 DMACn DMACn - 1 if DMACn = 0 then INTTC is generated 8 states (800 ns) @ byte/word transfer 12 states (1200 ns) @ 4-byte/word transfer 8 states (800 ns) @ byte/word transfer 12 states (1200 ns) @ 4-byte/word transfer 8 states (800 ns) @ byte/word transfer 12 states (1200 ns) @ 4-byte/word transfer 8 states (800 ns) @ byte/word transfer 12 states (1200 ns) @ 4-byte/word transfer 8 states (800 ns) @ byte/word transfer 12 states (1200 ns) @ 4-byte/word transfer 5 states (500 ns) 0 0 0 Z Z 0 0 1 Z Z 0 1 0 Z Z 0 1 1 Z Z 1 0 0 Z Z 1 0 1 0 0 Note 1: "n" is the corresponding micro DMA channels 0 to 3. DMADn+/DMASn+: Post-increment (Increment register value after transfer) DMADn-/DMASn-: Post-decrement (Decrement register value after transfer) The I/Os in the table mean fixed address and the memory means increment (INC) or decrement (DEC) addresses. Note 2: Execution time is under the condition of: 16-bit bus width (Both transfer and destination address area)/0 waits/ fc = 20 MHz/selected high-frequency mode (fc x 1) Note 3: Do not use an undefined code for the transfer mode register except for the defined codes listed in the above table. Page 36 2007-10-10 TMP91FU62 3.3 Interrupt Controller Operation The block diagram in Figure 3-3 shows the interrupt circuits. The left-hand side of the diagram shows the interrupt controller circuit. The right-hand side shows the CPU interrupt request signal circuit and the halt release circuit. For interrupt controller there is an interrupt request flag (Consisting of a flip-flop), an interrupt priority setting register and a micro DMA start vector register. The interrupt request flag latches interrupt requests from the peripherals. The flag is cleared to 0 in the following cases: * When reset occurs * When the CPU reads the channel vector after accepted its interrupt * When executing an instruction that clears the interrupt (Write DMA start vector to INTCLR register) * When the CPU receives a micro DMA request (when micro DMA is set) * When the micro DMA burst transfer is terminated An interrupt priority can be set independently for each interrupt source by writing the priority to the interrupt priority setting register (e.g., INTE0AD or INTE56). 6 interrupt priorities levels (1 to 6) are provided. Setting an interrupt source's priority level to 0 (or 7) disables interrupt requests from that source. The priority of non-maskable interrupts (watchdog timer interrupts) is fixed at 7. If interrupt request with the same level are generated at the same time, the default priority is used to determine which interrupt request is accepted first. The 3rd and 7th bits of the interrupt priority setting register indicate the state of the interrupt request flag and thus whether an interrupt request for a given channel has occurred. The interrupt controller sends the interrupt request and its vector address to the CPU. The CPU compares the priority value Page 37 2007-10-10 Interrupt controller CPU Interrupt request F/F RESET Interrupt vector read V = 20H V = 24H S R IFF2:0 Interrupt request signal to CPU 3 3 INTRQ2 to INTRQ0 3 Priority encoder 1 7 6 6 RESET EI 1 to 7 DI Q 1 Interrupt mask F/F INTWD Decoder Priority setting register Dn Dn+1 Dn+2 A B C Interrupt level detect D0 D1 D2 D3 D4 D5 D6 D7 Interrupt vector read If INTRQ2 to 0 then 1. IFF2 to 0 DQ CLR Interrupt request F/F Y1 Y2 Y3 Y4 Y5 Y6 Dn+3 1 2 Highest A priority 3 interrupt B 4 level C select 5 6 7 48 Interrupt request signal INT0 Interrupt request F/F RESET S R Q Interrupt vector read Micro DMA acknowledge V = 28H V = 2CH V = 30H V=3 34H V = 38H V = 3CH Interrupt vector generator Figure 3-3 Block Diagram of Interrupt Controller V = 40H V = 44H V = 48H V = CCH V = D0H V = D4H V = D8H V = DCH Page 38 Software start 4 4 input OR INT1 INT2 INT3 INT4 INT5 INT6 INT7 INT8 During IDLE1 During STOP Halt release RESET INT0, INTRTC Micro DMA counter zero interrupt INTAD INTTC0 INTTC1 INTTC2 INTTC3 Micro DMA request If IFF = 7 then 0 S Selector Micro DMA start vector setting register D5 D4 D3 42 DQ D2 D1 6 CLR D0 A B Micro DMA channel priority encoder 2 2 Micro DMA channel specification TMP91FU62 2007-10-10 INTTC0 DMA0V DMA1V DMA2V DMA3V RESET 0 1 2 3 TMP91FU62 3.3.1 Interrupt Level Setting Registers Interrupt Level Setting Registers Symbol Name Address 7 6 INTAD INTE0AD INT0 & INTAD enable IADC 90H R 0 0 INT2 INTE12 INT1 & INT2 enable I2C 91H R 0 0 INT4 INTE34 INT3 & INT4 enable I4C 92H R 0 0 INT6 INTE56 INT5 & INT6 enable I6C 93H R 0 0 INT8 INTE78 INT7 & INT8 enable I8C 94H R 0 0 R/W 0 0 R 0 0 R/W 0 0 I8M2 I8M1 I8M0 I7C I7M2 R/W 0 0 R 0 0 INT7 I7M1 I7M0 R/W 0 0 I6M2 I6M1 I6M0 I5C I5M2 R/W 0 0 R 0 0 INT5 I5M1 I5M0 R/W 0 0 I4M2 I4M1 I4M0 I3C I3M2 R/W 0 0 R 0 0 INT3 I3M1 I3M0 R/W 0 0 I2M2 I2M1 I2M0 I1C I1M2 R/W 0 0 R 0 0 INT1 I1M1 I1M0 R/W 0 0 IADM2 IADM1 IADM0 I0C I0M2 5 4 3 2 INT0 I0M1 I0M0 1 0 INTTA1(TMRA1) INTETA01 INTTA0 & INTTA1 enable ITA1C 96H R 0 0 R/W 0 0 R 0 ITA1M2 ITA1M1 ITA1M0 ITA0C INTTA0 (TMRA0) ITA0M2 ITA0M1 R/W 0 0 0 ITA0M0 IxxxC Interrupt request flag IxxM2 0 0 0 0 1 1 1 1 IxxM1 0 0 1 1 0 0 1 1 IxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests Page 39 2007-10-10 TMP91FU62 Interrupt Level Setting Registers Symbol Name Address 7 6 5 4 3 2 1 0 INTTA5 (TMRA5) INTETA45 INTTA4 & INTTA5 enable ITA5C 98H R 0 0 R/W 0 0 R 0 ITA5M2 ITA5M1 ITA5M0 ITA4C INTTA4 (TMRA4) ITA4M2 ITA4M1 R/W 0 0 0 ITA4M0 INTTB01(TMRB0) INTETB0 Interrupt enable TMRB0 ITB01C 99H R 0 0 R/W 0 0 R 0 ITB01M2 ITB01M1 ITB01M0 ITB00C INTTB00(TMRB0) ITB00M2 ITB00M1 R/W 0 0 0 ITB00M0 INTTB11(TMRB1) INTETB1 Interrupt enable TMRB1 ITB11C 9AH R 0 0 R/W 0 0 R 0 ITB11M2 ITB11M1 ITB11M0 ITB10C INTTB10(TMRB1) ITB10M2 ITB10M1 R/W 0 0 0 ITB10M0 INTTB21(TMRB2) INTETB2 Interrupt enable TMRB2 ITB21C 9BH R 0 0 R/W 0 0 R 0 ITB21M2 ITB21M1 ITB21M0 ITB20C INTTB20(TMRB2) ITB20M2 ITB20M1 R/W 0 0 0 ITB20M0 INTTB31(TMRB3) INTETB3 Interrupt enable TMRB3 ITB31C 9CH R 0 Interrupt enable TMRB0/1 (Over flow) 0 R/W 0 0 R 0 ITB31M2 ITB31M1 ITB31M0 ITB30C INTTB30(TMRB3) ITB30M2 ITB30M1 R/W 0 0 0 ITB30M0 INTTBOF1(TMRB1 Over flow) ITF1C 9EH R 0 0 R/W 0 0 R 0 ITF1M2 ITF1M1 ITF1M0 ITF0C INTETB01V INTTBOF0(TMRB0 Over flow) ITF0M2 ITF0M1 R/W 0 0 0 ITF0M0 IxxxC Interrupt request flag IxxM2 0 0 0 0 1 1 1 1 IxxM1 0 0 1 1 0 0 1 1 IxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests Page 40 2007-10-10 TMP91FU62 Interrupt Level Setting Registers Symbol Name Interrupt enable TMRB2/3 (Over flow) Address 7 6 5 4 3 2 1 0 INTTBOF3(TMRB3 Over flow) ITF3C 9FH R 0 0 INTRTC INTERTC Interrupt enable INTRTC IRTCC A0H R 0 0 INTTX0 INTES0 INTRX0 & INTTX0 enable ITX0C A1H R 0 0 INTTX1 INTES1 INTRX1 & INTTX1 enable ITX1C A2H R 0 0 INTTX2 INTES2 INTRX2 & INTTX2 enable ITX2C A3H R 0 0 - INTESBI0 INTSBI0 enable - A4H - - - INTTC1 INTETC01 INTTC0 & INTTC1 enable ITC1C A5H R 0 0 INTTC3 INTETC23 INTTC2 & INTTC3 enable ITC3C A6H R 0 0 R/W 0 0 R 0 ITC3M2 ITC3M1 ITC3M0 ITC2C R/W 0 0 R 0 ITC1M2 ITC1M1 ITC1M0 ITC0C - - - R 0 - - - ISBI0C R/W 0 0 R 0 ITX2M2 ITX2M1 ITX2M0 IRX2C R/W 0 0 R 0 ITX1M2 ITX1M1 ITX1M0 IRX1C R/W 0 0 R 0 ITX0M2 ITX0M1 ITX0M0 IRX0C R/W 0 0 - - IRTCM2 IRTCM1 IRTCM0 - R/W 0 0 R 0 ITF3M2 ITF3M1 ITF3M0 ITF2C INTETB23V INTTBOF2(TMRB2 Over flow) ITF2M2 ITF2M1 R/W 0 - - - - - INTRX0 IRX0M2 IRX0M1 R/W 0 INTRX1 IRX1M2 IRX1M1 R/W 0 INTRX2 IRX2M2 IRX2M1 R/W 0 INTSBI0 ISBI0M2 ISBI0M1 R/W 0 INTTC0 ITC0M2 ITC0M1 R/W 0 INTTC2 ITC2M2 ITC2M1 R/W 0 0 0 ITC2M0 0 0 ITC0M0 0 0 ISBI0M0 0 0 IRX2M0 0 0 IRX1M0 0 0 IRX0M0 - - - 0 0 ITF2M0 IxxxC Interrupt request flag IxxM2 0 0 0 0 1 1 1 1 IxxM1 0 0 1 1 0 0 1 1 IxxM0 0 1 0 1 0 1 0 1 Function (Write) Disables interrupt requests Sets interrupt priority level to 1 Sets interrupt priority level to 2 Sets interrupt priority level to 3 Sets interrupt priority level to 4 Sets interrupt priority level to 5 Sets interrupt priority level to 6 Disables interrupt requests Page 41 2007-10-10 TMP91FU62 3.3.2 External Interrupt Control External Interrupt Control Register (IIMC) Symbol Name Address 7 - 8CH 0 RMW instructions are prohibited. 0 0 0 6 - 5 - 4 - W 0 0 INT0 EDGE 0: Rising 1: Falling 0 INT0 mode 0: Edge 1: Level 0 3 - 2 I0EDGE 1 I0LE 0 - IIMC Interrupt input mode control Always write "0". - - - - - INT0 setting P7FC 3.3.3 Interrupt Request Flag Clear Register The interrupt request flag is cleared by writing the appropriate micro DMA start vector, as given in Table 31, to the register INTCLR. For example, to clear the interrupt flag INT0, perform the following register operation after execution of the DI instruction. INTCLR 0AH: Clears interrupt request flag INT0. Interrupt Request Flag Clear Register (INTCLR) Symbol Name Address 88H Interrupt Clear Control RMW instructions are prohibited. 7 - - - 6 - - - 0 0 0 5 CLRV5 4 CLRV4 3 CLRV3 W 0 0 0 2 CLRV2 1 CLRV1 0 CLRV0 INTCLR Interrupt vector Page 42 2007-10-10 TMP91FU62 3.3.4 Micro DMA Start Vector Registers This register assigns micro DMA processing to which interrupt source. The interrupt source with a micro DMA start vector that matches the vector set in this register is assigned as the micro DMA start source. When the micro DMA transfer counter value reaches 0, the micro DMA transfer end interrupt corresponding to the channel is sent to the interrupt controller, the micro DMA start vector register is cleared, and the micro DMA start source for the channel is cleared. Therefore, to continue micro DMA processing, set the micro DMA start vector register again during the processing of the micro DMA transfer end interrupt. If the same vector is set in the micro DMA start vector registers of more than one channel, the channel with the lowest number has a higher priority. Accordingly, if the same vector is set in the micro DMA start vector registers of two channels, the interrupt generated in the channel with the lower number is executed until micro DMA transfer is complete. If the micro DMA start vector for this channel is not set again, the next micro DMA is started for the channel with the higher number. (Micro DMA chaining) Micro DMA Start Vector Registers (DMAnV) Symbol Name Address 7 - DMA0 Start Vector - 80H - - 0 0 0 0 0 0 6 - - 5 DMA0V5 4 DMA0V4 3 DMA0V3 R/W 2 DMA0V2 1 DMA0V1 0 DMA0V0 DMA0V DMA0 start vector - DMA1 Start Vector - 81H - - 0 0 0 0 0 0 - - DMA1V5 DMA1V4 DMA1V3 R/W DMA1V2 DMA1V1 DMA1V0 DMA1V DMA1 start vector - DMA2 Start Vector - 82H - - 0 0 0 0 0 0 - - DMA2V5 DMA2V4 DMA2V3 R/W DMA2V2 DMA2V1 DMA2V0 DMA2V DMA2 start vector - DMA3 Start Vector - 83H - - 0 0 0 0 0 0 - - DMA3V5 DMA3V4 DMA3V3 R/W DMA3V2 DMA3V1 DMA3V0 DMA3V DMA3 start vector Page 43 2007-10-10 TMP91FU62 3.3.5 Micro DMA Burst Specification Specifying the micro DMA burst continues the micro DMA transfer until the transfer counter register reaches 0 after micro DMA start. Setting a bit which corresponds to the micro DMA channel of the DMAB registers mentioned below to "1" specifies a burst. If other interrupts (maskable/nonmaskable is not concerned) are generated during burst transfer, interrupt is executed after completed burst transfer. Micro DMA Burst Request Registers (DMAR) Symbol Name Address 89H DMA Software Request Register RMW instructions are prohibited. 7 - - - 6 - - - 5 - - - 4 - - - 0 0 3 DMAR3 2 DMAR2 R/W 0 0 1 DMAR1 0 DMAR0 DMAR 1: DMA software request - - - - - - - - - - 0 0 DMAB3 DMAB2 R/W 0 0 DMAB1 DMAB0 DMAB DMA Burst Register - 8AH - 1: DMA burst request Page 44 2007-10-10 TMP91FU62 3.3.6 Attention Point The instruction execution unit and the bus interface unit of this CPU operate independently. Therefore, immediately before an interrupt is generated, if the CPU fetches an instruction that clears the corresponding interrupt request flag, the CPU may execute the instruction that clears the interrupt request flag (Note) between accepting and reading the interrupt vector. In this case, the CPU reads the default vector 0008H and reads the interrupt vector address FFFF08H. To avoid the above problem, place instructions that clear interrupt request flags after a DI instruction. And in the case of setting an interrupt enable again by EI instruction after the execution of clearing instruction, execute EI instruction after clearing and more than 1-instructions (ex. "NOP" * 1 times). If executed EI instruction without waiting NOP instruction after execution of clearing instruction, interrupt will be enable before request flag is cleared. In the case of changing the value of the interrupt mask register In level mode INT0 is not an edge-triggered interrupt. Hence, in level mode the interrupt request flip-flop for INT0 does not function. The peripheral interrupt request passes through the S input of the flip-flop and becomes the Q output. If the interrupt input mode is changed from edge mode to level mode, the interrupt request flag is cleared automatically. If the CPU enters the interrupt response sequence as a result of INT0 going from 0 to 1, INT0 must then be held at 1 until the interrupt response sequence has been completed. If INT0 is set to level mode so as to release a halt state, INT0 must be held at 1 from the time INT0 changes from 0 to 1 until the halt state is released. (Hence, it is necessary to ensure that input noise is not interpreted as a 0, causing INT0 to revert to 0 before the halt state has been released.) When the mode changes from level mode to edge mode, interrupt request flags which were set in level mode will not be cleared. Interrupt request flags must be cleared using the following sequence. DI LD (IIMC), 00H ; Switches interrupt input mode from level mode to edge mode. LD (INTCLR), 0AH ; Clears interrupt request flag. NOP ; Wait EI instruction EI The interrupt request flip-flop can only be cleared by reset or by reading the serial channel receive buffer. It cannot be cleared by writing INTCLR register. INT0 level mode INTRXn Note: The following instructions or pin input state changes are equivalent to instructions that clear the interrupt request flag. INT0: Instructions which switch to level mode after an interrupt request has been generated in edge mode. The pin input change from high to low after interrupt request has been generated in level mode. (H L) INTRXn: Instruction which reads the receive buffer. Page 45 2007-10-10 TMP91FU62 4. Port Function The TMP91FU62 features 69 bit settings which relate to the various I/O ports. As well as general-purpose I/O port functionality, the port pins also have I/O functions which relate to the built-in CPU and internal I/Os. Table 4-1 lists the functions of each port pin. Table 4-1 lists the functions of each port pin. Table 4-2 lists I/O registers and their specifications. Table 4-1 Port Functions (R: PU = with programmable pull-up resistor) (1/2) Port Names Port0 Port1 Pin Names P00 to P07 P10 to P17 P30 P31 Port3 P32 P33 P40 P41 Port4 P42 P43 P50 P51 P52 P53 Port5 P54 P55 P56 P57 P60 P61 P62 P63 Port6 P64 P65 P66 P67 P70 P71 P72 Port7 P73 P74 P75 1 1 1 I/O I/O I/O 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O PU PU Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit TA4IN TA5OUT INT0 RXD2, TXD2 SCLK2, CTS2 AN0 AN1 AN2 AN3 AN4 AN5 AN6 AN7 AN8 AN9 AN10 AN11 AN12 AN13 AN14 AN15 TA0IN TA1OUT 1 1 1 1 I/O I/O I/O I/O Number of Pins 8 8 1 1 Direction I/O I/O I/O I/O R Direction Setting Unit Bit Bit Bit Bit Bit Bit Bit Bit TB3IN0, INT3, SDA0 TB3IN1, INT4, SCL0 TB3OUT0 TB3OUT1 SCOUT TXD2, RXD2 Pin Names for Built-in Functions - - - - - - PU PU - - - - - - - - - - - - - - - - - - - - - - Page 46 2007-10-10 TMP91FU62 Table 4-1 Port Functions (R: PU = with programmable pull-up resistor) (2/2) Port Names Pin Names P80 P81 P82 P83 Port8 P84 P85 P86 P87 P90 P91 P92 P93 Port9 P94 P95 P96 P97 PA0 PA1 PortA PA2 PA3 PB0 PortB PB1 PB2 1 1 1 1 1 I/O I/O I/O I/O I/O 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O 1 1 1 1 1 1 1 1 I/O I/O I/O I/O I/O I/O I/O I/O Number of Pins 1 1 1 1 Direction I/O I/O I/O I/O R Direction Setting Unit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Bit Pin Names for Built-in Functions TB0IN0, INT5 TB0IN1, INT6 TB0OUT0 TB0OUT1 TB1IN0, INT7 TB1IN1, INT8 TB1OUT0 TB1OUT1 TXD0, RXD0 RXD0, TXD0 SCLK0, CTS0 TXD1, RXD1 RXD1, TXD1 SCLK1, CTS1 XT1 XT2 TB2IN0, INT1 TB2IN1, INT2 TB2OUT0 TB2OUT1 - - - - - - - - - - - - - - - - - - - - - - - Page 47 2007-10-10 TMP91FU62 Table 4-2 Ports I/O Port Setting List(1/3) I/O Register Setting Values Pin Names Specifications Pn Input port PnCR 0 None 1 0 None 1 0 1 1 0 1 0 1 1 0 1 1 1 1 0 0 1 0 0 1 1 0 0 1 1 1 1 0 0 1 0 0 1 0 0 1 0 0 0 0 0 None 0 1 0 0 1 0 0 1 None 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 1 0 0 None None None None 1 1 1 None 0 1 0 None None 0 1 None None None 0 0 0 0 0 0 0 None None 0 1 1 0 1 1 None 0 0 0 None None None None PnFC PnFC2 ODE Port0 P00 to P07 Output port Input port x x x x x x x x x x x #1 Port1 P10 to P17 Output port Input port P30 to P31 Output port (CMOS output) Output port (open drain output) Input port P32 to P33 Output port TB3IN0 Input, INT3 Input - 0 1 - 0 1 Port3 P30 SDA0 input/output (CMOS output) SDA0 input/output (open drain output) TB3IN1 Input, INT4 Input x x x x x x 0 1 - 0 1 P31 SCL0 input/output (CMOS output) SCL0 input/output (open drain output)#2 P32 P33 TB3OUT0 output TB3OUT1 output Input port (without pull up) P40, P43 Input port (with pull up) Output port Input port (without pull up) Input port (with pull up) x 0 1 - - 0 1 P41 Output port (CMOS output) Output port (open drain output) Input port (without pull up) Port4 P42 Input port (with pull up) Output port P40 SCOUT output TXD2 output (CMOS output) P41 TXD2 output (open drain output)#2 P42 RXD2 Input SCLK2 Input P43 SCLK2 output CTS2 Input Input port Port5 P50 to P57 Output port AN0 to AN7 Input #2 Input port Port6 P60 to P67 Output port AN8 to AN15 Input #3 x x 0 1 x x x x x x x x x x x x x x Page 48 2007-10-10 TMP91FU62 Table 4-2 Ports I/O Port Setting List(2/3) I/O Register Setting Values Pin Names Specifications Pn Input port P70 to P75 Output port P70 TA0IN Input TA1OUT output TA4IN Input TA5OUT output INT0 Input Input port P80 to P87 Output port P80 P81 P82 TB0IN0, INT5 Input TB0IN1, INT6 Input TB0OUT0 output TB0OUT1 output TB1IN0, INT7 Input TB1IN1, INT8 Input TB1OUT0 output TB1OUT1 output PnCR 0 1 0 1 0 1 0 0 1 0 0 1 1 0 0 1 1 PnFC 0 0 None 1 None 1 1 0 0 1 1 1 None 1 1 1 1 1 None None None PnFC2 ODE x x x x x x x x x x x x x x x x x Port7 P71 P73 P74 P75 Port8 P83 P84 P85 P86 P87 Page 49 2007-10-10 TMP91FU62 Table 4-2 Ports I/O Port Setting List(3/3) I/O Register Setting Values Pin Names Specifications Pn P91 to P92, P94 to P95 Input port Output port Input port P90, P93 Output port (CMOS output) Output port (open drain output) TXD0 output (CMOS output) P90 TXD0 output (open drain output)#2 P91 RXD0 Input SCLK0 Input P92 SCLK0 output CTS0 Input TXD1 output (CMOS output) P93 TXD1 output (open drain output)#2 P94 RXD1 Input SCLK1 Input P95 SCLK1 output CTS1 Input Input port P96 to P97 Output port XT1 to XT2 Input port PA0 to PA3 Output port PA0 TB2IN0 Input, INT1 Input TB2IN1 Input, INT2 Input TB2OUT0 TB2OUT1 Input port #3 PnCR 0 1 0 1 1 1 1 0 0 1 0 1 1 0 0 1 0 0 1 0 0 1 0 0 1 1 0 PnFC 0 PnFC2 ODE x x x x x x x x x x x x x x x x x x x x x x x x x x x x None 0 0 0 0 1 1 None 0 1 None 0 1 1 None 0 1 0 1 1 0 0 0 1 None 1 1 1 None None None 0 1 None None - 0 1 0 1 None Port9 PortA PA1 PA2 PA3 PortB PB0 to PB2 Output port None 1 None None #1 #2 #3 If using P30/P31/P41/P90/P93 as open-drain output in SDA0/SCL0/TXD2/TXD0/TXD1 output, please set ODE. If using P50 to P57,P60 to P67 as an analog input, please set ADCCR1 Note: x:Don't care Page 50 2007-10-10 TMP91FU62 4.1 Port 0 (P00 to P07) Port 0 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P0CR. Reset operation initializes all bits of the control register P0CR to "0" and sets port 0 to input port. Reset Direction control (on bit basis) Internal data bus P0CR write Port 0 P00 to P07 Output buffer P0 write S B A P0 read Figure 4-1 Port 0 Port 0 Register 7 Bit symbol P0 (0000H) Read/Write After reset P07 6 P06 5 P05 4 P04 R/W Data from external port (Output latch register is undefined.) 3 P03 2 P02 1 P01 0 P00 Port 0 Control Register (Read-modify-write instructions are prohibited.) 7 6 P06C 5 P05C 4 P04C W 0 0 0 0 0 0 0 0 3 P03C 2 P02C 1 P01C 0 P00C Bit symbol P0CR (0002H) Read/Write After reset Function P07C 0: Input 1: Output P0xC 0 1 P07 function input port output port P06 function input port output port P05 function input port output port P04 function input port output port P03 function input port output port P02 function input port output port P01 function input port output port P00 function input port output port Note: Page 51 2007-10-10 TMP91FU62 4.2 Port 1 (P10 to P17) Port 1 is an 8-bit general-purpose I/O port. Each bit can be set individually for input or output using the control register P1CR. Reset operation initializes all bits of output latch P1, the control register P1CR to "0" and sets port 1 to input port. Reset Direction control (on bit basis) Internal data bus P1CR write Port 1 P10 to P17 Output buffer P1 write S B A P1 read Figure 4-2 Port 1 Page 52 2007-10-10 TMP91FU62 Port 1 Register 7 P1 (0001H) Bit symbol Read/Write After reset P17 6 P16 5 P15 4 P14 R/W Data from external port (Output latch register is cleared to "0".) 3 P13 2 P12 1 P11 0 P10 Port 1 Control Register (Read-modify-write instructions are prohibited.) 7 Bit symbol P1CR (0004H) Read/Write After reset Function 0 0 0 0 P17C 6 P16C 5 P15C 4 P14C W 0 0 0 0 3 P13C 2 P12C 1 P11C 0 P10C 0: Input 1: Output P1xC 0 1 P17 function input port output port P16 function input port output port P15 function input port output port P14 function input port output port P13 function input port output port P12 function input port output port P11 function input port output port P10 function input port output port Note: Page 53 2007-10-10 TMP91FU62 4.3 Port3 (P30 to P33) Port 3 is an 4-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register P3 are set to "1". There are the following functions in addition to an I/O port. This function enable each function by writing "1" to applicable bit of port 3 function register P3FC. *The input function of external interrupt (INT3, INT4) *The input function of 16-bit timer 3 (TB3IN0, TB3IN1) *The output function of 16-bit timer 3 (TB3OUT0, TB3OUT1) *The I/O function of serial bus interface 0 (SDA0, SCL0) Reset operation initializes, P3CR,P3FC and P3FC2 to "0", all bits are set to input port. And Port 30 and 31 have a programmable open-drain function which can be controlled by the ODE register. Direction control (on bit basis) P3CR write Function control 2 (on bit basis) Internal data bus P3FC2 write S A S Open-drain possible: ODE P3 write B P30(TB3IN0,INT3,SDA0) P31(TB3IN1,INT4,SCL0) SDA0 SCL0 Function control (on bit basis) P3FC write SB P3 TB3IN0,INT3 TB3IN1,INT4 SDA0 SCL0 A Figure 4-3 Port 30 and 31 Page 54 2007-10-10 TMP91FU62 Direction control (on bit basis) P3CR Function control (on bit basis) Internal data bus P3FC S A S P32(TB3OUT0) P3 TB3OUT0 B SB P3 A Direction control (on bit basis) P3CR ( ) P3FC write S Internal data bus A S P33(TB3OUT1) P3 TB3OUT1 B SB P3 A Figure 4-4 Port 32 and 33 Page 55 2007-10-10 TMP91FU62 Port 3 Register 7 P3 (000CH) Bit symbol Read/Write After reset Function 6 5 4 3 P33 2 P32 R/W Data from external port (Output latch register is set to "1".) output mode 1 P31 0 P30 - - - - - - - - - - - - - Port 3 Control Register (Read-modify-write instructions are prohibited.) 7 Bit symbol P3CR (000EH) Read/Write After reset Function 6 5 4 3 P33C 2 P32C W 0 0 0 0 1 P31C 0 P30C - - - - - - - - - - - - - 0:Input 1:Output Port 3 Function Register (Read-modify-write instructions are prohibited.) 7 P3FC (000FH) Bit symbol Read/Write After reset 6 5 4 3 P33F 2 P32F W 0 0 0 0 1 P31F 0 P30F - - - - - - - - - - - - Port 3 Function Register 2 (Read-modify-write instructions are prohibited.) 7 P3FC2 (000DH) Bit symbol Read/Write After reset 6 5 4 3 2 1 P31F2 W 0 0 0 P30F2 - - - - - - - - - - - - - - - - - - P3xF2 0 0 0 0 1 1 1 1 P3xF 0 0 1 1 0 0 1 1 P3xC 0 1 0 1 0 1 0 1 P33 function input port output port reserved TB3OUT1 reserved reserved reserved reserved P32 function input port output port reserved TB3OUT0 reserved reserved reserved reserved P31 function input port output port TB3IN1/INT4 reserved reserved SCL0 reserved reserved P30 function input port output port TB3IN0/INT3 reserved reserved SDA0 reserved reserved Note 1: Page 56 2007-10-10 TMP91FU62 4.4 Port 4 (P40 to P43) Port 4 is an 4-bit general-purpose I/O port. Reset operation initializes to input port, and connects a pull-up resistor. All bits of output latch register P4 are set to "1". There are the following functions in addition to an I/O port. This function enable each function by writing "1" to applicable bit of port 4 function register P4FC. *The I/O function of the serial channel 2 (RXD2, TXD2, SCLK2/CTS2) *The output function of a system clock signal (SCOUT) Reset operation initializes, P4CR,P4FC and P4FC2 to "0", all bits are set to input port. And Port 41 have a programmable open-drain function which can be controlled by the ODE register. Reset Direction control (on bit basis) P4CR write Function control 2 (on bit basis) Internal data bus P-ch P4FC2 write (Programmable pull up) Selector Output buffer P4 write P4 read Selector Figure 4-5 Port 40 Page 57 2007-10-10 TMP91FU62 Reset Direction control (on bit basis) P4CR write Function control 2 (on bit basis) P4FC2 write Internal data bus Open-drain possible: ODE (Programmable pull up) SIO exchange 1 SIOCHG1 write P4 write P4 read Selector Figure 4-6 Port 41 Selector Page 58 2007-10-10 TMP91FU62 Reset Direction control (on bit basis) P4CR write Open-drain possible: SIOCHG1 (Programmable pull up) Internal data bus SIO exchang 1 SIOCHG1 write Selector Output buffer P4 write P4 read Selector Figure 4-7 Port 42 Page 59 2007-10-10 TMP91FU62 Reset Direction control (on bit basis) P4CR write Function control 2 (on bit basis) P-ch P4FC2 write (Programmable pull up) Internal data bus Selector Output buffer P4 write P4 read Selector Figure 4-8 Port 43 Page 60 2007-10-10 TMP91FU62 Port 4 Register 7 P4 (0010H) Bit symbol Read/Write After reset 6 5 4 3 P43 2 P42 R/W Data from external port (Output latch register is set to "1".) 0 (Output latch register): Pull-up resistor OFF 1 (Output latch register): Pull-up resistor ON 1 P41 0 P40 - - - - - - - - - - - - Function Port 4 Control Register (Read-modify-write instructions are prohibited.) 7 Bit symbol P4CR (0012H) Read/Write After reset Function 6 5 4 3 P43C 2 P42C W 0 0 0 0 1 P41C 0 P40C - - - - - - - - - - - - 0: Input 1: Output Port 4 Function Register 2 (Read-modify-write instructions are prohibited.) 7 P4FC2 (0011H) Bit symbol Read/Write After reset 6 5 4 3 P43F2 W 0 2 1 P41F2 W 0 0 0 P40F2 - - - - - - - - - - - - - - - P4xF2 P4xC P43 function input port (SCLK2/CTS2) output port reserved SCLK2 P42 function input port (RXD2) output port reserved reserved P41 function input port output port reserved TXD2 P40 function input port output port reserved SCOUT 0 0 1 1 0 1 0 1 Note 1: Page 61 2007-10-10 TMP91FU62 4.5 Port 5 (P50 to P57) Port 5 is an 8-bit general-purpose I/O port. By the reset action, it becomes Hi-Z and becomes analog input permission.All bits of output latch register P5 are set to "1". There are the following functions in addition to an I/O port. *The input function of the Analog/Digital Converter (AN0 to AN7) Reset operation initializes, P5CR,P5FC to "0", all bits are set to input port. Reset Direction control (on bit basis) P5CR write Function control (on bit basis) P5FC write Internal data bus S P5 write P5 read S Port 5 P50 to P57 (AN0 to AN7) B A AD AD read Figure 4-9 Port 5 Page 62 2007-10-10 TMP91FU62 Port 5 Register 7 P5 (0014H) Bit symbol Read/Write After reset P57 6 P56 5 P55 4 P54 R/W Data from external port (Output latch register is set to "1".) 3 P53 2 P52 1 P51 0 P50 Port 5 Control Register (Read-modify-write instructions are prohibited.) 7 Bit symbol P5CR (0016H) Read/Write After reset Function 0 0 0 0 P57C 6 P56C 5 P55C 4 P54C W 0 0 0 0 3 P53C 2 P52C 1 P51C 0 P50C 0: Input 1: Output Port 5 Function Register (Read-modify-write instructions are prohibited.) 7 Bit symbol Read/Write P5FC (0017H) After reset 0 P57 input 0:disable 1:enable 0 P56 input 0:disable 1:enable 0 P55 input 0:disable 1:enable 0 P54 input 0:disable 1:enable P57F 6 P56F 5 P55F 4 P54F W 0 P53 input 0:disable 1:enable 0 P52 input 0:disable 1:enable 0 P51 input 0:disable 1:enable 0 P50 input 0:disable 1:enable 3 P53F 2 P52F 1 P51F 0 P50F Function P5xF 0 0 1 1 P5xC 0 1 0 1 P57 function input disable output port input enable output port P56 function input disable output port input enable output port P55 function input disable output port input enable output port P54 function input disable output port input enable output port P53 function input disable output port input enable output port P52 function input disable output port input enable output port P51 function input disable output port input enable output port P50 function input disable output port input enable output port Note 1: Page 63 2007-10-10 TMP91FU62 4.6 Port 6 (P60 to P67) Port 6 is an 8-bit general-purpose I/O port. By the reset action, it becomes Hi-Z and becomes analog input permission.All bits of output latch register P6 are set to "1". There are the following functions in addition to an I/O port. *The input function of the Analog/Digital Converter (AN8 to AN15) Reset operation initializes, P6CR,P6FC to "0", all bits are set to input port. Reset Direction control (on bit basis) P6CR write Function control (on bit basis) P6FC write Internal data bus S S P6 write P6 read B Port 6 P60 to P67 (AN8 to AN15) A AD AD read Figure 4-10 Port 6 Page 64 2007-10-10 TMP91FU62 Port 6 Register 7 P6 (0018H) Bit symbol Read/Write After reset P67 6 P66 5 P65 4 P64 R/W Data from external port (Output latch register is set to "1".) 3 P63 2 P62 1 P61 0 P60 Port 6 Control Register (Read-modify-write instructions are prohibited.) 7 Bit symbol P6CR (001AH) Read/Write After reset Function 0 0 0 0 P67C 6 P66C 5 P65C 4 P64C W 0 0 0 0 3 P63C 2 P62C 1 P61C 0 P60C 0: Input 1: Output Port 6 Function Register (Read-modify-write instructions are prohibited.) 7 Bit symbol Read/Write P6FC (001BH) After reset 0 P67 input 0:disable 1:enable 0 P66 input 0:disable 1:enable 0 P65 input 0:disable 1:enable 0 P64 input 0:disable 1:enable P67F 6 P66F 5 P65F 4 P64F W 0 P63 input 0:disable 1:enable 0 P62 input 0:disable 1:enable 0 P61 input 0:disable 1:enable 0 P60 input 0:disable 1:enable 3 P63F 2 P62F 1 P61F 0 P60F Function P6xF 0 0 1 1 P6xC 0 1 0 1 P67 function input disable output port input enable output port P66 function input disable output port input enable output port P65 function input disable output port input enable output port P64 function input disable output port input enable output port P63 function input disable output port input enable output port P62 function input disable output port input enable output port P61 function input disable output port input enable output port P60 function input disable output port input enable output port Note 1: Page 65 2007-10-10 TMP91FU62 4.7 Port 7 (P70 to P75) Port 7 is an 6-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register P7 are set to "1". There are the following functions in addition to an I/O port. This function enable each function by writing "1" to applicable bit of port 7 function register P7FC. *The I/O function of 8-bit timer 01 (TA0IN,TA1OUT) *The I/O function of 8-bit timer 45 (TA4IN,TA5OUT) *The input function of external interrupt (INT0) Reset operation initializes, P7CR and P7FC to "0", all bits are set to input port. Direction control (on bit basis) P7CR S P70 (TA0IN) P73 (TA4IN) P7 SB A TA0IN TA4IN P7 Internal data bus Direction control (on bit basis) P7CR Function control (on bit basis) P7FC S AS B P7 F/F OUT TA1OUT: TMRA1 TA3OUT: TMRA3 TA5OUT: TMRA5 P71 (TA1OUT) P74 (TA5OUT) B S P7 Figure 4-11 Port 70, 71, 73 and 74 Page 66 2007-10-10 TMP91FU62 Reset Direction control (on bit basis) Internal data bus P7CR write P72 Output buffer P7 write S B A P7 read Figure 4-12 Port 72 Direction control (on bit basis) Internal data bus P7CR Function control (on bit basis) P7FC S Output latch P7 P75(INT0) S B Selector P7 A & IIMC Figure 4-13 Port 75 Page 67 2007-10-10 TMP91FU62 Port 7 Register 7 P7 (001CH) Bit symbol Read/Write After reset 6 5 P75 4 P74 3 P73 R/W Data from external port (Output latch register is set to "1".) 2 P72 1 P71 0 P70 - - - - - - Port 7 Control Register (Read-modify-write instructions are prohibited.) 7 Bit symbol P7CR (001EH) Read/Write After reset Function 6 5 P75C 4 P74C 3 P73C W 0 0 0 0 0 0 2 P72C 1 P71C 0 P70C - - - - - - 0: Input 1: Output Port 7 Function Register (Read-modify-write instructions are prohibited.) 7 Bit symbol P7FC (001FH) Read/Write After reset Function 6 5 P75F W 0 0: port 1: INT0 0 0: port 1: TA5OUT 4 P74F 3 2 1 P71F W 0 0: port 1: TA1OUT 0 - - - - - - - - - - - - - - - P75 INT0 setting P7xF P7xC P75 function input port output port INT0 reserved P74 function input port output port reserved TA5OUT P73 function input port (TA4IN) output port reserved reserved P72 function input port output port reserved reserved P71 function input port output port reserved TA1OUT P70 function input port (TA0IN) output port reserved reserved 0 0 1 1 0 1 0 1 Note 1: Page 68 2007-10-10 TMP91FU62 4.8 Port 8 (P80 to P87) Port 8 is an 8-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register P8 are set to "1". There are the following functions in addition to an I/O port. This function enable each function by writing "1" to applicable bit of port 8 function register P8FC. *The I/O function of 16-bit timer 0 (TB0IN0,TB0IN1,TB0OUT0,TB0OUT1) *The I/O function of 16-bit timer 1 (TB1IN0,TB1IN1,TB1OUT0,TB1OUT1) *The input function of external interrupt (INT5 to INT8) Reset operation initializes, P8CR and P8FC to "0", all bits are set to input port. Direction control (on bit basis) P8CR Function control (on bit basis) P8FC S P80 (TB0IN0/INT5) P81 (TB0IN1/INT6) P84 (TB1IN0/INT7) P85 (TB1IN1/INT8) SB A P8 Internal data bus P8 TB0IN0, INT5 TB0IN1, INT6 TB1IN0, INT7 TB1IN1, INT8 Direction control (on bit basis) P8CR Function control (on bit basis) P8FC S AS B P8 F/F OUT TB0OUT0: TMRB0 TB0OUT1: TMRB0 TB1OUT0: TMRB1 TB1OUT1: TMRB1 P82 (TB0OUT0) P83 (TB0OUT1) P86 (TB1OUT0) P87 (TB1OUT1) B S P8 Figure 4-14 Port 8 Page 69 2007-10-10 TMP91FU62 Port 8 Register 7 P8 (0020H) Bit symbol Read/Write After reset P87 6 P86 5 P85 4 P84 R/W Data from external port (Output latch register is set to "1".) 3 P83 2 P82 1 P81 0 P80 Port 8 Control Register (Read-modify-write instructions are prohibited.) 7 Bit symbol P8CR (0022H) Read/Write After reset Function 0 0 0 0 P87C 6 P86C 5 P85C 4 P84C W 0 0 0 0 3 P83C 2 P82C 1 P81C 0 P80C 0: Input 1: Output Port 8 Function Register (Read-modify-write instructions are prohibited.) 7 Bit symbol P8FC (0023H) Read/Write After reset 0 0: port 1: TB1OUT1 0 0: port 1: TB1OUT0 0 0: port 1: TB1IN1, INT8 0 0: port 1: TB1IN0, INT7 P87F 6 P86F 5 P85F 4 P84F W 0 0: port 1: TB0OUT1 0 0: port 1: TB0OUT0 0 0: port 1: TB0IN1, INT6 0 0: port 1: TB0IN0, INT5 3 P83F 2 P82F 1 P81F 0 P80F Function P8xF 0 0 1 1 P8xC 0 1 0 1 P87 function input port output port reserved TB1OUT1 P86 function input port output port reserved TB1OUT0 P85 function input port output port TB1IN1/ INT8 reserved P84 function input port output port TB1IN0/ INT7 reserved P83 function input port output port reserved TB0OUT1 P82 function input port output port reserved TB0OUT0 P81 function input port output port TB0IN1/ INT6 reserved P80 function input port output port TB0IN0/ INT5 reserved Note: Page 70 2007-10-10 TMP91FU62 4.9 Port 9 (P90 to P97) * Port 90 to 95 Port 90 to 95 are a 6-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register are set to "1". In addition to functioning as a I/O port, port 90 to 95 can also function as I/O of SIO0, SIO1. This function enable each function by writing "1" to applicable bit of port 9 function register P9FC. Reset operation initializes P9CR and P9FC to "0", all bits are set to input port. * Port 96 to 97 Port 96 to 97 are a 2-bit general-purpose I/O port. In case of output port, this is open drain output. Reset operation initializes output latch register and control register to "1", and it is set to "High-Z" (High impedance). In addition to functioning as a I/O port, port 96 to 97 can also function as low-frequency oscillator connection pin (XT1 and XT2) during using low speed clock function. Therefore, dual clock function can use by setting of system clock control registers SYSCR0 and SYSCR1. 4.9.1 Port 90 (TXD0/RXD0), 93 (TXD1/RXD0) In addition to functioning as a I/O port, Port 90 and 93 can also function as TXD output pin or RXD input pin of serial channel. And Port 90 and 93 have a programmable open-drain function which can be controlled by the ODE register. Direction control (on bit basis) P9CR Function control (on bit basis) Internal data bus P9FC SIO exchange 1 SIOCHG0 S AS B P9 TXD0, TXD1 SB A P9 Open-drain possible: ODE RXD0, RXD1 Figure 4-15 Port 90 and 93 Page 71 2007-10-10 TMP91FU62 4.9.2 Port 91 (RXD0/TXD0), 94 (RXD1/TXD1) In addition to functioning as a I/O port, port 91 and 94 can also function as RXD input pin or TXD output pin of serial channel. And Port 91 and 94 have a programmable open-drain function which can be controlled by the SIOCHG0 register. Direction control (on bit basis) P9CR Internal data bus SIO exchange Open-drain possible: SIOCHG SIOCHG0 S Figure 4-16 Port 91 and 94 Page 72 2007-10-10 TMP91FU62 4.9.3 Port 92(CTS0/SCLK0), 95 (CTS1/SCLK1) In addition to functioning as a I/O port, port 92 and 95 can also function as CTS input pin or SCLK I/O pin of serial channel. Direction control (on bit basis) P9CR Internal data bus Function control (on bit basis) P9FC S AS B P9 SCLK0, SCLK1 SB P9 CTS0, CTS1 SCLK0, SCLK1 A P92 (SCLK0/CTS0) P95 (SCLK1/CTS1) Figure 4-17 Port 92 and 95 Page 73 2007-10-10 TMP91FU62 4.9.4 Port 96 (XT1), 97 (XT2) In addition to functioning as a I/O port, port 96 and 97 can also function as low frequency oscillator connection pins. Function control (on bit basis) Direction control (on bit basis) Internal data bus Function control (on bit basis) Direction control (on bit basis) Figure 4-18 Port 96 and 97 Page 74 2007-10-10 TMP91FU62 Port 9 Register 7 P9 (0024H) Bit symbol Read/Write After reset P97 6 P96 5 P95 4 P94 R/W Data from external port (Output latch register is set to "1".) 3 P93 2 P92 1 P91 0 P90 Port 9 Control Register (Read-modify-write instructions are prohibited.) 7 Bit symbol P9CR (0026H) Read/Write After reset Function 1 1 0 0 P97C 6 P96C 5 P95C 4 P94C W 0 0 0 0 3 P93C 2 P92C 1 P91C 0 P90C 0: Input 1: Output Port 9 Function Register (Read-modify-write instructions are prohibited.) 7 Bit Symbol P9FC (0027H) Read/Write After reset 0 Port 0: disable 1: enable P97F 6 P96F W 0 Port 0: disable 1: enable 0 0: port 1: SCLK1 output 5 P95F 4 - - - 0 0: port 1: TXD1 output 3 P93F W 0 0: port 1: SCLK0 output 2 P92F 1 - - - 0 P90F W 0 0: port 1: TXD0 output Function P9xF P9xC P97 function P96 function P95 function input port (SCLK1/ CTS1) output port reserved SCLK1 P94 function input port (RXD1) output port reserved reserved P93 function P92 function input port (SCLK0/ CTS0) output port reserved SCLK0 P91 function input port (RXD0) output port reserved reserved P90 function 0 0 XT2 XT1 input port input port 0 1 1 1 0 1 reserved input port output port reserved input port output port output port reserved TXD1 output port reserved TXD0 Note 1: Page 75 2007-10-10 TMP91FU62 4.10 Port A (PA0 to PA3) Port A is an 4-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register PA are set to "1". There are the following functions in addition to an I/O port. This function enable each function by writing "1" to applicable bit of port A function register PAFC. *The I/O function of 16-bit timer 2 (TB2IN0,TB2IN1,TB2OUT0,TB2OUT1) *The input function of external interrupt (INT1, INT2) Reset operation initializes, PACR and PAFC to "0", all bits are set to input port. Direction control (on bit basis) PACR Function control (on bit basis) PAFC S PA0 (TB2IN0/INT1) PA1 (TB2IN1/INT2) PA SB A Internal data bus PA TB2IN0, INT1 TB2IN1, INT2 Direction control (on bit basis) PACR Function control (on bit basis) PAFC S AS B PA F/F OUT TB02UT0: TMRB2 TB02UT1: TMRB2 PA2 (TB2OUT0) PA3 (TB2OUT1) B S PA Figure 4-19 Port A Page 76 2007-10-10 TMP91FU62 Port A Register 7 PA (0028H) Bit symbol Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 3 PA3 2 PA2 R/W Data from external port (Output latch register is set to "1".) 1 PA1 0 PA0 Port A Control Register (Read-modify-write instructions are prohibited.) 7 Bit symbol PACR (002AH) Read/Write After reset Function - - - - 6 - - - - 5 - - - - 4 - - - - 0 0 3 PA3C 2 PA2C W 0 0 1 PA1C 0 PA0C 0: Input 1: Output Port A Function Register (Read-modify-write instructions are prohibited.) 7 Bit symbol PAFC (002BH) Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 0 0: port 1: TB2OUT1 0 0:port 1: TB2OUT0 3 PA3F 2 PA2F W 0 0: port 1: TB2IN1, INT2 0 0: port 1: TB2IN0, INT1 1 PA1F 0 PA0F Function - - - - PAxC 0 0 1 1 PAxF 0 1 0 1 PA3 function input port output port reserved TB2OUT1 PA2 function input port output port reserved TB2OUT0 PA1 function input port output port TB2IN1/ INT2 reserved PA0 function input port output port TB2IN0/INT1 reserved Note: Page 77 2007-10-10 TMP91FU62 4.11 Port B (PB0 to PB2) Port B is an 3-bit general-purpose I/O port. Reset operation initializes to input port. All bits of output latch register PB are set to "1". Reset operation initializes, PBCR to "0", all bits are set to input port. Reset Direction control (on bit basis) Internal data bus PBCR write Port B PB0 to PB2 Output buffer PB write S B A PB read Figure 4-20 Port B0 to B2 Page 78 2007-10-10 TMP91FU62 Port B Register 7 PB (002CH) Bit symbol Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 3 - - - 2 PB2 1 PB1 R/W Data from external port (Output latch register is set to "1".) 0 PB0 Port B Control Register (Read-modify-write instructions are prohibited.) 7 Bit symbol PBCR (002EH) Read/Write After reset Function - - - - 6 - - - - 5 - - - - 4 - - - - 3 - - - - 0 2 PB2C 1 PB1C W 0 0: Input 1: Output 0 0 PB0C PBxC 0 1 PB2 function input port output port PB1 function input port output port PB0 function input port output port Note: Page 79 2007-10-10 TMP91FU62 4.12 Open-drain Control P30,P31,P41,P90,P93 can perform selection of an open-drain output per bit. Reset operation initializes all bits of the control register ODE to "0" and sets to CMOS output. Open-drain Control Register 7 ODE (003FH) Bit symbol Read/Write After reset Function 6 5 4 ODE93 3 ODE90 2 ODE41 R/W 0 0 0 0 0 1 ODE31 0 ODE30 - - - - - - - - - 0: CMOS output 1:Open drain output 4.13 Serial pins switching / Open-drain output Control TXD pin and RXD pin for a serial channel are interchangeable in P41, P42, P90, P91, P93 and P94. Serial pins switching / Open-drain Control Register 0 (Read-modify-write instructions are prohibited.) 7 SIOCHG0 (0025H) Bit symbol Read/Write After reset 6 5 SIOCHG05 4 SIOCHG04 3 SIOCHG03 W 0 P94 port 0: CMOS output 1: Opendrain output 0 0 0 P91 port 0: CMOS output 1: Opendrain output 0 0 2 SIOCHG02 1 SIOCHG01 0 SIOCHG00 - - - - - - Function 0: Setting of P94C 1: TXD1 0: Setting of P93C and P93F 1: RXD1 0: Setting of P91C 1: TXD0 0: Setting of P90C and P90F 1: RXD0 SIOCHG02 0 0 SIOCHG01 0 1 SIOCHG00 0 1 P91 Setting of P91C TXD0 (CMOS output) TXD0 (Open-drain output) P90 Setting of P90C and P90F RXD0 1 1 1 RXD0 SIOCHG05 0 0 SIOCHG04 0 1 SIOCHG03 0 1 P94 Setting of P94C TXD1 (CMOS output) TXD1 (Open-drain output) P93 Setting of P93C and P93F RXD1 1 1 1 RXD1 Page 80 2007-10-10 TMP91FU62 Serial pins switching / Open-drain Control Register 1 (Read-modify-write instructions are prohibited.) 7 SIOCHG1 (0015H) Bit symbol Read/Write After reset 6 5 4 SIOCHG14 W 0 P42 port 0: CMOS output 1: Opendrain output 3 2 SIOCHG12 W 0 0 1 SIOCHG11 0 - - - - - - - - - - - - - - - Function 0: Setting of P42C 1: TXD2 0: Setting of P41C and P41F2 1: RXD2 SIOCHG14 0 0 SIOCHG12 0 1 SIOCHG11 0 1 P42 Setting of P42C TXD2 (CMOS output) TXD2 (Open-drain output) P41 Setting of P41C and P41F2 RXD2 1 1 1 RXD2 Page 81 2007-10-10 TMP91FU62 5. 8-Bit Timers (TMRA) The TMP91FU62 features 4 channels (TMRA0, TMRA1, TMRA4, TMRA5) built-in 8-bit timers. These timers are paired into 2 modules: TMRA01 and TMRA45. Each module consists of 2 channels and can operate in any of the following 4 operating modes. * 8-bit interval timer mode * 16-bit interval timer mode * 8-bit programmable square wave pulse generation output mode (PPG - Variable duty cycle with variable period) * 8-bit pulse width modulation output mode (PWM - Variable duty cycle with constant period) Figure 5-1 to Figure 5-2 show block diagrams for TMRA01 and TMRA45. Each channel consists of an 8-bit up counter, an 8-bit comparator and an 8-bit timer register. In addition, a timer flip-flop and a prescaler are provided for each pair of channels. The operation mode and timer flip-flops are controlled by 5-byte registers SFRs (Special function registers). Each of the three modules (TMRA01 and TMRA45) can be operated independently. All modules operate in the same manner; hence only the operation of TMRA01 is explained here. Table 5-1 Specification Input pin for external clock External pin Output pin for timer flip-flop TA1OUT (Shared with P71) TA01RUN (0100H) TA0REG (0102H) TA1REG (0103H) TA01MOD (0104H) TA1FFCR (0105H) TA5OUT (Shared with P74) TA45RUN (0110H) TA4REG (0112H) TA5REG (0113H) TA45MOD (0114H) TA5FFCR (0115H) Registers and Pins for Each Module Module TMRA01 TA0IN (Shared with P70) TMRA45 TA4IN (Shared with P73) Timer run register Timer register SFR (Address) Timer mode register Timer flip-flop control register Page 82 2007-10-10 Prescaler 2 5.1 Block Diagrams Prescaler clock: T0 Selector TA01RUN n External input clock: TA0IN 8-bit up counter (UC0) T1 T16 T256 TA01MOD TA01RUN Timer flip-flop TA1FF Timer flip-flop output: TA1OUT TA1FFCR Figure 5-1 TMRA01 Block Diagram TA01MOD TA01MOD Page 83 8-bit comparator (CP0) 8-bit timer register TA0REG TA01RUN Match detect 8-bit comparator (CP1) 8-bit timer register TA1REG Internal data bus TMRA1 interrupt output: INTTA1 TMP91FU62 2007-10-10 Prescaler 2 Prescaler clock: T0 Selector TA45RUN n External input clock: TA4IN 8-bit up counter (UC4) T1 T16 T256 TA45MOD TA45RUN Timer flip-flop TA5FF Timer flip-flop output: TA5OUT TA5FFCR Figure 5-2 TMRA45 Block Diagram TA45MOD TA45MOD Page 84 8-bit comparator (CP4) 8-bit timer register TA4REG TA45RUN Match detect 8-bit comparator (CP5) 8-bit timer register TA5REG Internal data bus TMRA5 interrupt output: INTTA5 TMP91FU62 2007-10-10 TMP91FU62 5.2 Operation of Each Circuit 5.2.1 Prescalers A 9-bit prescaler generates the input clock to TMRA01. The "T0" as the input clock to prescaler is a clock divided by 4 which is selected using the prescaler clock selection register SYSCR0 @ fc = 20 MHz, fs = 32.768 kHz System Clock Selection SYSCR1 Gear Value SYSCR1 XXX 000 (fc) 001 (fc/2) 010 (fc/4) 0 (fc) 011 (fc/8) 100 (fc/16) XXX Note: xxx: Don't care 5.2.2 Up counters (UC0 and UC1) These are 8-bit binary counters which count up the input clock pulses for the clock specified by TA01MOD. The input clock for UC0 is selectable and can be either the external clock input via the TA0IN pin or one of the three internal clocks T1, T4, or T16. The clock setting is specified by the value set in TA01MOD Page 85 2007-10-10 TMP91FU62 5.2.3 Timer registers (TA0REG and TA1REG) These are 8-bit registers which can be used to set a time interval. When the value set in the timer register TA0REG or TA1REG matches the value in the corresponding up counter, the comparator match detect signal goes active. If the value set in the timer register is 00H, the signal goes active when the up counter overflows. The TA0REG are double buffer structure, each of which makes a pair with register buffer. The setting of the bit TA01RUN Timer registers 0 (TA0REG) B Y Selector A Shift trigger Register buffers 0 Write Internal data bus Matching detection in PPG cycle 2n overflow PWM Write to TA0REG S TA01RUN Figure 5-3 Configuration of TA0REG Note:The same memory address is allocated to the timer register TA0REG and the register buffer 0. When Page 86 2007-10-10 TMP91FU62 5.2.4 Comparator (CP0 and CP1) The comparator compares the value in an up counter with the value set in a timer register. If they match, the up counter is cleared to 0 and an interrupt signal (INTTA0 or INTTA1) is generated. If timer flip-flop inversion is enabled, the timer flip-flop is inverted at the same time. Note:If a value smaller than the up-counter value is written to the timer register while the timer is counting up, this will cause the timer to overflow and an interrupt cannot be generated at the expected time. (The value in the timer register can be changed without any problem if the new value is larger than the up-counter value.) In 16bit interval timer mode, be sure to write to both TA0REG and TA1REG in this order (16 bits in total), The compare circuit will not function if only the lower 8 bits are set. 5.2.5 Timer flip-flop (TA1FF) The timer flip-flop (TA1FF) is a flip-flop inverted by the match detects signal (8-bit comparator output) of each interval timer. Whether inversion is enabled or disabled is determined by the setting of the bit TA1FFCR The condition for TA1FF inversion varies with mode as shown below 8-bit interval timer mode 16-bit interval timer mode 8 bit PWM mode 8 bit PPG mode : UC0 matches TA0REG or UC1 matches TA1REG (Select either one of the two) : UC0 matches TA0REG or UC1 matches TA1REG : UC0 matches TA0REG or a 2n overflow occurs : UC0 matches TA0REG or UC0 matches TA1REG Note: If an inversion by the match-detect signal and a setting change via the TMRA1 flip-flop control register occur simultaneously, the resultant operation varies depending on the situation, as shown below. * If an inversion by the match-detect signal and an inversion via the register occur simultaneously, the flip-flop will be inverted only once. * If an inversion by the match-detect signal and an attempt to set the flip-flop to 1 via the register occur simultaneously, the timer flip-flop will be set to 1. * If an inversion by the match-detect signal and an attempt to clear the flip-flop to 0 via the register occur simultaneously the flip-flop will be cleared to 1. Be sure to stop the timer before changing the flip-flop insertion setting. If the setting is changed while the timer is counting, proper operation cannot be obtained. Page 87 2007-10-10 TMP91FU62 5.3 SFR TMRA01 Run Register 7 Bit symbol TA01RUN (0100H) Read/Write After Reset TA0RDE R/W 0 Double buffer 0: Disable 1: Enable 6 - - - 5 - - - 4 - - - 0 0 TMRA01 prescaler 3 I2TA01 2 TA01PRUN R/W 0 Up counter (UC1) 0 Up counter (UC0) 1 TA1RUN 0 TA0RUN Function IDLE2 0: Stop 1: Operate 0: Stop and clear 1: Run (count up) Count operation TA01PRUN TA1RUN / TA0RUN 0 1 Stop and clear TA0REG double buffer control 0 TA0RDE Run (Count up) 1 Enable Disable Note: The values of bits 4 to 6 of TA01RUN are "1" when read. TMRA45 Run Register 7 Bit symbol TA45RUN (0110H) Read/Write After Reset TA4RDE R/W 0 Double buffer 0: Disable 1: Enable 6 - - - 5 - - - 4 - - - 0 0 TMRA45 prescaler 3 I2TA45 2 TA45PRUN R/W 0 Up counter (UC5) 0 Up counter (UC4) 1 TA5RUN 0 TA4RUN Function IDLE2 0: Stop 1: Operate 0: Stop and clear 1: Run (count up) TA4REG double buffer control Count operation TA45PRUN TA5RUN / TA4RUN 0 1 Stop and clear 0 TA4RDE 1 Disable Enable Run (Count up) Note: The values of bits 4 to 6 of TA45RUN are "1" when read. Page 88 2007-10-10 TMP91FU62 TMRA01 Mode Register 7 Bit symbol TA01MOD (0104H) Read/Write After reset 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 PWM cycle 00: Reserved 01: 26 10: 27 11: 28 0 TA01M1 6 TA01M0 5 PWM01 4 PWM00 R/W 0 0 0 0 3 TA1CLK1 2 TA1CLK0 1 TA0CLK1 0 TA0CLK0 Function Input clock for TMRA1 00: TA0TRG 01: T1 10: T16 11: T256 Input clock for TMRA0 00: TA0IN pin 01: T1 10: T4 11: T16 TMRA0 input clock selection 00 01 TMRA1 input clock selection TA01MOD PWM cycle selection 00 01 TMRA01 operation mode selection 00 01 Page 89 2007-10-10 TMP91FU62 TMRA45 Mode Register 7 Bit symbol TA45MOD (0114H) Read/Write After reset 0 Operation mode 00: 8-bit timer mode 01: 16-bit timer mode 10: 8-bit PPG mode 11: 8-bit PWM mode 0 0 PWM cycle 00: Reserved 01: 26 10: 27 11: 28 0 TA45M1 6 TA45M0 5 PWM41 4 PWM40 R/W 0 0 0 0 3 TA5CLK1 2 TA5CLK0 1 TA4CLK1 0 TA4CLK0 Function Input clock for TMRA5 00: TA4TRG 01: T1 10: T16 11: T256 Input clock for TMRA4 00: TA4IN pin 01: T1 10: T4 11: T16 TMRA4 input clock selection 00 01 TMRA5 input clock selection TA45MOD PWM cycle selection 00 01 TMRA45 operation mode selection 00 01 Page 90 2007-10-10 TMP91FU62 TMRA1 Flip-Flop Control Register 7 Bit symbol TA1FFCR (0105H) Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 1 00: Invert TA1FF 01: Set TA1FF 10: Clear TA1FF 11: Don't care 3 TA1FFC1 R/W 1 0 TA1FF control for inversion 0: Disable 1: Enable 2 TA1FFC0 1 TA1FFIE R/W 0 TA1FF inversion select 0: TMRA0 1:TMRA1 0 TA1FFIS Function Inverse signal for timer flip-flop 1 (TA1FF) (Don't care except in 8-bit timer mode) 0 TA1FFIS 1 Inversion by TMRA1 Inversion by TMRA0 Inversion of TA1FF 0 TA1FFIE 1 Enabled Disabled Control of TA1FF 00 01 Note: The values of bits 4 to 7 of TA1FFCR are "1" when read. TMRA5 Flip-Flop Control Register 7 Bit symbol TA5FFCR (0115H) Read/Write After reset - - - 6 - - - 5 - - - 4 - - - 1 00: Invert TA5FF 01: Set TA5FF 10: Clear TA5FF 11: Don't care 3 TA5FFC1 R/W 1 0 TA5FF control for inversion 0: Disable 1: Enable 2 TA5FFC0 1 TA5FFIE R/W 0 TA5FF inversion select 0: TMRA4 1:TMRA5 0 TA5FFIS Function Inverse signal for timer flip-flop 5 (TA5FF) (Don't care except in 8-bit timer mode) 0 TA5FFIS 1 Inversion by TMRA5 Inversion by TMRA4 Inversion of TA5FF 0 TA5FFIE 1 Enabled Disabled Control of TA5FF 00 01 Note: The values of bits 4 to 7 of TA5FFCR are "1" when read. Page 91 2007-10-10 TMP91FU62 Timer Register 7 Bit symbol TA0REG (0102H) Read/Write After Reset Bit symbol TA1REG (0103H) Read/Write After Reset Bit symbol TA4REG (0112H) Read/Write After Reset Bit symbol TA5REG (0113H) Read/Write After Reset 6 5 4 - W 0 - W 0 - W 0 - W 0 3 2 1 0 Page 92 2007-10-10 TMP91FU62 5.4 Operation in Each Mode 5.4.1 8-bit timer mode Both TMRA0 and TMRA1 can be used independently as 8-bit interval timers. Set its function or counter data for TMRA0 and TMRA1 after stop these registers. 5.4.1.1 Generating interrupts at a fixed interval (Using TMRA1) To generate interrupts at constant intervals using TMRA1 (INTTA1), first stop TMRA1 then set the operation mode, input clock and a cycle to TA01MOD and TA1REG register, respectively. Then, enable the interrupt INTTA1 and start TMRA1 counting. Example: To generate an INTTA1 interrupt every 12 s at fc = 20 MHz, set each register as follows: * Clock state System clock Prescaler clock Clock gear : High frequency (fc) : fFPH : 1 (fc) MSB 7 TA01RUN TA01MOD TA1REG INTETA01 TA01RUN - 0 0 X - 6 X 0 0 1 X 5 X X 0 0 X 4 X X 1 1 X 3 - 0 1 X - 2 - 1 1 - 1 1 0 X 1 - 1 LSB 0 - X 0 - - Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (0.4 s at fc = 20 MHz) as the input clock. Set TA1REG to 12 s / T1 = 30 = 1EH Enable INTTA1 and set it to level 5. Start TMRA1 counting. Note: X: Don't care, -: No change Select the input clock using Table 5-2. Note: The input clocks for TMRA0 and TMRA1 are different from as follows. TMRA0: TA0IN input, T1, T4 or T16 TMRA1: Match output of TMRA0, T1, T16, T256 Page 93 2007-10-10 TMP91FU62 5.4.1.2 Generating a 50% duty ratio square wave pulse The state of the timer flip-flop (TA1FF) is inverted at constant intervals and its status output via the timer output pin (TA1OUT). Example: To output a 2.4 s square wave pulse from the TA1OUT pin at fc = 20 MHz, use the following procedure to make the appropriate register settings. This example uses TMRA1; however, either TMRA0 or TMRA1 may be used. * Clock state System clock Prescaler clock Clock gear : High frequency (fc) : fFPH : 1 (fc) MSB 7 TA01RUN TA01MOD TA1REG TA1FFCR P7CR P7FC TA01RUN - 0 0 X X X - 6 X 0 0 X X X X 5 X X 0 X X X X 4 X X 0 X - - X 3 - 0 0 1 - - - 2 - 1 0 0 - - 1 1 0 - 1 1 1 1 1 LSB 0 - - 1 1 - Set P71 to function as the TA1OUT pin. - - Start TMRA1 counting. Stop TMRA1 and clear it to 0. Select 8-bit timer mode and select T1 (0.4 s at fc = 20 MHz) as the input clock. Set the timer register to 2.4 s / T1 / 2 = 03H Clear TA1FF to "0" and set it to invert on the match detects signal from TMRA1. Note: X: Don't care, -: No change Page 94 2007-10-10 TMP91FU62 T1 TA01RUN Up counter Bit1 0 1 2 3 0 1 2 3 0 1 2 3 0 Bit0 Comparator timig Comparator output (Match detect) INTTA1 UC1 clear TA1FF TA1OUT 0.9 s at fc = 20 MHz Figure 5-4 Square Wave Output Timing Chart (50% duty) 5.4.1.3 Making TMRA1 count up on the match signal from the TMRA0 comparator Select 8-bit timer mode and set the comparator output from TMRA0 to be the input clock to TMRA1. Comparator output (TMRA0 match) TMRA0 up counter (when TA0REG = 5) TMRA1 up counter (when TA1REG = 2) 1 2 3 4 5 1 2 3 4 5 1 2 3 1 2 1 TMRA1 match output Figure 5-5 TMRA1 Count Up on Signal from TMRA0 Page 95 2007-10-10 TMP91FU62 5.4.2 16-bit timer mode A 16-bit interval timer is configured by pairing the two 8-bit timers TMRA0 and TMRA1. To make a 16-bit interval timer in which TMRA0 and TMRA1 are cascaded together, set TA01MOD * Clock state System clock Prescaler clock Clock gear : High frequency (fc) : fFPH : 1 (fc) If T16 (27/fc s at fc = 20 MHz) is used as the input clock for counting, set the following value in the registers: 0.4 s/(27/fc) s 62500 = F424H (e.g., set TA1REG to F4H and TA0REG to 24H). As a result, INTTA1 interrupt can be generated every 0.4 [s]. The comparator match signal is output from TMRA0 each time the up counter UC0 matches TA0REG, though the up counter UC0 is not cleared and also INTTA0 is not generated. In the case of the TMRA1 comparator, the match detect signal is output on each comparator pulse on which the values in the up counter UC1 and TA1REG match. When the match detect signal is output simultaneously from both the comparators TMRA0 and TMRA1, the up counters UC0 and UC1 are cleared to 0 and the interrupt INTTA1 is generated. Also, if inversion is enabled, the value of the timer flip-flop TA1FF is inverted. Example: When TA1REG = 04H and TA0REG = 80H Value of up counter (UC1, UC0) TMRA0 comparator match detect signal TMRA1 comparator match detect signal Interrupt INTTA0 Interrupt INTTA1 0080H 0180H 0280H 0380H 0480H 0080H Timer output TA1OUT Inversion Figure 5-6 Timer Output by 16-Bit Timer Mode Page 96 2007-10-10 TMP91FU62 5.4.3 8-bit PPG (Programmable pulse generation) output mode Square wave pulses can be generated at any frequency and duty ratio by TMRA0. The output pulses may be active low or active high. In this mode TMRA1 cannot be used. TMRA0 outputs pulses on the TA1OUT pin. tH Example: TA0REG and UC0 match (Interrupt INTTA0) TA1REG and UC0 match (Interrupt INTTA1) TA1OUT TA0REG TA1REG Figure 5-7 8-Bit PPG Output Waveforms In this mode, a programmable square wave is generated by inverting the timer output each time the 8-bit up counter (UC0) matches the value in one of the timer registers TA0REG or TA1REG. The value set in TA0REG must be smaller than the value set in TA1REG. Although the up counter for TMRA1 (UC1) is not used in this mode, TA01RUN TA1OUT TA01RUN Selector TA0IN T1 T4 T16 TA01MOD TA1FF 8-bit up counter (UC0) TA1FFCR Inversion INTTA0 Comparator Comparator INTTA1 Selector TA0REG-WR TA0REG Shift trigger Register buffer TA01RUN TA1REG Internal data bus Figure 5-8 Block Diagram of 8-Bit PPG Output Mode Page 97 2007-10-10 TMP91FU62 If the TA0REG double buffer is enabled in this mode, the value of the register buffer will be shifted into TA0REG each time TA1REG matches UC0. Use of the double buffer facilitates the handling of low-duty waves (when duty is varied). Match with TA0REG and up counter (Up counter = Q1) Match wiht TA1REG Shift from register buffer 0 TA0REG (Value to be compared) Register buffer (Up counter = Q2) Q1 Q2 Q2 Q3 TA0REG (Register buffer 0) write Figure 5-9 Operation of Register Buffer 0 Note:The values that can be set in TAxREG range from 01h to 00h (equivalent to 100h). If the maximum value 00h is set, the match-detect signal goes active when the up-counter overfolws. Example: To generate 1/4-duty 50-kHz pulses (at fc = 20 MHz): 20 s * Clock state System clock Prescaler clock Clock gear : High frequency (fc) : fFPH : 1 (fc) Calculate the value which should be set in the timer register. To obtain a frequency of 50 kHz, the pulse cycle t should be: t = 1/50 kHz = 20 s T1 = 23/fc s (at fc = 20 MHz); 20 s/(23/fc) s = 50 Therefore set TA1REG to 50 (32H), and 50-kHz pulses can be obtained. The duty is to be set to 1/4: t x 1/4 = 20 s x 1/4 = 5 s 5 s/(23/fc) s 13 Therefore, set TA0REG = 13 = 0DH. Page 98 2007-10-10 TMP91FU62 7 TA01RUN TA01MOD TA0REG TA1REG TA1FFCR 0 1 0 0 X 6 X 0 0 0 X 5 X X 0 1 X 4 X X 0 1 X 3 - X 1 0 0 2 - X 1 0 1 1 0 0 0 1 1 0 0 1 1 0 X Stop TMRA0 and TMRA01 and clear it to "0".(Double buffer disable) Set the 8-bit PPG mode, and select T1 as input clock. Write 0DH. Write 32H. Set TA1FF, enabling both inversion and the double buffer. Writing "10" provides negative logic pulse. P7CR P7FC TA01RUN X X 1 X X X X X X - - X - - - - - 1 1 1 1 - Set P71 as the TA1OUT pin. - 1 Start TMRA0 and TMRA01 counting.(Double buffer enable) Note:X : Don't Care - : No change Page 99 2007-10-10 TMP91FU62 5.4.4 8-bit PWM output mode This mode is only valid for TMRA0. In this mode, a PWM pulse with the maximum resolution of 8 bits can be output. When TMRA0 is used the PWM pulse is output on the TA1OUT pin. TMRA1 can also be used as an 8-bit timer. The timer output is inverted when the up counter (UC0) matches the value set in the timer register TA0REG or when 2n counter overflow occurs (n = 6, 7 or 8 as specified by TA01MOD TA0REG and UC0 match 2n overflow (INTTA0 interrupt) TA1OUT tPWM (PWM cycle) Figure 5-10 8-Bit PWM Waveforms Figure 5-11 shows a block diagram representing this mode. Selector TA0IN T1 T4 T16 8-bit up counter (UC0) TA01RUN TA1OUT Clear 2n overflow control Overflow TA1FF Invert TA01MOD TA1FFCR TA01MOD Comparator INTTA0 Selector TA0REG-WR TA0REG Shift trigger Register buffer0 TA01RUN Figure 5-11 Block Diagram of 8-Bit PWM Mode In this mode, the value of the register buffer will be shifted into TA0REG if 2n overflow is detected when the TA0REG double buffer is enabled. Page 100 2007-10-10 TMP91FU62 Use of the double buffer facilitates the handling of low duty ratio waves. Match with TA0REG (Up counter = Q1) 2n overflow (Up counter = Q2) Shift into TA0REG TA0REG (Value to be compared) Register buffer 0 Q1 Q2 Q2 Q3 TA0REG (Register buffer 0) write Figure 5-12 Operation of Register Buffer 0 Example: To output the following PWM waves on the TA1OUT pin at fc = 20 MHz: * Clock state System clock Prescaler clock Clock gear : High frequency (fc) : fFPH : 1 (fc) To achieve a 51.2 s PWM cycle by setting T1 to 23/fc s (at fc = 20 MHz): 51.2 s/(23/fc) s 128 = 2n Therefore n should be set to 7. Since the low-level period is 29.6 s when T1 = 23/fc s (at fc = 20 MHz), set the following value for TA0REG: 29.6 s/(23/fc) s 74 = 4AH MSB 7 TA01RUN TA01MOD TA0REG TA1FFCR P7CR P7FC TA01RUN - 1 0 X X X 1 6 X 1 1 X X X X 5 X 1 0 X X X X 4 X 0 0 X - - X 3 - - 1 1 - - - 2 - - 0 0 - - 1 1 - 0 1 1 1 1 - LSB 0 0 1 0 X - Set P71 and the TA1OUT pin. - 1 Start TMRA0 counting. Stop TMRA0 and clear it to 0. Select 8-bit PWM mode (Cycle: 27) and select T1 as the input clock. Write 4AH. Clear TA1FF to 0, enable the inversion and double buffer. Note:X : Don't Care - : No change Page 101 2007-10-10 TMP91FU62 Table 5-3 PWM Cycle Select System Clock SYSCR1 @ fc = 20 MHz, fs = 32.768 kHz 28 T16 500 ms 819.2 s 1638 s 3277 s 6554 s 13107 s 13107 s T1 62.5 ms 102.4 s 204.8 s 409.6 s 819.2 s 1638 s 1638 s T4 250 ms 409.6 s 819.2 s 1638 s 3277 s 6554 s 6554 s T16 1000 ms 1638 s 3277 s 6554 s 13107 s 26214 s 26214 s Note: xxx: Don't care 5.4.5 Settings for each mode Table 5-4 shows the SFR settings for each mode. Table 5-4 Timer Mode Setting Registers Register Name 8-bit timer x 2 channels 00 - 16-bit timer mode 01 - - - 8-bit PPG x 1 channel 10 - - - 8-bit PWM x 1 channel 11 26, 27, 28 (01, 10, 11) - - 8-bit timer x 1 channel 11 - T1, T16, T256 (01, 10, 11) Output disabled Note: - : Don't care Page 102 2007-10-10 TMP91FU62 6. 16-Bit Timer/Event Counters (TMRB) The TMP91FU62 incorporates four multifunctional 16-bit timer/event counters (TMRB0, TMRB1, TMRB2, TMRB3) which have the following operation modes: * 16-bit interval timer mode * 16-bit event counter mode * 16-bit programmable pulse generation (PPG) output mode The capture function enables selection of the following modes: * Frequency measurement mode * Pulse width measurement mode * Time differential measurement Figure 6-1 show block diagrams for TMRB0, TMRB1, TMRB2 and TMRB3. Each timer/event counter channel consists of a 16-bit up-counter, two 16-bit timer registers (one of them with a double-buffer structure), two 16-bit capture registers, two comparators, a capture input controller, two timer flipflops and a timer flip-flop controller. Each timer/event counter is controlled by an 11-byte SFR (special-function register). Each of the four channels (TMRB0, TMRB1, TMRB2, TMRB3) can be used independently. Each channel features the same operations except for those described in Table 6-1. Hence, only the operation of TMRB0 is explained below. Table 6-1 Registers and Pins for TMRB Channel TMRB0 Specification TB0IN0 (also used as P80) TB0IN1 (also used as P81) TB0OUT0 (also used as P82) TB0OUT1 (also used as P83) TB0RUN (0180H) TB0MOD (0182H) TB0FFCR (0183H) TB0RG0L (0188H) SFR (address) TB0RG0H (0189H) Timer registers TB0RG1L (018AH) TB0RG1H (018BH) TB0CP0L (018CH) TB0CP0H (018DH) Capture registers TB0CP1L (018EH) TB0CP1H (018FH) capture of TMRA Capture timing of TMRA TA1OUT TB1CP1L (019EH) TB1CP1H (019FH) TA1OUT TB2CP1L (01AEH) TB2CP1H (01AFH) TA1OUT TB3CP1L (01BEH) TB3CP1H (01BFH) Don't care TB1RG1L (019AH) TB1RG1H (019BH) TB1CP0L (019CH) TB1CP0H (019DH) TB2RG1L (01AAH) TB2RG1H (01ABH) TB2CP0L (01ACH) TB2CP0H (01ADH) TB3RG1L (01BAH) TB3RG1H (01BBH) TB3CP0L (01BCH) TB3CP0H (01BDH) TB1IN0 (also used as P84) TB1IN1 (also used as P85) TB1OUT0 (also used as P86) TB1OUT1 (also used as P87) TB1RUN (0190H) TB1MOD (0192H) TB1FFCR (0193H) TB1RG0L (0198H) TB1RG0H (0199H) TB2IN0 (also used as PA0) TB2IN1 (also used as PA1) TB2OUT0 (also used as PA2) TB2OUT1 (also used as PA3) TB2RUN (01A0H) TB2MOD (01A2H) TB2FFCR (01A3H) TB2RG0L (01A8H) TB2RG0H (01A9H) TB3IN0 (also used as P30) TB3IN1 (also used as P31) TB3OUT0 (also used as P32) TB3OUT1 (also used as P33) TB3RUN (01B0H) TB3MOD (01B2H) TB3FFCR (01B3H) TB3RG0L (01B8H) TB3RG0H (01B9H) TMRB1 TMRB2 TMRB3 External clock/capture trigger input pins External pins Timer flip-flop output pins Timer run register Timer mode register Timer flip-flop control register Page 103 2007-10-10 Internal data bus Internal data bus Run/ clear TBnRUN INT output INTTBn0 INTTBn1 6.1 Block Diagrams Prescaler clock: T0 2 T1 TBnMOD 4 T4 T16 Capture register 0 TBnCP0H/L Capture register 1 TBnCP1H/L 8 16 32 External INT input INTx INTy Timer flip-flop TBnFF0 TBnFF1 TAzOUT (From TMRA) TBnIN0 TBnIN1 Timer flip-flop output TBnOUT0 TBnOUT1 Figure 6-1 Block Diagrams of TMRB0 to TMRB3 T1 T4 T16 TBnMOD Match detection Page 104 16-bit comparator (CPn0) 16-bit timer register TBnRG0H/L 16-bit comparator (CPn1) 16-bit timer register TBnRG1H/L TBnRUN Overflow interrupt INTTBOFn Timer TMRB0 TMRB1 TMRB2 TMRB3 Match detection n 0 1 2 3 INTx INT5 INT7 INT1 INT3 INTy INT6 INT8 INT2 INT4 TAzOUT TA1OUT TA1OUT TA1OUT TMP91FU62 Internal data bus Internal data bus 2007-10-10 TMP91FU62 6.2 Operation of Each Block 6.2.1 Prescaler The 5-bit prescaler generates the source clock for TMRB0. The prescaler clock (T0) is divided clock (divided by 4) from selected clock by the register SYSCR0 Clock Gear Value SYSCR1 @fc = 20 MHz, fs = 32.768 kHz Prescaler Output Clock Resolution T1 (1/2) 23/fs (244 s) 23/fc (0.4 s) T4 (1/8) 25/fs (977 s) 25/fc (1.6 s) 26/fc (3.2 s) 27/fc (6.4 s) 28/fc (12.8 s) 29/fc (25.6 s) 29/fc (25.6 s) T16 (1/32) 27/fs (3.9 ms) 27/fc(6.4 s) 28/fc (12.8 s) 29/fc (25.6 s) 210/fc (51.2 s) 211/fc (102.4 s) 211/fc (102.4 s) System Clock SelectionSYSC1< SYSCK> 1 (fs) XXX 000 (fc) 001 (fc/2) 010 (fc/4) 0 (1/1) fFPH 24/fc (0.8 s) 25/fc (1.6 s) 26/fc (3.2 s) 27/fc (6.4 s) 0 (fc) 011 (fc/8) 100 (fc/16) XXX 1 (1/16) fc/16 clock 27/fc (6.4 s) Note: xxx: Don't care 6.2.2 Up counter (UC0) UC0 is a 16-bit binary counter which counts up according to input from the clock specified by TB0MOD 6.2.3 Timer registers (TB0RG0H/L, TB0RG1H/L) These two 16-bit registers are used to set the interval time. When the value in the up counter UC0 matches the value set in this timer register, the comparator match detect signal will go active. Setting data for both upper and lower timer registers is needed. For example, using 2-byte data transfer instruction or using 1-byte data transfer instruction twice for lower 8 bits and upper 8 bits in order. (The compare circuit will not operate if only the lower 8 bits are written. Be sure to write to both timer registers (16 bits) from the lower 8 bits followed by the upper 8 bits.) The TB0RG0H/L timer register has a double-buffer structure, which is paired with register buffer 0. The value set in TB0RUN Page 105 2007-10-10 TMP91FU62 When the double buffer is enabled, data is transferred from the register buffer 0 to the timer register when the values in the up counter (UC0) and the timer register TB0RG1H/L match. The double buffer circuit incorporates two flags to indicate whether or not data is written to the lower 8 bits and the upper 8 bits of the register buffer, respectively. Only when both flags are set can data be transferred from the register buffer to the timer register by a match between the up-counter UC0 and the timer register TB0RG1. This data transfer is performed so long as 16-bit data is written in the register buffer regardless of the register buffer to the timer register unexpectedly as explained below. For example, let us assume that an interrupt occurs when only the lower 8 bits (L1) of the register buffer data (H1L1) have been written and the interrupt routine includes writes to all 16 bits in the register buffer and a transfer of the data to the timer register. In this case, if the higher 8 bits (H1) are written after the interrupt routine is completed, only the flag for the higher 8 bits will be set, the flag for the lower 8 bits having been cleared in the interrupt routine. Therefore, even if a match occurs between UC0 and TB0RG1, no data transfer will be performed. Then, in an attempt to set the next set of data (H2L2) in the register buffer, when the lower 8 bits (L2) are written, this will cause the flag for the lower 8 bits to be set as well as the flag for the higher 8 bits which has been set by writing the previous data (H1). If a match between UC0 and TB0RG1 occurs before the higher 8 bits (H2) are written, this will cause unexpected data (H1L2) to be sent to the timer register instead of the intended data (H2L2). To avoid such transfer timing problems due to interrupts, the DI instruction (disable interrupts) and the EI (enable interrupts) can be executed before and after setting data in the register buffer, respectively. After a reset, TB0RG0H/L and TB0RG1H/L are undefined. If the 16-bit timer is to be used after a reset, data should be written to it beforehand. On a reset TMRB0 TB0RG0H/L Upper 8 bits 000189H Lower 8 bits 000188H TB0RG1H/L Upper 8 bits 00018BH Lower 8 bits 00018AH TMRB1 TB1RG0H/L Upper 8 bits 000199H Lower 8 bits 000198H TB1RG1H/L Upper 8 bits 00019BH Lower 8 bits 00019AH TMRB2 TB2RG0H/L Upper 8 bits 0001A9H Lower 8 bits 0001A8H TB2RG1H/L Upper 8 bits 0001ABH Lower 8 bits 0001AAH TMRB3 TB3RG0H/L Upper 8 bits 0001B9H Lower 8 bits 0001B8H TB3RG1H/L Upper 8 bits 0001BBH Lower 8 bits 0001BAH Note:The timer registers are write-only registers and thus cannot be read. Page 106 2007-10-10 TMP91FU62 6.2.4 Capture registers (TB0CP0H/L, TB0CP1H/L) These 16-bit registers are used to latch the values in the up counter (UC0). Data in the capture registers should be read all 16 bits. For example, using a 2-byte data load instruction or two 1-byte data load instructions. The least significant byte is read first, followed by the most significant byte. (during capture is read, capture operation is prohibited. In that case, the lower 8 bits should be read first, followed by the 8 bits.) The addresses of the capture registers are as follows; TMRB0 TB0CP0H/L Upper 8 bits 00018DH Lower 8 bits 00018CH TB0CP1H/L Upper 8 bits 00018FH Lower 8 bits 00018EH TMRB1 TB1CP0H/L Upper 8 bits 00019DH Lower 8 bits 00019CH TB1CP1H/L Upper 8 bits 00019FH Lower 8 bits 00019EH TMRB2 TB2CP0H/L Upper 8 bits 0001ADH Lower 8 bits 0001ACH TB2CP1H/L Upper 8 bits 0001AFH Lower 8 bits 0001AEH TMRB3 TB3CP0H/L Upper 8 bits 0001BDH Lower 8 bits 0001BCH TB3CP1H/L Upper 8 bits 0001BFH Lower 8 bits 0001BEH Note:The capture registers are read-only registers and thus cannot be written to. 6.2.5 Capture Input Control and External Interrupt Control This circuit controls the timing to latch the value of up-counter UC0 into TB0CP0H/L and TB0CP1H/L, and generates external interrupt.The latch timing of capture register and selection of edge for external interrupt is controlled by TB0MOD Page 107 2007-10-10 TMP91FU62 6.2.6 Comparators (CP00, CP01) CP10 and CP11 are 16-bit comparators which compare the value in the up counter UC0 with the value set in TB0RG0H/L or TB0RG1H/L respectively, in order to detect a match. If a match is detected, the comparator generates an interrupt (INTTB00 or INTTB01 respectively). 6.2.7 Timer flip-flops (TB0FF0, TB0FF1) These flip-flops are inverted by the match detect signals from the comparators and the latch signals to the capture registers. Inversion can be enabled and disabled for each element using TB0FFCR Note:If an inversion by the match-detect signal and a setting change via the TB0FFCR register occurs simultaneously, the resultant operation varies depending on the situation, as shown below. * If an inversion by the match-detect signal and an inversion via the register occur simultaneously, the flip-flop will be inverted only once. * If an inversion by the match-detect signal and an attempt to set the flip-flop to 1 via the register occur simultaneously, the flip-flop will be set to 1. * If an inversion by the match-detect signal and an attempt to clear the flip-flop to 0 via the register occur simultaneously, the flip-flop will be cleared to 0. If an inversion by match-detect signal and inversion disable setting occur simultaneously, two case (it is inverted and it is not inverted) are occurred. Therefore, if changing inversion control (inversion enable/disable), stop timer operation beforehand. The values of TB0FF0 and TB0FF1 can be output via the timer output pins TB0OUT0 (which is shared with P82 and TB0OUT1 (which is shared with P83). Timer output should be specified using the port P function register. Page 108 2007-10-10 TMP91FU62 6.3 SFR TMRB Run Register 7 Bit symbol TB0RUN (0180H) Read/Write After reset TB0RDE R/W 0 Double Buffer 0: Disable 1: Enable TB1RDE R/W 0 Double Buffer 0: Disable 1: Enable TB2RDE R/W 0 Double Buffer 0: Disable 1: Enable TB3RDE R/W 0 Double Buffer 0: Disable 1: Enable 6 - R/W 0 5 - - 4 - - 3 I2TB0 R/W 0 IDLE2 0: Stop 1: Operate - - I2TB1 R/W 0 IDLE2 0: Stop 1: Operate - - I2TB2 R/W 0 IDLE2 0: Stop 1: Operate - - I2TB3 R/W 0 IDLE2 0: Stop 1: Operate 2 TB0PRUN R/W 0 TMRB0 prescaler 0: Stop and Clear 1: Run (count up) TB1PRUN R/W 0 TMRB1 prescaler 0: Stop and Clear 1: Run (count up) TB2PRUN R/W 0 TMRB2 prescaler 0: Stop and Clear 1: Run (count up) TB3PRUN R/W 0 TMRB3 prescaler 0: Stop and Clear 1: Run (count up) - - - UC3 TB3RUN R/W 0 - - - UC2 TB2RUN R/W 0 - - - UC1 TB1RUN R/W 0 1 - - - UC0 0 TB0RUN R/W 0 Function Always write 0. Not in use Bit symbol TB1RUN (0190H) Read/Write After reset - R/W 0 - - Function Always write 0. Not in use Bit symbol TB2RUN (01A0H) Read/Write After reset - R/W 0 - - Function Always write 0. Not in use Bit symbol TB3RUN (01B0H) Read/Write After reset - R/W 0 - - Function Always write 0. Not in use Operation I2TB0, I2TB1, I2TB2, I2TB3: Operation of IDLE2 mode TB0PRUN, TB1PRUN, TB2PRUN, TB3PRUN: Operation of prescaler TB0RUN, TB1RUN, TB2RUN, TB3RUN: Operation of TMRB 0 1 Stop and Clear Count Note: Bits 1, 4 and 5 of TB0RUN/TB1RUN/TB2RUN/TB3RUN are "1" when read. Page 109 2007-10-10 TMP91FU62 TMRB Mode Register (Read-modify-write instructions are prohibited.) (1/2) 7 Bit symbol TB0MOD (0182H) Read/Write After reset 0 TB0CT1 R/W 0 6 TB0ET1 5 TB0CP0I W* 1 0 0 4 TB0CPM1 3 TB0CPM0 2 TB0CLE R/W 0 0 0 1 TB0CLK1 0 TB0CLK0 TB0FF1 inversion trigger 0: Trigger disable 1: Trigger enable Function Invert when UC0 is loaded into TB0CP1H/L Bit symbol TB1MOD (0192H) Read/Write After reset 0 TB1CT1 R/W 0 Invert when UC0 matches with TB0RG1H/L TB1ET1 Software capture control 0: Software capture 1: Undefined Capture timing 00: Disable INT5 occurs at rising edge 01: TB0IN0 TB0IN1 INT5 occurs at rising edge 10: TB0IN0 TB0IN0 INT5 occurs at falling edge 11: TA1OUT TA1OUT INT5 occurs at rising edge Up counter control 0: Clear disable 1: Clear enable TMRB0 input clock select 00: TB0IN0 pin input 01: T1 10: T4 11: T16 TB1CP0I W* 1 TB1CPM1 TB1CPM0 TB1CLE R/W TB1CLK1 TB1CLK0 0 0 0 0 0 TB1FF1 inversion trigger 0: Trigger disable 1: Trigger enable Function Invert when UC1 is loaded into TB1CP1H/L Bit symbol TB2MOD (01A2H) Read/Write After reset 0 TB2CT1 R/W 0 Invert when UC1 matches with TB1RG1H/L TB2ET1 Software capture control 0: Software capture 1: Undefined Capture timing 00: Disable INT7 occurs at rising edge 01: TB1IN0 TB1IN1 INT7 occurs at rising edge 10: TB1IN0 TB1IN0 INT7 occurs at falling edge 11: TA1OUT TA1OUT INT7 occurs at rising edge Up counter control 0: Clear disable 1: Clear enable TMRB1 input clock select 00: TB1IN0 pin input 01: T1 10: T4 11: T16 TB2CP0I W* 1 TB2CPM1 TB2CPM0 TB2CLE R/W TB2CLK1 TB2CLK0 0 0 0 0 0 TB2FF1 inversion trigger 0: Trigger disable 1: Trigger enable Function Invert when UC2 is loaded into TB2CP1H/L Bit symbol TB3MOD (01B2H) Read/Write After reset 0 TB3CT1 R/W 0 Invert when UC2 matches with TB2RG1H/L TB3ET1 Software capture control 0: Software capture 1: Undefined Capture timing 00: Disable INT1 occurs at rising edge 01: TB2IN0 TB2IN1 INT1 occurs at rising edge 10: TB2IN0 TB2IN0 INT1 occurs at falling edge 11: TA1OUT TA1OUT INT1 occurs at rising edge Up counter control 0: Clear disable 1: Clear enable TMRB2 input clock select 00: TB2IN0 pin input 01: T1 10: T4 11: T16 TB3CP0I W* 1 TB3CPM1 TB3CPM0 TB3CLE R/W TB3CLK1 TB3CLK0 0 0 0 0 0 TB3FF1 inversion trigger 0: Trigger disable 1: Trigger enable Function Invert when UC3 is loaded into TB3CP1H/L Invert when UC3 matches with TB3RG1H/L Software capture control 0: Software capture 1: Undefined Capture timing 00: Disable INT3 occurs at rising edge 01: TB3IN0| TB3IN1| INT3 occurs at rising edge 10: TB3IN0| TB3IN0O INT3 occurs at falling edge 11: Don't care Up counter control 0: Clear disable 1: Clear enable TMRB3 input clock select 00: TB3IN0 pin input 01: T1 10: T4 11: T16 Page 110 2007-10-10 TMP91FU62 TMRB source clock 00 01 Up counter clear control (UCn) 0 Capture/Interrupt timing Capture control 00 01 10 11 Software capture 0 Note 1: n=0,1,2,3 Note 2: As described above, whenever 0 is written to TBnMOD Page 111 2007-10-10 TMP91FU62 TMRB Flip-Flop Control Register (Read-modify-write instructions are prohibited.) (1/2) 7 Bit symbol TB0FFCR (0183H) Read/Write After reset 1 TB0FF1 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. Bit symbol TB1FFCR (0193H) Read/Write After reset 1 TB1FF1 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. Bit symbol TB2FFCR (01A3H) Read/Write After reset 1 TB2FF1 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. Bit symbol TB3FFCR (01B3H) Read/Write After reset 1 TB3FF1 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. TB3FF1C1 W* 1 0 0 TB3FF1C0 TB2FF1C1 W* 1 0 0 TB2FF1C0 TB1FF1C1 W* 1 0 0 TB1FF1C0 TB0FF1C1 W* 1 0 0 6 TB0FF1C0 5 TB0C1T1 4 TB0C0T1 R/W 0 0 1 TB0FF0 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. TB1FF0C1 W* 0 0 1 TB1FF0 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. TB2FF0C1 W* 0 0 1 TB2FF0 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. TB3FF0C1 W* 0 0 1 TB3FF0 control 00: Invert 01: Set 10: Clear 11: Don't care Note: Always read as 11. 1 TB3FF0C0 1 TB2FF0C0 1 TB1FF0C0 3 TB0E1T1 2 TB0E0T1 1 TB0FF0C1 W* 1 0 TB0FF0C0 TB0FF0 inversion trigger 0: Disable 1: Enable Invert when UC0 is loaded into TB0CP1H/L. TB1C1T1 Invert when UC0 is loaded into TB0CP0H/L. TB1C0T1 R/W Invert when UC0 matches TB0RG1H/L. TB1E1T1 Invert when UC0 matches TB0RG0H/L. TB1E0T1 Function TB1FF0 inversion trigger 0: Disable 1: Enable Invert when UC1 is loaded into TB1CP1H/L. TB2C1T1 Invert when UC1 is loaded into TB1CP0H/L. TB2C0T1 R/W Invert when UC1 matches TB1RG1H/L. TB2E1T1 Invert when UC1 matches TB1RG0H/L. TB2E0T1 Function TB2FF0 inversion trigger 0: Disable 1: Enable Invert when UC2 is loaded into TB2CP1H/L. TB3C1T1 Invert when UC2 is loaded into TB2CP0H/L. TB3C0T1 R/W Invert when UC2 matches TB2RG1H/L. TB3E1T1 Invert when UC2 matches TB2RG0H/L. TB3E0T1 Function TB3FF0 inversion trigger 0: Disable 1: Enable Invert when UC3 is loaded into TB3CP1H/L. Invert when UC3 is loaded into TB3CP0H/L. Invert when UC3 matches TB3RG1H/L. Invert when UC3 matches TB3RG0H/L. Function Page 112 2007-10-10 TMP91FU62 00 01 0 0 0 0 00 01 Note: n=0,1,2,3 Page 113 2007-10-10 TMP91FU62 6.4 Operation in Each Mode 6.4.1 16-Bit Interval Timer Mode Generating interrupts at fixed intervals In this example the interrupt INTTB01 is set to be generated at fixed intervals. The interval time is set in the timer register TB0RG1H/L. 7 TB0RUN INTETB0 TB0FFCR TB0MOD 0 X 1 0 6 0 1 1 0 5 X 0 0 1 4 X 0 0 0 3 - X 0 0 2 0 0 0 1 1 X 0 1 * 0 0 0 1 * Select internal clock for input and disable the capture function. Stop TMRB0. Enable INTTB01 and set it to interrupt level 4. Disable INTTB00. Disable trigger. (**=01, 10, 11) TB0RG1 * * TB0RUN 0 * * 0 * * X * * X * * - * * 1 * * X * * 1 Start TMRB0. Set interval time (16 bits). Note:X: Don't care, -: No change 6.4.2 16-Bit Event Counter Mode If the external clock (TB0IN0 pin input) is selected as the input clock in 16-bit timer mode, the timer can be used as an event counter. The up-counter counts up on the rising edge of TB0IN0 input. To read the value of the counter, first perform software capture once, then read the captured value. 6 TB0RUN P8CR P8FC INTETB0 TB0FFCR TB0MOD TB0RG1 0 - - X 1 0 * * TB0RUN 0 0 - - 1 1 0 * * 0 5 X - - 0 0 1 * * X 4 X - - 0 0 0 * * X 3 - - - X 0 0 * * - 2 0 - - 0 0 1 * * 1 1 X - - 0 1 0 * * X 0 0 0 1 0 1 0 * * 1 Start TMRB0. Stop TMRB0. Set port to input mode. Set port to input mode. Enable INTTB01 and set interrupt level 4. Disable INTTB00. Disable trigger. Select TB0IN0 as the input clock. Set the number of counts (16 bits). Note 1: X: Don't care, -: No change Note 2: When the timer is used as an event counter, set the prescaler to run mode (TB0RUN |